1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /*
3  * Copyright 2014-2022 Advanced Micro Devices, Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  */
23 
24 #include <linux/bsearch.h>
25 #include <linux/pci.h>
26 #include <linux/slab.h>
27 #include "kfd_priv.h"
28 #include "kfd_device_queue_manager.h"
29 #include "kfd_pm4_headers_vi.h"
30 #include "kfd_pm4_headers_aldebaran.h"
31 #include "cwsr_trap_handler.h"
32 #include "amdgpu_amdkfd.h"
33 #include "kfd_smi_events.h"
34 #include "kfd_svm.h"
35 #include "kfd_migrate.h"
36 #include "amdgpu.h"
37 #include "amdgpu_xcp.h"
38 
39 #define MQD_SIZE_ALIGNED 768
40 
41 /*
42  * kfd_locked is used to lock the kfd driver during suspend or reset
43  * once locked, kfd driver will stop any further GPU execution.
44  * create process (open) will return -EAGAIN.
45  */
46 static int kfd_locked;
47 
48 #ifdef CONFIG_DRM_AMDGPU_CIK
49 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd;
50 #endif
51 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd;
52 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd;
53 extern const struct kfd2kgd_calls arcturus_kfd2kgd;
54 extern const struct kfd2kgd_calls aldebaran_kfd2kgd;
55 extern const struct kfd2kgd_calls gc_9_4_3_kfd2kgd;
56 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd;
57 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd;
58 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd;
59 
60 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
61 				unsigned int chunk_size);
62 static void kfd_gtt_sa_fini(struct kfd_dev *kfd);
63 
64 static int kfd_resume(struct kfd_node *kfd);
65 
66 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd)
67 {
68 	uint32_t sdma_version = kfd->adev->ip_versions[SDMA0_HWIP][0];
69 
70 	switch (sdma_version) {
71 	case IP_VERSION(4, 0, 0):/* VEGA10 */
72 	case IP_VERSION(4, 0, 1):/* VEGA12 */
73 	case IP_VERSION(4, 1, 0):/* RAVEN */
74 	case IP_VERSION(4, 1, 1):/* RAVEN */
75 	case IP_VERSION(4, 1, 2):/* RENOIR */
76 	case IP_VERSION(5, 2, 1):/* VANGOGH */
77 	case IP_VERSION(5, 2, 3):/* YELLOW_CARP */
78 	case IP_VERSION(5, 2, 6):/* GC 10.3.6 */
79 	case IP_VERSION(5, 2, 7):/* GC 10.3.7 */
80 		kfd->device_info.num_sdma_queues_per_engine = 2;
81 		break;
82 	case IP_VERSION(4, 2, 0):/* VEGA20 */
83 	case IP_VERSION(4, 2, 2):/* ARCTURUS */
84 	case IP_VERSION(4, 4, 0):/* ALDEBARAN */
85 	case IP_VERSION(4, 4, 2):
86 	case IP_VERSION(5, 0, 0):/* NAVI10 */
87 	case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */
88 	case IP_VERSION(5, 0, 2):/* NAVI14 */
89 	case IP_VERSION(5, 0, 5):/* NAVI12 */
90 	case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */
91 	case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */
92 	case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */
93 	case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */
94 	case IP_VERSION(6, 0, 0):
95 	case IP_VERSION(6, 0, 1):
96 	case IP_VERSION(6, 0, 2):
97 	case IP_VERSION(6, 0, 3):
98 		kfd->device_info.num_sdma_queues_per_engine = 8;
99 		break;
100 	default:
101 		dev_warn(kfd_device,
102 			"Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n",
103 			sdma_version);
104 		kfd->device_info.num_sdma_queues_per_engine = 8;
105 	}
106 
107 	bitmap_zero(kfd->device_info.reserved_sdma_queues_bitmap, KFD_MAX_SDMA_QUEUES);
108 
109 	switch (sdma_version) {
110 	case IP_VERSION(6, 0, 0):
111 	case IP_VERSION(6, 0, 1):
112 	case IP_VERSION(6, 0, 2):
113 	case IP_VERSION(6, 0, 3):
114 		/* Reserve 1 for paging and 1 for gfx */
115 		kfd->device_info.num_reserved_sdma_queues_per_engine = 2;
116 		/* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */
117 		bitmap_set(kfd->device_info.reserved_sdma_queues_bitmap, 0,
118 			   kfd->adev->sdma.num_instances *
119 			   kfd->device_info.num_reserved_sdma_queues_per_engine);
120 		break;
121 	default:
122 		break;
123 	}
124 }
125 
126 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd)
127 {
128 	uint32_t gc_version = KFD_GC_VERSION(kfd);
129 
130 	switch (gc_version) {
131 	case IP_VERSION(9, 0, 1): /* VEGA10 */
132 	case IP_VERSION(9, 1, 0): /* RAVEN */
133 	case IP_VERSION(9, 2, 1): /* VEGA12 */
134 	case IP_VERSION(9, 2, 2): /* RAVEN */
135 	case IP_VERSION(9, 3, 0): /* RENOIR */
136 	case IP_VERSION(9, 4, 0): /* VEGA20 */
137 	case IP_VERSION(9, 4, 1): /* ARCTURUS */
138 	case IP_VERSION(9, 4, 2): /* ALDEBARAN */
139 		kfd->device_info.event_interrupt_class = &event_interrupt_class_v9;
140 		break;
141 	case IP_VERSION(9, 4, 3): /* GC 9.4.3 */
142 		kfd->device_info.event_interrupt_class =
143 						&event_interrupt_class_v9_4_3;
144 		break;
145 	case IP_VERSION(10, 3, 1): /* VANGOGH */
146 	case IP_VERSION(10, 3, 3): /* YELLOW_CARP */
147 	case IP_VERSION(10, 3, 6): /* GC 10.3.6 */
148 	case IP_VERSION(10, 3, 7): /* GC 10.3.7 */
149 	case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */
150 	case IP_VERSION(10, 1, 4):
151 	case IP_VERSION(10, 1, 10): /* NAVI10 */
152 	case IP_VERSION(10, 1, 2): /* NAVI12 */
153 	case IP_VERSION(10, 1, 1): /* NAVI14 */
154 	case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */
155 	case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */
156 	case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */
157 	case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */
158 		kfd->device_info.event_interrupt_class = &event_interrupt_class_v10;
159 		break;
160 	case IP_VERSION(11, 0, 0):
161 	case IP_VERSION(11, 0, 1):
162 	case IP_VERSION(11, 0, 2):
163 	case IP_VERSION(11, 0, 3):
164 	case IP_VERSION(11, 0, 4):
165 		kfd->device_info.event_interrupt_class = &event_interrupt_class_v11;
166 		break;
167 	default:
168 		dev_warn(kfd_device, "v9 event interrupt handler is set due to "
169 			"mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version);
170 		kfd->device_info.event_interrupt_class = &event_interrupt_class_v9;
171 	}
172 }
173 
174 static void kfd_device_info_init(struct kfd_dev *kfd,
175 				 bool vf, uint32_t gfx_target_version)
176 {
177 	uint32_t gc_version = KFD_GC_VERSION(kfd);
178 	uint32_t asic_type = kfd->adev->asic_type;
179 
180 	kfd->device_info.max_pasid_bits = 16;
181 	kfd->device_info.max_no_of_hqd = 24;
182 	kfd->device_info.num_of_watch_points = 4;
183 	kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED;
184 	kfd->device_info.gfx_target_version = gfx_target_version;
185 
186 	if (KFD_IS_SOC15(kfd)) {
187 		kfd->device_info.doorbell_size = 8;
188 		kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t);
189 		kfd->device_info.supports_cwsr = true;
190 
191 		kfd_device_info_set_sdma_info(kfd);
192 
193 		kfd_device_info_set_event_interrupt_class(kfd);
194 
195 		if (gc_version < IP_VERSION(11, 0, 0)) {
196 			/* Navi2x+, Navi1x+ */
197 			if (gc_version == IP_VERSION(10, 3, 6))
198 				kfd->device_info.no_atomic_fw_version = 14;
199 			else if (gc_version == IP_VERSION(10, 3, 7))
200 				kfd->device_info.no_atomic_fw_version = 3;
201 			else if (gc_version >= IP_VERSION(10, 3, 0))
202 				kfd->device_info.no_atomic_fw_version = 92;
203 			else if (gc_version >= IP_VERSION(10, 1, 1))
204 				kfd->device_info.no_atomic_fw_version = 145;
205 
206 			/* Navi1x+ */
207 			if (gc_version >= IP_VERSION(10, 1, 1))
208 				kfd->device_info.needs_pci_atomics = true;
209 		} else if (gc_version < IP_VERSION(12, 0, 0)) {
210 			/*
211 			 * PCIe atomics support acknowledgment in GFX11 RS64 CPFW requires
212 			 * MEC version >= 509. Prior RS64 CPFW versions (and all F32) require
213 			 * PCIe atomics support.
214 			 */
215 			kfd->device_info.needs_pci_atomics = true;
216 			kfd->device_info.no_atomic_fw_version = kfd->adev->gfx.rs64_enable ? 509 : 0;
217 		}
218 	} else {
219 		kfd->device_info.doorbell_size = 4;
220 		kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t);
221 		kfd->device_info.event_interrupt_class = &event_interrupt_class_cik;
222 		kfd->device_info.num_sdma_queues_per_engine = 2;
223 
224 		if (asic_type != CHIP_KAVERI &&
225 		    asic_type != CHIP_HAWAII &&
226 		    asic_type != CHIP_TONGA)
227 			kfd->device_info.supports_cwsr = true;
228 
229 		if (asic_type != CHIP_HAWAII && !vf)
230 			kfd->device_info.needs_pci_atomics = true;
231 	}
232 }
233 
234 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf)
235 {
236 	struct kfd_dev *kfd = NULL;
237 	const struct kfd2kgd_calls *f2g = NULL;
238 	uint32_t gfx_target_version = 0;
239 
240 	switch (adev->asic_type) {
241 #ifdef CONFIG_DRM_AMDGPU_CIK
242 	case CHIP_KAVERI:
243 		gfx_target_version = 70000;
244 		if (!vf)
245 			f2g = &gfx_v7_kfd2kgd;
246 		break;
247 #endif
248 	case CHIP_CARRIZO:
249 		gfx_target_version = 80001;
250 		if (!vf)
251 			f2g = &gfx_v8_kfd2kgd;
252 		break;
253 #ifdef CONFIG_DRM_AMDGPU_CIK
254 	case CHIP_HAWAII:
255 		gfx_target_version = 70001;
256 		if (!amdgpu_exp_hw_support)
257 			pr_info(
258 	"KFD support on Hawaii is experimental. See modparam exp_hw_support\n"
259 				);
260 		else if (!vf)
261 			f2g = &gfx_v7_kfd2kgd;
262 		break;
263 #endif
264 	case CHIP_TONGA:
265 		gfx_target_version = 80002;
266 		if (!vf)
267 			f2g = &gfx_v8_kfd2kgd;
268 		break;
269 	case CHIP_FIJI:
270 	case CHIP_POLARIS10:
271 		gfx_target_version = 80003;
272 		f2g = &gfx_v8_kfd2kgd;
273 		break;
274 	case CHIP_POLARIS11:
275 	case CHIP_POLARIS12:
276 	case CHIP_VEGAM:
277 		gfx_target_version = 80003;
278 		if (!vf)
279 			f2g = &gfx_v8_kfd2kgd;
280 		break;
281 	default:
282 		switch (adev->ip_versions[GC_HWIP][0]) {
283 		/* Vega 10 */
284 		case IP_VERSION(9, 0, 1):
285 			gfx_target_version = 90000;
286 			f2g = &gfx_v9_kfd2kgd;
287 			break;
288 		/* Raven */
289 		case IP_VERSION(9, 1, 0):
290 		case IP_VERSION(9, 2, 2):
291 			gfx_target_version = 90002;
292 			if (!vf)
293 				f2g = &gfx_v9_kfd2kgd;
294 			break;
295 		/* Vega12 */
296 		case IP_VERSION(9, 2, 1):
297 			gfx_target_version = 90004;
298 			if (!vf)
299 				f2g = &gfx_v9_kfd2kgd;
300 			break;
301 		/* Renoir */
302 		case IP_VERSION(9, 3, 0):
303 			gfx_target_version = 90012;
304 			if (!vf)
305 				f2g = &gfx_v9_kfd2kgd;
306 			break;
307 		/* Vega20 */
308 		case IP_VERSION(9, 4, 0):
309 			gfx_target_version = 90006;
310 			if (!vf)
311 				f2g = &gfx_v9_kfd2kgd;
312 			break;
313 		/* Arcturus */
314 		case IP_VERSION(9, 4, 1):
315 			gfx_target_version = 90008;
316 			f2g = &arcturus_kfd2kgd;
317 			break;
318 		/* Aldebaran */
319 		case IP_VERSION(9, 4, 2):
320 			gfx_target_version = 90010;
321 			f2g = &aldebaran_kfd2kgd;
322 			break;
323 		case IP_VERSION(9, 4, 3):
324 			gfx_target_version = adev->rev_id >= 1 ? 90402
325 					   : adev->flags & AMD_IS_APU ? 90400
326 					   : 90401;
327 			f2g = &gc_9_4_3_kfd2kgd;
328 			break;
329 		/* Navi10 */
330 		case IP_VERSION(10, 1, 10):
331 			gfx_target_version = 100100;
332 			if (!vf)
333 				f2g = &gfx_v10_kfd2kgd;
334 			break;
335 		/* Navi12 */
336 		case IP_VERSION(10, 1, 2):
337 			gfx_target_version = 100101;
338 			f2g = &gfx_v10_kfd2kgd;
339 			break;
340 		/* Navi14 */
341 		case IP_VERSION(10, 1, 1):
342 			gfx_target_version = 100102;
343 			if (!vf)
344 				f2g = &gfx_v10_kfd2kgd;
345 			break;
346 		/* Cyan Skillfish */
347 		case IP_VERSION(10, 1, 3):
348 		case IP_VERSION(10, 1, 4):
349 			gfx_target_version = 100103;
350 			if (!vf)
351 				f2g = &gfx_v10_kfd2kgd;
352 			break;
353 		/* Sienna Cichlid */
354 		case IP_VERSION(10, 3, 0):
355 			gfx_target_version = 100300;
356 			f2g = &gfx_v10_3_kfd2kgd;
357 			break;
358 		/* Navy Flounder */
359 		case IP_VERSION(10, 3, 2):
360 			gfx_target_version = 100301;
361 			f2g = &gfx_v10_3_kfd2kgd;
362 			break;
363 		/* Van Gogh */
364 		case IP_VERSION(10, 3, 1):
365 			gfx_target_version = 100303;
366 			if (!vf)
367 				f2g = &gfx_v10_3_kfd2kgd;
368 			break;
369 		/* Dimgrey Cavefish */
370 		case IP_VERSION(10, 3, 4):
371 			gfx_target_version = 100302;
372 			f2g = &gfx_v10_3_kfd2kgd;
373 			break;
374 		/* Beige Goby */
375 		case IP_VERSION(10, 3, 5):
376 			gfx_target_version = 100304;
377 			f2g = &gfx_v10_3_kfd2kgd;
378 			break;
379 		/* Yellow Carp */
380 		case IP_VERSION(10, 3, 3):
381 			gfx_target_version = 100305;
382 			if (!vf)
383 				f2g = &gfx_v10_3_kfd2kgd;
384 			break;
385 		case IP_VERSION(10, 3, 6):
386 		case IP_VERSION(10, 3, 7):
387 			gfx_target_version = 100306;
388 			if (!vf)
389 				f2g = &gfx_v10_3_kfd2kgd;
390 			break;
391 		case IP_VERSION(11, 0, 0):
392 			gfx_target_version = 110000;
393 			f2g = &gfx_v11_kfd2kgd;
394 			break;
395 		case IP_VERSION(11, 0, 1):
396 		case IP_VERSION(11, 0, 4):
397 			gfx_target_version = 110003;
398 			f2g = &gfx_v11_kfd2kgd;
399 			break;
400 		case IP_VERSION(11, 0, 2):
401 			gfx_target_version = 110002;
402 			f2g = &gfx_v11_kfd2kgd;
403 			break;
404 		case IP_VERSION(11, 0, 3):
405 			/* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */
406 			gfx_target_version = 110001;
407 			f2g = &gfx_v11_kfd2kgd;
408 			break;
409 		default:
410 			break;
411 		}
412 		break;
413 	}
414 
415 	if (!f2g) {
416 		if (adev->ip_versions[GC_HWIP][0])
417 			dev_err(kfd_device, "GC IP %06x %s not supported in kfd\n",
418 				adev->ip_versions[GC_HWIP][0], vf ? "VF" : "");
419 		else
420 			dev_err(kfd_device, "%s %s not supported in kfd\n",
421 				amdgpu_asic_name[adev->asic_type], vf ? "VF" : "");
422 		return NULL;
423 	}
424 
425 	kfd = kzalloc(sizeof(*kfd), GFP_KERNEL);
426 	if (!kfd)
427 		return NULL;
428 
429 	kfd->adev = adev;
430 	kfd_device_info_init(kfd, vf, gfx_target_version);
431 	kfd->init_complete = false;
432 	kfd->kfd2kgd = f2g;
433 	atomic_set(&kfd->compute_profile, 0);
434 
435 	mutex_init(&kfd->doorbell_mutex);
436 
437 	ida_init(&kfd->doorbell_ida);
438 
439 	return kfd;
440 }
441 
442 static void kfd_cwsr_init(struct kfd_dev *kfd)
443 {
444 	if (cwsr_enable && kfd->device_info.supports_cwsr) {
445 		if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) {
446 			BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE);
447 			kfd->cwsr_isa = cwsr_trap_gfx8_hex;
448 			kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex);
449 		} else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) {
450 			BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE);
451 			kfd->cwsr_isa = cwsr_trap_arcturus_hex;
452 			kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex);
453 		} else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) {
454 			BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) > PAGE_SIZE);
455 			kfd->cwsr_isa = cwsr_trap_aldebaran_hex;
456 			kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex);
457 		} else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3)) {
458 			BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_4_3_hex) > PAGE_SIZE);
459 			kfd->cwsr_isa = cwsr_trap_gfx9_4_3_hex;
460 			kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_4_3_hex);
461 		} else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) {
462 			BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE);
463 			kfd->cwsr_isa = cwsr_trap_gfx9_hex;
464 			kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex);
465 		} else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) {
466 			BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE);
467 			kfd->cwsr_isa = cwsr_trap_nv1x_hex;
468 			kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex);
469 		} else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) {
470 			BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE);
471 			kfd->cwsr_isa = cwsr_trap_gfx10_hex;
472 			kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex);
473 		} else {
474 			BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE);
475 			kfd->cwsr_isa = cwsr_trap_gfx11_hex;
476 			kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex);
477 		}
478 
479 		kfd->cwsr_enabled = true;
480 	}
481 }
482 
483 static int kfd_gws_init(struct kfd_node *node)
484 {
485 	int ret = 0;
486 	struct kfd_dev *kfd = node->kfd;
487 	uint32_t mes_rev = node->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK;
488 
489 	if (node->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS)
490 		return 0;
491 
492 	if (hws_gws_support || (KFD_IS_SOC15(node) &&
493 		((KFD_GC_VERSION(node) == IP_VERSION(9, 0, 1)
494 			&& kfd->mec2_fw_version >= 0x81b3) ||
495 		(KFD_GC_VERSION(node) <= IP_VERSION(9, 4, 0)
496 			&& kfd->mec2_fw_version >= 0x1b3)  ||
497 		(KFD_GC_VERSION(node) == IP_VERSION(9, 4, 1)
498 			&& kfd->mec2_fw_version >= 0x30)   ||
499 		(KFD_GC_VERSION(node) == IP_VERSION(9, 4, 2)
500 			&& kfd->mec2_fw_version >= 0x28) ||
501 		(KFD_GC_VERSION(node) == IP_VERSION(9, 4, 3)) ||
502 		(KFD_GC_VERSION(node) >= IP_VERSION(10, 3, 0)
503 			&& KFD_GC_VERSION(node) < IP_VERSION(11, 0, 0)
504 			&& kfd->mec2_fw_version >= 0x6b) ||
505 		(KFD_GC_VERSION(node) >= IP_VERSION(11, 0, 0)
506 			&& KFD_GC_VERSION(node) < IP_VERSION(12, 0, 0)
507 			&& mes_rev >= 68))))
508 		ret = amdgpu_amdkfd_alloc_gws(node->adev,
509 				node->adev->gds.gws_size, &node->gws);
510 
511 	return ret;
512 }
513 
514 static void kfd_smi_init(struct kfd_node *dev)
515 {
516 	INIT_LIST_HEAD(&dev->smi_clients);
517 	spin_lock_init(&dev->smi_lock);
518 }
519 
520 static int kfd_init_node(struct kfd_node *node)
521 {
522 	int err = -1;
523 
524 	if (kfd_interrupt_init(node)) {
525 		dev_err(kfd_device, "Error initializing interrupts\n");
526 		goto kfd_interrupt_error;
527 	}
528 
529 	node->dqm = device_queue_manager_init(node);
530 	if (!node->dqm) {
531 		dev_err(kfd_device, "Error initializing queue manager\n");
532 		goto device_queue_manager_error;
533 	}
534 
535 	if (kfd_gws_init(node)) {
536 		dev_err(kfd_device, "Could not allocate %d gws\n",
537 			node->adev->gds.gws_size);
538 		goto gws_error;
539 	}
540 
541 	if (kfd_resume(node))
542 		goto kfd_resume_error;
543 
544 	if (kfd_topology_add_device(node)) {
545 		dev_err(kfd_device, "Error adding device to topology\n");
546 		goto kfd_topology_add_device_error;
547 	}
548 
549 	kfd_smi_init(node);
550 
551 	return 0;
552 
553 kfd_topology_add_device_error:
554 kfd_resume_error:
555 gws_error:
556 	device_queue_manager_uninit(node->dqm);
557 device_queue_manager_error:
558 	kfd_interrupt_exit(node);
559 kfd_interrupt_error:
560 	if (node->gws)
561 		amdgpu_amdkfd_free_gws(node->adev, node->gws);
562 
563 	/* Cleanup the node memory here */
564 	kfree(node);
565 	return err;
566 }
567 
568 static void kfd_cleanup_nodes(struct kfd_dev *kfd, unsigned int num_nodes)
569 {
570 	struct kfd_node *knode;
571 	unsigned int i;
572 
573 	for (i = 0; i < num_nodes; i++) {
574 		knode = kfd->nodes[i];
575 		device_queue_manager_uninit(knode->dqm);
576 		kfd_interrupt_exit(knode);
577 		kfd_topology_remove_device(knode);
578 		if (knode->gws)
579 			amdgpu_amdkfd_free_gws(knode->adev, knode->gws);
580 		kfree(knode);
581 		kfd->nodes[i] = NULL;
582 	}
583 }
584 
585 static void kfd_setup_interrupt_bitmap(struct kfd_node *node,
586 				       unsigned int kfd_node_idx)
587 {
588 	struct amdgpu_device *adev = node->adev;
589 	uint32_t xcc_mask = node->xcc_mask;
590 	uint32_t xcc, mapped_xcc;
591 	/*
592 	 * Interrupt bitmap is setup for processing interrupts from
593 	 * different XCDs and AIDs.
594 	 * Interrupt bitmap is defined as follows:
595 	 * 1. Bits 0-15 - correspond to the NodeId field.
596 	 *    Each bit corresponds to NodeId number. For example, if
597 	 *    a KFD node has interrupt bitmap set to 0x7, then this
598 	 *    KFD node will process interrupts with NodeId = 0, 1 and 2
599 	 *    in the IH cookie.
600 	 * 2. Bits 16-31 - unused.
601 	 *
602 	 * Please note that the kfd_node_idx argument passed to this
603 	 * function is not related to NodeId field received in the
604 	 * IH cookie.
605 	 *
606 	 * In CPX mode, a KFD node will process an interrupt if:
607 	 * - the Node Id matches the corresponding bit set in
608 	 *   Bits 0-15.
609 	 * - AND VMID reported in the interrupt lies within the
610 	 *   VMID range of the node.
611 	 */
612 	for_each_inst(xcc, xcc_mask) {
613 		mapped_xcc = GET_INST(GC, xcc);
614 		node->interrupt_bitmap |= (mapped_xcc % 2 ? 5 : 3) << (4 * (mapped_xcc / 2));
615 	}
616 	dev_info(kfd_device, "Node: %d, interrupt_bitmap: %x\n", kfd_node_idx,
617 							node->interrupt_bitmap);
618 }
619 
620 bool kgd2kfd_device_init(struct kfd_dev *kfd,
621 			 const struct kgd2kfd_shared_resources *gpu_resources)
622 {
623 	unsigned int size, map_process_packet_size, i;
624 	struct kfd_node *node;
625 	uint32_t first_vmid_kfd, last_vmid_kfd, vmid_num_kfd;
626 	unsigned int max_proc_per_quantum;
627 	int partition_mode;
628 	int xcp_idx;
629 
630 	kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev,
631 			KGD_ENGINE_MEC1);
632 	kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev,
633 			KGD_ENGINE_MEC2);
634 	kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev,
635 			KGD_ENGINE_SDMA1);
636 	kfd->shared_resources = *gpu_resources;
637 
638 	kfd->num_nodes = amdgpu_xcp_get_num_xcp(kfd->adev->xcp_mgr);
639 
640 	if (kfd->num_nodes == 0) {
641 		dev_err(kfd_device,
642 			"KFD num nodes cannot be 0, num_xcc_in_node: %d\n",
643 			kfd->adev->gfx.num_xcc_per_xcp);
644 		goto out;
645 	}
646 
647 	/* Allow BIF to recode atomics to PCIe 3.0 AtomicOps.
648 	 * 32 and 64-bit requests are possible and must be
649 	 * supported.
650 	 */
651 	kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev);
652 	if (!kfd->pci_atomic_requested &&
653 	    kfd->device_info.needs_pci_atomics &&
654 	    (!kfd->device_info.no_atomic_fw_version ||
655 	     kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) {
656 		dev_info(kfd_device,
657 			 "skipped device %x:%x, PCI rejects atomics %d<%d\n",
658 			 kfd->adev->pdev->vendor, kfd->adev->pdev->device,
659 			 kfd->mec_fw_version,
660 			 kfd->device_info.no_atomic_fw_version);
661 		return false;
662 	}
663 
664 	first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1;
665 	last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1;
666 	vmid_num_kfd = last_vmid_kfd - first_vmid_kfd + 1;
667 
668 	/* For GFX9.4.3, we need special handling for VMIDs depending on
669 	 * partition mode.
670 	 * In CPX mode, the VMID range needs to be shared between XCDs.
671 	 * Additionally, there are 13 VMIDs (3-15) available for KFD. To
672 	 * divide them equally, we change starting VMID to 4 and not use
673 	 * VMID 3.
674 	 * If the VMID range changes for GFX9.4.3, then this code MUST be
675 	 * revisited.
676 	 */
677 	if (kfd->adev->xcp_mgr) {
678 		partition_mode = amdgpu_xcp_query_partition_mode(kfd->adev->xcp_mgr,
679 								 AMDGPU_XCP_FL_LOCKED);
680 		if (partition_mode == AMDGPU_CPX_PARTITION_MODE &&
681 		    kfd->num_nodes != 1) {
682 			vmid_num_kfd /= 2;
683 			first_vmid_kfd = last_vmid_kfd + 1 - vmid_num_kfd*2;
684 		}
685 	}
686 
687 	/* Verify module parameters regarding mapped process number*/
688 	if (hws_max_conc_proc >= 0)
689 		max_proc_per_quantum = min((u32)hws_max_conc_proc, vmid_num_kfd);
690 	else
691 		max_proc_per_quantum = vmid_num_kfd;
692 
693 	/* calculate max size of mqds needed for queues */
694 	size = max_num_of_queues_per_device *
695 			kfd->device_info.mqd_size_aligned;
696 
697 	/*
698 	 * calculate max size of runlist packet.
699 	 * There can be only 2 packets at once
700 	 */
701 	map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ?
702 				sizeof(struct pm4_mes_map_process_aldebaran) :
703 				sizeof(struct pm4_mes_map_process);
704 	size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size +
705 		max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues)
706 		+ sizeof(struct pm4_mes_runlist)) * 2;
707 
708 	/* Add size of HIQ & DIQ */
709 	size += KFD_KERNEL_QUEUE_SIZE * 2;
710 
711 	/* add another 512KB for all other allocations on gart (HPD, fences) */
712 	size += 512 * 1024;
713 
714 	if (amdgpu_amdkfd_alloc_gtt_mem(
715 			kfd->adev, size, &kfd->gtt_mem,
716 			&kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr,
717 			false)) {
718 		dev_err(kfd_device, "Could not allocate %d bytes\n", size);
719 		goto alloc_gtt_mem_failure;
720 	}
721 
722 	dev_info(kfd_device, "Allocated %d bytes on gart\n", size);
723 
724 	/* Initialize GTT sa with 512 byte chunk size */
725 	if (kfd_gtt_sa_init(kfd, size, 512) != 0) {
726 		dev_err(kfd_device, "Error initializing gtt sub-allocator\n");
727 		goto kfd_gtt_sa_init_error;
728 	}
729 
730 	if (kfd_doorbell_init(kfd)) {
731 		dev_err(kfd_device,
732 			"Error initializing doorbell aperture\n");
733 		goto kfd_doorbell_error;
734 	}
735 
736 	if (amdgpu_use_xgmi_p2p)
737 		kfd->hive_id = kfd->adev->gmc.xgmi.hive_id;
738 
739 	/*
740 	 * For GFX9.4.3, the KFD abstracts all partitions within a socket as
741 	 * xGMI connected in the topology so assign a unique hive id per
742 	 * device based on the pci device location if device is in PCIe mode.
743 	 */
744 	if (!kfd->hive_id && (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3)) && kfd->num_nodes > 1)
745 		kfd->hive_id = pci_dev_id(kfd->adev->pdev);
746 
747 	kfd->noretry = kfd->adev->gmc.noretry;
748 
749 	kfd_cwsr_init(kfd);
750 
751 	dev_info(kfd_device, "Total number of KFD nodes to be created: %d\n",
752 				kfd->num_nodes);
753 
754 	/* Allocate the KFD nodes */
755 	for (i = 0, xcp_idx = 0; i < kfd->num_nodes; i++) {
756 		node = kzalloc(sizeof(struct kfd_node), GFP_KERNEL);
757 		if (!node)
758 			goto node_alloc_error;
759 
760 		node->node_id = i;
761 		node->adev = kfd->adev;
762 		node->kfd = kfd;
763 		node->kfd2kgd = kfd->kfd2kgd;
764 		node->vm_info.vmid_num_kfd = vmid_num_kfd;
765 		node->xcp = amdgpu_get_next_xcp(kfd->adev->xcp_mgr, &xcp_idx);
766 		/* TODO : Check if error handling is needed */
767 		if (node->xcp) {
768 			amdgpu_xcp_get_inst_details(node->xcp, AMDGPU_XCP_GFX,
769 						    &node->xcc_mask);
770 			++xcp_idx;
771 		} else {
772 			node->xcc_mask =
773 				(1U << NUM_XCC(kfd->adev->gfx.xcc_mask)) - 1;
774 		}
775 
776 		if (node->xcp) {
777 			dev_info(kfd_device, "KFD node %d partition %d size %lldM\n",
778 				node->node_id, node->xcp->mem_id,
779 				KFD_XCP_MEMORY_SIZE(node->adev, node->node_id) >> 20);
780 		}
781 
782 		if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) &&
783 		    partition_mode == AMDGPU_CPX_PARTITION_MODE &&
784 		    kfd->num_nodes != 1) {
785 			/* For GFX9.4.3 and CPX mode, first XCD gets VMID range
786 			 * 4-9 and second XCD gets VMID range 10-15.
787 			 */
788 
789 			node->vm_info.first_vmid_kfd = (i%2 == 0) ?
790 						first_vmid_kfd :
791 						first_vmid_kfd+vmid_num_kfd;
792 			node->vm_info.last_vmid_kfd = (i%2 == 0) ?
793 						last_vmid_kfd-vmid_num_kfd :
794 						last_vmid_kfd;
795 			node->compute_vmid_bitmap =
796 				((0x1 << (node->vm_info.last_vmid_kfd + 1)) - 1) -
797 				((0x1 << (node->vm_info.first_vmid_kfd)) - 1);
798 		} else {
799 			node->vm_info.first_vmid_kfd = first_vmid_kfd;
800 			node->vm_info.last_vmid_kfd = last_vmid_kfd;
801 			node->compute_vmid_bitmap =
802 				gpu_resources->compute_vmid_bitmap;
803 		}
804 		node->max_proc_per_quantum = max_proc_per_quantum;
805 		atomic_set(&node->sram_ecc_flag, 0);
806 
807 		amdgpu_amdkfd_get_local_mem_info(kfd->adev,
808 					&node->local_mem_info, node->xcp);
809 
810 		if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3))
811 			kfd_setup_interrupt_bitmap(node, i);
812 
813 		/* Initialize the KFD node */
814 		if (kfd_init_node(node)) {
815 			dev_err(kfd_device, "Error initializing KFD node\n");
816 			goto node_init_error;
817 		}
818 		kfd->nodes[i] = node;
819 	}
820 
821 	svm_range_set_max_pages(kfd->adev);
822 
823 	spin_lock_init(&kfd->watch_points_lock);
824 
825 	kfd->init_complete = true;
826 	dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor,
827 		 kfd->adev->pdev->device);
828 
829 	pr_debug("Starting kfd with the following scheduling policy %d\n",
830 		node->dqm->sched_policy);
831 
832 	goto out;
833 
834 node_init_error:
835 node_alloc_error:
836 	kfd_cleanup_nodes(kfd, i);
837 	kfd_doorbell_fini(kfd);
838 kfd_doorbell_error:
839 	kfd_gtt_sa_fini(kfd);
840 kfd_gtt_sa_init_error:
841 	amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem);
842 alloc_gtt_mem_failure:
843 	dev_err(kfd_device,
844 		"device %x:%x NOT added due to errors\n",
845 		kfd->adev->pdev->vendor, kfd->adev->pdev->device);
846 out:
847 	return kfd->init_complete;
848 }
849 
850 void kgd2kfd_device_exit(struct kfd_dev *kfd)
851 {
852 	if (kfd->init_complete) {
853 		/* Cleanup KFD nodes */
854 		kfd_cleanup_nodes(kfd, kfd->num_nodes);
855 		/* Cleanup common/shared resources */
856 		kfd_doorbell_fini(kfd);
857 		ida_destroy(&kfd->doorbell_ida);
858 		kfd_gtt_sa_fini(kfd);
859 		amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem);
860 	}
861 
862 	kfree(kfd);
863 }
864 
865 int kgd2kfd_pre_reset(struct kfd_dev *kfd)
866 {
867 	struct kfd_node *node;
868 	int i;
869 
870 	if (!kfd->init_complete)
871 		return 0;
872 
873 	for (i = 0; i < kfd->num_nodes; i++) {
874 		node = kfd->nodes[i];
875 		kfd_smi_event_update_gpu_reset(node, false);
876 		node->dqm->ops.pre_reset(node->dqm);
877 	}
878 
879 	kgd2kfd_suspend(kfd, false);
880 
881 	for (i = 0; i < kfd->num_nodes; i++)
882 		kfd_signal_reset_event(kfd->nodes[i]);
883 
884 	return 0;
885 }
886 
887 /*
888  * Fix me. KFD won't be able to resume existing process for now.
889  * We will keep all existing process in a evicted state and
890  * wait the process to be terminated.
891  */
892 
893 int kgd2kfd_post_reset(struct kfd_dev *kfd)
894 {
895 	int ret;
896 	struct kfd_node *node;
897 	int i;
898 
899 	if (!kfd->init_complete)
900 		return 0;
901 
902 	for (i = 0; i < kfd->num_nodes; i++) {
903 		ret = kfd_resume(kfd->nodes[i]);
904 		if (ret)
905 			return ret;
906 	}
907 
908 	mutex_lock(&kfd_processes_mutex);
909 	--kfd_locked;
910 	mutex_unlock(&kfd_processes_mutex);
911 
912 	for (i = 0; i < kfd->num_nodes; i++) {
913 		node = kfd->nodes[i];
914 		atomic_set(&node->sram_ecc_flag, 0);
915 		kfd_smi_event_update_gpu_reset(node, true);
916 	}
917 
918 	return 0;
919 }
920 
921 bool kfd_is_locked(void)
922 {
923 	lockdep_assert_held(&kfd_processes_mutex);
924 	return  (kfd_locked > 0);
925 }
926 
927 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)
928 {
929 	struct kfd_node *node;
930 	int i;
931 
932 	if (!kfd->init_complete)
933 		return;
934 
935 	/* for runtime suspend, skip locking kfd */
936 	if (!run_pm) {
937 		mutex_lock(&kfd_processes_mutex);
938 		/* For first KFD device suspend all the KFD processes */
939 		if (++kfd_locked == 1)
940 			kfd_suspend_all_processes();
941 		mutex_unlock(&kfd_processes_mutex);
942 	}
943 
944 	for (i = 0; i < kfd->num_nodes; i++) {
945 		node = kfd->nodes[i];
946 		node->dqm->ops.stop(node->dqm);
947 	}
948 }
949 
950 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
951 {
952 	int ret, i;
953 
954 	if (!kfd->init_complete)
955 		return 0;
956 
957 	for (i = 0; i < kfd->num_nodes; i++) {
958 		ret = kfd_resume(kfd->nodes[i]);
959 		if (ret)
960 			return ret;
961 	}
962 
963 	/* for runtime resume, skip unlocking kfd */
964 	if (!run_pm) {
965 		mutex_lock(&kfd_processes_mutex);
966 		if (--kfd_locked == 0)
967 			ret = kfd_resume_all_processes();
968 		WARN_ONCE(kfd_locked < 0, "KFD suspend / resume ref. error");
969 		mutex_unlock(&kfd_processes_mutex);
970 	}
971 
972 	return ret;
973 }
974 
975 static int kfd_resume(struct kfd_node *node)
976 {
977 	int err = 0;
978 
979 	err = node->dqm->ops.start(node->dqm);
980 	if (err)
981 		dev_err(kfd_device,
982 			"Error starting queue manager for device %x:%x\n",
983 			node->adev->pdev->vendor, node->adev->pdev->device);
984 
985 	return err;
986 }
987 
988 static inline void kfd_queue_work(struct workqueue_struct *wq,
989 				  struct work_struct *work)
990 {
991 	int cpu, new_cpu;
992 
993 	cpu = new_cpu = smp_processor_id();
994 	do {
995 		new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids;
996 		if (cpu_to_node(new_cpu) == numa_node_id())
997 			break;
998 	} while (cpu != new_cpu);
999 
1000 	queue_work_on(new_cpu, wq, work);
1001 }
1002 
1003 /* This is called directly from KGD at ISR. */
1004 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
1005 {
1006 	uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE], i;
1007 	bool is_patched = false;
1008 	unsigned long flags;
1009 	struct kfd_node *node;
1010 
1011 	if (!kfd->init_complete)
1012 		return;
1013 
1014 	if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) {
1015 		dev_err_once(kfd_device, "Ring entry too small\n");
1016 		return;
1017 	}
1018 
1019 	for (i = 0; i < kfd->num_nodes; i++) {
1020 		node = kfd->nodes[i];
1021 		spin_lock_irqsave(&node->interrupt_lock, flags);
1022 
1023 		if (node->interrupts_active
1024 		    && interrupt_is_wanted(node, ih_ring_entry,
1025 			    	patched_ihre, &is_patched)
1026 		    && enqueue_ih_ring_entry(node,
1027 			    	is_patched ? patched_ihre : ih_ring_entry)) {
1028 			kfd_queue_work(node->ih_wq, &node->interrupt_work);
1029 			spin_unlock_irqrestore(&node->interrupt_lock, flags);
1030 			return;
1031 		}
1032 		spin_unlock_irqrestore(&node->interrupt_lock, flags);
1033 	}
1034 
1035 }
1036 
1037 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger)
1038 {
1039 	struct kfd_process *p;
1040 	int r;
1041 
1042 	/* Because we are called from arbitrary context (workqueue) as opposed
1043 	 * to process context, kfd_process could attempt to exit while we are
1044 	 * running so the lookup function increments the process ref count.
1045 	 */
1046 	p = kfd_lookup_process_by_mm(mm);
1047 	if (!p)
1048 		return -ESRCH;
1049 
1050 	WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid);
1051 	r = kfd_process_evict_queues(p, trigger);
1052 
1053 	kfd_unref_process(p);
1054 	return r;
1055 }
1056 
1057 int kgd2kfd_resume_mm(struct mm_struct *mm)
1058 {
1059 	struct kfd_process *p;
1060 	int r;
1061 
1062 	/* Because we are called from arbitrary context (workqueue) as opposed
1063 	 * to process context, kfd_process could attempt to exit while we are
1064 	 * running so the lookup function increments the process ref count.
1065 	 */
1066 	p = kfd_lookup_process_by_mm(mm);
1067 	if (!p)
1068 		return -ESRCH;
1069 
1070 	r = kfd_process_restore_queues(p);
1071 
1072 	kfd_unref_process(p);
1073 	return r;
1074 }
1075 
1076 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will
1077  *   prepare for safe eviction of KFD BOs that belong to the specified
1078  *   process.
1079  *
1080  * @mm: mm_struct that identifies the specified KFD process
1081  * @fence: eviction fence attached to KFD process BOs
1082  *
1083  */
1084 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
1085 					       struct dma_fence *fence)
1086 {
1087 	struct kfd_process *p;
1088 	unsigned long active_time;
1089 	unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS);
1090 
1091 	if (!fence)
1092 		return -EINVAL;
1093 
1094 	if (dma_fence_is_signaled(fence))
1095 		return 0;
1096 
1097 	p = kfd_lookup_process_by_mm(mm);
1098 	if (!p)
1099 		return -ENODEV;
1100 
1101 	if (fence->seqno == p->last_eviction_seqno)
1102 		goto out;
1103 
1104 	p->last_eviction_seqno = fence->seqno;
1105 
1106 	/* Avoid KFD process starvation. Wait for at least
1107 	 * PROCESS_ACTIVE_TIME_MS before evicting the process again
1108 	 */
1109 	active_time = get_jiffies_64() - p->last_restore_timestamp;
1110 	if (delay_jiffies > active_time)
1111 		delay_jiffies -= active_time;
1112 	else
1113 		delay_jiffies = 0;
1114 
1115 	/* During process initialization eviction_work.dwork is initialized
1116 	 * to kfd_evict_bo_worker
1117 	 */
1118 	WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies",
1119 	     p->lead_thread->pid, delay_jiffies);
1120 	schedule_delayed_work(&p->eviction_work, delay_jiffies);
1121 out:
1122 	kfd_unref_process(p);
1123 	return 0;
1124 }
1125 
1126 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
1127 				unsigned int chunk_size)
1128 {
1129 	if (WARN_ON(buf_size < chunk_size))
1130 		return -EINVAL;
1131 	if (WARN_ON(buf_size == 0))
1132 		return -EINVAL;
1133 	if (WARN_ON(chunk_size == 0))
1134 		return -EINVAL;
1135 
1136 	kfd->gtt_sa_chunk_size = chunk_size;
1137 	kfd->gtt_sa_num_of_chunks = buf_size / chunk_size;
1138 
1139 	kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks,
1140 					   GFP_KERNEL);
1141 	if (!kfd->gtt_sa_bitmap)
1142 		return -ENOMEM;
1143 
1144 	pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n",
1145 			kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap);
1146 
1147 	mutex_init(&kfd->gtt_sa_lock);
1148 
1149 	return 0;
1150 }
1151 
1152 static void kfd_gtt_sa_fini(struct kfd_dev *kfd)
1153 {
1154 	mutex_destroy(&kfd->gtt_sa_lock);
1155 	bitmap_free(kfd->gtt_sa_bitmap);
1156 }
1157 
1158 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr,
1159 						unsigned int bit_num,
1160 						unsigned int chunk_size)
1161 {
1162 	return start_addr + bit_num * chunk_size;
1163 }
1164 
1165 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr,
1166 						unsigned int bit_num,
1167 						unsigned int chunk_size)
1168 {
1169 	return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size);
1170 }
1171 
1172 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size,
1173 			struct kfd_mem_obj **mem_obj)
1174 {
1175 	unsigned int found, start_search, cur_size;
1176 	struct kfd_dev *kfd = node->kfd;
1177 
1178 	if (size == 0)
1179 		return -EINVAL;
1180 
1181 	if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size)
1182 		return -ENOMEM;
1183 
1184 	*mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
1185 	if (!(*mem_obj))
1186 		return -ENOMEM;
1187 
1188 	pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size);
1189 
1190 	start_search = 0;
1191 
1192 	mutex_lock(&kfd->gtt_sa_lock);
1193 
1194 kfd_gtt_restart_search:
1195 	/* Find the first chunk that is free */
1196 	found = find_next_zero_bit(kfd->gtt_sa_bitmap,
1197 					kfd->gtt_sa_num_of_chunks,
1198 					start_search);
1199 
1200 	pr_debug("Found = %d\n", found);
1201 
1202 	/* If there wasn't any free chunk, bail out */
1203 	if (found == kfd->gtt_sa_num_of_chunks)
1204 		goto kfd_gtt_no_free_chunk;
1205 
1206 	/* Update fields of mem_obj */
1207 	(*mem_obj)->range_start = found;
1208 	(*mem_obj)->range_end = found;
1209 	(*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr(
1210 					kfd->gtt_start_gpu_addr,
1211 					found,
1212 					kfd->gtt_sa_chunk_size);
1213 	(*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr(
1214 					kfd->gtt_start_cpu_ptr,
1215 					found,
1216 					kfd->gtt_sa_chunk_size);
1217 
1218 	pr_debug("gpu_addr = %p, cpu_addr = %p\n",
1219 			(uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr);
1220 
1221 	/* If we need only one chunk, mark it as allocated and get out */
1222 	if (size <= kfd->gtt_sa_chunk_size) {
1223 		pr_debug("Single bit\n");
1224 		__set_bit(found, kfd->gtt_sa_bitmap);
1225 		goto kfd_gtt_out;
1226 	}
1227 
1228 	/* Otherwise, try to see if we have enough contiguous chunks */
1229 	cur_size = size - kfd->gtt_sa_chunk_size;
1230 	do {
1231 		(*mem_obj)->range_end =
1232 			find_next_zero_bit(kfd->gtt_sa_bitmap,
1233 					kfd->gtt_sa_num_of_chunks, ++found);
1234 		/*
1235 		 * If next free chunk is not contiguous than we need to
1236 		 * restart our search from the last free chunk we found (which
1237 		 * wasn't contiguous to the previous ones
1238 		 */
1239 		if ((*mem_obj)->range_end != found) {
1240 			start_search = found;
1241 			goto kfd_gtt_restart_search;
1242 		}
1243 
1244 		/*
1245 		 * If we reached end of buffer, bail out with error
1246 		 */
1247 		if (found == kfd->gtt_sa_num_of_chunks)
1248 			goto kfd_gtt_no_free_chunk;
1249 
1250 		/* Check if we don't need another chunk */
1251 		if (cur_size <= kfd->gtt_sa_chunk_size)
1252 			cur_size = 0;
1253 		else
1254 			cur_size -= kfd->gtt_sa_chunk_size;
1255 
1256 	} while (cur_size > 0);
1257 
1258 	pr_debug("range_start = %d, range_end = %d\n",
1259 		(*mem_obj)->range_start, (*mem_obj)->range_end);
1260 
1261 	/* Mark the chunks as allocated */
1262 	bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start,
1263 		   (*mem_obj)->range_end - (*mem_obj)->range_start + 1);
1264 
1265 kfd_gtt_out:
1266 	mutex_unlock(&kfd->gtt_sa_lock);
1267 	return 0;
1268 
1269 kfd_gtt_no_free_chunk:
1270 	pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj);
1271 	mutex_unlock(&kfd->gtt_sa_lock);
1272 	kfree(*mem_obj);
1273 	return -ENOMEM;
1274 }
1275 
1276 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj)
1277 {
1278 	struct kfd_dev *kfd = node->kfd;
1279 
1280 	/* Act like kfree when trying to free a NULL object */
1281 	if (!mem_obj)
1282 		return 0;
1283 
1284 	pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n",
1285 			mem_obj, mem_obj->range_start, mem_obj->range_end);
1286 
1287 	mutex_lock(&kfd->gtt_sa_lock);
1288 
1289 	/* Mark the chunks as free */
1290 	bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start,
1291 		     mem_obj->range_end - mem_obj->range_start + 1);
1292 
1293 	mutex_unlock(&kfd->gtt_sa_lock);
1294 
1295 	kfree(mem_obj);
1296 	return 0;
1297 }
1298 
1299 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
1300 {
1301 	/*
1302 	 * TODO: Currently update SRAM ECC flag for first node.
1303 	 * This needs to be updated later when we can
1304 	 * identify SRAM ECC error on other nodes also.
1305 	 */
1306 	if (kfd)
1307 		atomic_inc(&kfd->nodes[0]->sram_ecc_flag);
1308 }
1309 
1310 void kfd_inc_compute_active(struct kfd_node *node)
1311 {
1312 	if (atomic_inc_return(&node->kfd->compute_profile) == 1)
1313 		amdgpu_amdkfd_set_compute_idle(node->adev, false);
1314 }
1315 
1316 void kfd_dec_compute_active(struct kfd_node *node)
1317 {
1318 	int count = atomic_dec_return(&node->kfd->compute_profile);
1319 
1320 	if (count == 0)
1321 		amdgpu_amdkfd_set_compute_idle(node->adev, true);
1322 	WARN_ONCE(count < 0, "Compute profile ref. count error");
1323 }
1324 
1325 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask)
1326 {
1327 	/*
1328 	 * TODO: For now, raise the throttling event only on first node.
1329 	 * This will need to change after we are able to determine
1330 	 * which node raised the throttling event.
1331 	 */
1332 	if (kfd && kfd->init_complete)
1333 		kfd_smi_event_update_thermal_throttling(kfd->nodes[0],
1334 							throttle_bitmask);
1335 }
1336 
1337 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and
1338  * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA.
1339  * When the device has more than two engines, we reserve two for PCIe to enable
1340  * full-duplex and the rest are used as XGMI.
1341  */
1342 unsigned int kfd_get_num_sdma_engines(struct kfd_node *node)
1343 {
1344 	/* If XGMI is not supported, all SDMA engines are PCIe */
1345 	if (!node->adev->gmc.xgmi.supported)
1346 		return node->adev->sdma.num_instances/(int)node->kfd->num_nodes;
1347 
1348 	return min(node->adev->sdma.num_instances/(int)node->kfd->num_nodes, 2);
1349 }
1350 
1351 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *node)
1352 {
1353 	/* After reserved for PCIe, the rest of engines are XGMI */
1354 	return node->adev->sdma.num_instances/(int)node->kfd->num_nodes -
1355 		kfd_get_num_sdma_engines(node);
1356 }
1357 
1358 int kgd2kfd_check_and_lock_kfd(void)
1359 {
1360 	mutex_lock(&kfd_processes_mutex);
1361 	if (!hash_empty(kfd_processes_table) || kfd_is_locked()) {
1362 		mutex_unlock(&kfd_processes_mutex);
1363 		return -EBUSY;
1364 	}
1365 
1366 	++kfd_locked;
1367 	mutex_unlock(&kfd_processes_mutex);
1368 
1369 	return 0;
1370 }
1371 
1372 void kgd2kfd_unlock_kfd(void)
1373 {
1374 	mutex_lock(&kfd_processes_mutex);
1375 	--kfd_locked;
1376 	mutex_unlock(&kfd_processes_mutex);
1377 }
1378 
1379 #if defined(CONFIG_DEBUG_FS)
1380 
1381 /* This function will send a package to HIQ to hang the HWS
1382  * which will trigger a GPU reset and bring the HWS back to normal state
1383  */
1384 int kfd_debugfs_hang_hws(struct kfd_node *dev)
1385 {
1386 	if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) {
1387 		pr_err("HWS is not enabled");
1388 		return -EINVAL;
1389 	}
1390 
1391 	return dqm_debugfs_hang_hws(dev->dqm);
1392 }
1393 
1394 #endif
1395