1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/bsearch.h> 24 #include <linux/pci.h> 25 #include <linux/slab.h> 26 #include "kfd_priv.h" 27 #include "kfd_device_queue_manager.h" 28 #include "kfd_pm4_headers_vi.h" 29 #include "kfd_pm4_headers_aldebaran.h" 30 #include "cwsr_trap_handler.h" 31 #include "kfd_iommu.h" 32 #include "amdgpu_amdkfd.h" 33 #include "kfd_smi_events.h" 34 #include "kfd_migrate.h" 35 36 #define MQD_SIZE_ALIGNED 768 37 38 /* 39 * kfd_locked is used to lock the kfd driver during suspend or reset 40 * once locked, kfd driver will stop any further GPU execution. 41 * create process (open) will return -EAGAIN. 42 */ 43 static atomic_t kfd_locked = ATOMIC_INIT(0); 44 45 #ifdef CONFIG_DRM_AMDGPU_CIK 46 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 47 #endif 48 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 49 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 50 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 51 extern const struct kfd2kgd_calls aldebaran_kfd2kgd; 52 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 53 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 54 55 static const struct kfd2kgd_calls *kfd2kgd_funcs[] = { 56 #ifdef KFD_SUPPORT_IOMMU_V2 57 #ifdef CONFIG_DRM_AMDGPU_CIK 58 [CHIP_KAVERI] = &gfx_v7_kfd2kgd, 59 #endif 60 [CHIP_CARRIZO] = &gfx_v8_kfd2kgd, 61 [CHIP_RAVEN] = &gfx_v9_kfd2kgd, 62 #endif 63 #ifdef CONFIG_DRM_AMDGPU_CIK 64 [CHIP_HAWAII] = &gfx_v7_kfd2kgd, 65 #endif 66 [CHIP_TONGA] = &gfx_v8_kfd2kgd, 67 [CHIP_FIJI] = &gfx_v8_kfd2kgd, 68 [CHIP_POLARIS10] = &gfx_v8_kfd2kgd, 69 [CHIP_POLARIS11] = &gfx_v8_kfd2kgd, 70 [CHIP_POLARIS12] = &gfx_v8_kfd2kgd, 71 [CHIP_VEGAM] = &gfx_v8_kfd2kgd, 72 [CHIP_VEGA10] = &gfx_v9_kfd2kgd, 73 [CHIP_VEGA12] = &gfx_v9_kfd2kgd, 74 [CHIP_VEGA20] = &gfx_v9_kfd2kgd, 75 [CHIP_RENOIR] = &gfx_v9_kfd2kgd, 76 [CHIP_ARCTURUS] = &arcturus_kfd2kgd, 77 [CHIP_ALDEBARAN] = &aldebaran_kfd2kgd, 78 [CHIP_NAVI10] = &gfx_v10_kfd2kgd, 79 [CHIP_NAVI12] = &gfx_v10_kfd2kgd, 80 [CHIP_NAVI14] = &gfx_v10_kfd2kgd, 81 [CHIP_SIENNA_CICHLID] = &gfx_v10_3_kfd2kgd, 82 [CHIP_NAVY_FLOUNDER] = &gfx_v10_3_kfd2kgd, 83 [CHIP_VANGOGH] = &gfx_v10_3_kfd2kgd, 84 [CHIP_DIMGREY_CAVEFISH] = &gfx_v10_3_kfd2kgd, 85 [CHIP_BEIGE_GOBY] = &gfx_v10_3_kfd2kgd, 86 [CHIP_YELLOW_CARP] = &gfx_v10_3_kfd2kgd, 87 [CHIP_CYAN_SKILLFISH] = &gfx_v10_kfd2kgd, 88 }; 89 90 #ifdef KFD_SUPPORT_IOMMU_V2 91 static const struct kfd_device_info kaveri_device_info = { 92 .asic_family = CHIP_KAVERI, 93 .asic_name = "kaveri", 94 .max_pasid_bits = 16, 95 /* max num of queues for KV.TODO should be a dynamic value */ 96 .max_no_of_hqd = 24, 97 .doorbell_size = 4, 98 .ih_ring_entry_size = 4 * sizeof(uint32_t), 99 .event_interrupt_class = &event_interrupt_class_cik, 100 .num_of_watch_points = 4, 101 .mqd_size_aligned = MQD_SIZE_ALIGNED, 102 .supports_cwsr = false, 103 .needs_iommu_device = true, 104 .needs_pci_atomics = false, 105 .num_sdma_engines = 2, 106 .num_xgmi_sdma_engines = 0, 107 .num_sdma_queues_per_engine = 2, 108 }; 109 110 static const struct kfd_device_info carrizo_device_info = { 111 .asic_family = CHIP_CARRIZO, 112 .asic_name = "carrizo", 113 .max_pasid_bits = 16, 114 /* max num of queues for CZ.TODO should be a dynamic value */ 115 .max_no_of_hqd = 24, 116 .doorbell_size = 4, 117 .ih_ring_entry_size = 4 * sizeof(uint32_t), 118 .event_interrupt_class = &event_interrupt_class_cik, 119 .num_of_watch_points = 4, 120 .mqd_size_aligned = MQD_SIZE_ALIGNED, 121 .supports_cwsr = true, 122 .needs_iommu_device = true, 123 .needs_pci_atomics = false, 124 .num_sdma_engines = 2, 125 .num_xgmi_sdma_engines = 0, 126 .num_sdma_queues_per_engine = 2, 127 }; 128 #endif 129 130 static const struct kfd_device_info raven_device_info = { 131 .asic_family = CHIP_RAVEN, 132 .asic_name = "raven", 133 .max_pasid_bits = 16, 134 .max_no_of_hqd = 24, 135 .doorbell_size = 8, 136 .ih_ring_entry_size = 8 * sizeof(uint32_t), 137 .event_interrupt_class = &event_interrupt_class_v9, 138 .num_of_watch_points = 4, 139 .mqd_size_aligned = MQD_SIZE_ALIGNED, 140 .supports_cwsr = true, 141 .needs_iommu_device = true, 142 .needs_pci_atomics = true, 143 .num_sdma_engines = 1, 144 .num_xgmi_sdma_engines = 0, 145 .num_sdma_queues_per_engine = 2, 146 }; 147 148 static const struct kfd_device_info hawaii_device_info = { 149 .asic_family = CHIP_HAWAII, 150 .asic_name = "hawaii", 151 .max_pasid_bits = 16, 152 /* max num of queues for KV.TODO should be a dynamic value */ 153 .max_no_of_hqd = 24, 154 .doorbell_size = 4, 155 .ih_ring_entry_size = 4 * sizeof(uint32_t), 156 .event_interrupt_class = &event_interrupt_class_cik, 157 .num_of_watch_points = 4, 158 .mqd_size_aligned = MQD_SIZE_ALIGNED, 159 .supports_cwsr = false, 160 .needs_iommu_device = false, 161 .needs_pci_atomics = false, 162 .num_sdma_engines = 2, 163 .num_xgmi_sdma_engines = 0, 164 .num_sdma_queues_per_engine = 2, 165 }; 166 167 static const struct kfd_device_info tonga_device_info = { 168 .asic_family = CHIP_TONGA, 169 .asic_name = "tonga", 170 .max_pasid_bits = 16, 171 .max_no_of_hqd = 24, 172 .doorbell_size = 4, 173 .ih_ring_entry_size = 4 * sizeof(uint32_t), 174 .event_interrupt_class = &event_interrupt_class_cik, 175 .num_of_watch_points = 4, 176 .mqd_size_aligned = MQD_SIZE_ALIGNED, 177 .supports_cwsr = false, 178 .needs_iommu_device = false, 179 .needs_pci_atomics = true, 180 .num_sdma_engines = 2, 181 .num_xgmi_sdma_engines = 0, 182 .num_sdma_queues_per_engine = 2, 183 }; 184 185 static const struct kfd_device_info fiji_device_info = { 186 .asic_family = CHIP_FIJI, 187 .asic_name = "fiji", 188 .max_pasid_bits = 16, 189 .max_no_of_hqd = 24, 190 .doorbell_size = 4, 191 .ih_ring_entry_size = 4 * sizeof(uint32_t), 192 .event_interrupt_class = &event_interrupt_class_cik, 193 .num_of_watch_points = 4, 194 .mqd_size_aligned = MQD_SIZE_ALIGNED, 195 .supports_cwsr = true, 196 .needs_iommu_device = false, 197 .needs_pci_atomics = true, 198 .num_sdma_engines = 2, 199 .num_xgmi_sdma_engines = 0, 200 .num_sdma_queues_per_engine = 2, 201 }; 202 203 static const struct kfd_device_info fiji_vf_device_info = { 204 .asic_family = CHIP_FIJI, 205 .asic_name = "fiji", 206 .max_pasid_bits = 16, 207 .max_no_of_hqd = 24, 208 .doorbell_size = 4, 209 .ih_ring_entry_size = 4 * sizeof(uint32_t), 210 .event_interrupt_class = &event_interrupt_class_cik, 211 .num_of_watch_points = 4, 212 .mqd_size_aligned = MQD_SIZE_ALIGNED, 213 .supports_cwsr = true, 214 .needs_iommu_device = false, 215 .needs_pci_atomics = false, 216 .num_sdma_engines = 2, 217 .num_xgmi_sdma_engines = 0, 218 .num_sdma_queues_per_engine = 2, 219 }; 220 221 222 static const struct kfd_device_info polaris10_device_info = { 223 .asic_family = CHIP_POLARIS10, 224 .asic_name = "polaris10", 225 .max_pasid_bits = 16, 226 .max_no_of_hqd = 24, 227 .doorbell_size = 4, 228 .ih_ring_entry_size = 4 * sizeof(uint32_t), 229 .event_interrupt_class = &event_interrupt_class_cik, 230 .num_of_watch_points = 4, 231 .mqd_size_aligned = MQD_SIZE_ALIGNED, 232 .supports_cwsr = true, 233 .needs_iommu_device = false, 234 .needs_pci_atomics = true, 235 .num_sdma_engines = 2, 236 .num_xgmi_sdma_engines = 0, 237 .num_sdma_queues_per_engine = 2, 238 }; 239 240 static const struct kfd_device_info polaris10_vf_device_info = { 241 .asic_family = CHIP_POLARIS10, 242 .asic_name = "polaris10", 243 .max_pasid_bits = 16, 244 .max_no_of_hqd = 24, 245 .doorbell_size = 4, 246 .ih_ring_entry_size = 4 * sizeof(uint32_t), 247 .event_interrupt_class = &event_interrupt_class_cik, 248 .num_of_watch_points = 4, 249 .mqd_size_aligned = MQD_SIZE_ALIGNED, 250 .supports_cwsr = true, 251 .needs_iommu_device = false, 252 .needs_pci_atomics = false, 253 .num_sdma_engines = 2, 254 .num_xgmi_sdma_engines = 0, 255 .num_sdma_queues_per_engine = 2, 256 }; 257 258 static const struct kfd_device_info polaris11_device_info = { 259 .asic_family = CHIP_POLARIS11, 260 .asic_name = "polaris11", 261 .max_pasid_bits = 16, 262 .max_no_of_hqd = 24, 263 .doorbell_size = 4, 264 .ih_ring_entry_size = 4 * sizeof(uint32_t), 265 .event_interrupt_class = &event_interrupt_class_cik, 266 .num_of_watch_points = 4, 267 .mqd_size_aligned = MQD_SIZE_ALIGNED, 268 .supports_cwsr = true, 269 .needs_iommu_device = false, 270 .needs_pci_atomics = true, 271 .num_sdma_engines = 2, 272 .num_xgmi_sdma_engines = 0, 273 .num_sdma_queues_per_engine = 2, 274 }; 275 276 static const struct kfd_device_info polaris12_device_info = { 277 .asic_family = CHIP_POLARIS12, 278 .asic_name = "polaris12", 279 .max_pasid_bits = 16, 280 .max_no_of_hqd = 24, 281 .doorbell_size = 4, 282 .ih_ring_entry_size = 4 * sizeof(uint32_t), 283 .event_interrupt_class = &event_interrupt_class_cik, 284 .num_of_watch_points = 4, 285 .mqd_size_aligned = MQD_SIZE_ALIGNED, 286 .supports_cwsr = true, 287 .needs_iommu_device = false, 288 .needs_pci_atomics = true, 289 .num_sdma_engines = 2, 290 .num_xgmi_sdma_engines = 0, 291 .num_sdma_queues_per_engine = 2, 292 }; 293 294 static const struct kfd_device_info vegam_device_info = { 295 .asic_family = CHIP_VEGAM, 296 .asic_name = "vegam", 297 .max_pasid_bits = 16, 298 .max_no_of_hqd = 24, 299 .doorbell_size = 4, 300 .ih_ring_entry_size = 4 * sizeof(uint32_t), 301 .event_interrupt_class = &event_interrupt_class_cik, 302 .num_of_watch_points = 4, 303 .mqd_size_aligned = MQD_SIZE_ALIGNED, 304 .supports_cwsr = true, 305 .needs_iommu_device = false, 306 .needs_pci_atomics = true, 307 .num_sdma_engines = 2, 308 .num_xgmi_sdma_engines = 0, 309 .num_sdma_queues_per_engine = 2, 310 }; 311 312 static const struct kfd_device_info vega10_device_info = { 313 .asic_family = CHIP_VEGA10, 314 .asic_name = "vega10", 315 .max_pasid_bits = 16, 316 .max_no_of_hqd = 24, 317 .doorbell_size = 8, 318 .ih_ring_entry_size = 8 * sizeof(uint32_t), 319 .event_interrupt_class = &event_interrupt_class_v9, 320 .num_of_watch_points = 4, 321 .mqd_size_aligned = MQD_SIZE_ALIGNED, 322 .supports_cwsr = true, 323 .needs_iommu_device = false, 324 .needs_pci_atomics = false, 325 .num_sdma_engines = 2, 326 .num_xgmi_sdma_engines = 0, 327 .num_sdma_queues_per_engine = 2, 328 }; 329 330 static const struct kfd_device_info vega10_vf_device_info = { 331 .asic_family = CHIP_VEGA10, 332 .asic_name = "vega10", 333 .max_pasid_bits = 16, 334 .max_no_of_hqd = 24, 335 .doorbell_size = 8, 336 .ih_ring_entry_size = 8 * sizeof(uint32_t), 337 .event_interrupt_class = &event_interrupt_class_v9, 338 .num_of_watch_points = 4, 339 .mqd_size_aligned = MQD_SIZE_ALIGNED, 340 .supports_cwsr = true, 341 .needs_iommu_device = false, 342 .needs_pci_atomics = false, 343 .num_sdma_engines = 2, 344 .num_xgmi_sdma_engines = 0, 345 .num_sdma_queues_per_engine = 2, 346 }; 347 348 static const struct kfd_device_info vega12_device_info = { 349 .asic_family = CHIP_VEGA12, 350 .asic_name = "vega12", 351 .max_pasid_bits = 16, 352 .max_no_of_hqd = 24, 353 .doorbell_size = 8, 354 .ih_ring_entry_size = 8 * sizeof(uint32_t), 355 .event_interrupt_class = &event_interrupt_class_v9, 356 .num_of_watch_points = 4, 357 .mqd_size_aligned = MQD_SIZE_ALIGNED, 358 .supports_cwsr = true, 359 .needs_iommu_device = false, 360 .needs_pci_atomics = false, 361 .num_sdma_engines = 2, 362 .num_xgmi_sdma_engines = 0, 363 .num_sdma_queues_per_engine = 2, 364 }; 365 366 static const struct kfd_device_info vega20_device_info = { 367 .asic_family = CHIP_VEGA20, 368 .asic_name = "vega20", 369 .max_pasid_bits = 16, 370 .max_no_of_hqd = 24, 371 .doorbell_size = 8, 372 .ih_ring_entry_size = 8 * sizeof(uint32_t), 373 .event_interrupt_class = &event_interrupt_class_v9, 374 .num_of_watch_points = 4, 375 .mqd_size_aligned = MQD_SIZE_ALIGNED, 376 .supports_cwsr = true, 377 .needs_iommu_device = false, 378 .needs_pci_atomics = false, 379 .num_sdma_engines = 2, 380 .num_xgmi_sdma_engines = 0, 381 .num_sdma_queues_per_engine = 8, 382 }; 383 384 static const struct kfd_device_info arcturus_device_info = { 385 .asic_family = CHIP_ARCTURUS, 386 .asic_name = "arcturus", 387 .max_pasid_bits = 16, 388 .max_no_of_hqd = 24, 389 .doorbell_size = 8, 390 .ih_ring_entry_size = 8 * sizeof(uint32_t), 391 .event_interrupt_class = &event_interrupt_class_v9, 392 .num_of_watch_points = 4, 393 .mqd_size_aligned = MQD_SIZE_ALIGNED, 394 .supports_cwsr = true, 395 .needs_iommu_device = false, 396 .needs_pci_atomics = false, 397 .num_sdma_engines = 2, 398 .num_xgmi_sdma_engines = 6, 399 .num_sdma_queues_per_engine = 8, 400 }; 401 402 static const struct kfd_device_info aldebaran_device_info = { 403 .asic_family = CHIP_ALDEBARAN, 404 .asic_name = "aldebaran", 405 .max_pasid_bits = 16, 406 .max_no_of_hqd = 24, 407 .doorbell_size = 8, 408 .ih_ring_entry_size = 8 * sizeof(uint32_t), 409 .event_interrupt_class = &event_interrupt_class_v9, 410 .num_of_watch_points = 4, 411 .mqd_size_aligned = MQD_SIZE_ALIGNED, 412 .supports_cwsr = true, 413 .needs_iommu_device = false, 414 .needs_pci_atomics = false, 415 .num_sdma_engines = 2, 416 .num_xgmi_sdma_engines = 3, 417 .num_sdma_queues_per_engine = 8, 418 }; 419 420 static const struct kfd_device_info renoir_device_info = { 421 .asic_family = CHIP_RENOIR, 422 .asic_name = "renoir", 423 .max_pasid_bits = 16, 424 .max_no_of_hqd = 24, 425 .doorbell_size = 8, 426 .ih_ring_entry_size = 8 * sizeof(uint32_t), 427 .event_interrupt_class = &event_interrupt_class_v9, 428 .num_of_watch_points = 4, 429 .mqd_size_aligned = MQD_SIZE_ALIGNED, 430 .supports_cwsr = true, 431 .needs_iommu_device = false, 432 .needs_pci_atomics = false, 433 .num_sdma_engines = 1, 434 .num_xgmi_sdma_engines = 0, 435 .num_sdma_queues_per_engine = 2, 436 }; 437 438 static const struct kfd_device_info navi10_device_info = { 439 .asic_family = CHIP_NAVI10, 440 .asic_name = "navi10", 441 .max_pasid_bits = 16, 442 .max_no_of_hqd = 24, 443 .doorbell_size = 8, 444 .ih_ring_entry_size = 8 * sizeof(uint32_t), 445 .event_interrupt_class = &event_interrupt_class_v9, 446 .num_of_watch_points = 4, 447 .mqd_size_aligned = MQD_SIZE_ALIGNED, 448 .needs_iommu_device = false, 449 .supports_cwsr = true, 450 .needs_pci_atomics = true, 451 .num_sdma_engines = 2, 452 .num_xgmi_sdma_engines = 0, 453 .num_sdma_queues_per_engine = 8, 454 }; 455 456 static const struct kfd_device_info navi12_device_info = { 457 .asic_family = CHIP_NAVI12, 458 .asic_name = "navi12", 459 .max_pasid_bits = 16, 460 .max_no_of_hqd = 24, 461 .doorbell_size = 8, 462 .ih_ring_entry_size = 8 * sizeof(uint32_t), 463 .event_interrupt_class = &event_interrupt_class_v9, 464 .num_of_watch_points = 4, 465 .mqd_size_aligned = MQD_SIZE_ALIGNED, 466 .needs_iommu_device = false, 467 .supports_cwsr = true, 468 .needs_pci_atomics = true, 469 .num_sdma_engines = 2, 470 .num_xgmi_sdma_engines = 0, 471 .num_sdma_queues_per_engine = 8, 472 }; 473 474 static const struct kfd_device_info navi14_device_info = { 475 .asic_family = CHIP_NAVI14, 476 .asic_name = "navi14", 477 .max_pasid_bits = 16, 478 .max_no_of_hqd = 24, 479 .doorbell_size = 8, 480 .ih_ring_entry_size = 8 * sizeof(uint32_t), 481 .event_interrupt_class = &event_interrupt_class_v9, 482 .num_of_watch_points = 4, 483 .mqd_size_aligned = MQD_SIZE_ALIGNED, 484 .needs_iommu_device = false, 485 .supports_cwsr = true, 486 .needs_pci_atomics = true, 487 .num_sdma_engines = 2, 488 .num_xgmi_sdma_engines = 0, 489 .num_sdma_queues_per_engine = 8, 490 }; 491 492 static const struct kfd_device_info sienna_cichlid_device_info = { 493 .asic_family = CHIP_SIENNA_CICHLID, 494 .asic_name = "sienna_cichlid", 495 .max_pasid_bits = 16, 496 .max_no_of_hqd = 24, 497 .doorbell_size = 8, 498 .ih_ring_entry_size = 8 * sizeof(uint32_t), 499 .event_interrupt_class = &event_interrupt_class_v9, 500 .num_of_watch_points = 4, 501 .mqd_size_aligned = MQD_SIZE_ALIGNED, 502 .needs_iommu_device = false, 503 .supports_cwsr = true, 504 .needs_pci_atomics = true, 505 .num_sdma_engines = 4, 506 .num_xgmi_sdma_engines = 0, 507 .num_sdma_queues_per_engine = 8, 508 }; 509 510 static const struct kfd_device_info navy_flounder_device_info = { 511 .asic_family = CHIP_NAVY_FLOUNDER, 512 .asic_name = "navy_flounder", 513 .max_pasid_bits = 16, 514 .max_no_of_hqd = 24, 515 .doorbell_size = 8, 516 .ih_ring_entry_size = 8 * sizeof(uint32_t), 517 .event_interrupt_class = &event_interrupt_class_v9, 518 .num_of_watch_points = 4, 519 .mqd_size_aligned = MQD_SIZE_ALIGNED, 520 .needs_iommu_device = false, 521 .supports_cwsr = true, 522 .needs_pci_atomics = true, 523 .num_sdma_engines = 2, 524 .num_xgmi_sdma_engines = 0, 525 .num_sdma_queues_per_engine = 8, 526 }; 527 528 static const struct kfd_device_info vangogh_device_info = { 529 .asic_family = CHIP_VANGOGH, 530 .asic_name = "vangogh", 531 .max_pasid_bits = 16, 532 .max_no_of_hqd = 24, 533 .doorbell_size = 8, 534 .ih_ring_entry_size = 8 * sizeof(uint32_t), 535 .event_interrupt_class = &event_interrupt_class_v9, 536 .num_of_watch_points = 4, 537 .mqd_size_aligned = MQD_SIZE_ALIGNED, 538 .needs_iommu_device = false, 539 .supports_cwsr = true, 540 .needs_pci_atomics = false, 541 .num_sdma_engines = 1, 542 .num_xgmi_sdma_engines = 0, 543 .num_sdma_queues_per_engine = 2, 544 }; 545 546 static const struct kfd_device_info dimgrey_cavefish_device_info = { 547 .asic_family = CHIP_DIMGREY_CAVEFISH, 548 .asic_name = "dimgrey_cavefish", 549 .max_pasid_bits = 16, 550 .max_no_of_hqd = 24, 551 .doorbell_size = 8, 552 .ih_ring_entry_size = 8 * sizeof(uint32_t), 553 .event_interrupt_class = &event_interrupt_class_v9, 554 .num_of_watch_points = 4, 555 .mqd_size_aligned = MQD_SIZE_ALIGNED, 556 .needs_iommu_device = false, 557 .supports_cwsr = true, 558 .needs_pci_atomics = true, 559 .num_sdma_engines = 2, 560 .num_xgmi_sdma_engines = 0, 561 .num_sdma_queues_per_engine = 8, 562 }; 563 564 static const struct kfd_device_info beige_goby_device_info = { 565 .asic_family = CHIP_BEIGE_GOBY, 566 .asic_name = "beige_goby", 567 .max_pasid_bits = 16, 568 .max_no_of_hqd = 24, 569 .doorbell_size = 8, 570 .ih_ring_entry_size = 8 * sizeof(uint32_t), 571 .event_interrupt_class = &event_interrupt_class_v9, 572 .num_of_watch_points = 4, 573 .mqd_size_aligned = MQD_SIZE_ALIGNED, 574 .needs_iommu_device = false, 575 .supports_cwsr = true, 576 .needs_pci_atomics = true, 577 .num_sdma_engines = 1, 578 .num_xgmi_sdma_engines = 0, 579 .num_sdma_queues_per_engine = 8, 580 }; 581 582 static const struct kfd_device_info yellow_carp_device_info = { 583 .asic_family = CHIP_YELLOW_CARP, 584 .asic_name = "yellow_carp", 585 .max_pasid_bits = 16, 586 .max_no_of_hqd = 24, 587 .doorbell_size = 8, 588 .ih_ring_entry_size = 8 * sizeof(uint32_t), 589 .event_interrupt_class = &event_interrupt_class_v9, 590 .num_of_watch_points = 4, 591 .mqd_size_aligned = MQD_SIZE_ALIGNED, 592 .needs_iommu_device = false, 593 .supports_cwsr = true, 594 .needs_pci_atomics = false, 595 .num_sdma_engines = 1, 596 .num_xgmi_sdma_engines = 0, 597 .num_sdma_queues_per_engine = 2, 598 }; 599 600 static const struct kfd_device_info cyan_skillfish_device_info = { 601 .asic_family = CHIP_CYAN_SKILLFISH, 602 .asic_name = "cyan_skillfish", 603 .max_pasid_bits = 16, 604 .max_no_of_hqd = 24, 605 .doorbell_size = 8, 606 .ih_ring_entry_size = 8 * sizeof(uint32_t), 607 .event_interrupt_class = &event_interrupt_class_v9, 608 .num_of_watch_points = 4, 609 .mqd_size_aligned = MQD_SIZE_ALIGNED, 610 .needs_iommu_device = false, 611 .supports_cwsr = true, 612 .needs_pci_atomics = true, 613 .num_sdma_engines = 2, 614 .num_xgmi_sdma_engines = 0, 615 .num_sdma_queues_per_engine = 8, 616 }; 617 618 /* For each entry, [0] is regular and [1] is virtualisation device. */ 619 static const struct kfd_device_info *kfd_supported_devices[][2] = { 620 #ifdef KFD_SUPPORT_IOMMU_V2 621 [CHIP_KAVERI] = {&kaveri_device_info, NULL}, 622 [CHIP_CARRIZO] = {&carrizo_device_info, NULL}, 623 #endif 624 [CHIP_RAVEN] = {&raven_device_info, NULL}, 625 [CHIP_HAWAII] = {&hawaii_device_info, NULL}, 626 [CHIP_TONGA] = {&tonga_device_info, NULL}, 627 [CHIP_FIJI] = {&fiji_device_info, &fiji_vf_device_info}, 628 [CHIP_POLARIS10] = {&polaris10_device_info, &polaris10_vf_device_info}, 629 [CHIP_POLARIS11] = {&polaris11_device_info, NULL}, 630 [CHIP_POLARIS12] = {&polaris12_device_info, NULL}, 631 [CHIP_VEGAM] = {&vegam_device_info, NULL}, 632 [CHIP_VEGA10] = {&vega10_device_info, &vega10_vf_device_info}, 633 [CHIP_VEGA12] = {&vega12_device_info, NULL}, 634 [CHIP_VEGA20] = {&vega20_device_info, NULL}, 635 [CHIP_RENOIR] = {&renoir_device_info, NULL}, 636 [CHIP_ARCTURUS] = {&arcturus_device_info, &arcturus_device_info}, 637 [CHIP_ALDEBARAN] = {&aldebaran_device_info, &aldebaran_device_info}, 638 [CHIP_NAVI10] = {&navi10_device_info, NULL}, 639 [CHIP_NAVI12] = {&navi12_device_info, &navi12_device_info}, 640 [CHIP_NAVI14] = {&navi14_device_info, NULL}, 641 [CHIP_SIENNA_CICHLID] = {&sienna_cichlid_device_info, &sienna_cichlid_device_info}, 642 [CHIP_NAVY_FLOUNDER] = {&navy_flounder_device_info, &navy_flounder_device_info}, 643 [CHIP_VANGOGH] = {&vangogh_device_info, NULL}, 644 [CHIP_DIMGREY_CAVEFISH] = {&dimgrey_cavefish_device_info, &dimgrey_cavefish_device_info}, 645 [CHIP_BEIGE_GOBY] = {&beige_goby_device_info, &beige_goby_device_info}, 646 [CHIP_YELLOW_CARP] = {&yellow_carp_device_info, NULL}, 647 [CHIP_CYAN_SKILLFISH] = {&cyan_skillfish_device_info, NULL}, 648 }; 649 650 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 651 unsigned int chunk_size); 652 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 653 654 static int kfd_resume(struct kfd_dev *kfd); 655 656 struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, 657 struct pci_dev *pdev, unsigned int asic_type, bool vf) 658 { 659 struct kfd_dev *kfd; 660 const struct kfd_device_info *device_info; 661 const struct kfd2kgd_calls *f2g; 662 663 if (asic_type >= sizeof(kfd_supported_devices) / (sizeof(void *) * 2) 664 || asic_type >= sizeof(kfd2kgd_funcs) / sizeof(void *)) { 665 dev_err(kfd_device, "asic_type %d out of range\n", asic_type); 666 return NULL; /* asic_type out of range */ 667 } 668 669 device_info = kfd_supported_devices[asic_type][vf]; 670 f2g = kfd2kgd_funcs[asic_type]; 671 672 if (!device_info || !f2g) { 673 dev_err(kfd_device, "%s %s not supported in kfd\n", 674 amdgpu_asic_name[asic_type], vf ? "VF" : ""); 675 return NULL; 676 } 677 678 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 679 if (!kfd) 680 return NULL; 681 682 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 683 * 32 and 64-bit requests are possible and must be 684 * supported. 685 */ 686 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kgd); 687 if (device_info->needs_pci_atomics && 688 !kfd->pci_atomic_requested) { 689 dev_info(kfd_device, 690 "skipped device %x:%x, PCI rejects atomics\n", 691 pdev->vendor, pdev->device); 692 kfree(kfd); 693 return NULL; 694 } 695 696 kfd->kgd = kgd; 697 kfd->device_info = device_info; 698 kfd->pdev = pdev; 699 kfd->init_complete = false; 700 kfd->kfd2kgd = f2g; 701 atomic_set(&kfd->compute_profile, 0); 702 703 mutex_init(&kfd->doorbell_mutex); 704 memset(&kfd->doorbell_available_index, 0, 705 sizeof(kfd->doorbell_available_index)); 706 707 atomic_set(&kfd->sram_ecc_flag, 0); 708 709 ida_init(&kfd->doorbell_ida); 710 711 return kfd; 712 } 713 714 static void kfd_cwsr_init(struct kfd_dev *kfd) 715 { 716 if (cwsr_enable && kfd->device_info->supports_cwsr) { 717 if (kfd->device_info->asic_family < CHIP_VEGA10) { 718 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE); 719 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 720 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 721 } else if (kfd->device_info->asic_family == CHIP_ARCTURUS) { 722 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE); 723 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 724 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 725 } else if (kfd->device_info->asic_family == CHIP_ALDEBARAN) { 726 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) > PAGE_SIZE); 727 kfd->cwsr_isa = cwsr_trap_aldebaran_hex; 728 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); 729 } else if (kfd->device_info->asic_family < CHIP_NAVI10) { 730 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE); 731 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 732 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 733 } else if (kfd->device_info->asic_family < CHIP_SIENNA_CICHLID) { 734 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE); 735 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 736 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 737 } else { 738 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE); 739 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 740 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 741 } 742 743 kfd->cwsr_enabled = true; 744 } 745 } 746 747 static int kfd_gws_init(struct kfd_dev *kfd) 748 { 749 int ret = 0; 750 751 if (kfd->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 752 return 0; 753 754 if (hws_gws_support 755 || (kfd->device_info->asic_family == CHIP_VEGA10 756 && kfd->mec2_fw_version >= 0x81b3) 757 || (kfd->device_info->asic_family >= CHIP_VEGA12 758 && kfd->device_info->asic_family <= CHIP_RAVEN 759 && kfd->mec2_fw_version >= 0x1b3) 760 || (kfd->device_info->asic_family == CHIP_ARCTURUS 761 && kfd->mec2_fw_version >= 0x30) 762 || (kfd->device_info->asic_family == CHIP_ALDEBARAN 763 && kfd->mec2_fw_version >= 0x28)) 764 ret = amdgpu_amdkfd_alloc_gws(kfd->kgd, 765 amdgpu_amdkfd_get_num_gws(kfd->kgd), &kfd->gws); 766 767 return ret; 768 } 769 770 static void kfd_smi_init(struct kfd_dev *dev) { 771 INIT_LIST_HEAD(&dev->smi_clients); 772 spin_lock_init(&dev->smi_lock); 773 } 774 775 bool kgd2kfd_device_init(struct kfd_dev *kfd, 776 struct drm_device *ddev, 777 const struct kgd2kfd_shared_resources *gpu_resources) 778 { 779 unsigned int size, map_process_packet_size; 780 781 kfd->ddev = ddev; 782 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd, 783 KGD_ENGINE_MEC1); 784 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd, 785 KGD_ENGINE_MEC2); 786 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd, 787 KGD_ENGINE_SDMA1); 788 kfd->shared_resources = *gpu_resources; 789 790 kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 791 kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 792 kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd 793 - kfd->vm_info.first_vmid_kfd + 1; 794 795 /* Verify module parameters regarding mapped process number*/ 796 if ((hws_max_conc_proc < 0) 797 || (hws_max_conc_proc > kfd->vm_info.vmid_num_kfd)) { 798 dev_err(kfd_device, 799 "hws_max_conc_proc %d must be between 0 and %d, use %d instead\n", 800 hws_max_conc_proc, kfd->vm_info.vmid_num_kfd, 801 kfd->vm_info.vmid_num_kfd); 802 kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd; 803 } else 804 kfd->max_proc_per_quantum = hws_max_conc_proc; 805 806 /* calculate max size of mqds needed for queues */ 807 size = max_num_of_queues_per_device * 808 kfd->device_info->mqd_size_aligned; 809 810 /* 811 * calculate max size of runlist packet. 812 * There can be only 2 packets at once 813 */ 814 map_process_packet_size = 815 kfd->device_info->asic_family == CHIP_ALDEBARAN ? 816 sizeof(struct pm4_mes_map_process_aldebaran) : 817 sizeof(struct pm4_mes_map_process); 818 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + 819 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 820 + sizeof(struct pm4_mes_runlist)) * 2; 821 822 /* Add size of HIQ & DIQ */ 823 size += KFD_KERNEL_QUEUE_SIZE * 2; 824 825 /* add another 512KB for all other allocations on gart (HPD, fences) */ 826 size += 512 * 1024; 827 828 if (amdgpu_amdkfd_alloc_gtt_mem( 829 kfd->kgd, size, &kfd->gtt_mem, 830 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 831 false)) { 832 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 833 goto alloc_gtt_mem_failure; 834 } 835 836 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 837 838 /* Initialize GTT sa with 512 byte chunk size */ 839 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 840 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 841 goto kfd_gtt_sa_init_error; 842 } 843 844 if (kfd_doorbell_init(kfd)) { 845 dev_err(kfd_device, 846 "Error initializing doorbell aperture\n"); 847 goto kfd_doorbell_error; 848 } 849 850 kfd->hive_id = amdgpu_amdkfd_get_hive_id(kfd->kgd); 851 852 kfd->noretry = amdgpu_amdkfd_get_noretry(kfd->kgd); 853 854 if (kfd_interrupt_init(kfd)) { 855 dev_err(kfd_device, "Error initializing interrupts\n"); 856 goto kfd_interrupt_error; 857 } 858 859 kfd->dqm = device_queue_manager_init(kfd); 860 if (!kfd->dqm) { 861 dev_err(kfd_device, "Error initializing queue manager\n"); 862 goto device_queue_manager_error; 863 } 864 865 /* If supported on this device, allocate global GWS that is shared 866 * by all KFD processes 867 */ 868 if (kfd_gws_init(kfd)) { 869 dev_err(kfd_device, "Could not allocate %d gws\n", 870 amdgpu_amdkfd_get_num_gws(kfd->kgd)); 871 goto gws_error; 872 } 873 874 /* If CRAT is broken, won't set iommu enabled */ 875 kfd_double_confirm_iommu_support(kfd); 876 877 if (kfd_iommu_device_init(kfd)) { 878 dev_err(kfd_device, "Error initializing iommuv2\n"); 879 goto device_iommu_error; 880 } 881 882 kfd_cwsr_init(kfd); 883 884 svm_migrate_init((struct amdgpu_device *)kfd->kgd); 885 886 if (kfd_resume(kfd)) 887 goto kfd_resume_error; 888 889 kfd->dbgmgr = NULL; 890 891 if (kfd_topology_add_device(kfd)) { 892 dev_err(kfd_device, "Error adding device to topology\n"); 893 goto kfd_topology_add_device_error; 894 } 895 896 kfd_smi_init(kfd); 897 898 kfd->init_complete = true; 899 dev_info(kfd_device, "added device %x:%x\n", kfd->pdev->vendor, 900 kfd->pdev->device); 901 902 pr_debug("Starting kfd with the following scheduling policy %d\n", 903 kfd->dqm->sched_policy); 904 905 goto out; 906 907 kfd_topology_add_device_error: 908 kfd_resume_error: 909 device_iommu_error: 910 gws_error: 911 device_queue_manager_uninit(kfd->dqm); 912 device_queue_manager_error: 913 kfd_interrupt_exit(kfd); 914 kfd_interrupt_error: 915 kfd_doorbell_fini(kfd); 916 kfd_doorbell_error: 917 kfd_gtt_sa_fini(kfd); 918 kfd_gtt_sa_init_error: 919 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem); 920 alloc_gtt_mem_failure: 921 if (kfd->gws) 922 amdgpu_amdkfd_free_gws(kfd->kgd, kfd->gws); 923 dev_err(kfd_device, 924 "device %x:%x NOT added due to errors\n", 925 kfd->pdev->vendor, kfd->pdev->device); 926 out: 927 return kfd->init_complete; 928 } 929 930 void kgd2kfd_device_exit(struct kfd_dev *kfd) 931 { 932 if (kfd->init_complete) { 933 svm_migrate_fini((struct amdgpu_device *)kfd->kgd); 934 device_queue_manager_uninit(kfd->dqm); 935 kfd_interrupt_exit(kfd); 936 kfd_topology_remove_device(kfd); 937 kfd_doorbell_fini(kfd); 938 ida_destroy(&kfd->doorbell_ida); 939 kfd_gtt_sa_fini(kfd); 940 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem); 941 if (kfd->gws) 942 amdgpu_amdkfd_free_gws(kfd->kgd, kfd->gws); 943 } 944 945 kfree(kfd); 946 } 947 948 int kgd2kfd_pre_reset(struct kfd_dev *kfd) 949 { 950 if (!kfd->init_complete) 951 return 0; 952 953 kfd_smi_event_update_gpu_reset(kfd, false); 954 955 kfd->dqm->ops.pre_reset(kfd->dqm); 956 957 kgd2kfd_suspend(kfd, false); 958 959 kfd_signal_reset_event(kfd); 960 return 0; 961 } 962 963 /* 964 * Fix me. KFD won't be able to resume existing process for now. 965 * We will keep all existing process in a evicted state and 966 * wait the process to be terminated. 967 */ 968 969 int kgd2kfd_post_reset(struct kfd_dev *kfd) 970 { 971 int ret; 972 973 if (!kfd->init_complete) 974 return 0; 975 976 ret = kfd_resume(kfd); 977 if (ret) 978 return ret; 979 atomic_dec(&kfd_locked); 980 981 atomic_set(&kfd->sram_ecc_flag, 0); 982 983 kfd_smi_event_update_gpu_reset(kfd, true); 984 985 return 0; 986 } 987 988 bool kfd_is_locked(void) 989 { 990 return (atomic_read(&kfd_locked) > 0); 991 } 992 993 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 994 { 995 if (!kfd->init_complete) 996 return; 997 998 /* for runtime suspend, skip locking kfd */ 999 if (!run_pm) { 1000 /* For first KFD device suspend all the KFD processes */ 1001 if (atomic_inc_return(&kfd_locked) == 1) 1002 kfd_suspend_all_processes(); 1003 } 1004 1005 kfd->dqm->ops.stop(kfd->dqm); 1006 kfd_iommu_suspend(kfd); 1007 } 1008 1009 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 1010 { 1011 int ret, count; 1012 1013 if (!kfd->init_complete) 1014 return 0; 1015 1016 ret = kfd_resume(kfd); 1017 if (ret) 1018 return ret; 1019 1020 /* for runtime resume, skip unlocking kfd */ 1021 if (!run_pm) { 1022 count = atomic_dec_return(&kfd_locked); 1023 WARN_ONCE(count < 0, "KFD suspend / resume ref. error"); 1024 if (count == 0) 1025 ret = kfd_resume_all_processes(); 1026 } 1027 1028 return ret; 1029 } 1030 1031 static int kfd_resume(struct kfd_dev *kfd) 1032 { 1033 int err = 0; 1034 1035 err = kfd_iommu_resume(kfd); 1036 if (err) { 1037 dev_err(kfd_device, 1038 "Failed to resume IOMMU for device %x:%x\n", 1039 kfd->pdev->vendor, kfd->pdev->device); 1040 return err; 1041 } 1042 1043 err = kfd->dqm->ops.start(kfd->dqm); 1044 if (err) { 1045 dev_err(kfd_device, 1046 "Error starting queue manager for device %x:%x\n", 1047 kfd->pdev->vendor, kfd->pdev->device); 1048 goto dqm_start_error; 1049 } 1050 1051 return err; 1052 1053 dqm_start_error: 1054 kfd_iommu_suspend(kfd); 1055 return err; 1056 } 1057 1058 static inline void kfd_queue_work(struct workqueue_struct *wq, 1059 struct work_struct *work) 1060 { 1061 int cpu, new_cpu; 1062 1063 cpu = new_cpu = smp_processor_id(); 1064 do { 1065 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids; 1066 if (cpu_to_node(new_cpu) == numa_node_id()) 1067 break; 1068 } while (cpu != new_cpu); 1069 1070 queue_work_on(new_cpu, wq, work); 1071 } 1072 1073 /* This is called directly from KGD at ISR. */ 1074 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 1075 { 1076 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE]; 1077 bool is_patched = false; 1078 unsigned long flags; 1079 1080 if (!kfd->init_complete) 1081 return; 1082 1083 if (kfd->device_info->ih_ring_entry_size > sizeof(patched_ihre)) { 1084 dev_err_once(kfd_device, "Ring entry too small\n"); 1085 return; 1086 } 1087 1088 spin_lock_irqsave(&kfd->interrupt_lock, flags); 1089 1090 if (kfd->interrupts_active 1091 && interrupt_is_wanted(kfd, ih_ring_entry, 1092 patched_ihre, &is_patched) 1093 && enqueue_ih_ring_entry(kfd, 1094 is_patched ? patched_ihre : ih_ring_entry)) 1095 kfd_queue_work(kfd->ih_wq, &kfd->interrupt_work); 1096 1097 spin_unlock_irqrestore(&kfd->interrupt_lock, flags); 1098 } 1099 1100 int kgd2kfd_quiesce_mm(struct mm_struct *mm) 1101 { 1102 struct kfd_process *p; 1103 int r; 1104 1105 /* Because we are called from arbitrary context (workqueue) as opposed 1106 * to process context, kfd_process could attempt to exit while we are 1107 * running so the lookup function increments the process ref count. 1108 */ 1109 p = kfd_lookup_process_by_mm(mm); 1110 if (!p) 1111 return -ESRCH; 1112 1113 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 1114 r = kfd_process_evict_queues(p); 1115 1116 kfd_unref_process(p); 1117 return r; 1118 } 1119 1120 int kgd2kfd_resume_mm(struct mm_struct *mm) 1121 { 1122 struct kfd_process *p; 1123 int r; 1124 1125 /* Because we are called from arbitrary context (workqueue) as opposed 1126 * to process context, kfd_process could attempt to exit while we are 1127 * running so the lookup function increments the process ref count. 1128 */ 1129 p = kfd_lookup_process_by_mm(mm); 1130 if (!p) 1131 return -ESRCH; 1132 1133 r = kfd_process_restore_queues(p); 1134 1135 kfd_unref_process(p); 1136 return r; 1137 } 1138 1139 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 1140 * prepare for safe eviction of KFD BOs that belong to the specified 1141 * process. 1142 * 1143 * @mm: mm_struct that identifies the specified KFD process 1144 * @fence: eviction fence attached to KFD process BOs 1145 * 1146 */ 1147 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 1148 struct dma_fence *fence) 1149 { 1150 struct kfd_process *p; 1151 unsigned long active_time; 1152 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 1153 1154 if (!fence) 1155 return -EINVAL; 1156 1157 if (dma_fence_is_signaled(fence)) 1158 return 0; 1159 1160 p = kfd_lookup_process_by_mm(mm); 1161 if (!p) 1162 return -ENODEV; 1163 1164 if (fence->seqno == p->last_eviction_seqno) 1165 goto out; 1166 1167 p->last_eviction_seqno = fence->seqno; 1168 1169 /* Avoid KFD process starvation. Wait for at least 1170 * PROCESS_ACTIVE_TIME_MS before evicting the process again 1171 */ 1172 active_time = get_jiffies_64() - p->last_restore_timestamp; 1173 if (delay_jiffies > active_time) 1174 delay_jiffies -= active_time; 1175 else 1176 delay_jiffies = 0; 1177 1178 /* During process initialization eviction_work.dwork is initialized 1179 * to kfd_evict_bo_worker 1180 */ 1181 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 1182 p->lead_thread->pid, delay_jiffies); 1183 schedule_delayed_work(&p->eviction_work, delay_jiffies); 1184 out: 1185 kfd_unref_process(p); 1186 return 0; 1187 } 1188 1189 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 1190 unsigned int chunk_size) 1191 { 1192 unsigned int num_of_longs; 1193 1194 if (WARN_ON(buf_size < chunk_size)) 1195 return -EINVAL; 1196 if (WARN_ON(buf_size == 0)) 1197 return -EINVAL; 1198 if (WARN_ON(chunk_size == 0)) 1199 return -EINVAL; 1200 1201 kfd->gtt_sa_chunk_size = chunk_size; 1202 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 1203 1204 num_of_longs = (kfd->gtt_sa_num_of_chunks + BITS_PER_LONG - 1) / 1205 BITS_PER_LONG; 1206 1207 kfd->gtt_sa_bitmap = kcalloc(num_of_longs, sizeof(long), GFP_KERNEL); 1208 1209 if (!kfd->gtt_sa_bitmap) 1210 return -ENOMEM; 1211 1212 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 1213 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 1214 1215 mutex_init(&kfd->gtt_sa_lock); 1216 1217 return 0; 1218 1219 } 1220 1221 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 1222 { 1223 mutex_destroy(&kfd->gtt_sa_lock); 1224 kfree(kfd->gtt_sa_bitmap); 1225 } 1226 1227 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 1228 unsigned int bit_num, 1229 unsigned int chunk_size) 1230 { 1231 return start_addr + bit_num * chunk_size; 1232 } 1233 1234 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 1235 unsigned int bit_num, 1236 unsigned int chunk_size) 1237 { 1238 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 1239 } 1240 1241 int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size, 1242 struct kfd_mem_obj **mem_obj) 1243 { 1244 unsigned int found, start_search, cur_size; 1245 1246 if (size == 0) 1247 return -EINVAL; 1248 1249 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 1250 return -ENOMEM; 1251 1252 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 1253 if (!(*mem_obj)) 1254 return -ENOMEM; 1255 1256 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 1257 1258 start_search = 0; 1259 1260 mutex_lock(&kfd->gtt_sa_lock); 1261 1262 kfd_gtt_restart_search: 1263 /* Find the first chunk that is free */ 1264 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1265 kfd->gtt_sa_num_of_chunks, 1266 start_search); 1267 1268 pr_debug("Found = %d\n", found); 1269 1270 /* If there wasn't any free chunk, bail out */ 1271 if (found == kfd->gtt_sa_num_of_chunks) 1272 goto kfd_gtt_no_free_chunk; 1273 1274 /* Update fields of mem_obj */ 1275 (*mem_obj)->range_start = found; 1276 (*mem_obj)->range_end = found; 1277 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1278 kfd->gtt_start_gpu_addr, 1279 found, 1280 kfd->gtt_sa_chunk_size); 1281 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1282 kfd->gtt_start_cpu_ptr, 1283 found, 1284 kfd->gtt_sa_chunk_size); 1285 1286 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1287 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1288 1289 /* If we need only one chunk, mark it as allocated and get out */ 1290 if (size <= kfd->gtt_sa_chunk_size) { 1291 pr_debug("Single bit\n"); 1292 set_bit(found, kfd->gtt_sa_bitmap); 1293 goto kfd_gtt_out; 1294 } 1295 1296 /* Otherwise, try to see if we have enough contiguous chunks */ 1297 cur_size = size - kfd->gtt_sa_chunk_size; 1298 do { 1299 (*mem_obj)->range_end = 1300 find_next_zero_bit(kfd->gtt_sa_bitmap, 1301 kfd->gtt_sa_num_of_chunks, ++found); 1302 /* 1303 * If next free chunk is not contiguous than we need to 1304 * restart our search from the last free chunk we found (which 1305 * wasn't contiguous to the previous ones 1306 */ 1307 if ((*mem_obj)->range_end != found) { 1308 start_search = found; 1309 goto kfd_gtt_restart_search; 1310 } 1311 1312 /* 1313 * If we reached end of buffer, bail out with error 1314 */ 1315 if (found == kfd->gtt_sa_num_of_chunks) 1316 goto kfd_gtt_no_free_chunk; 1317 1318 /* Check if we don't need another chunk */ 1319 if (cur_size <= kfd->gtt_sa_chunk_size) 1320 cur_size = 0; 1321 else 1322 cur_size -= kfd->gtt_sa_chunk_size; 1323 1324 } while (cur_size > 0); 1325 1326 pr_debug("range_start = %d, range_end = %d\n", 1327 (*mem_obj)->range_start, (*mem_obj)->range_end); 1328 1329 /* Mark the chunks as allocated */ 1330 for (found = (*mem_obj)->range_start; 1331 found <= (*mem_obj)->range_end; 1332 found++) 1333 set_bit(found, kfd->gtt_sa_bitmap); 1334 1335 kfd_gtt_out: 1336 mutex_unlock(&kfd->gtt_sa_lock); 1337 return 0; 1338 1339 kfd_gtt_no_free_chunk: 1340 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1341 mutex_unlock(&kfd->gtt_sa_lock); 1342 kfree(*mem_obj); 1343 return -ENOMEM; 1344 } 1345 1346 int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj) 1347 { 1348 unsigned int bit; 1349 1350 /* Act like kfree when trying to free a NULL object */ 1351 if (!mem_obj) 1352 return 0; 1353 1354 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1355 mem_obj, mem_obj->range_start, mem_obj->range_end); 1356 1357 mutex_lock(&kfd->gtt_sa_lock); 1358 1359 /* Mark the chunks as free */ 1360 for (bit = mem_obj->range_start; 1361 bit <= mem_obj->range_end; 1362 bit++) 1363 clear_bit(bit, kfd->gtt_sa_bitmap); 1364 1365 mutex_unlock(&kfd->gtt_sa_lock); 1366 1367 kfree(mem_obj); 1368 return 0; 1369 } 1370 1371 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1372 { 1373 if (kfd) 1374 atomic_inc(&kfd->sram_ecc_flag); 1375 } 1376 1377 void kfd_inc_compute_active(struct kfd_dev *kfd) 1378 { 1379 if (atomic_inc_return(&kfd->compute_profile) == 1) 1380 amdgpu_amdkfd_set_compute_idle(kfd->kgd, false); 1381 } 1382 1383 void kfd_dec_compute_active(struct kfd_dev *kfd) 1384 { 1385 int count = atomic_dec_return(&kfd->compute_profile); 1386 1387 if (count == 0) 1388 amdgpu_amdkfd_set_compute_idle(kfd->kgd, true); 1389 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1390 } 1391 1392 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 1393 { 1394 if (kfd && kfd->init_complete) 1395 kfd_smi_event_update_thermal_throttling(kfd, throttle_bitmask); 1396 } 1397 1398 #if defined(CONFIG_DEBUG_FS) 1399 1400 /* This function will send a package to HIQ to hang the HWS 1401 * which will trigger a GPU reset and bring the HWS back to normal state 1402 */ 1403 int kfd_debugfs_hang_hws(struct kfd_dev *dev) 1404 { 1405 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1406 pr_err("HWS is not enabled"); 1407 return -EINVAL; 1408 } 1409 1410 return dqm_debugfs_hang_hws(dev->dqm); 1411 } 1412 1413 #endif 1414