1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/bsearch.h> 25 #include <linux/pci.h> 26 #include <linux/slab.h> 27 #include "kfd_priv.h" 28 #include "kfd_device_queue_manager.h" 29 #include "kfd_pm4_headers_vi.h" 30 #include "kfd_pm4_headers_aldebaran.h" 31 #include "cwsr_trap_handler.h" 32 #include "kfd_iommu.h" 33 #include "amdgpu_amdkfd.h" 34 #include "kfd_smi_events.h" 35 #include "kfd_svm.h" 36 #include "kfd_migrate.h" 37 #include "amdgpu.h" 38 #include "amdgpu_xcp.h" 39 40 #define MQD_SIZE_ALIGNED 768 41 42 /* 43 * kfd_locked is used to lock the kfd driver during suspend or reset 44 * once locked, kfd driver will stop any further GPU execution. 45 * create process (open) will return -EAGAIN. 46 */ 47 static int kfd_locked; 48 49 #ifdef CONFIG_DRM_AMDGPU_CIK 50 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 51 #endif 52 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 53 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 54 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 55 extern const struct kfd2kgd_calls aldebaran_kfd2kgd; 56 extern const struct kfd2kgd_calls gc_9_4_3_kfd2kgd; 57 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 58 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 59 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd; 60 61 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 62 unsigned int chunk_size); 63 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 64 65 static int kfd_resume_iommu(struct kfd_dev *kfd); 66 static int kfd_resume(struct kfd_node *kfd); 67 68 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) 69 { 70 uint32_t sdma_version = kfd->adev->ip_versions[SDMA0_HWIP][0]; 71 72 switch (sdma_version) { 73 case IP_VERSION(4, 0, 0):/* VEGA10 */ 74 case IP_VERSION(4, 0, 1):/* VEGA12 */ 75 case IP_VERSION(4, 1, 0):/* RAVEN */ 76 case IP_VERSION(4, 1, 1):/* RAVEN */ 77 case IP_VERSION(4, 1, 2):/* RENOIR */ 78 case IP_VERSION(5, 2, 1):/* VANGOGH */ 79 case IP_VERSION(5, 2, 3):/* YELLOW_CARP */ 80 case IP_VERSION(5, 2, 6):/* GC 10.3.6 */ 81 case IP_VERSION(5, 2, 7):/* GC 10.3.7 */ 82 kfd->device_info.num_sdma_queues_per_engine = 2; 83 break; 84 case IP_VERSION(4, 2, 0):/* VEGA20 */ 85 case IP_VERSION(4, 2, 2):/* ARCTURUS */ 86 case IP_VERSION(4, 4, 0):/* ALDEBARAN */ 87 case IP_VERSION(4, 4, 2): 88 case IP_VERSION(5, 0, 0):/* NAVI10 */ 89 case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */ 90 case IP_VERSION(5, 0, 2):/* NAVI14 */ 91 case IP_VERSION(5, 0, 5):/* NAVI12 */ 92 case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */ 93 case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */ 94 case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */ 95 case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */ 96 case IP_VERSION(6, 0, 0): 97 case IP_VERSION(6, 0, 1): 98 case IP_VERSION(6, 0, 2): 99 case IP_VERSION(6, 0, 3): 100 kfd->device_info.num_sdma_queues_per_engine = 8; 101 break; 102 default: 103 dev_warn(kfd_device, 104 "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n", 105 sdma_version); 106 kfd->device_info.num_sdma_queues_per_engine = 8; 107 } 108 109 bitmap_zero(kfd->device_info.reserved_sdma_queues_bitmap, KFD_MAX_SDMA_QUEUES); 110 111 switch (sdma_version) { 112 case IP_VERSION(6, 0, 0): 113 case IP_VERSION(6, 0, 1): 114 case IP_VERSION(6, 0, 2): 115 case IP_VERSION(6, 0, 3): 116 /* Reserve 1 for paging and 1 for gfx */ 117 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 118 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */ 119 bitmap_set(kfd->device_info.reserved_sdma_queues_bitmap, 0, 120 kfd->adev->sdma.num_instances * 121 kfd->device_info.num_reserved_sdma_queues_per_engine); 122 break; 123 default: 124 break; 125 } 126 } 127 128 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) 129 { 130 uint32_t gc_version = KFD_GC_VERSION(kfd); 131 132 switch (gc_version) { 133 case IP_VERSION(9, 0, 1): /* VEGA10 */ 134 case IP_VERSION(9, 1, 0): /* RAVEN */ 135 case IP_VERSION(9, 2, 1): /* VEGA12 */ 136 case IP_VERSION(9, 2, 2): /* RAVEN */ 137 case IP_VERSION(9, 3, 0): /* RENOIR */ 138 case IP_VERSION(9, 4, 0): /* VEGA20 */ 139 case IP_VERSION(9, 4, 1): /* ARCTURUS */ 140 case IP_VERSION(9, 4, 2): /* ALDEBARAN */ 141 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 142 break; 143 case IP_VERSION(9, 4, 3): /* GC 9.4.3 */ 144 kfd->device_info.event_interrupt_class = 145 &event_interrupt_class_v9_4_3; 146 break; 147 case IP_VERSION(10, 3, 1): /* VANGOGH */ 148 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */ 149 case IP_VERSION(10, 3, 6): /* GC 10.3.6 */ 150 case IP_VERSION(10, 3, 7): /* GC 10.3.7 */ 151 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */ 152 case IP_VERSION(10, 1, 4): 153 case IP_VERSION(10, 1, 10): /* NAVI10 */ 154 case IP_VERSION(10, 1, 2): /* NAVI12 */ 155 case IP_VERSION(10, 1, 1): /* NAVI14 */ 156 case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */ 157 case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */ 158 case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */ 159 case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */ 160 kfd->device_info.event_interrupt_class = &event_interrupt_class_v10; 161 break; 162 case IP_VERSION(11, 0, 0): 163 case IP_VERSION(11, 0, 1): 164 case IP_VERSION(11, 0, 2): 165 case IP_VERSION(11, 0, 3): 166 case IP_VERSION(11, 0, 4): 167 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 168 break; 169 default: 170 dev_warn(kfd_device, "v9 event interrupt handler is set due to " 171 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version); 172 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 173 } 174 } 175 176 static void kfd_device_info_init(struct kfd_dev *kfd, 177 bool vf, uint32_t gfx_target_version) 178 { 179 uint32_t gc_version = KFD_GC_VERSION(kfd); 180 uint32_t asic_type = kfd->adev->asic_type; 181 182 kfd->device_info.max_pasid_bits = 16; 183 kfd->device_info.max_no_of_hqd = 24; 184 kfd->device_info.num_of_watch_points = 4; 185 kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED; 186 kfd->device_info.gfx_target_version = gfx_target_version; 187 188 if (KFD_IS_SOC15(kfd)) { 189 kfd->device_info.doorbell_size = 8; 190 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t); 191 kfd->device_info.supports_cwsr = true; 192 193 kfd_device_info_set_sdma_info(kfd); 194 195 kfd_device_info_set_event_interrupt_class(kfd); 196 197 /* Raven */ 198 if (gc_version == IP_VERSION(9, 1, 0) || 199 gc_version == IP_VERSION(9, 2, 2)) 200 kfd->device_info.needs_iommu_device = true; 201 202 if (gc_version < IP_VERSION(11, 0, 0)) { 203 /* Navi2x+, Navi1x+ */ 204 if (gc_version == IP_VERSION(10, 3, 6)) 205 kfd->device_info.no_atomic_fw_version = 14; 206 else if (gc_version == IP_VERSION(10, 3, 7)) 207 kfd->device_info.no_atomic_fw_version = 3; 208 else if (gc_version >= IP_VERSION(10, 3, 0)) 209 kfd->device_info.no_atomic_fw_version = 92; 210 else if (gc_version >= IP_VERSION(10, 1, 1)) 211 kfd->device_info.no_atomic_fw_version = 145; 212 213 /* Navi1x+ */ 214 if (gc_version >= IP_VERSION(10, 1, 1)) 215 kfd->device_info.needs_pci_atomics = true; 216 } else if (gc_version < IP_VERSION(12, 0, 0)) { 217 /* 218 * PCIe atomics support acknowledgment in GFX11 RS64 CPFW requires 219 * MEC version >= 509. Prior RS64 CPFW versions (and all F32) require 220 * PCIe atomics support. 221 */ 222 kfd->device_info.needs_pci_atomics = true; 223 kfd->device_info.no_atomic_fw_version = kfd->adev->gfx.rs64_enable ? 509 : 0; 224 } 225 } else { 226 kfd->device_info.doorbell_size = 4; 227 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t); 228 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik; 229 kfd->device_info.num_sdma_queues_per_engine = 2; 230 231 if (asic_type != CHIP_KAVERI && 232 asic_type != CHIP_HAWAII && 233 asic_type != CHIP_TONGA) 234 kfd->device_info.supports_cwsr = true; 235 236 if (asic_type == CHIP_KAVERI || 237 asic_type == CHIP_CARRIZO) 238 kfd->device_info.needs_iommu_device = true; 239 240 if (asic_type != CHIP_HAWAII && !vf) 241 kfd->device_info.needs_pci_atomics = true; 242 } 243 } 244 245 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 246 { 247 struct kfd_dev *kfd = NULL; 248 const struct kfd2kgd_calls *f2g = NULL; 249 uint32_t gfx_target_version = 0; 250 251 switch (adev->asic_type) { 252 #ifdef KFD_SUPPORT_IOMMU_V2 253 #ifdef CONFIG_DRM_AMDGPU_CIK 254 case CHIP_KAVERI: 255 gfx_target_version = 70000; 256 if (!vf) 257 f2g = &gfx_v7_kfd2kgd; 258 break; 259 #endif 260 case CHIP_CARRIZO: 261 gfx_target_version = 80001; 262 if (!vf) 263 f2g = &gfx_v8_kfd2kgd; 264 break; 265 #endif 266 #ifdef CONFIG_DRM_AMDGPU_CIK 267 case CHIP_HAWAII: 268 gfx_target_version = 70001; 269 if (!amdgpu_exp_hw_support) 270 pr_info( 271 "KFD support on Hawaii is experimental. See modparam exp_hw_support\n" 272 ); 273 else if (!vf) 274 f2g = &gfx_v7_kfd2kgd; 275 break; 276 #endif 277 case CHIP_TONGA: 278 gfx_target_version = 80002; 279 if (!vf) 280 f2g = &gfx_v8_kfd2kgd; 281 break; 282 case CHIP_FIJI: 283 case CHIP_POLARIS10: 284 gfx_target_version = 80003; 285 f2g = &gfx_v8_kfd2kgd; 286 break; 287 case CHIP_POLARIS11: 288 case CHIP_POLARIS12: 289 case CHIP_VEGAM: 290 gfx_target_version = 80003; 291 if (!vf) 292 f2g = &gfx_v8_kfd2kgd; 293 break; 294 default: 295 switch (adev->ip_versions[GC_HWIP][0]) { 296 /* Vega 10 */ 297 case IP_VERSION(9, 0, 1): 298 gfx_target_version = 90000; 299 f2g = &gfx_v9_kfd2kgd; 300 break; 301 #ifdef KFD_SUPPORT_IOMMU_V2 302 /* Raven */ 303 case IP_VERSION(9, 1, 0): 304 case IP_VERSION(9, 2, 2): 305 gfx_target_version = 90002; 306 if (!vf) 307 f2g = &gfx_v9_kfd2kgd; 308 break; 309 #endif 310 /* Vega12 */ 311 case IP_VERSION(9, 2, 1): 312 gfx_target_version = 90004; 313 if (!vf) 314 f2g = &gfx_v9_kfd2kgd; 315 break; 316 /* Renoir */ 317 case IP_VERSION(9, 3, 0): 318 gfx_target_version = 90012; 319 if (!vf) 320 f2g = &gfx_v9_kfd2kgd; 321 break; 322 /* Vega20 */ 323 case IP_VERSION(9, 4, 0): 324 gfx_target_version = 90006; 325 if (!vf) 326 f2g = &gfx_v9_kfd2kgd; 327 break; 328 /* Arcturus */ 329 case IP_VERSION(9, 4, 1): 330 gfx_target_version = 90008; 331 f2g = &arcturus_kfd2kgd; 332 break; 333 /* Aldebaran */ 334 case IP_VERSION(9, 4, 2): 335 gfx_target_version = 90010; 336 f2g = &aldebaran_kfd2kgd; 337 break; 338 case IP_VERSION(9, 4, 3): 339 gfx_target_version = adev->rev_id >= 1 ? 90402 340 : adev->flags & AMD_IS_APU ? 90400 341 : 90401; 342 f2g = &gc_9_4_3_kfd2kgd; 343 break; 344 /* Navi10 */ 345 case IP_VERSION(10, 1, 10): 346 gfx_target_version = 100100; 347 if (!vf) 348 f2g = &gfx_v10_kfd2kgd; 349 break; 350 /* Navi12 */ 351 case IP_VERSION(10, 1, 2): 352 gfx_target_version = 100101; 353 f2g = &gfx_v10_kfd2kgd; 354 break; 355 /* Navi14 */ 356 case IP_VERSION(10, 1, 1): 357 gfx_target_version = 100102; 358 if (!vf) 359 f2g = &gfx_v10_kfd2kgd; 360 break; 361 /* Cyan Skillfish */ 362 case IP_VERSION(10, 1, 3): 363 case IP_VERSION(10, 1, 4): 364 gfx_target_version = 100103; 365 if (!vf) 366 f2g = &gfx_v10_kfd2kgd; 367 break; 368 /* Sienna Cichlid */ 369 case IP_VERSION(10, 3, 0): 370 gfx_target_version = 100300; 371 f2g = &gfx_v10_3_kfd2kgd; 372 break; 373 /* Navy Flounder */ 374 case IP_VERSION(10, 3, 2): 375 gfx_target_version = 100301; 376 f2g = &gfx_v10_3_kfd2kgd; 377 break; 378 /* Van Gogh */ 379 case IP_VERSION(10, 3, 1): 380 gfx_target_version = 100303; 381 if (!vf) 382 f2g = &gfx_v10_3_kfd2kgd; 383 break; 384 /* Dimgrey Cavefish */ 385 case IP_VERSION(10, 3, 4): 386 gfx_target_version = 100302; 387 f2g = &gfx_v10_3_kfd2kgd; 388 break; 389 /* Beige Goby */ 390 case IP_VERSION(10, 3, 5): 391 gfx_target_version = 100304; 392 f2g = &gfx_v10_3_kfd2kgd; 393 break; 394 /* Yellow Carp */ 395 case IP_VERSION(10, 3, 3): 396 gfx_target_version = 100305; 397 if (!vf) 398 f2g = &gfx_v10_3_kfd2kgd; 399 break; 400 case IP_VERSION(10, 3, 6): 401 case IP_VERSION(10, 3, 7): 402 gfx_target_version = 100306; 403 if (!vf) 404 f2g = &gfx_v10_3_kfd2kgd; 405 break; 406 case IP_VERSION(11, 0, 0): 407 gfx_target_version = 110000; 408 f2g = &gfx_v11_kfd2kgd; 409 break; 410 case IP_VERSION(11, 0, 1): 411 case IP_VERSION(11, 0, 4): 412 gfx_target_version = 110003; 413 f2g = &gfx_v11_kfd2kgd; 414 break; 415 case IP_VERSION(11, 0, 2): 416 gfx_target_version = 110002; 417 f2g = &gfx_v11_kfd2kgd; 418 break; 419 case IP_VERSION(11, 0, 3): 420 if ((adev->pdev->device == 0x7460 && 421 adev->pdev->revision == 0x00) || 422 (adev->pdev->device == 0x7461 && 423 adev->pdev->revision == 0x00)) 424 /* Note: Compiler version is 11.0.5 while HW version is 11.0.3 */ 425 gfx_target_version = 110005; 426 else 427 /* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */ 428 gfx_target_version = 110001; 429 f2g = &gfx_v11_kfd2kgd; 430 break; 431 default: 432 break; 433 } 434 break; 435 } 436 437 if (!f2g) { 438 if (adev->ip_versions[GC_HWIP][0]) 439 dev_err(kfd_device, "GC IP %06x %s not supported in kfd\n", 440 adev->ip_versions[GC_HWIP][0], vf ? "VF" : ""); 441 else 442 dev_err(kfd_device, "%s %s not supported in kfd\n", 443 amdgpu_asic_name[adev->asic_type], vf ? "VF" : ""); 444 return NULL; 445 } 446 447 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 448 if (!kfd) 449 return NULL; 450 451 kfd->adev = adev; 452 kfd_device_info_init(kfd, vf, gfx_target_version); 453 kfd->init_complete = false; 454 kfd->kfd2kgd = f2g; 455 atomic_set(&kfd->compute_profile, 0); 456 457 mutex_init(&kfd->doorbell_mutex); 458 memset(&kfd->doorbell_available_index, 0, 459 sizeof(kfd->doorbell_available_index)); 460 461 ida_init(&kfd->doorbell_ida); 462 463 return kfd; 464 } 465 466 static void kfd_cwsr_init(struct kfd_dev *kfd) 467 { 468 if (cwsr_enable && kfd->device_info.supports_cwsr) { 469 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) { 470 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE); 471 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 472 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 473 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) { 474 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE); 475 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 476 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 477 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) { 478 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) > PAGE_SIZE); 479 kfd->cwsr_isa = cwsr_trap_aldebaran_hex; 480 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); 481 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3)) { 482 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_4_3_hex) > PAGE_SIZE); 483 kfd->cwsr_isa = cwsr_trap_gfx9_4_3_hex; 484 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_4_3_hex); 485 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) { 486 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE); 487 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 488 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 489 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) { 490 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE); 491 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 492 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 493 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) { 494 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE); 495 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 496 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 497 } else { 498 BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE); 499 kfd->cwsr_isa = cwsr_trap_gfx11_hex; 500 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex); 501 } 502 503 kfd->cwsr_enabled = true; 504 } 505 } 506 507 static int kfd_gws_init(struct kfd_node *node) 508 { 509 int ret = 0; 510 struct kfd_dev *kfd = node->kfd; 511 512 if (node->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 513 return 0; 514 515 if (hws_gws_support || (KFD_IS_SOC15(node) && 516 ((KFD_GC_VERSION(node) == IP_VERSION(9, 0, 1) 517 && kfd->mec2_fw_version >= 0x81b3) || 518 (KFD_GC_VERSION(node) <= IP_VERSION(9, 4, 0) 519 && kfd->mec2_fw_version >= 0x1b3) || 520 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 1) 521 && kfd->mec2_fw_version >= 0x30) || 522 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 2) 523 && kfd->mec2_fw_version >= 0x28) || 524 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 3)) || 525 (KFD_GC_VERSION(node) >= IP_VERSION(10, 3, 0) 526 && KFD_GC_VERSION(node) < IP_VERSION(11, 0, 0) 527 && kfd->mec2_fw_version >= 0x6b)))) 528 ret = amdgpu_amdkfd_alloc_gws(node->adev, 529 node->adev->gds.gws_size, &node->gws); 530 531 return ret; 532 } 533 534 static void kfd_smi_init(struct kfd_node *dev) 535 { 536 INIT_LIST_HEAD(&dev->smi_clients); 537 spin_lock_init(&dev->smi_lock); 538 } 539 540 static int kfd_init_node(struct kfd_node *node) 541 { 542 int err = -1; 543 544 if (kfd_interrupt_init(node)) { 545 dev_err(kfd_device, "Error initializing interrupts\n"); 546 goto kfd_interrupt_error; 547 } 548 549 node->dqm = device_queue_manager_init(node); 550 if (!node->dqm) { 551 dev_err(kfd_device, "Error initializing queue manager\n"); 552 goto device_queue_manager_error; 553 } 554 555 if (kfd_gws_init(node)) { 556 dev_err(kfd_device, "Could not allocate %d gws\n", 557 node->adev->gds.gws_size); 558 goto gws_error; 559 } 560 561 if (kfd_resume(node)) 562 goto kfd_resume_error; 563 564 if (kfd_topology_add_device(node)) { 565 dev_err(kfd_device, "Error adding device to topology\n"); 566 goto kfd_topology_add_device_error; 567 } 568 569 kfd_smi_init(node); 570 571 return 0; 572 573 kfd_topology_add_device_error: 574 kfd_resume_error: 575 gws_error: 576 device_queue_manager_uninit(node->dqm); 577 device_queue_manager_error: 578 kfd_interrupt_exit(node); 579 kfd_interrupt_error: 580 if (node->gws) 581 amdgpu_amdkfd_free_gws(node->adev, node->gws); 582 583 /* Cleanup the node memory here */ 584 kfree(node); 585 return err; 586 } 587 588 static void kfd_cleanup_nodes(struct kfd_dev *kfd, unsigned int num_nodes) 589 { 590 struct kfd_node *knode; 591 unsigned int i; 592 593 for (i = 0; i < num_nodes; i++) { 594 knode = kfd->nodes[i]; 595 device_queue_manager_uninit(knode->dqm); 596 kfd_interrupt_exit(knode); 597 kfd_topology_remove_device(knode); 598 if (knode->gws) 599 amdgpu_amdkfd_free_gws(knode->adev, knode->gws); 600 kfree(knode); 601 kfd->nodes[i] = NULL; 602 } 603 } 604 605 static void kfd_setup_interrupt_bitmap(struct kfd_node *node, 606 unsigned int kfd_node_idx) 607 { 608 struct amdgpu_device *adev = node->adev; 609 uint32_t xcc_mask = node->xcc_mask; 610 uint32_t xcc, mapped_xcc; 611 /* 612 * Interrupt bitmap is setup for processing interrupts from 613 * different XCDs and AIDs. 614 * Interrupt bitmap is defined as follows: 615 * 1. Bits 0-15 - correspond to the NodeId field. 616 * Each bit corresponds to NodeId number. For example, if 617 * a KFD node has interrupt bitmap set to 0x7, then this 618 * KFD node will process interrupts with NodeId = 0, 1 and 2 619 * in the IH cookie. 620 * 2. Bits 16-31 - unused. 621 * 622 * Please note that the kfd_node_idx argument passed to this 623 * function is not related to NodeId field received in the 624 * IH cookie. 625 * 626 * In CPX mode, a KFD node will process an interrupt if: 627 * - the Node Id matches the corresponding bit set in 628 * Bits 0-15. 629 * - AND VMID reported in the interrupt lies within the 630 * VMID range of the node. 631 */ 632 for_each_inst(xcc, xcc_mask) { 633 mapped_xcc = GET_INST(GC, xcc); 634 node->interrupt_bitmap |= (mapped_xcc % 2 ? 5 : 3) << (4 * (mapped_xcc / 2)); 635 } 636 dev_info(kfd_device, "Node: %d, interrupt_bitmap: %x\n", kfd_node_idx, 637 node->interrupt_bitmap); 638 } 639 640 bool kgd2kfd_device_init(struct kfd_dev *kfd, 641 const struct kgd2kfd_shared_resources *gpu_resources) 642 { 643 unsigned int size, map_process_packet_size, i; 644 struct kfd_node *node; 645 uint32_t first_vmid_kfd, last_vmid_kfd, vmid_num_kfd; 646 unsigned int max_proc_per_quantum; 647 int partition_mode; 648 int xcp_idx; 649 650 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 651 KGD_ENGINE_MEC1); 652 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 653 KGD_ENGINE_MEC2); 654 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 655 KGD_ENGINE_SDMA1); 656 kfd->shared_resources = *gpu_resources; 657 658 kfd->num_nodes = amdgpu_xcp_get_num_xcp(kfd->adev->xcp_mgr); 659 660 if (kfd->num_nodes == 0) { 661 dev_err(kfd_device, 662 "KFD num nodes cannot be 0, num_xcc_in_node: %d\n", 663 kfd->adev->gfx.num_xcc_per_xcp); 664 goto out; 665 } 666 667 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 668 * 32 and 64-bit requests are possible and must be 669 * supported. 670 */ 671 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev); 672 if (!kfd->pci_atomic_requested && 673 kfd->device_info.needs_pci_atomics && 674 (!kfd->device_info.no_atomic_fw_version || 675 kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) { 676 dev_info(kfd_device, 677 "skipped device %x:%x, PCI rejects atomics %d<%d\n", 678 kfd->adev->pdev->vendor, kfd->adev->pdev->device, 679 kfd->mec_fw_version, 680 kfd->device_info.no_atomic_fw_version); 681 return false; 682 } 683 684 first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 685 last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 686 vmid_num_kfd = last_vmid_kfd - first_vmid_kfd + 1; 687 688 /* For GFX9.4.3, we need special handling for VMIDs depending on 689 * partition mode. 690 * In CPX mode, the VMID range needs to be shared between XCDs. 691 * Additionally, there are 13 VMIDs (3-15) available for KFD. To 692 * divide them equally, we change starting VMID to 4 and not use 693 * VMID 3. 694 * If the VMID range changes for GFX9.4.3, then this code MUST be 695 * revisited. 696 */ 697 if (kfd->adev->xcp_mgr) { 698 partition_mode = amdgpu_xcp_query_partition_mode(kfd->adev->xcp_mgr, 699 AMDGPU_XCP_FL_LOCKED); 700 if (partition_mode == AMDGPU_CPX_PARTITION_MODE && 701 kfd->num_nodes != 1) { 702 vmid_num_kfd /= 2; 703 first_vmid_kfd = last_vmid_kfd + 1 - vmid_num_kfd*2; 704 } 705 } 706 707 /* Verify module parameters regarding mapped process number*/ 708 if (hws_max_conc_proc >= 0) 709 max_proc_per_quantum = min((u32)hws_max_conc_proc, vmid_num_kfd); 710 else 711 max_proc_per_quantum = vmid_num_kfd; 712 713 /* calculate max size of mqds needed for queues */ 714 size = max_num_of_queues_per_device * 715 kfd->device_info.mqd_size_aligned; 716 717 /* 718 * calculate max size of runlist packet. 719 * There can be only 2 packets at once 720 */ 721 map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ? 722 sizeof(struct pm4_mes_map_process_aldebaran) : 723 sizeof(struct pm4_mes_map_process); 724 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + 725 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 726 + sizeof(struct pm4_mes_runlist)) * 2; 727 728 /* Add size of HIQ & DIQ */ 729 size += KFD_KERNEL_QUEUE_SIZE * 2; 730 731 /* add another 512KB for all other allocations on gart (HPD, fences) */ 732 size += 512 * 1024; 733 734 if (amdgpu_amdkfd_alloc_gtt_mem( 735 kfd->adev, size, &kfd->gtt_mem, 736 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 737 false)) { 738 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 739 goto alloc_gtt_mem_failure; 740 } 741 742 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 743 744 /* Initialize GTT sa with 512 byte chunk size */ 745 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 746 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 747 goto kfd_gtt_sa_init_error; 748 } 749 750 if (kfd_doorbell_init(kfd)) { 751 dev_err(kfd_device, 752 "Error initializing doorbell aperture\n"); 753 goto kfd_doorbell_error; 754 } 755 756 if (amdgpu_use_xgmi_p2p) 757 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id; 758 759 /* 760 * For GFX9.4.3, the KFD abstracts all partitions within a socket as 761 * xGMI connected in the topology so assign a unique hive id per 762 * device based on the pci device location if device is in PCIe mode. 763 */ 764 if (!kfd->hive_id && (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3)) && kfd->num_nodes > 1) 765 kfd->hive_id = pci_dev_id(kfd->adev->pdev); 766 767 kfd->noretry = kfd->adev->gmc.noretry; 768 769 /* If CRAT is broken, won't set iommu enabled */ 770 kfd_double_confirm_iommu_support(kfd); 771 772 if (kfd_iommu_device_init(kfd)) { 773 kfd->use_iommu_v2 = false; 774 dev_err(kfd_device, "Error initializing iommuv2\n"); 775 goto device_iommu_error; 776 } 777 778 kfd_cwsr_init(kfd); 779 780 dev_info(kfd_device, "Total number of KFD nodes to be created: %d\n", 781 kfd->num_nodes); 782 783 /* Allocate the KFD nodes */ 784 for (i = 0, xcp_idx = 0; i < kfd->num_nodes; i++) { 785 node = kzalloc(sizeof(struct kfd_node), GFP_KERNEL); 786 if (!node) 787 goto node_alloc_error; 788 789 node->node_id = i; 790 node->adev = kfd->adev; 791 node->kfd = kfd; 792 node->kfd2kgd = kfd->kfd2kgd; 793 node->vm_info.vmid_num_kfd = vmid_num_kfd; 794 node->xcp = amdgpu_get_next_xcp(kfd->adev->xcp_mgr, &xcp_idx); 795 /* TODO : Check if error handling is needed */ 796 if (node->xcp) { 797 amdgpu_xcp_get_inst_details(node->xcp, AMDGPU_XCP_GFX, 798 &node->xcc_mask); 799 ++xcp_idx; 800 } else { 801 node->xcc_mask = 802 (1U << NUM_XCC(kfd->adev->gfx.xcc_mask)) - 1; 803 } 804 805 if (node->xcp) { 806 dev_info(kfd_device, "KFD node %d partition %d size %lldM\n", 807 node->node_id, node->xcp->mem_id, 808 KFD_XCP_MEMORY_SIZE(node->adev, node->node_id) >> 20); 809 } 810 811 if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) && 812 partition_mode == AMDGPU_CPX_PARTITION_MODE && 813 kfd->num_nodes != 1) { 814 /* For GFX9.4.3 and CPX mode, first XCD gets VMID range 815 * 4-9 and second XCD gets VMID range 10-15. 816 */ 817 818 node->vm_info.first_vmid_kfd = (i%2 == 0) ? 819 first_vmid_kfd : 820 first_vmid_kfd+vmid_num_kfd; 821 node->vm_info.last_vmid_kfd = (i%2 == 0) ? 822 last_vmid_kfd-vmid_num_kfd : 823 last_vmid_kfd; 824 node->compute_vmid_bitmap = 825 ((0x1 << (node->vm_info.last_vmid_kfd + 1)) - 1) - 826 ((0x1 << (node->vm_info.first_vmid_kfd)) - 1); 827 } else { 828 node->vm_info.first_vmid_kfd = first_vmid_kfd; 829 node->vm_info.last_vmid_kfd = last_vmid_kfd; 830 node->compute_vmid_bitmap = 831 gpu_resources->compute_vmid_bitmap; 832 } 833 node->max_proc_per_quantum = max_proc_per_quantum; 834 atomic_set(&node->sram_ecc_flag, 0); 835 836 amdgpu_amdkfd_get_local_mem_info(kfd->adev, 837 &node->local_mem_info, node->xcp); 838 839 if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3)) 840 kfd_setup_interrupt_bitmap(node, i); 841 842 /* Initialize the KFD node */ 843 if (kfd_init_node(node)) { 844 dev_err(kfd_device, "Error initializing KFD node\n"); 845 goto node_init_error; 846 } 847 kfd->nodes[i] = node; 848 } 849 850 svm_range_set_max_pages(kfd->adev); 851 852 if (kfd_resume_iommu(kfd)) 853 goto kfd_resume_iommu_error; 854 855 spin_lock_init(&kfd->watch_points_lock); 856 857 kfd->init_complete = true; 858 dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, 859 kfd->adev->pdev->device); 860 861 pr_debug("Starting kfd with the following scheduling policy %d\n", 862 node->dqm->sched_policy); 863 864 goto out; 865 866 kfd_resume_iommu_error: 867 node_init_error: 868 node_alloc_error: 869 kfd_cleanup_nodes(kfd, i); 870 device_iommu_error: 871 kfd_doorbell_fini(kfd); 872 kfd_doorbell_error: 873 kfd_gtt_sa_fini(kfd); 874 kfd_gtt_sa_init_error: 875 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 876 alloc_gtt_mem_failure: 877 dev_err(kfd_device, 878 "device %x:%x NOT added due to errors\n", 879 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 880 out: 881 return kfd->init_complete; 882 } 883 884 void kgd2kfd_device_exit(struct kfd_dev *kfd) 885 { 886 if (kfd->init_complete) { 887 /* Cleanup KFD nodes */ 888 kfd_cleanup_nodes(kfd, kfd->num_nodes); 889 /* Cleanup common/shared resources */ 890 kfd_doorbell_fini(kfd); 891 ida_destroy(&kfd->doorbell_ida); 892 kfd_gtt_sa_fini(kfd); 893 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 894 } 895 896 kfree(kfd); 897 } 898 899 int kgd2kfd_pre_reset(struct kfd_dev *kfd) 900 { 901 struct kfd_node *node; 902 int i; 903 904 if (!kfd->init_complete) 905 return 0; 906 907 for (i = 0; i < kfd->num_nodes; i++) { 908 node = kfd->nodes[i]; 909 kfd_smi_event_update_gpu_reset(node, false); 910 node->dqm->ops.pre_reset(node->dqm); 911 } 912 913 kgd2kfd_suspend(kfd, false); 914 915 for (i = 0; i < kfd->num_nodes; i++) 916 kfd_signal_reset_event(kfd->nodes[i]); 917 918 return 0; 919 } 920 921 /* 922 * Fix me. KFD won't be able to resume existing process for now. 923 * We will keep all existing process in a evicted state and 924 * wait the process to be terminated. 925 */ 926 927 int kgd2kfd_post_reset(struct kfd_dev *kfd) 928 { 929 int ret; 930 struct kfd_node *node; 931 int i; 932 933 if (!kfd->init_complete) 934 return 0; 935 936 for (i = 0; i < kfd->num_nodes; i++) { 937 ret = kfd_resume(kfd->nodes[i]); 938 if (ret) 939 return ret; 940 } 941 942 mutex_lock(&kfd_processes_mutex); 943 --kfd_locked; 944 mutex_unlock(&kfd_processes_mutex); 945 946 for (i = 0; i < kfd->num_nodes; i++) { 947 node = kfd->nodes[i]; 948 atomic_set(&node->sram_ecc_flag, 0); 949 kfd_smi_event_update_gpu_reset(node, true); 950 } 951 952 return 0; 953 } 954 955 bool kfd_is_locked(void) 956 { 957 lockdep_assert_held(&kfd_processes_mutex); 958 return (kfd_locked > 0); 959 } 960 961 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 962 { 963 struct kfd_node *node; 964 int i; 965 int count; 966 967 if (!kfd->init_complete) 968 return; 969 970 /* for runtime suspend, skip locking kfd */ 971 if (!run_pm) { 972 mutex_lock(&kfd_processes_mutex); 973 count = ++kfd_locked; 974 mutex_unlock(&kfd_processes_mutex); 975 976 /* For first KFD device suspend all the KFD processes */ 977 if (count == 1) 978 kfd_suspend_all_processes(); 979 } 980 981 for (i = 0; i < kfd->num_nodes; i++) { 982 node = kfd->nodes[i]; 983 node->dqm->ops.stop(node->dqm); 984 } 985 kfd_iommu_suspend(kfd); 986 } 987 988 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 989 { 990 int ret, count, i; 991 992 if (!kfd->init_complete) 993 return 0; 994 995 for (i = 0; i < kfd->num_nodes; i++) { 996 ret = kfd_resume(kfd->nodes[i]); 997 if (ret) 998 return ret; 999 } 1000 1001 /* for runtime resume, skip unlocking kfd */ 1002 if (!run_pm) { 1003 mutex_lock(&kfd_processes_mutex); 1004 count = --kfd_locked; 1005 mutex_unlock(&kfd_processes_mutex); 1006 1007 WARN_ONCE(count < 0, "KFD suspend / resume ref. error"); 1008 if (count == 0) 1009 ret = kfd_resume_all_processes(); 1010 } 1011 1012 return ret; 1013 } 1014 1015 int kgd2kfd_resume_iommu(struct kfd_dev *kfd) 1016 { 1017 if (!kfd->init_complete) 1018 return 0; 1019 1020 return kfd_resume_iommu(kfd); 1021 } 1022 1023 static int kfd_resume_iommu(struct kfd_dev *kfd) 1024 { 1025 int err = 0; 1026 1027 err = kfd_iommu_resume(kfd); 1028 if (err) 1029 dev_err(kfd_device, 1030 "Failed to resume IOMMU for device %x:%x\n", 1031 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 1032 return err; 1033 } 1034 1035 static int kfd_resume(struct kfd_node *node) 1036 { 1037 int err = 0; 1038 1039 err = node->dqm->ops.start(node->dqm); 1040 if (err) 1041 dev_err(kfd_device, 1042 "Error starting queue manager for device %x:%x\n", 1043 node->adev->pdev->vendor, node->adev->pdev->device); 1044 1045 return err; 1046 } 1047 1048 static inline void kfd_queue_work(struct workqueue_struct *wq, 1049 struct work_struct *work) 1050 { 1051 int cpu, new_cpu; 1052 1053 cpu = new_cpu = smp_processor_id(); 1054 do { 1055 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids; 1056 if (cpu_to_node(new_cpu) == numa_node_id()) 1057 break; 1058 } while (cpu != new_cpu); 1059 1060 queue_work_on(new_cpu, wq, work); 1061 } 1062 1063 /* This is called directly from KGD at ISR. */ 1064 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 1065 { 1066 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE], i; 1067 bool is_patched = false; 1068 unsigned long flags; 1069 struct kfd_node *node; 1070 1071 if (!kfd->init_complete) 1072 return; 1073 1074 if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) { 1075 dev_err_once(kfd_device, "Ring entry too small\n"); 1076 return; 1077 } 1078 1079 for (i = 0; i < kfd->num_nodes; i++) { 1080 node = kfd->nodes[i]; 1081 spin_lock_irqsave(&node->interrupt_lock, flags); 1082 1083 if (node->interrupts_active 1084 && interrupt_is_wanted(node, ih_ring_entry, 1085 patched_ihre, &is_patched) 1086 && enqueue_ih_ring_entry(node, 1087 is_patched ? patched_ihre : ih_ring_entry)) { 1088 kfd_queue_work(node->ih_wq, &node->interrupt_work); 1089 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1090 return; 1091 } 1092 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1093 } 1094 1095 } 1096 1097 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger) 1098 { 1099 struct kfd_process *p; 1100 int r; 1101 1102 /* Because we are called from arbitrary context (workqueue) as opposed 1103 * to process context, kfd_process could attempt to exit while we are 1104 * running so the lookup function increments the process ref count. 1105 */ 1106 p = kfd_lookup_process_by_mm(mm); 1107 if (!p) 1108 return -ESRCH; 1109 1110 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 1111 r = kfd_process_evict_queues(p, trigger); 1112 1113 kfd_unref_process(p); 1114 return r; 1115 } 1116 1117 int kgd2kfd_resume_mm(struct mm_struct *mm) 1118 { 1119 struct kfd_process *p; 1120 int r; 1121 1122 /* Because we are called from arbitrary context (workqueue) as opposed 1123 * to process context, kfd_process could attempt to exit while we are 1124 * running so the lookup function increments the process ref count. 1125 */ 1126 p = kfd_lookup_process_by_mm(mm); 1127 if (!p) 1128 return -ESRCH; 1129 1130 r = kfd_process_restore_queues(p); 1131 1132 kfd_unref_process(p); 1133 return r; 1134 } 1135 1136 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 1137 * prepare for safe eviction of KFD BOs that belong to the specified 1138 * process. 1139 * 1140 * @mm: mm_struct that identifies the specified KFD process 1141 * @fence: eviction fence attached to KFD process BOs 1142 * 1143 */ 1144 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 1145 struct dma_fence *fence) 1146 { 1147 struct kfd_process *p; 1148 unsigned long active_time; 1149 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 1150 1151 if (!fence) 1152 return -EINVAL; 1153 1154 if (dma_fence_is_signaled(fence)) 1155 return 0; 1156 1157 p = kfd_lookup_process_by_mm(mm); 1158 if (!p) 1159 return -ENODEV; 1160 1161 if (fence->seqno == p->last_eviction_seqno) 1162 goto out; 1163 1164 p->last_eviction_seqno = fence->seqno; 1165 1166 /* Avoid KFD process starvation. Wait for at least 1167 * PROCESS_ACTIVE_TIME_MS before evicting the process again 1168 */ 1169 active_time = get_jiffies_64() - p->last_restore_timestamp; 1170 if (delay_jiffies > active_time) 1171 delay_jiffies -= active_time; 1172 else 1173 delay_jiffies = 0; 1174 1175 /* During process initialization eviction_work.dwork is initialized 1176 * to kfd_evict_bo_worker 1177 */ 1178 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 1179 p->lead_thread->pid, delay_jiffies); 1180 schedule_delayed_work(&p->eviction_work, delay_jiffies); 1181 out: 1182 kfd_unref_process(p); 1183 return 0; 1184 } 1185 1186 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 1187 unsigned int chunk_size) 1188 { 1189 if (WARN_ON(buf_size < chunk_size)) 1190 return -EINVAL; 1191 if (WARN_ON(buf_size == 0)) 1192 return -EINVAL; 1193 if (WARN_ON(chunk_size == 0)) 1194 return -EINVAL; 1195 1196 kfd->gtt_sa_chunk_size = chunk_size; 1197 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 1198 1199 kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks, 1200 GFP_KERNEL); 1201 if (!kfd->gtt_sa_bitmap) 1202 return -ENOMEM; 1203 1204 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 1205 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 1206 1207 mutex_init(&kfd->gtt_sa_lock); 1208 1209 return 0; 1210 } 1211 1212 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 1213 { 1214 mutex_destroy(&kfd->gtt_sa_lock); 1215 bitmap_free(kfd->gtt_sa_bitmap); 1216 } 1217 1218 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 1219 unsigned int bit_num, 1220 unsigned int chunk_size) 1221 { 1222 return start_addr + bit_num * chunk_size; 1223 } 1224 1225 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 1226 unsigned int bit_num, 1227 unsigned int chunk_size) 1228 { 1229 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 1230 } 1231 1232 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size, 1233 struct kfd_mem_obj **mem_obj) 1234 { 1235 unsigned int found, start_search, cur_size; 1236 struct kfd_dev *kfd = node->kfd; 1237 1238 if (size == 0) 1239 return -EINVAL; 1240 1241 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 1242 return -ENOMEM; 1243 1244 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 1245 if (!(*mem_obj)) 1246 return -ENOMEM; 1247 1248 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 1249 1250 start_search = 0; 1251 1252 mutex_lock(&kfd->gtt_sa_lock); 1253 1254 kfd_gtt_restart_search: 1255 /* Find the first chunk that is free */ 1256 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1257 kfd->gtt_sa_num_of_chunks, 1258 start_search); 1259 1260 pr_debug("Found = %d\n", found); 1261 1262 /* If there wasn't any free chunk, bail out */ 1263 if (found == kfd->gtt_sa_num_of_chunks) 1264 goto kfd_gtt_no_free_chunk; 1265 1266 /* Update fields of mem_obj */ 1267 (*mem_obj)->range_start = found; 1268 (*mem_obj)->range_end = found; 1269 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1270 kfd->gtt_start_gpu_addr, 1271 found, 1272 kfd->gtt_sa_chunk_size); 1273 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1274 kfd->gtt_start_cpu_ptr, 1275 found, 1276 kfd->gtt_sa_chunk_size); 1277 1278 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1279 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1280 1281 /* If we need only one chunk, mark it as allocated and get out */ 1282 if (size <= kfd->gtt_sa_chunk_size) { 1283 pr_debug("Single bit\n"); 1284 __set_bit(found, kfd->gtt_sa_bitmap); 1285 goto kfd_gtt_out; 1286 } 1287 1288 /* Otherwise, try to see if we have enough contiguous chunks */ 1289 cur_size = size - kfd->gtt_sa_chunk_size; 1290 do { 1291 (*mem_obj)->range_end = 1292 find_next_zero_bit(kfd->gtt_sa_bitmap, 1293 kfd->gtt_sa_num_of_chunks, ++found); 1294 /* 1295 * If next free chunk is not contiguous than we need to 1296 * restart our search from the last free chunk we found (which 1297 * wasn't contiguous to the previous ones 1298 */ 1299 if ((*mem_obj)->range_end != found) { 1300 start_search = found; 1301 goto kfd_gtt_restart_search; 1302 } 1303 1304 /* 1305 * If we reached end of buffer, bail out with error 1306 */ 1307 if (found == kfd->gtt_sa_num_of_chunks) 1308 goto kfd_gtt_no_free_chunk; 1309 1310 /* Check if we don't need another chunk */ 1311 if (cur_size <= kfd->gtt_sa_chunk_size) 1312 cur_size = 0; 1313 else 1314 cur_size -= kfd->gtt_sa_chunk_size; 1315 1316 } while (cur_size > 0); 1317 1318 pr_debug("range_start = %d, range_end = %d\n", 1319 (*mem_obj)->range_start, (*mem_obj)->range_end); 1320 1321 /* Mark the chunks as allocated */ 1322 bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start, 1323 (*mem_obj)->range_end - (*mem_obj)->range_start + 1); 1324 1325 kfd_gtt_out: 1326 mutex_unlock(&kfd->gtt_sa_lock); 1327 return 0; 1328 1329 kfd_gtt_no_free_chunk: 1330 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1331 mutex_unlock(&kfd->gtt_sa_lock); 1332 kfree(*mem_obj); 1333 return -ENOMEM; 1334 } 1335 1336 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj) 1337 { 1338 struct kfd_dev *kfd = node->kfd; 1339 1340 /* Act like kfree when trying to free a NULL object */ 1341 if (!mem_obj) 1342 return 0; 1343 1344 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1345 mem_obj, mem_obj->range_start, mem_obj->range_end); 1346 1347 mutex_lock(&kfd->gtt_sa_lock); 1348 1349 /* Mark the chunks as free */ 1350 bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start, 1351 mem_obj->range_end - mem_obj->range_start + 1); 1352 1353 mutex_unlock(&kfd->gtt_sa_lock); 1354 1355 kfree(mem_obj); 1356 return 0; 1357 } 1358 1359 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1360 { 1361 /* 1362 * TODO: Currently update SRAM ECC flag for first node. 1363 * This needs to be updated later when we can 1364 * identify SRAM ECC error on other nodes also. 1365 */ 1366 if (kfd) 1367 atomic_inc(&kfd->nodes[0]->sram_ecc_flag); 1368 } 1369 1370 void kfd_inc_compute_active(struct kfd_node *node) 1371 { 1372 if (atomic_inc_return(&node->kfd->compute_profile) == 1) 1373 amdgpu_amdkfd_set_compute_idle(node->adev, false); 1374 } 1375 1376 void kfd_dec_compute_active(struct kfd_node *node) 1377 { 1378 int count = atomic_dec_return(&node->kfd->compute_profile); 1379 1380 if (count == 0) 1381 amdgpu_amdkfd_set_compute_idle(node->adev, true); 1382 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1383 } 1384 1385 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 1386 { 1387 /* 1388 * TODO: For now, raise the throttling event only on first node. 1389 * This will need to change after we are able to determine 1390 * which node raised the throttling event. 1391 */ 1392 if (kfd && kfd->init_complete) 1393 kfd_smi_event_update_thermal_throttling(kfd->nodes[0], 1394 throttle_bitmask); 1395 } 1396 1397 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and 1398 * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA. 1399 * When the device has more than two engines, we reserve two for PCIe to enable 1400 * full-duplex and the rest are used as XGMI. 1401 */ 1402 unsigned int kfd_get_num_sdma_engines(struct kfd_node *node) 1403 { 1404 /* If XGMI is not supported, all SDMA engines are PCIe */ 1405 if (!node->adev->gmc.xgmi.supported) 1406 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes; 1407 1408 return min(node->adev->sdma.num_instances/(int)node->kfd->num_nodes, 2); 1409 } 1410 1411 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *node) 1412 { 1413 /* After reserved for PCIe, the rest of engines are XGMI */ 1414 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes - 1415 kfd_get_num_sdma_engines(node); 1416 } 1417 1418 int kgd2kfd_check_and_lock_kfd(void) 1419 { 1420 mutex_lock(&kfd_processes_mutex); 1421 if (!hash_empty(kfd_processes_table) || kfd_is_locked()) { 1422 mutex_unlock(&kfd_processes_mutex); 1423 return -EBUSY; 1424 } 1425 1426 ++kfd_locked; 1427 mutex_unlock(&kfd_processes_mutex); 1428 1429 return 0; 1430 } 1431 1432 void kgd2kfd_unlock_kfd(void) 1433 { 1434 mutex_lock(&kfd_processes_mutex); 1435 --kfd_locked; 1436 mutex_unlock(&kfd_processes_mutex); 1437 } 1438 1439 #if defined(CONFIG_DEBUG_FS) 1440 1441 /* This function will send a package to HIQ to hang the HWS 1442 * which will trigger a GPU reset and bring the HWS back to normal state 1443 */ 1444 int kfd_debugfs_hang_hws(struct kfd_node *dev) 1445 { 1446 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1447 pr_err("HWS is not enabled"); 1448 return -EINVAL; 1449 } 1450 1451 return dqm_debugfs_hang_hws(dev->dqm); 1452 } 1453 1454 #endif 1455