1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/bsearch.h> 24 #include <linux/pci.h> 25 #include <linux/slab.h> 26 #include "kfd_priv.h" 27 #include "kfd_device_queue_manager.h" 28 #include "kfd_pm4_headers_vi.h" 29 #include "cwsr_trap_handler.h" 30 #include "kfd_iommu.h" 31 #include "amdgpu_amdkfd.h" 32 33 #define MQD_SIZE_ALIGNED 768 34 35 /* 36 * kfd_locked is used to lock the kfd driver during suspend or reset 37 * once locked, kfd driver will stop any further GPU execution. 38 * create process (open) will return -EAGAIN. 39 */ 40 static atomic_t kfd_locked = ATOMIC_INIT(0); 41 42 #ifdef KFD_SUPPORT_IOMMU_V2 43 static const struct kfd_device_info kaveri_device_info = { 44 .asic_family = CHIP_KAVERI, 45 .max_pasid_bits = 16, 46 /* max num of queues for KV.TODO should be a dynamic value */ 47 .max_no_of_hqd = 24, 48 .doorbell_size = 4, 49 .ih_ring_entry_size = 4 * sizeof(uint32_t), 50 .event_interrupt_class = &event_interrupt_class_cik, 51 .num_of_watch_points = 4, 52 .mqd_size_aligned = MQD_SIZE_ALIGNED, 53 .supports_cwsr = false, 54 .needs_iommu_device = true, 55 .needs_pci_atomics = false, 56 .num_sdma_engines = 2, 57 .num_xgmi_sdma_engines = 0, 58 .num_sdma_queues_per_engine = 2, 59 }; 60 61 static const struct kfd_device_info carrizo_device_info = { 62 .asic_family = CHIP_CARRIZO, 63 .max_pasid_bits = 16, 64 /* max num of queues for CZ.TODO should be a dynamic value */ 65 .max_no_of_hqd = 24, 66 .doorbell_size = 4, 67 .ih_ring_entry_size = 4 * sizeof(uint32_t), 68 .event_interrupt_class = &event_interrupt_class_cik, 69 .num_of_watch_points = 4, 70 .mqd_size_aligned = MQD_SIZE_ALIGNED, 71 .supports_cwsr = true, 72 .needs_iommu_device = true, 73 .needs_pci_atomics = false, 74 .num_sdma_engines = 2, 75 .num_xgmi_sdma_engines = 0, 76 .num_sdma_queues_per_engine = 2, 77 }; 78 79 static const struct kfd_device_info raven_device_info = { 80 .asic_family = CHIP_RAVEN, 81 .max_pasid_bits = 16, 82 .max_no_of_hqd = 24, 83 .doorbell_size = 8, 84 .ih_ring_entry_size = 8 * sizeof(uint32_t), 85 .event_interrupt_class = &event_interrupt_class_v9, 86 .num_of_watch_points = 4, 87 .mqd_size_aligned = MQD_SIZE_ALIGNED, 88 .supports_cwsr = true, 89 .needs_iommu_device = true, 90 .needs_pci_atomics = true, 91 .num_sdma_engines = 1, 92 .num_xgmi_sdma_engines = 0, 93 .num_sdma_queues_per_engine = 2, 94 }; 95 #endif 96 97 static const struct kfd_device_info hawaii_device_info = { 98 .asic_family = CHIP_HAWAII, 99 .max_pasid_bits = 16, 100 /* max num of queues for KV.TODO should be a dynamic value */ 101 .max_no_of_hqd = 24, 102 .doorbell_size = 4, 103 .ih_ring_entry_size = 4 * sizeof(uint32_t), 104 .event_interrupt_class = &event_interrupt_class_cik, 105 .num_of_watch_points = 4, 106 .mqd_size_aligned = MQD_SIZE_ALIGNED, 107 .supports_cwsr = false, 108 .needs_iommu_device = false, 109 .needs_pci_atomics = false, 110 .num_sdma_engines = 2, 111 .num_xgmi_sdma_engines = 0, 112 .num_sdma_queues_per_engine = 2, 113 }; 114 115 static const struct kfd_device_info tonga_device_info = { 116 .asic_family = CHIP_TONGA, 117 .max_pasid_bits = 16, 118 .max_no_of_hqd = 24, 119 .doorbell_size = 4, 120 .ih_ring_entry_size = 4 * sizeof(uint32_t), 121 .event_interrupt_class = &event_interrupt_class_cik, 122 .num_of_watch_points = 4, 123 .mqd_size_aligned = MQD_SIZE_ALIGNED, 124 .supports_cwsr = false, 125 .needs_iommu_device = false, 126 .needs_pci_atomics = true, 127 .num_sdma_engines = 2, 128 .num_xgmi_sdma_engines = 0, 129 .num_sdma_queues_per_engine = 2, 130 }; 131 132 static const struct kfd_device_info fiji_device_info = { 133 .asic_family = CHIP_FIJI, 134 .max_pasid_bits = 16, 135 .max_no_of_hqd = 24, 136 .doorbell_size = 4, 137 .ih_ring_entry_size = 4 * sizeof(uint32_t), 138 .event_interrupt_class = &event_interrupt_class_cik, 139 .num_of_watch_points = 4, 140 .mqd_size_aligned = MQD_SIZE_ALIGNED, 141 .supports_cwsr = true, 142 .needs_iommu_device = false, 143 .needs_pci_atomics = true, 144 .num_sdma_engines = 2, 145 .num_xgmi_sdma_engines = 0, 146 .num_sdma_queues_per_engine = 2, 147 }; 148 149 static const struct kfd_device_info fiji_vf_device_info = { 150 .asic_family = CHIP_FIJI, 151 .max_pasid_bits = 16, 152 .max_no_of_hqd = 24, 153 .doorbell_size = 4, 154 .ih_ring_entry_size = 4 * sizeof(uint32_t), 155 .event_interrupt_class = &event_interrupt_class_cik, 156 .num_of_watch_points = 4, 157 .mqd_size_aligned = MQD_SIZE_ALIGNED, 158 .supports_cwsr = true, 159 .needs_iommu_device = false, 160 .needs_pci_atomics = false, 161 .num_sdma_engines = 2, 162 .num_xgmi_sdma_engines = 0, 163 .num_sdma_queues_per_engine = 2, 164 }; 165 166 167 static const struct kfd_device_info polaris10_device_info = { 168 .asic_family = CHIP_POLARIS10, 169 .max_pasid_bits = 16, 170 .max_no_of_hqd = 24, 171 .doorbell_size = 4, 172 .ih_ring_entry_size = 4 * sizeof(uint32_t), 173 .event_interrupt_class = &event_interrupt_class_cik, 174 .num_of_watch_points = 4, 175 .mqd_size_aligned = MQD_SIZE_ALIGNED, 176 .supports_cwsr = true, 177 .needs_iommu_device = false, 178 .needs_pci_atomics = true, 179 .num_sdma_engines = 2, 180 .num_xgmi_sdma_engines = 0, 181 .num_sdma_queues_per_engine = 2, 182 }; 183 184 static const struct kfd_device_info polaris10_vf_device_info = { 185 .asic_family = CHIP_POLARIS10, 186 .max_pasid_bits = 16, 187 .max_no_of_hqd = 24, 188 .doorbell_size = 4, 189 .ih_ring_entry_size = 4 * sizeof(uint32_t), 190 .event_interrupt_class = &event_interrupt_class_cik, 191 .num_of_watch_points = 4, 192 .mqd_size_aligned = MQD_SIZE_ALIGNED, 193 .supports_cwsr = true, 194 .needs_iommu_device = false, 195 .needs_pci_atomics = false, 196 .num_sdma_engines = 2, 197 .num_xgmi_sdma_engines = 0, 198 .num_sdma_queues_per_engine = 2, 199 }; 200 201 static const struct kfd_device_info polaris11_device_info = { 202 .asic_family = CHIP_POLARIS11, 203 .max_pasid_bits = 16, 204 .max_no_of_hqd = 24, 205 .doorbell_size = 4, 206 .ih_ring_entry_size = 4 * sizeof(uint32_t), 207 .event_interrupt_class = &event_interrupt_class_cik, 208 .num_of_watch_points = 4, 209 .mqd_size_aligned = MQD_SIZE_ALIGNED, 210 .supports_cwsr = true, 211 .needs_iommu_device = false, 212 .needs_pci_atomics = true, 213 .num_sdma_engines = 2, 214 .num_xgmi_sdma_engines = 0, 215 .num_sdma_queues_per_engine = 2, 216 }; 217 218 static const struct kfd_device_info polaris12_device_info = { 219 .asic_family = CHIP_POLARIS12, 220 .max_pasid_bits = 16, 221 .max_no_of_hqd = 24, 222 .doorbell_size = 4, 223 .ih_ring_entry_size = 4 * sizeof(uint32_t), 224 .event_interrupt_class = &event_interrupt_class_cik, 225 .num_of_watch_points = 4, 226 .mqd_size_aligned = MQD_SIZE_ALIGNED, 227 .supports_cwsr = true, 228 .needs_iommu_device = false, 229 .needs_pci_atomics = true, 230 .num_sdma_engines = 2, 231 .num_xgmi_sdma_engines = 0, 232 .num_sdma_queues_per_engine = 2, 233 }; 234 235 static const struct kfd_device_info vegam_device_info = { 236 .asic_family = CHIP_VEGAM, 237 .max_pasid_bits = 16, 238 .max_no_of_hqd = 24, 239 .doorbell_size = 4, 240 .ih_ring_entry_size = 4 * sizeof(uint32_t), 241 .event_interrupt_class = &event_interrupt_class_cik, 242 .num_of_watch_points = 4, 243 .mqd_size_aligned = MQD_SIZE_ALIGNED, 244 .supports_cwsr = true, 245 .needs_iommu_device = false, 246 .needs_pci_atomics = true, 247 .num_sdma_engines = 2, 248 .num_xgmi_sdma_engines = 0, 249 .num_sdma_queues_per_engine = 2, 250 }; 251 252 static const struct kfd_device_info vega10_device_info = { 253 .asic_family = CHIP_VEGA10, 254 .max_pasid_bits = 16, 255 .max_no_of_hqd = 24, 256 .doorbell_size = 8, 257 .ih_ring_entry_size = 8 * sizeof(uint32_t), 258 .event_interrupt_class = &event_interrupt_class_v9, 259 .num_of_watch_points = 4, 260 .mqd_size_aligned = MQD_SIZE_ALIGNED, 261 .supports_cwsr = true, 262 .needs_iommu_device = false, 263 .needs_pci_atomics = false, 264 .num_sdma_engines = 2, 265 .num_xgmi_sdma_engines = 0, 266 .num_sdma_queues_per_engine = 2, 267 }; 268 269 static const struct kfd_device_info vega10_vf_device_info = { 270 .asic_family = CHIP_VEGA10, 271 .max_pasid_bits = 16, 272 .max_no_of_hqd = 24, 273 .doorbell_size = 8, 274 .ih_ring_entry_size = 8 * sizeof(uint32_t), 275 .event_interrupt_class = &event_interrupt_class_v9, 276 .num_of_watch_points = 4, 277 .mqd_size_aligned = MQD_SIZE_ALIGNED, 278 .supports_cwsr = true, 279 .needs_iommu_device = false, 280 .needs_pci_atomics = false, 281 .num_sdma_engines = 2, 282 .num_xgmi_sdma_engines = 0, 283 .num_sdma_queues_per_engine = 2, 284 }; 285 286 static const struct kfd_device_info vega12_device_info = { 287 .asic_family = CHIP_VEGA12, 288 .max_pasid_bits = 16, 289 .max_no_of_hqd = 24, 290 .doorbell_size = 8, 291 .ih_ring_entry_size = 8 * sizeof(uint32_t), 292 .event_interrupt_class = &event_interrupt_class_v9, 293 .num_of_watch_points = 4, 294 .mqd_size_aligned = MQD_SIZE_ALIGNED, 295 .supports_cwsr = true, 296 .needs_iommu_device = false, 297 .needs_pci_atomics = false, 298 .num_sdma_engines = 2, 299 .num_xgmi_sdma_engines = 0, 300 .num_sdma_queues_per_engine = 2, 301 }; 302 303 static const struct kfd_device_info vega20_device_info = { 304 .asic_family = CHIP_VEGA20, 305 .max_pasid_bits = 16, 306 .max_no_of_hqd = 24, 307 .doorbell_size = 8, 308 .ih_ring_entry_size = 8 * sizeof(uint32_t), 309 .event_interrupt_class = &event_interrupt_class_v9, 310 .num_of_watch_points = 4, 311 .mqd_size_aligned = MQD_SIZE_ALIGNED, 312 .supports_cwsr = true, 313 .needs_iommu_device = false, 314 .needs_pci_atomics = false, 315 .num_sdma_engines = 2, 316 .num_xgmi_sdma_engines = 0, 317 .num_sdma_queues_per_engine = 8, 318 }; 319 320 static const struct kfd_device_info arcturus_device_info = { 321 .asic_family = CHIP_ARCTURUS, 322 .max_pasid_bits = 16, 323 .max_no_of_hqd = 24, 324 .doorbell_size = 8, 325 .ih_ring_entry_size = 8 * sizeof(uint32_t), 326 .event_interrupt_class = &event_interrupt_class_v9, 327 .num_of_watch_points = 4, 328 .mqd_size_aligned = MQD_SIZE_ALIGNED, 329 .supports_cwsr = true, 330 .needs_iommu_device = false, 331 .needs_pci_atomics = false, 332 .num_sdma_engines = 2, 333 .num_xgmi_sdma_engines = 6, 334 .num_sdma_queues_per_engine = 8, 335 }; 336 337 static const struct kfd_device_info navi10_device_info = { 338 .asic_family = CHIP_NAVI10, 339 .max_pasid_bits = 16, 340 .max_no_of_hqd = 24, 341 .doorbell_size = 8, 342 .ih_ring_entry_size = 8 * sizeof(uint32_t), 343 .event_interrupt_class = &event_interrupt_class_v9, 344 .num_of_watch_points = 4, 345 .mqd_size_aligned = MQD_SIZE_ALIGNED, 346 .needs_iommu_device = false, 347 .supports_cwsr = true, 348 .needs_pci_atomics = false, 349 .num_sdma_engines = 2, 350 .num_xgmi_sdma_engines = 0, 351 .num_sdma_queues_per_engine = 8, 352 }; 353 354 struct kfd_deviceid { 355 unsigned short did; 356 const struct kfd_device_info *device_info; 357 }; 358 359 static const struct kfd_deviceid supported_devices[] = { 360 #ifdef KFD_SUPPORT_IOMMU_V2 361 { 0x1304, &kaveri_device_info }, /* Kaveri */ 362 { 0x1305, &kaveri_device_info }, /* Kaveri */ 363 { 0x1306, &kaveri_device_info }, /* Kaveri */ 364 { 0x1307, &kaveri_device_info }, /* Kaveri */ 365 { 0x1309, &kaveri_device_info }, /* Kaveri */ 366 { 0x130A, &kaveri_device_info }, /* Kaveri */ 367 { 0x130B, &kaveri_device_info }, /* Kaveri */ 368 { 0x130C, &kaveri_device_info }, /* Kaveri */ 369 { 0x130D, &kaveri_device_info }, /* Kaveri */ 370 { 0x130E, &kaveri_device_info }, /* Kaveri */ 371 { 0x130F, &kaveri_device_info }, /* Kaveri */ 372 { 0x1310, &kaveri_device_info }, /* Kaveri */ 373 { 0x1311, &kaveri_device_info }, /* Kaveri */ 374 { 0x1312, &kaveri_device_info }, /* Kaveri */ 375 { 0x1313, &kaveri_device_info }, /* Kaveri */ 376 { 0x1315, &kaveri_device_info }, /* Kaveri */ 377 { 0x1316, &kaveri_device_info }, /* Kaveri */ 378 { 0x1317, &kaveri_device_info }, /* Kaveri */ 379 { 0x1318, &kaveri_device_info }, /* Kaveri */ 380 { 0x131B, &kaveri_device_info }, /* Kaveri */ 381 { 0x131C, &kaveri_device_info }, /* Kaveri */ 382 { 0x131D, &kaveri_device_info }, /* Kaveri */ 383 { 0x9870, &carrizo_device_info }, /* Carrizo */ 384 { 0x9874, &carrizo_device_info }, /* Carrizo */ 385 { 0x9875, &carrizo_device_info }, /* Carrizo */ 386 { 0x9876, &carrizo_device_info }, /* Carrizo */ 387 { 0x9877, &carrizo_device_info }, /* Carrizo */ 388 { 0x15DD, &raven_device_info }, /* Raven */ 389 { 0x15D8, &raven_device_info }, /* Raven */ 390 #endif 391 { 0x67A0, &hawaii_device_info }, /* Hawaii */ 392 { 0x67A1, &hawaii_device_info }, /* Hawaii */ 393 { 0x67A2, &hawaii_device_info }, /* Hawaii */ 394 { 0x67A8, &hawaii_device_info }, /* Hawaii */ 395 { 0x67A9, &hawaii_device_info }, /* Hawaii */ 396 { 0x67AA, &hawaii_device_info }, /* Hawaii */ 397 { 0x67B0, &hawaii_device_info }, /* Hawaii */ 398 { 0x67B1, &hawaii_device_info }, /* Hawaii */ 399 { 0x67B8, &hawaii_device_info }, /* Hawaii */ 400 { 0x67B9, &hawaii_device_info }, /* Hawaii */ 401 { 0x67BA, &hawaii_device_info }, /* Hawaii */ 402 { 0x67BE, &hawaii_device_info }, /* Hawaii */ 403 { 0x6920, &tonga_device_info }, /* Tonga */ 404 { 0x6921, &tonga_device_info }, /* Tonga */ 405 { 0x6928, &tonga_device_info }, /* Tonga */ 406 { 0x6929, &tonga_device_info }, /* Tonga */ 407 { 0x692B, &tonga_device_info }, /* Tonga */ 408 { 0x6938, &tonga_device_info }, /* Tonga */ 409 { 0x6939, &tonga_device_info }, /* Tonga */ 410 { 0x7300, &fiji_device_info }, /* Fiji */ 411 { 0x730F, &fiji_vf_device_info }, /* Fiji vf*/ 412 { 0x67C0, &polaris10_device_info }, /* Polaris10 */ 413 { 0x67C1, &polaris10_device_info }, /* Polaris10 */ 414 { 0x67C2, &polaris10_device_info }, /* Polaris10 */ 415 { 0x67C4, &polaris10_device_info }, /* Polaris10 */ 416 { 0x67C7, &polaris10_device_info }, /* Polaris10 */ 417 { 0x67C8, &polaris10_device_info }, /* Polaris10 */ 418 { 0x67C9, &polaris10_device_info }, /* Polaris10 */ 419 { 0x67CA, &polaris10_device_info }, /* Polaris10 */ 420 { 0x67CC, &polaris10_device_info }, /* Polaris10 */ 421 { 0x67CF, &polaris10_device_info }, /* Polaris10 */ 422 { 0x67D0, &polaris10_vf_device_info }, /* Polaris10 vf*/ 423 { 0x67DF, &polaris10_device_info }, /* Polaris10 */ 424 { 0x6FDF, &polaris10_device_info }, /* Polaris10 */ 425 { 0x67E0, &polaris11_device_info }, /* Polaris11 */ 426 { 0x67E1, &polaris11_device_info }, /* Polaris11 */ 427 { 0x67E3, &polaris11_device_info }, /* Polaris11 */ 428 { 0x67E7, &polaris11_device_info }, /* Polaris11 */ 429 { 0x67E8, &polaris11_device_info }, /* Polaris11 */ 430 { 0x67E9, &polaris11_device_info }, /* Polaris11 */ 431 { 0x67EB, &polaris11_device_info }, /* Polaris11 */ 432 { 0x67EF, &polaris11_device_info }, /* Polaris11 */ 433 { 0x67FF, &polaris11_device_info }, /* Polaris11 */ 434 { 0x6980, &polaris12_device_info }, /* Polaris12 */ 435 { 0x6981, &polaris12_device_info }, /* Polaris12 */ 436 { 0x6985, &polaris12_device_info }, /* Polaris12 */ 437 { 0x6986, &polaris12_device_info }, /* Polaris12 */ 438 { 0x6987, &polaris12_device_info }, /* Polaris12 */ 439 { 0x6995, &polaris12_device_info }, /* Polaris12 */ 440 { 0x6997, &polaris12_device_info }, /* Polaris12 */ 441 { 0x699F, &polaris12_device_info }, /* Polaris12 */ 442 { 0x694C, &vegam_device_info }, /* VegaM */ 443 { 0x694E, &vegam_device_info }, /* VegaM */ 444 { 0x694F, &vegam_device_info }, /* VegaM */ 445 { 0x6860, &vega10_device_info }, /* Vega10 */ 446 { 0x6861, &vega10_device_info }, /* Vega10 */ 447 { 0x6862, &vega10_device_info }, /* Vega10 */ 448 { 0x6863, &vega10_device_info }, /* Vega10 */ 449 { 0x6864, &vega10_device_info }, /* Vega10 */ 450 { 0x6867, &vega10_device_info }, /* Vega10 */ 451 { 0x6868, &vega10_device_info }, /* Vega10 */ 452 { 0x6869, &vega10_device_info }, /* Vega10 */ 453 { 0x686A, &vega10_device_info }, /* Vega10 */ 454 { 0x686B, &vega10_device_info }, /* Vega10 */ 455 { 0x686C, &vega10_vf_device_info }, /* Vega10 vf*/ 456 { 0x686D, &vega10_device_info }, /* Vega10 */ 457 { 0x686E, &vega10_device_info }, /* Vega10 */ 458 { 0x686F, &vega10_device_info }, /* Vega10 */ 459 { 0x687F, &vega10_device_info }, /* Vega10 */ 460 { 0x69A0, &vega12_device_info }, /* Vega12 */ 461 { 0x69A1, &vega12_device_info }, /* Vega12 */ 462 { 0x69A2, &vega12_device_info }, /* Vega12 */ 463 { 0x69A3, &vega12_device_info }, /* Vega12 */ 464 { 0x69AF, &vega12_device_info }, /* Vega12 */ 465 { 0x66a0, &vega20_device_info }, /* Vega20 */ 466 { 0x66a1, &vega20_device_info }, /* Vega20 */ 467 { 0x66a2, &vega20_device_info }, /* Vega20 */ 468 { 0x66a3, &vega20_device_info }, /* Vega20 */ 469 { 0x66a4, &vega20_device_info }, /* Vega20 */ 470 { 0x66a7, &vega20_device_info }, /* Vega20 */ 471 { 0x66af, &vega20_device_info }, /* Vega20 */ 472 { 0x738C, &arcturus_device_info }, /* Arcturus */ 473 { 0x7388, &arcturus_device_info }, /* Arcturus */ 474 { 0x738E, &arcturus_device_info }, /* Arcturus */ 475 { 0x7310, &navi10_device_info }, /* Navi10 */ 476 { 0x7312, &navi10_device_info }, /* Navi10 */ 477 { 0x7318, &navi10_device_info }, /* Navi10 */ 478 { 0x731a, &navi10_device_info }, /* Navi10 */ 479 { 0x731f, &navi10_device_info }, /* Navi10 */ 480 }; 481 482 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 483 unsigned int chunk_size); 484 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 485 486 static int kfd_resume(struct kfd_dev *kfd); 487 488 static const struct kfd_device_info *lookup_device_info(unsigned short did) 489 { 490 size_t i; 491 492 for (i = 0; i < ARRAY_SIZE(supported_devices); i++) { 493 if (supported_devices[i].did == did) { 494 WARN_ON(!supported_devices[i].device_info); 495 return supported_devices[i].device_info; 496 } 497 } 498 499 dev_warn(kfd_device, "DID %04x is missing in supported_devices\n", 500 did); 501 502 return NULL; 503 } 504 505 struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, 506 struct pci_dev *pdev, const struct kfd2kgd_calls *f2g) 507 { 508 struct kfd_dev *kfd; 509 const struct kfd_device_info *device_info = 510 lookup_device_info(pdev->device); 511 512 if (!device_info) { 513 dev_err(kfd_device, "kgd2kfd_probe failed\n"); 514 return NULL; 515 } 516 517 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 518 if (!kfd) 519 return NULL; 520 521 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 522 * 32 and 64-bit requests are possible and must be 523 * supported. 524 */ 525 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kgd); 526 if (device_info->needs_pci_atomics && 527 !kfd->pci_atomic_requested) { 528 dev_info(kfd_device, 529 "skipped device %x:%x, PCI rejects atomics\n", 530 pdev->vendor, pdev->device); 531 kfree(kfd); 532 return NULL; 533 } 534 535 kfd->kgd = kgd; 536 kfd->device_info = device_info; 537 kfd->pdev = pdev; 538 kfd->init_complete = false; 539 kfd->kfd2kgd = f2g; 540 atomic_set(&kfd->compute_profile, 0); 541 542 mutex_init(&kfd->doorbell_mutex); 543 memset(&kfd->doorbell_available_index, 0, 544 sizeof(kfd->doorbell_available_index)); 545 546 atomic_set(&kfd->sram_ecc_flag, 0); 547 548 return kfd; 549 } 550 551 static void kfd_cwsr_init(struct kfd_dev *kfd) 552 { 553 if (cwsr_enable && kfd->device_info->supports_cwsr) { 554 if (kfd->device_info->asic_family < CHIP_VEGA10) { 555 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE); 556 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 557 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 558 } else if (kfd->device_info->asic_family == CHIP_ARCTURUS) { 559 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE); 560 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 561 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 562 } else if (kfd->device_info->asic_family < CHIP_NAVI10) { 563 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE); 564 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 565 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 566 } else { 567 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE); 568 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 569 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 570 } 571 572 kfd->cwsr_enabled = true; 573 } 574 } 575 576 bool kgd2kfd_device_init(struct kfd_dev *kfd, 577 const struct kgd2kfd_shared_resources *gpu_resources) 578 { 579 unsigned int size; 580 581 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd, 582 KGD_ENGINE_MEC1); 583 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd, 584 KGD_ENGINE_SDMA1); 585 kfd->shared_resources = *gpu_resources; 586 587 kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 588 kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 589 kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd 590 - kfd->vm_info.first_vmid_kfd + 1; 591 592 /* Verify module parameters regarding mapped process number*/ 593 if ((hws_max_conc_proc < 0) 594 || (hws_max_conc_proc > kfd->vm_info.vmid_num_kfd)) { 595 dev_err(kfd_device, 596 "hws_max_conc_proc %d must be between 0 and %d, use %d instead\n", 597 hws_max_conc_proc, kfd->vm_info.vmid_num_kfd, 598 kfd->vm_info.vmid_num_kfd); 599 kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd; 600 } else 601 kfd->max_proc_per_quantum = hws_max_conc_proc; 602 603 /* Allocate global GWS that is shared by all KFD processes */ 604 if (hws_gws_support && amdgpu_amdkfd_alloc_gws(kfd->kgd, 605 amdgpu_amdkfd_get_num_gws(kfd->kgd), &kfd->gws)) { 606 dev_err(kfd_device, "Could not allocate %d gws\n", 607 amdgpu_amdkfd_get_num_gws(kfd->kgd)); 608 goto out; 609 } 610 /* calculate max size of mqds needed for queues */ 611 size = max_num_of_queues_per_device * 612 kfd->device_info->mqd_size_aligned; 613 614 /* 615 * calculate max size of runlist packet. 616 * There can be only 2 packets at once 617 */ 618 size += (KFD_MAX_NUM_OF_PROCESSES * sizeof(struct pm4_mes_map_process) + 619 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 620 + sizeof(struct pm4_mes_runlist)) * 2; 621 622 /* Add size of HIQ & DIQ */ 623 size += KFD_KERNEL_QUEUE_SIZE * 2; 624 625 /* add another 512KB for all other allocations on gart (HPD, fences) */ 626 size += 512 * 1024; 627 628 if (amdgpu_amdkfd_alloc_gtt_mem( 629 kfd->kgd, size, &kfd->gtt_mem, 630 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 631 false)) { 632 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 633 goto alloc_gtt_mem_failure; 634 } 635 636 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 637 638 /* Initialize GTT sa with 512 byte chunk size */ 639 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 640 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 641 goto kfd_gtt_sa_init_error; 642 } 643 644 if (kfd_doorbell_init(kfd)) { 645 dev_err(kfd_device, 646 "Error initializing doorbell aperture\n"); 647 goto kfd_doorbell_error; 648 } 649 650 if (kfd->kfd2kgd->get_hive_id) 651 kfd->hive_id = kfd->kfd2kgd->get_hive_id(kfd->kgd); 652 653 if (kfd_interrupt_init(kfd)) { 654 dev_err(kfd_device, "Error initializing interrupts\n"); 655 goto kfd_interrupt_error; 656 } 657 658 kfd->dqm = device_queue_manager_init(kfd); 659 if (!kfd->dqm) { 660 dev_err(kfd_device, "Error initializing queue manager\n"); 661 goto device_queue_manager_error; 662 } 663 664 if (kfd_iommu_device_init(kfd)) { 665 dev_err(kfd_device, "Error initializing iommuv2\n"); 666 goto device_iommu_error; 667 } 668 669 kfd_cwsr_init(kfd); 670 671 if (kfd_resume(kfd)) 672 goto kfd_resume_error; 673 674 kfd->dbgmgr = NULL; 675 676 if (kfd_topology_add_device(kfd)) { 677 dev_err(kfd_device, "Error adding device to topology\n"); 678 goto kfd_topology_add_device_error; 679 } 680 681 kfd->init_complete = true; 682 dev_info(kfd_device, "added device %x:%x\n", kfd->pdev->vendor, 683 kfd->pdev->device); 684 685 pr_debug("Starting kfd with the following scheduling policy %d\n", 686 kfd->dqm->sched_policy); 687 688 goto out; 689 690 kfd_topology_add_device_error: 691 kfd_resume_error: 692 device_iommu_error: 693 device_queue_manager_uninit(kfd->dqm); 694 device_queue_manager_error: 695 kfd_interrupt_exit(kfd); 696 kfd_interrupt_error: 697 kfd_doorbell_fini(kfd); 698 kfd_doorbell_error: 699 kfd_gtt_sa_fini(kfd); 700 kfd_gtt_sa_init_error: 701 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem); 702 alloc_gtt_mem_failure: 703 if (hws_gws_support) 704 amdgpu_amdkfd_free_gws(kfd->kgd, kfd->gws); 705 dev_err(kfd_device, 706 "device %x:%x NOT added due to errors\n", 707 kfd->pdev->vendor, kfd->pdev->device); 708 out: 709 return kfd->init_complete; 710 } 711 712 void kgd2kfd_device_exit(struct kfd_dev *kfd) 713 { 714 if (kfd->init_complete) { 715 kgd2kfd_suspend(kfd); 716 device_queue_manager_uninit(kfd->dqm); 717 kfd_interrupt_exit(kfd); 718 kfd_topology_remove_device(kfd); 719 kfd_doorbell_fini(kfd); 720 kfd_gtt_sa_fini(kfd); 721 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem); 722 if (hws_gws_support) 723 amdgpu_amdkfd_free_gws(kfd->kgd, kfd->gws); 724 } 725 726 kfree(kfd); 727 } 728 729 int kgd2kfd_pre_reset(struct kfd_dev *kfd) 730 { 731 if (!kfd->init_complete) 732 return 0; 733 kgd2kfd_suspend(kfd); 734 735 /* hold dqm->lock to prevent further execution*/ 736 dqm_lock(kfd->dqm); 737 738 kfd_signal_reset_event(kfd); 739 return 0; 740 } 741 742 /* 743 * Fix me. KFD won't be able to resume existing process for now. 744 * We will keep all existing process in a evicted state and 745 * wait the process to be terminated. 746 */ 747 748 int kgd2kfd_post_reset(struct kfd_dev *kfd) 749 { 750 int ret, count; 751 752 if (!kfd->init_complete) 753 return 0; 754 755 dqm_unlock(kfd->dqm); 756 757 ret = kfd_resume(kfd); 758 if (ret) 759 return ret; 760 count = atomic_dec_return(&kfd_locked); 761 762 atomic_set(&kfd->sram_ecc_flag, 0); 763 764 return 0; 765 } 766 767 bool kfd_is_locked(void) 768 { 769 return (atomic_read(&kfd_locked) > 0); 770 } 771 772 void kgd2kfd_suspend(struct kfd_dev *kfd) 773 { 774 if (!kfd->init_complete) 775 return; 776 777 /* For first KFD device suspend all the KFD processes */ 778 if (atomic_inc_return(&kfd_locked) == 1) 779 kfd_suspend_all_processes(); 780 781 kfd->dqm->ops.stop(kfd->dqm); 782 783 kfd_iommu_suspend(kfd); 784 } 785 786 int kgd2kfd_resume(struct kfd_dev *kfd) 787 { 788 int ret, count; 789 790 if (!kfd->init_complete) 791 return 0; 792 793 ret = kfd_resume(kfd); 794 if (ret) 795 return ret; 796 797 count = atomic_dec_return(&kfd_locked); 798 WARN_ONCE(count < 0, "KFD suspend / resume ref. error"); 799 if (count == 0) 800 ret = kfd_resume_all_processes(); 801 802 return ret; 803 } 804 805 static int kfd_resume(struct kfd_dev *kfd) 806 { 807 int err = 0; 808 809 err = kfd_iommu_resume(kfd); 810 if (err) { 811 dev_err(kfd_device, 812 "Failed to resume IOMMU for device %x:%x\n", 813 kfd->pdev->vendor, kfd->pdev->device); 814 return err; 815 } 816 817 err = kfd->dqm->ops.start(kfd->dqm); 818 if (err) { 819 dev_err(kfd_device, 820 "Error starting queue manager for device %x:%x\n", 821 kfd->pdev->vendor, kfd->pdev->device); 822 goto dqm_start_error; 823 } 824 825 return err; 826 827 dqm_start_error: 828 kfd_iommu_suspend(kfd); 829 return err; 830 } 831 832 /* This is called directly from KGD at ISR. */ 833 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 834 { 835 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE]; 836 bool is_patched = false; 837 unsigned long flags; 838 839 if (!kfd->init_complete) 840 return; 841 842 if (kfd->device_info->ih_ring_entry_size > sizeof(patched_ihre)) { 843 dev_err_once(kfd_device, "Ring entry too small\n"); 844 return; 845 } 846 847 spin_lock_irqsave(&kfd->interrupt_lock, flags); 848 849 if (kfd->interrupts_active 850 && interrupt_is_wanted(kfd, ih_ring_entry, 851 patched_ihre, &is_patched) 852 && enqueue_ih_ring_entry(kfd, 853 is_patched ? patched_ihre : ih_ring_entry)) 854 queue_work(kfd->ih_wq, &kfd->interrupt_work); 855 856 spin_unlock_irqrestore(&kfd->interrupt_lock, flags); 857 } 858 859 int kgd2kfd_quiesce_mm(struct mm_struct *mm) 860 { 861 struct kfd_process *p; 862 int r; 863 864 /* Because we are called from arbitrary context (workqueue) as opposed 865 * to process context, kfd_process could attempt to exit while we are 866 * running so the lookup function increments the process ref count. 867 */ 868 p = kfd_lookup_process_by_mm(mm); 869 if (!p) 870 return -ESRCH; 871 872 r = kfd_process_evict_queues(p); 873 874 kfd_unref_process(p); 875 return r; 876 } 877 878 int kgd2kfd_resume_mm(struct mm_struct *mm) 879 { 880 struct kfd_process *p; 881 int r; 882 883 /* Because we are called from arbitrary context (workqueue) as opposed 884 * to process context, kfd_process could attempt to exit while we are 885 * running so the lookup function increments the process ref count. 886 */ 887 p = kfd_lookup_process_by_mm(mm); 888 if (!p) 889 return -ESRCH; 890 891 r = kfd_process_restore_queues(p); 892 893 kfd_unref_process(p); 894 return r; 895 } 896 897 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 898 * prepare for safe eviction of KFD BOs that belong to the specified 899 * process. 900 * 901 * @mm: mm_struct that identifies the specified KFD process 902 * @fence: eviction fence attached to KFD process BOs 903 * 904 */ 905 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 906 struct dma_fence *fence) 907 { 908 struct kfd_process *p; 909 unsigned long active_time; 910 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 911 912 if (!fence) 913 return -EINVAL; 914 915 if (dma_fence_is_signaled(fence)) 916 return 0; 917 918 p = kfd_lookup_process_by_mm(mm); 919 if (!p) 920 return -ENODEV; 921 922 if (fence->seqno == p->last_eviction_seqno) 923 goto out; 924 925 p->last_eviction_seqno = fence->seqno; 926 927 /* Avoid KFD process starvation. Wait for at least 928 * PROCESS_ACTIVE_TIME_MS before evicting the process again 929 */ 930 active_time = get_jiffies_64() - p->last_restore_timestamp; 931 if (delay_jiffies > active_time) 932 delay_jiffies -= active_time; 933 else 934 delay_jiffies = 0; 935 936 /* During process initialization eviction_work.dwork is initialized 937 * to kfd_evict_bo_worker 938 */ 939 schedule_delayed_work(&p->eviction_work, delay_jiffies); 940 out: 941 kfd_unref_process(p); 942 return 0; 943 } 944 945 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 946 unsigned int chunk_size) 947 { 948 unsigned int num_of_longs; 949 950 if (WARN_ON(buf_size < chunk_size)) 951 return -EINVAL; 952 if (WARN_ON(buf_size == 0)) 953 return -EINVAL; 954 if (WARN_ON(chunk_size == 0)) 955 return -EINVAL; 956 957 kfd->gtt_sa_chunk_size = chunk_size; 958 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 959 960 num_of_longs = (kfd->gtt_sa_num_of_chunks + BITS_PER_LONG - 1) / 961 BITS_PER_LONG; 962 963 kfd->gtt_sa_bitmap = kcalloc(num_of_longs, sizeof(long), GFP_KERNEL); 964 965 if (!kfd->gtt_sa_bitmap) 966 return -ENOMEM; 967 968 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 969 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 970 971 mutex_init(&kfd->gtt_sa_lock); 972 973 return 0; 974 975 } 976 977 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 978 { 979 mutex_destroy(&kfd->gtt_sa_lock); 980 kfree(kfd->gtt_sa_bitmap); 981 } 982 983 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 984 unsigned int bit_num, 985 unsigned int chunk_size) 986 { 987 return start_addr + bit_num * chunk_size; 988 } 989 990 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 991 unsigned int bit_num, 992 unsigned int chunk_size) 993 { 994 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 995 } 996 997 int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size, 998 struct kfd_mem_obj **mem_obj) 999 { 1000 unsigned int found, start_search, cur_size; 1001 1002 if (size == 0) 1003 return -EINVAL; 1004 1005 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 1006 return -ENOMEM; 1007 1008 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 1009 if (!(*mem_obj)) 1010 return -ENOMEM; 1011 1012 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 1013 1014 start_search = 0; 1015 1016 mutex_lock(&kfd->gtt_sa_lock); 1017 1018 kfd_gtt_restart_search: 1019 /* Find the first chunk that is free */ 1020 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1021 kfd->gtt_sa_num_of_chunks, 1022 start_search); 1023 1024 pr_debug("Found = %d\n", found); 1025 1026 /* If there wasn't any free chunk, bail out */ 1027 if (found == kfd->gtt_sa_num_of_chunks) 1028 goto kfd_gtt_no_free_chunk; 1029 1030 /* Update fields of mem_obj */ 1031 (*mem_obj)->range_start = found; 1032 (*mem_obj)->range_end = found; 1033 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1034 kfd->gtt_start_gpu_addr, 1035 found, 1036 kfd->gtt_sa_chunk_size); 1037 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1038 kfd->gtt_start_cpu_ptr, 1039 found, 1040 kfd->gtt_sa_chunk_size); 1041 1042 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1043 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1044 1045 /* If we need only one chunk, mark it as allocated and get out */ 1046 if (size <= kfd->gtt_sa_chunk_size) { 1047 pr_debug("Single bit\n"); 1048 set_bit(found, kfd->gtt_sa_bitmap); 1049 goto kfd_gtt_out; 1050 } 1051 1052 /* Otherwise, try to see if we have enough contiguous chunks */ 1053 cur_size = size - kfd->gtt_sa_chunk_size; 1054 do { 1055 (*mem_obj)->range_end = 1056 find_next_zero_bit(kfd->gtt_sa_bitmap, 1057 kfd->gtt_sa_num_of_chunks, ++found); 1058 /* 1059 * If next free chunk is not contiguous than we need to 1060 * restart our search from the last free chunk we found (which 1061 * wasn't contiguous to the previous ones 1062 */ 1063 if ((*mem_obj)->range_end != found) { 1064 start_search = found; 1065 goto kfd_gtt_restart_search; 1066 } 1067 1068 /* 1069 * If we reached end of buffer, bail out with error 1070 */ 1071 if (found == kfd->gtt_sa_num_of_chunks) 1072 goto kfd_gtt_no_free_chunk; 1073 1074 /* Check if we don't need another chunk */ 1075 if (cur_size <= kfd->gtt_sa_chunk_size) 1076 cur_size = 0; 1077 else 1078 cur_size -= kfd->gtt_sa_chunk_size; 1079 1080 } while (cur_size > 0); 1081 1082 pr_debug("range_start = %d, range_end = %d\n", 1083 (*mem_obj)->range_start, (*mem_obj)->range_end); 1084 1085 /* Mark the chunks as allocated */ 1086 for (found = (*mem_obj)->range_start; 1087 found <= (*mem_obj)->range_end; 1088 found++) 1089 set_bit(found, kfd->gtt_sa_bitmap); 1090 1091 kfd_gtt_out: 1092 mutex_unlock(&kfd->gtt_sa_lock); 1093 return 0; 1094 1095 kfd_gtt_no_free_chunk: 1096 pr_debug("Allocation failed with mem_obj = %p\n", mem_obj); 1097 mutex_unlock(&kfd->gtt_sa_lock); 1098 kfree(mem_obj); 1099 return -ENOMEM; 1100 } 1101 1102 int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj) 1103 { 1104 unsigned int bit; 1105 1106 /* Act like kfree when trying to free a NULL object */ 1107 if (!mem_obj) 1108 return 0; 1109 1110 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1111 mem_obj, mem_obj->range_start, mem_obj->range_end); 1112 1113 mutex_lock(&kfd->gtt_sa_lock); 1114 1115 /* Mark the chunks as free */ 1116 for (bit = mem_obj->range_start; 1117 bit <= mem_obj->range_end; 1118 bit++) 1119 clear_bit(bit, kfd->gtt_sa_bitmap); 1120 1121 mutex_unlock(&kfd->gtt_sa_lock); 1122 1123 kfree(mem_obj); 1124 return 0; 1125 } 1126 1127 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1128 { 1129 if (kfd) 1130 atomic_inc(&kfd->sram_ecc_flag); 1131 } 1132 1133 void kfd_inc_compute_active(struct kfd_dev *kfd) 1134 { 1135 if (atomic_inc_return(&kfd->compute_profile) == 1) 1136 amdgpu_amdkfd_set_compute_idle(kfd->kgd, false); 1137 } 1138 1139 void kfd_dec_compute_active(struct kfd_dev *kfd) 1140 { 1141 int count = atomic_dec_return(&kfd->compute_profile); 1142 1143 if (count == 0) 1144 amdgpu_amdkfd_set_compute_idle(kfd->kgd, true); 1145 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1146 } 1147 1148 #if defined(CONFIG_DEBUG_FS) 1149 1150 /* This function will send a package to HIQ to hang the HWS 1151 * which will trigger a GPU reset and bring the HWS back to normal state 1152 */ 1153 int kfd_debugfs_hang_hws(struct kfd_dev *dev) 1154 { 1155 int r = 0; 1156 1157 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1158 pr_err("HWS is not enabled"); 1159 return -EINVAL; 1160 } 1161 1162 r = pm_debugfs_hang_hws(&dev->dqm->packets); 1163 if (!r) 1164 r = dqm_debugfs_execute_queues(dev->dqm); 1165 1166 return r; 1167 } 1168 1169 #endif 1170