1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/bsearch.h> 25 #include <linux/pci.h> 26 #include <linux/slab.h> 27 #include "kfd_priv.h" 28 #include "kfd_device_queue_manager.h" 29 #include "kfd_pm4_headers_vi.h" 30 #include "kfd_pm4_headers_aldebaran.h" 31 #include "cwsr_trap_handler.h" 32 #include "kfd_iommu.h" 33 #include "amdgpu_amdkfd.h" 34 #include "kfd_smi_events.h" 35 #include "kfd_migrate.h" 36 #include "amdgpu.h" 37 38 #define MQD_SIZE_ALIGNED 768 39 40 /* 41 * kfd_locked is used to lock the kfd driver during suspend or reset 42 * once locked, kfd driver will stop any further GPU execution. 43 * create process (open) will return -EAGAIN. 44 */ 45 static atomic_t kfd_locked = ATOMIC_INIT(0); 46 47 #ifdef CONFIG_DRM_AMDGPU_CIK 48 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 49 #endif 50 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 51 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 52 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 53 extern const struct kfd2kgd_calls aldebaran_kfd2kgd; 54 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 55 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 56 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd; 57 58 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 59 unsigned int chunk_size); 60 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 61 62 static int kfd_resume(struct kfd_dev *kfd); 63 64 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) 65 { 66 uint32_t sdma_version = kfd->adev->ip_versions[SDMA0_HWIP][0]; 67 68 switch (sdma_version) { 69 case IP_VERSION(4, 0, 0):/* VEGA10 */ 70 case IP_VERSION(4, 0, 1):/* VEGA12 */ 71 case IP_VERSION(4, 1, 0):/* RAVEN */ 72 case IP_VERSION(4, 1, 1):/* RAVEN */ 73 case IP_VERSION(4, 1, 2):/* RENOIR */ 74 case IP_VERSION(5, 2, 1):/* VANGOGH */ 75 case IP_VERSION(5, 2, 3):/* YELLOW_CARP */ 76 case IP_VERSION(5, 2, 6):/* GC 10.3.6 */ 77 case IP_VERSION(5, 2, 7):/* GC 10.3.7 */ 78 case IP_VERSION(6, 0, 1): 79 kfd->device_info.num_sdma_queues_per_engine = 2; 80 break; 81 case IP_VERSION(4, 2, 0):/* VEGA20 */ 82 case IP_VERSION(4, 2, 2):/* ARCTURUS */ 83 case IP_VERSION(4, 4, 0):/* ALDEBARAN */ 84 case IP_VERSION(5, 0, 0):/* NAVI10 */ 85 case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */ 86 case IP_VERSION(5, 0, 2):/* NAVI14 */ 87 case IP_VERSION(5, 0, 5):/* NAVI12 */ 88 case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */ 89 case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */ 90 case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */ 91 case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */ 92 case IP_VERSION(6, 0, 0): 93 case IP_VERSION(6, 0, 2): 94 kfd->device_info.num_sdma_queues_per_engine = 8; 95 break; 96 default: 97 dev_warn(kfd_device, 98 "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n", 99 sdma_version); 100 kfd->device_info.num_sdma_queues_per_engine = 8; 101 } 102 103 switch (sdma_version) { 104 case IP_VERSION(6, 0, 0): 105 case IP_VERSION(6, 0, 1): 106 case IP_VERSION(6, 0, 2): 107 /* Reserve 1 for paging and 1 for gfx */ 108 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 109 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */ 110 kfd->device_info.reserved_sdma_queues_bitmap = 0xFULL; 111 break; 112 default: 113 break; 114 } 115 } 116 117 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) 118 { 119 uint32_t gc_version = KFD_GC_VERSION(kfd); 120 121 switch (gc_version) { 122 case IP_VERSION(9, 0, 1): /* VEGA10 */ 123 case IP_VERSION(9, 1, 0): /* RAVEN */ 124 case IP_VERSION(9, 2, 1): /* VEGA12 */ 125 case IP_VERSION(9, 2, 2): /* RAVEN */ 126 case IP_VERSION(9, 3, 0): /* RENOIR */ 127 case IP_VERSION(9, 4, 0): /* VEGA20 */ 128 case IP_VERSION(9, 4, 1): /* ARCTURUS */ 129 case IP_VERSION(9, 4, 2): /* ALDEBARAN */ 130 case IP_VERSION(10, 3, 1): /* VANGOGH */ 131 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */ 132 case IP_VERSION(10, 3, 6): /* GC 10.3.6 */ 133 case IP_VERSION(10, 3, 7): /* GC 10.3.7 */ 134 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */ 135 case IP_VERSION(10, 1, 4): 136 case IP_VERSION(10, 1, 10): /* NAVI10 */ 137 case IP_VERSION(10, 1, 2): /* NAVI12 */ 138 case IP_VERSION(10, 1, 1): /* NAVI14 */ 139 case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */ 140 case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */ 141 case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */ 142 case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */ 143 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 144 break; 145 case IP_VERSION(11, 0, 0): 146 case IP_VERSION(11, 0, 1): 147 case IP_VERSION(11, 0, 2): 148 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 149 break; 150 default: 151 dev_warn(kfd_device, "v9 event interrupt handler is set due to " 152 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version); 153 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 154 } 155 } 156 157 static void kfd_device_info_init(struct kfd_dev *kfd, 158 bool vf, uint32_t gfx_target_version) 159 { 160 uint32_t gc_version = KFD_GC_VERSION(kfd); 161 uint32_t asic_type = kfd->adev->asic_type; 162 163 kfd->device_info.max_pasid_bits = 16; 164 kfd->device_info.max_no_of_hqd = 24; 165 kfd->device_info.num_of_watch_points = 4; 166 kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED; 167 kfd->device_info.gfx_target_version = gfx_target_version; 168 169 if (KFD_IS_SOC15(kfd)) { 170 kfd->device_info.doorbell_size = 8; 171 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t); 172 kfd->device_info.supports_cwsr = true; 173 174 kfd_device_info_set_sdma_info(kfd); 175 176 kfd_device_info_set_event_interrupt_class(kfd); 177 178 /* Raven */ 179 if (gc_version == IP_VERSION(9, 1, 0) || 180 gc_version == IP_VERSION(9, 2, 2)) 181 kfd->device_info.needs_iommu_device = true; 182 183 if (gc_version < IP_VERSION(11, 0, 0)) { 184 /* Navi2x+, Navi1x+ */ 185 if (gc_version >= IP_VERSION(10, 3, 0)) 186 kfd->device_info.no_atomic_fw_version = 92; 187 else if (gc_version >= IP_VERSION(10, 1, 1)) 188 kfd->device_info.no_atomic_fw_version = 145; 189 190 /* Navi1x+ */ 191 if (gc_version >= IP_VERSION(10, 1, 1)) 192 kfd->device_info.needs_pci_atomics = true; 193 } 194 } else { 195 kfd->device_info.doorbell_size = 4; 196 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t); 197 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik; 198 kfd->device_info.num_sdma_queues_per_engine = 2; 199 200 if (asic_type != CHIP_KAVERI && 201 asic_type != CHIP_HAWAII && 202 asic_type != CHIP_TONGA) 203 kfd->device_info.supports_cwsr = true; 204 205 if (asic_type == CHIP_KAVERI || 206 asic_type == CHIP_CARRIZO) 207 kfd->device_info.needs_iommu_device = true; 208 209 if (asic_type != CHIP_HAWAII && !vf) 210 kfd->device_info.needs_pci_atomics = true; 211 } 212 } 213 214 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 215 { 216 struct kfd_dev *kfd = NULL; 217 const struct kfd2kgd_calls *f2g = NULL; 218 struct pci_dev *pdev = adev->pdev; 219 uint32_t gfx_target_version = 0; 220 221 switch (adev->asic_type) { 222 #ifdef KFD_SUPPORT_IOMMU_V2 223 #ifdef CONFIG_DRM_AMDGPU_CIK 224 case CHIP_KAVERI: 225 gfx_target_version = 70000; 226 if (!vf) 227 f2g = &gfx_v7_kfd2kgd; 228 break; 229 #endif 230 case CHIP_CARRIZO: 231 gfx_target_version = 80001; 232 if (!vf) 233 f2g = &gfx_v8_kfd2kgd; 234 break; 235 #endif 236 #ifdef CONFIG_DRM_AMDGPU_CIK 237 case CHIP_HAWAII: 238 gfx_target_version = 70001; 239 if (!amdgpu_exp_hw_support) 240 pr_info( 241 "KFD support on Hawaii is experimental. See modparam exp_hw_support\n" 242 ); 243 else if (!vf) 244 f2g = &gfx_v7_kfd2kgd; 245 break; 246 #endif 247 case CHIP_TONGA: 248 gfx_target_version = 80002; 249 if (!vf) 250 f2g = &gfx_v8_kfd2kgd; 251 break; 252 case CHIP_FIJI: 253 gfx_target_version = 80003; 254 f2g = &gfx_v8_kfd2kgd; 255 break; 256 case CHIP_POLARIS10: 257 gfx_target_version = 80003; 258 f2g = &gfx_v8_kfd2kgd; 259 break; 260 case CHIP_POLARIS11: 261 gfx_target_version = 80003; 262 if (!vf) 263 f2g = &gfx_v8_kfd2kgd; 264 break; 265 case CHIP_POLARIS12: 266 gfx_target_version = 80003; 267 if (!vf) 268 f2g = &gfx_v8_kfd2kgd; 269 break; 270 case CHIP_VEGAM: 271 gfx_target_version = 80003; 272 if (!vf) 273 f2g = &gfx_v8_kfd2kgd; 274 break; 275 default: 276 switch (adev->ip_versions[GC_HWIP][0]) { 277 /* Vega 10 */ 278 case IP_VERSION(9, 0, 1): 279 gfx_target_version = 90000; 280 f2g = &gfx_v9_kfd2kgd; 281 break; 282 #ifdef KFD_SUPPORT_IOMMU_V2 283 /* Raven */ 284 case IP_VERSION(9, 1, 0): 285 case IP_VERSION(9, 2, 2): 286 gfx_target_version = 90002; 287 if (!vf) 288 f2g = &gfx_v9_kfd2kgd; 289 break; 290 #endif 291 /* Vega12 */ 292 case IP_VERSION(9, 2, 1): 293 gfx_target_version = 90004; 294 if (!vf) 295 f2g = &gfx_v9_kfd2kgd; 296 break; 297 /* Renoir */ 298 case IP_VERSION(9, 3, 0): 299 gfx_target_version = 90012; 300 if (!vf) 301 f2g = &gfx_v9_kfd2kgd; 302 break; 303 /* Vega20 */ 304 case IP_VERSION(9, 4, 0): 305 gfx_target_version = 90006; 306 if (!vf) 307 f2g = &gfx_v9_kfd2kgd; 308 break; 309 /* Arcturus */ 310 case IP_VERSION(9, 4, 1): 311 gfx_target_version = 90008; 312 f2g = &arcturus_kfd2kgd; 313 break; 314 /* Aldebaran */ 315 case IP_VERSION(9, 4, 2): 316 gfx_target_version = 90010; 317 f2g = &aldebaran_kfd2kgd; 318 break; 319 /* Navi10 */ 320 case IP_VERSION(10, 1, 10): 321 gfx_target_version = 100100; 322 if (!vf) 323 f2g = &gfx_v10_kfd2kgd; 324 break; 325 /* Navi12 */ 326 case IP_VERSION(10, 1, 2): 327 gfx_target_version = 100101; 328 f2g = &gfx_v10_kfd2kgd; 329 break; 330 /* Navi14 */ 331 case IP_VERSION(10, 1, 1): 332 gfx_target_version = 100102; 333 if (!vf) 334 f2g = &gfx_v10_kfd2kgd; 335 break; 336 /* Cyan Skillfish */ 337 case IP_VERSION(10, 1, 3): 338 case IP_VERSION(10, 1, 4): 339 gfx_target_version = 100103; 340 if (!vf) 341 f2g = &gfx_v10_kfd2kgd; 342 break; 343 /* Sienna Cichlid */ 344 case IP_VERSION(10, 3, 0): 345 gfx_target_version = 100300; 346 f2g = &gfx_v10_3_kfd2kgd; 347 break; 348 /* Navy Flounder */ 349 case IP_VERSION(10, 3, 2): 350 gfx_target_version = 100301; 351 f2g = &gfx_v10_3_kfd2kgd; 352 break; 353 /* Van Gogh */ 354 case IP_VERSION(10, 3, 1): 355 gfx_target_version = 100303; 356 if (!vf) 357 f2g = &gfx_v10_3_kfd2kgd; 358 break; 359 /* Dimgrey Cavefish */ 360 case IP_VERSION(10, 3, 4): 361 gfx_target_version = 100302; 362 f2g = &gfx_v10_3_kfd2kgd; 363 break; 364 /* Beige Goby */ 365 case IP_VERSION(10, 3, 5): 366 gfx_target_version = 100304; 367 f2g = &gfx_v10_3_kfd2kgd; 368 break; 369 /* Yellow Carp */ 370 case IP_VERSION(10, 3, 3): 371 gfx_target_version = 100305; 372 if (!vf) 373 f2g = &gfx_v10_3_kfd2kgd; 374 break; 375 case IP_VERSION(10, 3, 6): 376 gfx_target_version = 100306; 377 if (!vf) 378 f2g = &gfx_v10_3_kfd2kgd; 379 break; 380 case IP_VERSION(10, 3, 7): 381 gfx_target_version = 100307; 382 if (!vf) 383 f2g = &gfx_v10_3_kfd2kgd; 384 break; 385 case IP_VERSION(11, 0, 0): 386 gfx_target_version = 110000; 387 f2g = &gfx_v11_kfd2kgd; 388 break; 389 case IP_VERSION(11, 0, 1): 390 gfx_target_version = 110003; 391 f2g = &gfx_v11_kfd2kgd; 392 break; 393 case IP_VERSION(11, 0, 2): 394 gfx_target_version = 110002; 395 f2g = &gfx_v11_kfd2kgd; 396 break; 397 default: 398 break; 399 } 400 break; 401 } 402 403 if (!f2g) { 404 if (adev->ip_versions[GC_HWIP][0]) 405 dev_err(kfd_device, "GC IP %06x %s not supported in kfd\n", 406 adev->ip_versions[GC_HWIP][0], vf ? "VF" : ""); 407 else 408 dev_err(kfd_device, "%s %s not supported in kfd\n", 409 amdgpu_asic_name[adev->asic_type], vf ? "VF" : ""); 410 return NULL; 411 } 412 413 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 414 if (!kfd) 415 return NULL; 416 417 kfd->adev = adev; 418 kfd_device_info_init(kfd, vf, gfx_target_version); 419 kfd->pdev = pdev; 420 kfd->init_complete = false; 421 kfd->kfd2kgd = f2g; 422 atomic_set(&kfd->compute_profile, 0); 423 424 mutex_init(&kfd->doorbell_mutex); 425 memset(&kfd->doorbell_available_index, 0, 426 sizeof(kfd->doorbell_available_index)); 427 428 atomic_set(&kfd->sram_ecc_flag, 0); 429 430 ida_init(&kfd->doorbell_ida); 431 432 return kfd; 433 } 434 435 static void kfd_cwsr_init(struct kfd_dev *kfd) 436 { 437 if (cwsr_enable && kfd->device_info.supports_cwsr) { 438 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) { 439 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE); 440 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 441 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 442 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) { 443 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE); 444 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 445 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 446 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) { 447 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) > PAGE_SIZE); 448 kfd->cwsr_isa = cwsr_trap_aldebaran_hex; 449 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); 450 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) { 451 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE); 452 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 453 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 454 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) { 455 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE); 456 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 457 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 458 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) { 459 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE); 460 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 461 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 462 } else { 463 BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE); 464 kfd->cwsr_isa = cwsr_trap_gfx11_hex; 465 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex); 466 } 467 468 kfd->cwsr_enabled = true; 469 } 470 } 471 472 static int kfd_gws_init(struct kfd_dev *kfd) 473 { 474 int ret = 0; 475 476 if (kfd->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 477 return 0; 478 479 if (hws_gws_support || (KFD_IS_SOC15(kfd) && 480 ((KFD_GC_VERSION(kfd) == IP_VERSION(9, 0, 1) 481 && kfd->mec2_fw_version >= 0x81b3) || 482 (KFD_GC_VERSION(kfd) <= IP_VERSION(9, 4, 0) 483 && kfd->mec2_fw_version >= 0x1b3) || 484 (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1) 485 && kfd->mec2_fw_version >= 0x30) || 486 (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) 487 && kfd->mec2_fw_version >= 0x28)))) 488 ret = amdgpu_amdkfd_alloc_gws(kfd->adev, 489 kfd->adev->gds.gws_size, &kfd->gws); 490 491 return ret; 492 } 493 494 static void kfd_smi_init(struct kfd_dev *dev) 495 { 496 INIT_LIST_HEAD(&dev->smi_clients); 497 spin_lock_init(&dev->smi_lock); 498 } 499 500 bool kgd2kfd_device_init(struct kfd_dev *kfd, 501 struct drm_device *ddev, 502 const struct kgd2kfd_shared_resources *gpu_resources) 503 { 504 unsigned int size, map_process_packet_size; 505 506 kfd->ddev = ddev; 507 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 508 KGD_ENGINE_MEC1); 509 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 510 KGD_ENGINE_MEC2); 511 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 512 KGD_ENGINE_SDMA1); 513 kfd->shared_resources = *gpu_resources; 514 515 kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 516 kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 517 kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd 518 - kfd->vm_info.first_vmid_kfd + 1; 519 520 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 521 * 32 and 64-bit requests are possible and must be 522 * supported. 523 */ 524 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev); 525 if (!kfd->pci_atomic_requested && 526 kfd->device_info.needs_pci_atomics && 527 (!kfd->device_info.no_atomic_fw_version || 528 kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) { 529 dev_info(kfd_device, 530 "skipped device %x:%x, PCI rejects atomics %d<%d\n", 531 kfd->pdev->vendor, kfd->pdev->device, 532 kfd->mec_fw_version, 533 kfd->device_info.no_atomic_fw_version); 534 return false; 535 } 536 537 /* Verify module parameters regarding mapped process number*/ 538 if (hws_max_conc_proc >= 0) 539 kfd->max_proc_per_quantum = min((u32)hws_max_conc_proc, kfd->vm_info.vmid_num_kfd); 540 else 541 kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd; 542 543 /* calculate max size of mqds needed for queues */ 544 size = max_num_of_queues_per_device * 545 kfd->device_info.mqd_size_aligned; 546 547 /* 548 * calculate max size of runlist packet. 549 * There can be only 2 packets at once 550 */ 551 map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ? 552 sizeof(struct pm4_mes_map_process_aldebaran) : 553 sizeof(struct pm4_mes_map_process); 554 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + 555 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 556 + sizeof(struct pm4_mes_runlist)) * 2; 557 558 /* Add size of HIQ & DIQ */ 559 size += KFD_KERNEL_QUEUE_SIZE * 2; 560 561 /* add another 512KB for all other allocations on gart (HPD, fences) */ 562 size += 512 * 1024; 563 564 if (amdgpu_amdkfd_alloc_gtt_mem( 565 kfd->adev, size, &kfd->gtt_mem, 566 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 567 false)) { 568 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 569 goto alloc_gtt_mem_failure; 570 } 571 572 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 573 574 /* Initialize GTT sa with 512 byte chunk size */ 575 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 576 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 577 goto kfd_gtt_sa_init_error; 578 } 579 580 if (kfd_doorbell_init(kfd)) { 581 dev_err(kfd_device, 582 "Error initializing doorbell aperture\n"); 583 goto kfd_doorbell_error; 584 } 585 586 if (amdgpu_use_xgmi_p2p) 587 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id; 588 589 kfd->noretry = kfd->adev->gmc.noretry; 590 591 if (kfd_interrupt_init(kfd)) { 592 dev_err(kfd_device, "Error initializing interrupts\n"); 593 goto kfd_interrupt_error; 594 } 595 596 kfd->dqm = device_queue_manager_init(kfd); 597 if (!kfd->dqm) { 598 dev_err(kfd_device, "Error initializing queue manager\n"); 599 goto device_queue_manager_error; 600 } 601 602 /* If supported on this device, allocate global GWS that is shared 603 * by all KFD processes 604 */ 605 if (kfd_gws_init(kfd)) { 606 dev_err(kfd_device, "Could not allocate %d gws\n", 607 kfd->adev->gds.gws_size); 608 goto gws_error; 609 } 610 611 /* If CRAT is broken, won't set iommu enabled */ 612 kfd_double_confirm_iommu_support(kfd); 613 614 if (kfd_iommu_device_init(kfd)) { 615 kfd->use_iommu_v2 = false; 616 dev_err(kfd_device, "Error initializing iommuv2\n"); 617 goto device_iommu_error; 618 } 619 620 kfd_cwsr_init(kfd); 621 622 svm_migrate_init(kfd->adev); 623 624 if (kgd2kfd_resume_iommu(kfd)) 625 goto device_iommu_error; 626 627 if (kfd_resume(kfd)) 628 goto kfd_resume_error; 629 630 amdgpu_amdkfd_get_local_mem_info(kfd->adev, &kfd->local_mem_info); 631 632 if (kfd_topology_add_device(kfd)) { 633 dev_err(kfd_device, "Error adding device to topology\n"); 634 goto kfd_topology_add_device_error; 635 } 636 637 kfd_smi_init(kfd); 638 639 kfd->init_complete = true; 640 dev_info(kfd_device, "added device %x:%x\n", kfd->pdev->vendor, 641 kfd->pdev->device); 642 643 pr_debug("Starting kfd with the following scheduling policy %d\n", 644 kfd->dqm->sched_policy); 645 646 goto out; 647 648 kfd_topology_add_device_error: 649 kfd_resume_error: 650 device_iommu_error: 651 gws_error: 652 device_queue_manager_uninit(kfd->dqm); 653 device_queue_manager_error: 654 kfd_interrupt_exit(kfd); 655 kfd_interrupt_error: 656 kfd_doorbell_fini(kfd); 657 kfd_doorbell_error: 658 kfd_gtt_sa_fini(kfd); 659 kfd_gtt_sa_init_error: 660 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 661 alloc_gtt_mem_failure: 662 if (kfd->gws) 663 amdgpu_amdkfd_free_gws(kfd->adev, kfd->gws); 664 dev_err(kfd_device, 665 "device %x:%x NOT added due to errors\n", 666 kfd->pdev->vendor, kfd->pdev->device); 667 out: 668 return kfd->init_complete; 669 } 670 671 void kgd2kfd_device_exit(struct kfd_dev *kfd) 672 { 673 if (kfd->init_complete) { 674 device_queue_manager_uninit(kfd->dqm); 675 kfd_interrupt_exit(kfd); 676 kfd_topology_remove_device(kfd); 677 kfd_doorbell_fini(kfd); 678 ida_destroy(&kfd->doorbell_ida); 679 kfd_gtt_sa_fini(kfd); 680 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 681 if (kfd->gws) 682 amdgpu_amdkfd_free_gws(kfd->adev, kfd->gws); 683 } 684 685 kfree(kfd); 686 } 687 688 int kgd2kfd_pre_reset(struct kfd_dev *kfd) 689 { 690 if (!kfd->init_complete) 691 return 0; 692 693 kfd_smi_event_update_gpu_reset(kfd, false); 694 695 kfd->dqm->ops.pre_reset(kfd->dqm); 696 697 kgd2kfd_suspend(kfd, false); 698 699 kfd_signal_reset_event(kfd); 700 return 0; 701 } 702 703 /* 704 * Fix me. KFD won't be able to resume existing process for now. 705 * We will keep all existing process in a evicted state and 706 * wait the process to be terminated. 707 */ 708 709 int kgd2kfd_post_reset(struct kfd_dev *kfd) 710 { 711 int ret; 712 713 if (!kfd->init_complete) 714 return 0; 715 716 ret = kfd_resume(kfd); 717 if (ret) 718 return ret; 719 atomic_dec(&kfd_locked); 720 721 atomic_set(&kfd->sram_ecc_flag, 0); 722 723 kfd_smi_event_update_gpu_reset(kfd, true); 724 725 return 0; 726 } 727 728 bool kfd_is_locked(void) 729 { 730 return (atomic_read(&kfd_locked) > 0); 731 } 732 733 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 734 { 735 if (!kfd->init_complete) 736 return; 737 738 /* for runtime suspend, skip locking kfd */ 739 if (!run_pm) { 740 /* For first KFD device suspend all the KFD processes */ 741 if (atomic_inc_return(&kfd_locked) == 1) 742 kfd_suspend_all_processes(); 743 } 744 745 kfd->dqm->ops.stop(kfd->dqm); 746 kfd_iommu_suspend(kfd); 747 } 748 749 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 750 { 751 int ret, count; 752 753 if (!kfd->init_complete) 754 return 0; 755 756 ret = kfd_resume(kfd); 757 if (ret) 758 return ret; 759 760 /* for runtime resume, skip unlocking kfd */ 761 if (!run_pm) { 762 count = atomic_dec_return(&kfd_locked); 763 WARN_ONCE(count < 0, "KFD suspend / resume ref. error"); 764 if (count == 0) 765 ret = kfd_resume_all_processes(); 766 } 767 768 return ret; 769 } 770 771 int kgd2kfd_resume_iommu(struct kfd_dev *kfd) 772 { 773 int err = 0; 774 775 err = kfd_iommu_resume(kfd); 776 if (err) 777 dev_err(kfd_device, 778 "Failed to resume IOMMU for device %x:%x\n", 779 kfd->pdev->vendor, kfd->pdev->device); 780 return err; 781 } 782 783 static int kfd_resume(struct kfd_dev *kfd) 784 { 785 int err = 0; 786 787 err = kfd->dqm->ops.start(kfd->dqm); 788 if (err) 789 dev_err(kfd_device, 790 "Error starting queue manager for device %x:%x\n", 791 kfd->pdev->vendor, kfd->pdev->device); 792 793 return err; 794 } 795 796 static inline void kfd_queue_work(struct workqueue_struct *wq, 797 struct work_struct *work) 798 { 799 int cpu, new_cpu; 800 801 cpu = new_cpu = smp_processor_id(); 802 do { 803 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids; 804 if (cpu_to_node(new_cpu) == numa_node_id()) 805 break; 806 } while (cpu != new_cpu); 807 808 queue_work_on(new_cpu, wq, work); 809 } 810 811 /* This is called directly from KGD at ISR. */ 812 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 813 { 814 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE]; 815 bool is_patched = false; 816 unsigned long flags; 817 818 if (!kfd->init_complete) 819 return; 820 821 if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) { 822 dev_err_once(kfd_device, "Ring entry too small\n"); 823 return; 824 } 825 826 spin_lock_irqsave(&kfd->interrupt_lock, flags); 827 828 if (kfd->interrupts_active 829 && interrupt_is_wanted(kfd, ih_ring_entry, 830 patched_ihre, &is_patched) 831 && enqueue_ih_ring_entry(kfd, 832 is_patched ? patched_ihre : ih_ring_entry)) 833 kfd_queue_work(kfd->ih_wq, &kfd->interrupt_work); 834 835 spin_unlock_irqrestore(&kfd->interrupt_lock, flags); 836 } 837 838 int kgd2kfd_quiesce_mm(struct mm_struct *mm) 839 { 840 struct kfd_process *p; 841 int r; 842 843 /* Because we are called from arbitrary context (workqueue) as opposed 844 * to process context, kfd_process could attempt to exit while we are 845 * running so the lookup function increments the process ref count. 846 */ 847 p = kfd_lookup_process_by_mm(mm); 848 if (!p) 849 return -ESRCH; 850 851 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 852 r = kfd_process_evict_queues(p); 853 854 kfd_unref_process(p); 855 return r; 856 } 857 858 int kgd2kfd_resume_mm(struct mm_struct *mm) 859 { 860 struct kfd_process *p; 861 int r; 862 863 /* Because we are called from arbitrary context (workqueue) as opposed 864 * to process context, kfd_process could attempt to exit while we are 865 * running so the lookup function increments the process ref count. 866 */ 867 p = kfd_lookup_process_by_mm(mm); 868 if (!p) 869 return -ESRCH; 870 871 r = kfd_process_restore_queues(p); 872 873 kfd_unref_process(p); 874 return r; 875 } 876 877 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 878 * prepare for safe eviction of KFD BOs that belong to the specified 879 * process. 880 * 881 * @mm: mm_struct that identifies the specified KFD process 882 * @fence: eviction fence attached to KFD process BOs 883 * 884 */ 885 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 886 struct dma_fence *fence) 887 { 888 struct kfd_process *p; 889 unsigned long active_time; 890 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 891 892 if (!fence) 893 return -EINVAL; 894 895 if (dma_fence_is_signaled(fence)) 896 return 0; 897 898 p = kfd_lookup_process_by_mm(mm); 899 if (!p) 900 return -ENODEV; 901 902 if (fence->seqno == p->last_eviction_seqno) 903 goto out; 904 905 p->last_eviction_seqno = fence->seqno; 906 907 /* Avoid KFD process starvation. Wait for at least 908 * PROCESS_ACTIVE_TIME_MS before evicting the process again 909 */ 910 active_time = get_jiffies_64() - p->last_restore_timestamp; 911 if (delay_jiffies > active_time) 912 delay_jiffies -= active_time; 913 else 914 delay_jiffies = 0; 915 916 /* During process initialization eviction_work.dwork is initialized 917 * to kfd_evict_bo_worker 918 */ 919 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 920 p->lead_thread->pid, delay_jiffies); 921 schedule_delayed_work(&p->eviction_work, delay_jiffies); 922 out: 923 kfd_unref_process(p); 924 return 0; 925 } 926 927 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 928 unsigned int chunk_size) 929 { 930 if (WARN_ON(buf_size < chunk_size)) 931 return -EINVAL; 932 if (WARN_ON(buf_size == 0)) 933 return -EINVAL; 934 if (WARN_ON(chunk_size == 0)) 935 return -EINVAL; 936 937 kfd->gtt_sa_chunk_size = chunk_size; 938 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 939 940 kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks, 941 GFP_KERNEL); 942 if (!kfd->gtt_sa_bitmap) 943 return -ENOMEM; 944 945 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 946 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 947 948 mutex_init(&kfd->gtt_sa_lock); 949 950 return 0; 951 } 952 953 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 954 { 955 mutex_destroy(&kfd->gtt_sa_lock); 956 bitmap_free(kfd->gtt_sa_bitmap); 957 } 958 959 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 960 unsigned int bit_num, 961 unsigned int chunk_size) 962 { 963 return start_addr + bit_num * chunk_size; 964 } 965 966 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 967 unsigned int bit_num, 968 unsigned int chunk_size) 969 { 970 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 971 } 972 973 int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size, 974 struct kfd_mem_obj **mem_obj) 975 { 976 unsigned int found, start_search, cur_size; 977 978 if (size == 0) 979 return -EINVAL; 980 981 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 982 return -ENOMEM; 983 984 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 985 if (!(*mem_obj)) 986 return -ENOMEM; 987 988 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 989 990 start_search = 0; 991 992 mutex_lock(&kfd->gtt_sa_lock); 993 994 kfd_gtt_restart_search: 995 /* Find the first chunk that is free */ 996 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 997 kfd->gtt_sa_num_of_chunks, 998 start_search); 999 1000 pr_debug("Found = %d\n", found); 1001 1002 /* If there wasn't any free chunk, bail out */ 1003 if (found == kfd->gtt_sa_num_of_chunks) 1004 goto kfd_gtt_no_free_chunk; 1005 1006 /* Update fields of mem_obj */ 1007 (*mem_obj)->range_start = found; 1008 (*mem_obj)->range_end = found; 1009 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1010 kfd->gtt_start_gpu_addr, 1011 found, 1012 kfd->gtt_sa_chunk_size); 1013 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1014 kfd->gtt_start_cpu_ptr, 1015 found, 1016 kfd->gtt_sa_chunk_size); 1017 1018 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1019 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1020 1021 /* If we need only one chunk, mark it as allocated and get out */ 1022 if (size <= kfd->gtt_sa_chunk_size) { 1023 pr_debug("Single bit\n"); 1024 __set_bit(found, kfd->gtt_sa_bitmap); 1025 goto kfd_gtt_out; 1026 } 1027 1028 /* Otherwise, try to see if we have enough contiguous chunks */ 1029 cur_size = size - kfd->gtt_sa_chunk_size; 1030 do { 1031 (*mem_obj)->range_end = 1032 find_next_zero_bit(kfd->gtt_sa_bitmap, 1033 kfd->gtt_sa_num_of_chunks, ++found); 1034 /* 1035 * If next free chunk is not contiguous than we need to 1036 * restart our search from the last free chunk we found (which 1037 * wasn't contiguous to the previous ones 1038 */ 1039 if ((*mem_obj)->range_end != found) { 1040 start_search = found; 1041 goto kfd_gtt_restart_search; 1042 } 1043 1044 /* 1045 * If we reached end of buffer, bail out with error 1046 */ 1047 if (found == kfd->gtt_sa_num_of_chunks) 1048 goto kfd_gtt_no_free_chunk; 1049 1050 /* Check if we don't need another chunk */ 1051 if (cur_size <= kfd->gtt_sa_chunk_size) 1052 cur_size = 0; 1053 else 1054 cur_size -= kfd->gtt_sa_chunk_size; 1055 1056 } while (cur_size > 0); 1057 1058 pr_debug("range_start = %d, range_end = %d\n", 1059 (*mem_obj)->range_start, (*mem_obj)->range_end); 1060 1061 /* Mark the chunks as allocated */ 1062 bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start, 1063 (*mem_obj)->range_end - (*mem_obj)->range_start + 1); 1064 1065 kfd_gtt_out: 1066 mutex_unlock(&kfd->gtt_sa_lock); 1067 return 0; 1068 1069 kfd_gtt_no_free_chunk: 1070 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1071 mutex_unlock(&kfd->gtt_sa_lock); 1072 kfree(*mem_obj); 1073 return -ENOMEM; 1074 } 1075 1076 int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj) 1077 { 1078 /* Act like kfree when trying to free a NULL object */ 1079 if (!mem_obj) 1080 return 0; 1081 1082 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1083 mem_obj, mem_obj->range_start, mem_obj->range_end); 1084 1085 mutex_lock(&kfd->gtt_sa_lock); 1086 1087 /* Mark the chunks as free */ 1088 bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start, 1089 mem_obj->range_end - mem_obj->range_start + 1); 1090 1091 mutex_unlock(&kfd->gtt_sa_lock); 1092 1093 kfree(mem_obj); 1094 return 0; 1095 } 1096 1097 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1098 { 1099 if (kfd) 1100 atomic_inc(&kfd->sram_ecc_flag); 1101 } 1102 1103 void kfd_inc_compute_active(struct kfd_dev *kfd) 1104 { 1105 if (atomic_inc_return(&kfd->compute_profile) == 1) 1106 amdgpu_amdkfd_set_compute_idle(kfd->adev, false); 1107 } 1108 1109 void kfd_dec_compute_active(struct kfd_dev *kfd) 1110 { 1111 int count = atomic_dec_return(&kfd->compute_profile); 1112 1113 if (count == 0) 1114 amdgpu_amdkfd_set_compute_idle(kfd->adev, true); 1115 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1116 } 1117 1118 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 1119 { 1120 if (kfd && kfd->init_complete) 1121 kfd_smi_event_update_thermal_throttling(kfd, throttle_bitmask); 1122 } 1123 1124 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and 1125 * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA. 1126 * When the device has more than two engines, we reserve two for PCIe to enable 1127 * full-duplex and the rest are used as XGMI. 1128 */ 1129 unsigned int kfd_get_num_sdma_engines(struct kfd_dev *kdev) 1130 { 1131 /* If XGMI is not supported, all SDMA engines are PCIe */ 1132 if (!kdev->adev->gmc.xgmi.supported) 1133 return kdev->adev->sdma.num_instances; 1134 1135 return min(kdev->adev->sdma.num_instances, 2); 1136 } 1137 1138 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_dev *kdev) 1139 { 1140 /* After reserved for PCIe, the rest of engines are XGMI */ 1141 return kdev->adev->sdma.num_instances - kfd_get_num_sdma_engines(kdev); 1142 } 1143 1144 #if defined(CONFIG_DEBUG_FS) 1145 1146 /* This function will send a package to HIQ to hang the HWS 1147 * which will trigger a GPU reset and bring the HWS back to normal state 1148 */ 1149 int kfd_debugfs_hang_hws(struct kfd_dev *dev) 1150 { 1151 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1152 pr_err("HWS is not enabled"); 1153 return -EINVAL; 1154 } 1155 1156 return dqm_debugfs_hang_hws(dev->dqm); 1157 } 1158 1159 #endif 1160