1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/bsearch.h> 25 #include <linux/pci.h> 26 #include <linux/slab.h> 27 #include "kfd_priv.h" 28 #include "kfd_device_queue_manager.h" 29 #include "kfd_pm4_headers_vi.h" 30 #include "kfd_pm4_headers_aldebaran.h" 31 #include "cwsr_trap_handler.h" 32 #include "kfd_iommu.h" 33 #include "amdgpu_amdkfd.h" 34 #include "kfd_smi_events.h" 35 #include "kfd_migrate.h" 36 #include "amdgpu.h" 37 38 #define MQD_SIZE_ALIGNED 768 39 40 /* 41 * kfd_locked is used to lock the kfd driver during suspend or reset 42 * once locked, kfd driver will stop any further GPU execution. 43 * create process (open) will return -EAGAIN. 44 */ 45 static atomic_t kfd_locked = ATOMIC_INIT(0); 46 47 #ifdef CONFIG_DRM_AMDGPU_CIK 48 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 49 #endif 50 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 51 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 52 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 53 extern const struct kfd2kgd_calls aldebaran_kfd2kgd; 54 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 55 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 56 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd; 57 58 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 59 unsigned int chunk_size); 60 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 61 62 static int kfd_resume(struct kfd_dev *kfd); 63 64 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) 65 { 66 uint32_t sdma_version = kfd->adev->ip_versions[SDMA0_HWIP][0]; 67 68 switch (sdma_version) { 69 case IP_VERSION(4, 0, 0):/* VEGA10 */ 70 case IP_VERSION(4, 0, 1):/* VEGA12 */ 71 case IP_VERSION(4, 1, 0):/* RAVEN */ 72 case IP_VERSION(4, 1, 1):/* RAVEN */ 73 case IP_VERSION(4, 1, 2):/* RENOIR */ 74 case IP_VERSION(5, 2, 1):/* VANGOGH */ 75 case IP_VERSION(5, 2, 3):/* YELLOW_CARP */ 76 case IP_VERSION(5, 2, 6):/* GC 10.3.6 */ 77 case IP_VERSION(5, 2, 7):/* GC 10.3.7 */ 78 kfd->device_info.num_sdma_queues_per_engine = 2; 79 break; 80 case IP_VERSION(4, 2, 0):/* VEGA20 */ 81 case IP_VERSION(4, 2, 2):/* ARCTURUS */ 82 case IP_VERSION(4, 4, 0):/* ALDEBARAN */ 83 case IP_VERSION(5, 0, 0):/* NAVI10 */ 84 case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */ 85 case IP_VERSION(5, 0, 2):/* NAVI14 */ 86 case IP_VERSION(5, 0, 5):/* NAVI12 */ 87 case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */ 88 case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */ 89 case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */ 90 case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */ 91 case IP_VERSION(6, 0, 0): 92 case IP_VERSION(6, 0, 1): 93 case IP_VERSION(6, 0, 2): 94 case IP_VERSION(6, 0, 3): 95 kfd->device_info.num_sdma_queues_per_engine = 8; 96 break; 97 default: 98 dev_warn(kfd_device, 99 "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n", 100 sdma_version); 101 kfd->device_info.num_sdma_queues_per_engine = 8; 102 } 103 104 switch (sdma_version) { 105 case IP_VERSION(6, 0, 0): 106 case IP_VERSION(6, 0, 2): 107 case IP_VERSION(6, 0, 3): 108 /* Reserve 1 for paging and 1 for gfx */ 109 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 110 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */ 111 kfd->device_info.reserved_sdma_queues_bitmap = 0xFULL; 112 break; 113 case IP_VERSION(6, 0, 1): 114 /* Reserve 1 for paging and 1 for gfx */ 115 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 116 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-0 queue-1; ... */ 117 kfd->device_info.reserved_sdma_queues_bitmap = 0x3ULL; 118 break; 119 default: 120 break; 121 } 122 } 123 124 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) 125 { 126 uint32_t gc_version = KFD_GC_VERSION(kfd); 127 128 switch (gc_version) { 129 case IP_VERSION(9, 0, 1): /* VEGA10 */ 130 case IP_VERSION(9, 1, 0): /* RAVEN */ 131 case IP_VERSION(9, 2, 1): /* VEGA12 */ 132 case IP_VERSION(9, 2, 2): /* RAVEN */ 133 case IP_VERSION(9, 3, 0): /* RENOIR */ 134 case IP_VERSION(9, 4, 0): /* VEGA20 */ 135 case IP_VERSION(9, 4, 1): /* ARCTURUS */ 136 case IP_VERSION(9, 4, 2): /* ALDEBARAN */ 137 case IP_VERSION(10, 3, 1): /* VANGOGH */ 138 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */ 139 case IP_VERSION(10, 3, 6): /* GC 10.3.6 */ 140 case IP_VERSION(10, 3, 7): /* GC 10.3.7 */ 141 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */ 142 case IP_VERSION(10, 1, 4): 143 case IP_VERSION(10, 1, 10): /* NAVI10 */ 144 case IP_VERSION(10, 1, 2): /* NAVI12 */ 145 case IP_VERSION(10, 1, 1): /* NAVI14 */ 146 case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */ 147 case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */ 148 case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */ 149 case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */ 150 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 151 break; 152 case IP_VERSION(11, 0, 0): 153 case IP_VERSION(11, 0, 1): 154 case IP_VERSION(11, 0, 2): 155 case IP_VERSION(11, 0, 3): 156 case IP_VERSION(11, 0, 4): 157 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 158 break; 159 default: 160 dev_warn(kfd_device, "v9 event interrupt handler is set due to " 161 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version); 162 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 163 } 164 } 165 166 static void kfd_device_info_init(struct kfd_dev *kfd, 167 bool vf, uint32_t gfx_target_version) 168 { 169 uint32_t gc_version = KFD_GC_VERSION(kfd); 170 uint32_t asic_type = kfd->adev->asic_type; 171 172 kfd->device_info.max_pasid_bits = 16; 173 kfd->device_info.max_no_of_hqd = 24; 174 kfd->device_info.num_of_watch_points = 4; 175 kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED; 176 kfd->device_info.gfx_target_version = gfx_target_version; 177 178 if (KFD_IS_SOC15(kfd)) { 179 kfd->device_info.doorbell_size = 8; 180 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t); 181 kfd->device_info.supports_cwsr = true; 182 183 kfd_device_info_set_sdma_info(kfd); 184 185 kfd_device_info_set_event_interrupt_class(kfd); 186 187 /* Raven */ 188 if (gc_version == IP_VERSION(9, 1, 0) || 189 gc_version == IP_VERSION(9, 2, 2)) 190 kfd->device_info.needs_iommu_device = true; 191 192 if (gc_version < IP_VERSION(11, 0, 0)) { 193 /* Navi2x+, Navi1x+ */ 194 if (gc_version == IP_VERSION(10, 3, 6)) 195 kfd->device_info.no_atomic_fw_version = 14; 196 else if (gc_version == IP_VERSION(10, 3, 7)) 197 kfd->device_info.no_atomic_fw_version = 3; 198 else if (gc_version >= IP_VERSION(10, 3, 0)) 199 kfd->device_info.no_atomic_fw_version = 92; 200 else if (gc_version >= IP_VERSION(10, 1, 1)) 201 kfd->device_info.no_atomic_fw_version = 145; 202 203 /* Navi1x+ */ 204 if (gc_version >= IP_VERSION(10, 1, 1)) 205 kfd->device_info.needs_pci_atomics = true; 206 } 207 } else { 208 kfd->device_info.doorbell_size = 4; 209 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t); 210 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik; 211 kfd->device_info.num_sdma_queues_per_engine = 2; 212 213 if (asic_type != CHIP_KAVERI && 214 asic_type != CHIP_HAWAII && 215 asic_type != CHIP_TONGA) 216 kfd->device_info.supports_cwsr = true; 217 218 if (asic_type == CHIP_KAVERI || 219 asic_type == CHIP_CARRIZO) 220 kfd->device_info.needs_iommu_device = true; 221 222 if (asic_type != CHIP_HAWAII && !vf) 223 kfd->device_info.needs_pci_atomics = true; 224 } 225 } 226 227 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 228 { 229 struct kfd_dev *kfd = NULL; 230 const struct kfd2kgd_calls *f2g = NULL; 231 uint32_t gfx_target_version = 0; 232 233 switch (adev->asic_type) { 234 #ifdef KFD_SUPPORT_IOMMU_V2 235 #ifdef CONFIG_DRM_AMDGPU_CIK 236 case CHIP_KAVERI: 237 gfx_target_version = 70000; 238 if (!vf) 239 f2g = &gfx_v7_kfd2kgd; 240 break; 241 #endif 242 case CHIP_CARRIZO: 243 gfx_target_version = 80001; 244 if (!vf) 245 f2g = &gfx_v8_kfd2kgd; 246 break; 247 #endif 248 #ifdef CONFIG_DRM_AMDGPU_CIK 249 case CHIP_HAWAII: 250 gfx_target_version = 70001; 251 if (!amdgpu_exp_hw_support) 252 pr_info( 253 "KFD support on Hawaii is experimental. See modparam exp_hw_support\n" 254 ); 255 else if (!vf) 256 f2g = &gfx_v7_kfd2kgd; 257 break; 258 #endif 259 case CHIP_TONGA: 260 gfx_target_version = 80002; 261 if (!vf) 262 f2g = &gfx_v8_kfd2kgd; 263 break; 264 case CHIP_FIJI: 265 case CHIP_POLARIS10: 266 gfx_target_version = 80003; 267 f2g = &gfx_v8_kfd2kgd; 268 break; 269 case CHIP_POLARIS11: 270 case CHIP_POLARIS12: 271 case CHIP_VEGAM: 272 gfx_target_version = 80003; 273 if (!vf) 274 f2g = &gfx_v8_kfd2kgd; 275 break; 276 default: 277 switch (adev->ip_versions[GC_HWIP][0]) { 278 /* Vega 10 */ 279 case IP_VERSION(9, 0, 1): 280 gfx_target_version = 90000; 281 f2g = &gfx_v9_kfd2kgd; 282 break; 283 #ifdef KFD_SUPPORT_IOMMU_V2 284 /* Raven */ 285 case IP_VERSION(9, 1, 0): 286 case IP_VERSION(9, 2, 2): 287 gfx_target_version = 90002; 288 if (!vf) 289 f2g = &gfx_v9_kfd2kgd; 290 break; 291 #endif 292 /* Vega12 */ 293 case IP_VERSION(9, 2, 1): 294 gfx_target_version = 90004; 295 if (!vf) 296 f2g = &gfx_v9_kfd2kgd; 297 break; 298 /* Renoir */ 299 case IP_VERSION(9, 3, 0): 300 gfx_target_version = 90012; 301 if (!vf) 302 f2g = &gfx_v9_kfd2kgd; 303 break; 304 /* Vega20 */ 305 case IP_VERSION(9, 4, 0): 306 gfx_target_version = 90006; 307 if (!vf) 308 f2g = &gfx_v9_kfd2kgd; 309 break; 310 /* Arcturus */ 311 case IP_VERSION(9, 4, 1): 312 gfx_target_version = 90008; 313 f2g = &arcturus_kfd2kgd; 314 break; 315 /* Aldebaran */ 316 case IP_VERSION(9, 4, 2): 317 gfx_target_version = 90010; 318 f2g = &aldebaran_kfd2kgd; 319 break; 320 /* Navi10 */ 321 case IP_VERSION(10, 1, 10): 322 gfx_target_version = 100100; 323 if (!vf) 324 f2g = &gfx_v10_kfd2kgd; 325 break; 326 /* Navi12 */ 327 case IP_VERSION(10, 1, 2): 328 gfx_target_version = 100101; 329 f2g = &gfx_v10_kfd2kgd; 330 break; 331 /* Navi14 */ 332 case IP_VERSION(10, 1, 1): 333 gfx_target_version = 100102; 334 if (!vf) 335 f2g = &gfx_v10_kfd2kgd; 336 break; 337 /* Cyan Skillfish */ 338 case IP_VERSION(10, 1, 3): 339 case IP_VERSION(10, 1, 4): 340 gfx_target_version = 100103; 341 if (!vf) 342 f2g = &gfx_v10_kfd2kgd; 343 break; 344 /* Sienna Cichlid */ 345 case IP_VERSION(10, 3, 0): 346 gfx_target_version = 100300; 347 f2g = &gfx_v10_3_kfd2kgd; 348 break; 349 /* Navy Flounder */ 350 case IP_VERSION(10, 3, 2): 351 gfx_target_version = 100301; 352 f2g = &gfx_v10_3_kfd2kgd; 353 break; 354 /* Van Gogh */ 355 case IP_VERSION(10, 3, 1): 356 gfx_target_version = 100303; 357 if (!vf) 358 f2g = &gfx_v10_3_kfd2kgd; 359 break; 360 /* Dimgrey Cavefish */ 361 case IP_VERSION(10, 3, 4): 362 gfx_target_version = 100302; 363 f2g = &gfx_v10_3_kfd2kgd; 364 break; 365 /* Beige Goby */ 366 case IP_VERSION(10, 3, 5): 367 gfx_target_version = 100304; 368 f2g = &gfx_v10_3_kfd2kgd; 369 break; 370 /* Yellow Carp */ 371 case IP_VERSION(10, 3, 3): 372 gfx_target_version = 100305; 373 if (!vf) 374 f2g = &gfx_v10_3_kfd2kgd; 375 break; 376 case IP_VERSION(10, 3, 6): 377 case IP_VERSION(10, 3, 7): 378 gfx_target_version = 100306; 379 if (!vf) 380 f2g = &gfx_v10_3_kfd2kgd; 381 break; 382 case IP_VERSION(11, 0, 0): 383 gfx_target_version = 110000; 384 f2g = &gfx_v11_kfd2kgd; 385 break; 386 case IP_VERSION(11, 0, 1): 387 case IP_VERSION(11, 0, 4): 388 gfx_target_version = 110003; 389 f2g = &gfx_v11_kfd2kgd; 390 break; 391 case IP_VERSION(11, 0, 2): 392 gfx_target_version = 110002; 393 f2g = &gfx_v11_kfd2kgd; 394 break; 395 case IP_VERSION(11, 0, 3): 396 /* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */ 397 gfx_target_version = 110001; 398 f2g = &gfx_v11_kfd2kgd; 399 break; 400 default: 401 break; 402 } 403 break; 404 } 405 406 if (!f2g) { 407 if (adev->ip_versions[GC_HWIP][0]) 408 dev_err(kfd_device, "GC IP %06x %s not supported in kfd\n", 409 adev->ip_versions[GC_HWIP][0], vf ? "VF" : ""); 410 else 411 dev_err(kfd_device, "%s %s not supported in kfd\n", 412 amdgpu_asic_name[adev->asic_type], vf ? "VF" : ""); 413 return NULL; 414 } 415 416 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 417 if (!kfd) 418 return NULL; 419 420 kfd->adev = adev; 421 kfd_device_info_init(kfd, vf, gfx_target_version); 422 kfd->init_complete = false; 423 kfd->kfd2kgd = f2g; 424 atomic_set(&kfd->compute_profile, 0); 425 426 mutex_init(&kfd->doorbell_mutex); 427 memset(&kfd->doorbell_available_index, 0, 428 sizeof(kfd->doorbell_available_index)); 429 430 atomic_set(&kfd->sram_ecc_flag, 0); 431 432 ida_init(&kfd->doorbell_ida); 433 434 return kfd; 435 } 436 437 static void kfd_cwsr_init(struct kfd_dev *kfd) 438 { 439 if (cwsr_enable && kfd->device_info.supports_cwsr) { 440 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) { 441 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE); 442 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 443 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 444 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) { 445 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE); 446 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 447 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 448 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) { 449 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) > PAGE_SIZE); 450 kfd->cwsr_isa = cwsr_trap_aldebaran_hex; 451 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); 452 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) { 453 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE); 454 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 455 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 456 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) { 457 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE); 458 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 459 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 460 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) { 461 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE); 462 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 463 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 464 } else { 465 BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE); 466 kfd->cwsr_isa = cwsr_trap_gfx11_hex; 467 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex); 468 } 469 470 kfd->cwsr_enabled = true; 471 } 472 } 473 474 static int kfd_gws_init(struct kfd_dev *kfd) 475 { 476 int ret = 0; 477 478 if (kfd->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 479 return 0; 480 481 if (hws_gws_support || (KFD_IS_SOC15(kfd) && 482 ((KFD_GC_VERSION(kfd) == IP_VERSION(9, 0, 1) 483 && kfd->mec2_fw_version >= 0x81b3) || 484 (KFD_GC_VERSION(kfd) <= IP_VERSION(9, 4, 0) 485 && kfd->mec2_fw_version >= 0x1b3) || 486 (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1) 487 && kfd->mec2_fw_version >= 0x30) || 488 (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) 489 && kfd->mec2_fw_version >= 0x28) || 490 (KFD_GC_VERSION(kfd) >= IP_VERSION(10, 3, 0) 491 && KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0) 492 && kfd->mec2_fw_version >= 0x6b)))) 493 ret = amdgpu_amdkfd_alloc_gws(kfd->adev, 494 kfd->adev->gds.gws_size, &kfd->gws); 495 496 return ret; 497 } 498 499 static void kfd_smi_init(struct kfd_dev *dev) 500 { 501 INIT_LIST_HEAD(&dev->smi_clients); 502 spin_lock_init(&dev->smi_lock); 503 } 504 505 bool kgd2kfd_device_init(struct kfd_dev *kfd, 506 const struct kgd2kfd_shared_resources *gpu_resources) 507 { 508 unsigned int size, map_process_packet_size; 509 510 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 511 KGD_ENGINE_MEC1); 512 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 513 KGD_ENGINE_MEC2); 514 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 515 KGD_ENGINE_SDMA1); 516 kfd->shared_resources = *gpu_resources; 517 518 kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 519 kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 520 kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd 521 - kfd->vm_info.first_vmid_kfd + 1; 522 523 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 524 * 32 and 64-bit requests are possible and must be 525 * supported. 526 */ 527 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev); 528 if (!kfd->pci_atomic_requested && 529 kfd->device_info.needs_pci_atomics && 530 (!kfd->device_info.no_atomic_fw_version || 531 kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) { 532 dev_info(kfd_device, 533 "skipped device %x:%x, PCI rejects atomics %d<%d\n", 534 kfd->adev->pdev->vendor, kfd->adev->pdev->device, 535 kfd->mec_fw_version, 536 kfd->device_info.no_atomic_fw_version); 537 return false; 538 } 539 540 /* Verify module parameters regarding mapped process number*/ 541 if (hws_max_conc_proc >= 0) 542 kfd->max_proc_per_quantum = min((u32)hws_max_conc_proc, kfd->vm_info.vmid_num_kfd); 543 else 544 kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd; 545 546 /* calculate max size of mqds needed for queues */ 547 size = max_num_of_queues_per_device * 548 kfd->device_info.mqd_size_aligned; 549 550 /* 551 * calculate max size of runlist packet. 552 * There can be only 2 packets at once 553 */ 554 map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ? 555 sizeof(struct pm4_mes_map_process_aldebaran) : 556 sizeof(struct pm4_mes_map_process); 557 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + 558 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 559 + sizeof(struct pm4_mes_runlist)) * 2; 560 561 /* Add size of HIQ & DIQ */ 562 size += KFD_KERNEL_QUEUE_SIZE * 2; 563 564 /* add another 512KB for all other allocations on gart (HPD, fences) */ 565 size += 512 * 1024; 566 567 if (amdgpu_amdkfd_alloc_gtt_mem( 568 kfd->adev, size, &kfd->gtt_mem, 569 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 570 false)) { 571 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 572 goto alloc_gtt_mem_failure; 573 } 574 575 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 576 577 /* Initialize GTT sa with 512 byte chunk size */ 578 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 579 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 580 goto kfd_gtt_sa_init_error; 581 } 582 583 if (kfd_doorbell_init(kfd)) { 584 dev_err(kfd_device, 585 "Error initializing doorbell aperture\n"); 586 goto kfd_doorbell_error; 587 } 588 589 if (amdgpu_use_xgmi_p2p) 590 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id; 591 592 kfd->noretry = kfd->adev->gmc.noretry; 593 594 if (kfd_interrupt_init(kfd)) { 595 dev_err(kfd_device, "Error initializing interrupts\n"); 596 goto kfd_interrupt_error; 597 } 598 599 kfd->dqm = device_queue_manager_init(kfd); 600 if (!kfd->dqm) { 601 dev_err(kfd_device, "Error initializing queue manager\n"); 602 goto device_queue_manager_error; 603 } 604 605 /* If supported on this device, allocate global GWS that is shared 606 * by all KFD processes 607 */ 608 if (kfd_gws_init(kfd)) { 609 dev_err(kfd_device, "Could not allocate %d gws\n", 610 kfd->adev->gds.gws_size); 611 goto gws_error; 612 } 613 614 /* If CRAT is broken, won't set iommu enabled */ 615 kfd_double_confirm_iommu_support(kfd); 616 617 if (kfd_iommu_device_init(kfd)) { 618 kfd->use_iommu_v2 = false; 619 dev_err(kfd_device, "Error initializing iommuv2\n"); 620 goto device_iommu_error; 621 } 622 623 kfd_cwsr_init(kfd); 624 625 svm_migrate_init(kfd->adev); 626 627 if (kgd2kfd_resume_iommu(kfd)) 628 goto device_iommu_error; 629 630 if (kfd_resume(kfd)) 631 goto kfd_resume_error; 632 633 amdgpu_amdkfd_get_local_mem_info(kfd->adev, &kfd->local_mem_info); 634 635 if (kfd_topology_add_device(kfd)) { 636 dev_err(kfd_device, "Error adding device to topology\n"); 637 goto kfd_topology_add_device_error; 638 } 639 640 kfd_smi_init(kfd); 641 642 kfd->init_complete = true; 643 dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, 644 kfd->adev->pdev->device); 645 646 pr_debug("Starting kfd with the following scheduling policy %d\n", 647 kfd->dqm->sched_policy); 648 649 goto out; 650 651 kfd_topology_add_device_error: 652 kfd_resume_error: 653 device_iommu_error: 654 gws_error: 655 device_queue_manager_uninit(kfd->dqm); 656 device_queue_manager_error: 657 kfd_interrupt_exit(kfd); 658 kfd_interrupt_error: 659 kfd_doorbell_fini(kfd); 660 kfd_doorbell_error: 661 kfd_gtt_sa_fini(kfd); 662 kfd_gtt_sa_init_error: 663 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 664 alloc_gtt_mem_failure: 665 if (kfd->gws) 666 amdgpu_amdkfd_free_gws(kfd->adev, kfd->gws); 667 dev_err(kfd_device, 668 "device %x:%x NOT added due to errors\n", 669 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 670 out: 671 return kfd->init_complete; 672 } 673 674 void kgd2kfd_device_exit(struct kfd_dev *kfd) 675 { 676 if (kfd->init_complete) { 677 device_queue_manager_uninit(kfd->dqm); 678 kfd_interrupt_exit(kfd); 679 kfd_topology_remove_device(kfd); 680 kfd_doorbell_fini(kfd); 681 ida_destroy(&kfd->doorbell_ida); 682 kfd_gtt_sa_fini(kfd); 683 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 684 if (kfd->gws) 685 amdgpu_amdkfd_free_gws(kfd->adev, kfd->gws); 686 } 687 688 kfree(kfd); 689 } 690 691 int kgd2kfd_pre_reset(struct kfd_dev *kfd) 692 { 693 if (!kfd->init_complete) 694 return 0; 695 696 kfd_smi_event_update_gpu_reset(kfd, false); 697 698 kfd->dqm->ops.pre_reset(kfd->dqm); 699 700 kgd2kfd_suspend(kfd, false); 701 702 kfd_signal_reset_event(kfd); 703 return 0; 704 } 705 706 /* 707 * Fix me. KFD won't be able to resume existing process for now. 708 * We will keep all existing process in a evicted state and 709 * wait the process to be terminated. 710 */ 711 712 int kgd2kfd_post_reset(struct kfd_dev *kfd) 713 { 714 int ret; 715 716 if (!kfd->init_complete) 717 return 0; 718 719 ret = kfd_resume(kfd); 720 if (ret) 721 return ret; 722 atomic_dec(&kfd_locked); 723 724 atomic_set(&kfd->sram_ecc_flag, 0); 725 726 kfd_smi_event_update_gpu_reset(kfd, true); 727 728 return 0; 729 } 730 731 bool kfd_is_locked(void) 732 { 733 return (atomic_read(&kfd_locked) > 0); 734 } 735 736 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 737 { 738 if (!kfd->init_complete) 739 return; 740 741 /* for runtime suspend, skip locking kfd */ 742 if (!run_pm) { 743 /* For first KFD device suspend all the KFD processes */ 744 if (atomic_inc_return(&kfd_locked) == 1) 745 kfd_suspend_all_processes(); 746 } 747 748 kfd->dqm->ops.stop(kfd->dqm); 749 kfd_iommu_suspend(kfd); 750 } 751 752 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 753 { 754 int ret, count; 755 756 if (!kfd->init_complete) 757 return 0; 758 759 ret = kfd_resume(kfd); 760 if (ret) 761 return ret; 762 763 /* for runtime resume, skip unlocking kfd */ 764 if (!run_pm) { 765 count = atomic_dec_return(&kfd_locked); 766 WARN_ONCE(count < 0, "KFD suspend / resume ref. error"); 767 if (count == 0) 768 ret = kfd_resume_all_processes(); 769 } 770 771 return ret; 772 } 773 774 int kgd2kfd_resume_iommu(struct kfd_dev *kfd) 775 { 776 int err = 0; 777 778 err = kfd_iommu_resume(kfd); 779 if (err) 780 dev_err(kfd_device, 781 "Failed to resume IOMMU for device %x:%x\n", 782 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 783 return err; 784 } 785 786 static int kfd_resume(struct kfd_dev *kfd) 787 { 788 int err = 0; 789 790 err = kfd->dqm->ops.start(kfd->dqm); 791 if (err) 792 dev_err(kfd_device, 793 "Error starting queue manager for device %x:%x\n", 794 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 795 796 return err; 797 } 798 799 static inline void kfd_queue_work(struct workqueue_struct *wq, 800 struct work_struct *work) 801 { 802 int cpu, new_cpu; 803 804 cpu = new_cpu = smp_processor_id(); 805 do { 806 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids; 807 if (cpu_to_node(new_cpu) == numa_node_id()) 808 break; 809 } while (cpu != new_cpu); 810 811 queue_work_on(new_cpu, wq, work); 812 } 813 814 /* This is called directly from KGD at ISR. */ 815 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 816 { 817 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE]; 818 bool is_patched = false; 819 unsigned long flags; 820 821 if (!kfd->init_complete) 822 return; 823 824 if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) { 825 dev_err_once(kfd_device, "Ring entry too small\n"); 826 return; 827 } 828 829 spin_lock_irqsave(&kfd->interrupt_lock, flags); 830 831 if (kfd->interrupts_active 832 && interrupt_is_wanted(kfd, ih_ring_entry, 833 patched_ihre, &is_patched) 834 && enqueue_ih_ring_entry(kfd, 835 is_patched ? patched_ihre : ih_ring_entry)) 836 kfd_queue_work(kfd->ih_wq, &kfd->interrupt_work); 837 838 spin_unlock_irqrestore(&kfd->interrupt_lock, flags); 839 } 840 841 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger) 842 { 843 struct kfd_process *p; 844 int r; 845 846 /* Because we are called from arbitrary context (workqueue) as opposed 847 * to process context, kfd_process could attempt to exit while we are 848 * running so the lookup function increments the process ref count. 849 */ 850 p = kfd_lookup_process_by_mm(mm); 851 if (!p) 852 return -ESRCH; 853 854 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 855 r = kfd_process_evict_queues(p, trigger); 856 857 kfd_unref_process(p); 858 return r; 859 } 860 861 int kgd2kfd_resume_mm(struct mm_struct *mm) 862 { 863 struct kfd_process *p; 864 int r; 865 866 /* Because we are called from arbitrary context (workqueue) as opposed 867 * to process context, kfd_process could attempt to exit while we are 868 * running so the lookup function increments the process ref count. 869 */ 870 p = kfd_lookup_process_by_mm(mm); 871 if (!p) 872 return -ESRCH; 873 874 r = kfd_process_restore_queues(p); 875 876 kfd_unref_process(p); 877 return r; 878 } 879 880 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 881 * prepare for safe eviction of KFD BOs that belong to the specified 882 * process. 883 * 884 * @mm: mm_struct that identifies the specified KFD process 885 * @fence: eviction fence attached to KFD process BOs 886 * 887 */ 888 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 889 struct dma_fence *fence) 890 { 891 struct kfd_process *p; 892 unsigned long active_time; 893 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 894 895 if (!fence) 896 return -EINVAL; 897 898 if (dma_fence_is_signaled(fence)) 899 return 0; 900 901 p = kfd_lookup_process_by_mm(mm); 902 if (!p) 903 return -ENODEV; 904 905 if (fence->seqno == p->last_eviction_seqno) 906 goto out; 907 908 p->last_eviction_seqno = fence->seqno; 909 910 /* Avoid KFD process starvation. Wait for at least 911 * PROCESS_ACTIVE_TIME_MS before evicting the process again 912 */ 913 active_time = get_jiffies_64() - p->last_restore_timestamp; 914 if (delay_jiffies > active_time) 915 delay_jiffies -= active_time; 916 else 917 delay_jiffies = 0; 918 919 /* During process initialization eviction_work.dwork is initialized 920 * to kfd_evict_bo_worker 921 */ 922 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 923 p->lead_thread->pid, delay_jiffies); 924 schedule_delayed_work(&p->eviction_work, delay_jiffies); 925 out: 926 kfd_unref_process(p); 927 return 0; 928 } 929 930 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 931 unsigned int chunk_size) 932 { 933 if (WARN_ON(buf_size < chunk_size)) 934 return -EINVAL; 935 if (WARN_ON(buf_size == 0)) 936 return -EINVAL; 937 if (WARN_ON(chunk_size == 0)) 938 return -EINVAL; 939 940 kfd->gtt_sa_chunk_size = chunk_size; 941 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 942 943 kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks, 944 GFP_KERNEL); 945 if (!kfd->gtt_sa_bitmap) 946 return -ENOMEM; 947 948 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 949 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 950 951 mutex_init(&kfd->gtt_sa_lock); 952 953 return 0; 954 } 955 956 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 957 { 958 mutex_destroy(&kfd->gtt_sa_lock); 959 bitmap_free(kfd->gtt_sa_bitmap); 960 } 961 962 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 963 unsigned int bit_num, 964 unsigned int chunk_size) 965 { 966 return start_addr + bit_num * chunk_size; 967 } 968 969 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 970 unsigned int bit_num, 971 unsigned int chunk_size) 972 { 973 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 974 } 975 976 int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size, 977 struct kfd_mem_obj **mem_obj) 978 { 979 unsigned int found, start_search, cur_size; 980 981 if (size == 0) 982 return -EINVAL; 983 984 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 985 return -ENOMEM; 986 987 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 988 if (!(*mem_obj)) 989 return -ENOMEM; 990 991 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 992 993 start_search = 0; 994 995 mutex_lock(&kfd->gtt_sa_lock); 996 997 kfd_gtt_restart_search: 998 /* Find the first chunk that is free */ 999 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1000 kfd->gtt_sa_num_of_chunks, 1001 start_search); 1002 1003 pr_debug("Found = %d\n", found); 1004 1005 /* If there wasn't any free chunk, bail out */ 1006 if (found == kfd->gtt_sa_num_of_chunks) 1007 goto kfd_gtt_no_free_chunk; 1008 1009 /* Update fields of mem_obj */ 1010 (*mem_obj)->range_start = found; 1011 (*mem_obj)->range_end = found; 1012 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1013 kfd->gtt_start_gpu_addr, 1014 found, 1015 kfd->gtt_sa_chunk_size); 1016 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1017 kfd->gtt_start_cpu_ptr, 1018 found, 1019 kfd->gtt_sa_chunk_size); 1020 1021 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1022 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1023 1024 /* If we need only one chunk, mark it as allocated and get out */ 1025 if (size <= kfd->gtt_sa_chunk_size) { 1026 pr_debug("Single bit\n"); 1027 __set_bit(found, kfd->gtt_sa_bitmap); 1028 goto kfd_gtt_out; 1029 } 1030 1031 /* Otherwise, try to see if we have enough contiguous chunks */ 1032 cur_size = size - kfd->gtt_sa_chunk_size; 1033 do { 1034 (*mem_obj)->range_end = 1035 find_next_zero_bit(kfd->gtt_sa_bitmap, 1036 kfd->gtt_sa_num_of_chunks, ++found); 1037 /* 1038 * If next free chunk is not contiguous than we need to 1039 * restart our search from the last free chunk we found (which 1040 * wasn't contiguous to the previous ones 1041 */ 1042 if ((*mem_obj)->range_end != found) { 1043 start_search = found; 1044 goto kfd_gtt_restart_search; 1045 } 1046 1047 /* 1048 * If we reached end of buffer, bail out with error 1049 */ 1050 if (found == kfd->gtt_sa_num_of_chunks) 1051 goto kfd_gtt_no_free_chunk; 1052 1053 /* Check if we don't need another chunk */ 1054 if (cur_size <= kfd->gtt_sa_chunk_size) 1055 cur_size = 0; 1056 else 1057 cur_size -= kfd->gtt_sa_chunk_size; 1058 1059 } while (cur_size > 0); 1060 1061 pr_debug("range_start = %d, range_end = %d\n", 1062 (*mem_obj)->range_start, (*mem_obj)->range_end); 1063 1064 /* Mark the chunks as allocated */ 1065 bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start, 1066 (*mem_obj)->range_end - (*mem_obj)->range_start + 1); 1067 1068 kfd_gtt_out: 1069 mutex_unlock(&kfd->gtt_sa_lock); 1070 return 0; 1071 1072 kfd_gtt_no_free_chunk: 1073 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1074 mutex_unlock(&kfd->gtt_sa_lock); 1075 kfree(*mem_obj); 1076 return -ENOMEM; 1077 } 1078 1079 int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj) 1080 { 1081 /* Act like kfree when trying to free a NULL object */ 1082 if (!mem_obj) 1083 return 0; 1084 1085 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1086 mem_obj, mem_obj->range_start, mem_obj->range_end); 1087 1088 mutex_lock(&kfd->gtt_sa_lock); 1089 1090 /* Mark the chunks as free */ 1091 bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start, 1092 mem_obj->range_end - mem_obj->range_start + 1); 1093 1094 mutex_unlock(&kfd->gtt_sa_lock); 1095 1096 kfree(mem_obj); 1097 return 0; 1098 } 1099 1100 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1101 { 1102 if (kfd) 1103 atomic_inc(&kfd->sram_ecc_flag); 1104 } 1105 1106 void kfd_inc_compute_active(struct kfd_dev *kfd) 1107 { 1108 if (atomic_inc_return(&kfd->compute_profile) == 1) 1109 amdgpu_amdkfd_set_compute_idle(kfd->adev, false); 1110 } 1111 1112 void kfd_dec_compute_active(struct kfd_dev *kfd) 1113 { 1114 int count = atomic_dec_return(&kfd->compute_profile); 1115 1116 if (count == 0) 1117 amdgpu_amdkfd_set_compute_idle(kfd->adev, true); 1118 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1119 } 1120 1121 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 1122 { 1123 if (kfd && kfd->init_complete) 1124 kfd_smi_event_update_thermal_throttling(kfd, throttle_bitmask); 1125 } 1126 1127 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and 1128 * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA. 1129 * When the device has more than two engines, we reserve two for PCIe to enable 1130 * full-duplex and the rest are used as XGMI. 1131 */ 1132 unsigned int kfd_get_num_sdma_engines(struct kfd_dev *kdev) 1133 { 1134 /* If XGMI is not supported, all SDMA engines are PCIe */ 1135 if (!kdev->adev->gmc.xgmi.supported) 1136 return kdev->adev->sdma.num_instances; 1137 1138 return min(kdev->adev->sdma.num_instances, 2); 1139 } 1140 1141 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_dev *kdev) 1142 { 1143 /* After reserved for PCIe, the rest of engines are XGMI */ 1144 return kdev->adev->sdma.num_instances - kfd_get_num_sdma_engines(kdev); 1145 } 1146 1147 #if defined(CONFIG_DEBUG_FS) 1148 1149 /* This function will send a package to HIQ to hang the HWS 1150 * which will trigger a GPU reset and bring the HWS back to normal state 1151 */ 1152 int kfd_debugfs_hang_hws(struct kfd_dev *dev) 1153 { 1154 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1155 pr_err("HWS is not enabled"); 1156 return -EINVAL; 1157 } 1158 1159 return dqm_debugfs_hang_hws(dev->dqm); 1160 } 1161 1162 #endif 1163