1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/bsearch.h> 25 #include <linux/pci.h> 26 #include <linux/slab.h> 27 #include "kfd_priv.h" 28 #include "kfd_device_queue_manager.h" 29 #include "kfd_pm4_headers_vi.h" 30 #include "kfd_pm4_headers_aldebaran.h" 31 #include "cwsr_trap_handler.h" 32 #include "kfd_iommu.h" 33 #include "amdgpu_amdkfd.h" 34 #include "kfd_smi_events.h" 35 #include "kfd_migrate.h" 36 #include "amdgpu.h" 37 38 #define MQD_SIZE_ALIGNED 768 39 40 /* 41 * kfd_locked is used to lock the kfd driver during suspend or reset 42 * once locked, kfd driver will stop any further GPU execution. 43 * create process (open) will return -EAGAIN. 44 */ 45 static atomic_t kfd_locked = ATOMIC_INIT(0); 46 47 #ifdef CONFIG_DRM_AMDGPU_CIK 48 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 49 #endif 50 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 51 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 52 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 53 extern const struct kfd2kgd_calls aldebaran_kfd2kgd; 54 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 55 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 56 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd; 57 58 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 59 unsigned int chunk_size); 60 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 61 62 static int kfd_resume(struct kfd_dev *kfd); 63 64 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) 65 { 66 uint32_t sdma_version = kfd->adev->ip_versions[SDMA0_HWIP][0]; 67 68 switch (sdma_version) { 69 case IP_VERSION(4, 0, 0):/* VEGA10 */ 70 case IP_VERSION(4, 0, 1):/* VEGA12 */ 71 case IP_VERSION(4, 1, 0):/* RAVEN */ 72 case IP_VERSION(4, 1, 1):/* RAVEN */ 73 case IP_VERSION(4, 1, 2):/* RENOIR */ 74 case IP_VERSION(5, 2, 1):/* VANGOGH */ 75 case IP_VERSION(5, 2, 3):/* YELLOW_CARP */ 76 case IP_VERSION(5, 2, 6):/* GC 10.3.6 */ 77 case IP_VERSION(5, 2, 7):/* GC 10.3.7 */ 78 case IP_VERSION(6, 0, 1): 79 kfd->device_info.num_sdma_queues_per_engine = 2; 80 break; 81 case IP_VERSION(4, 2, 0):/* VEGA20 */ 82 case IP_VERSION(4, 2, 2):/* ARCTURUS */ 83 case IP_VERSION(4, 4, 0):/* ALDEBARAN */ 84 case IP_VERSION(5, 0, 0):/* NAVI10 */ 85 case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */ 86 case IP_VERSION(5, 0, 2):/* NAVI14 */ 87 case IP_VERSION(5, 0, 5):/* NAVI12 */ 88 case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */ 89 case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */ 90 case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */ 91 case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */ 92 case IP_VERSION(6, 0, 0): 93 case IP_VERSION(6, 0, 2): 94 kfd->device_info.num_sdma_queues_per_engine = 8; 95 break; 96 default: 97 dev_warn(kfd_device, 98 "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n", 99 sdma_version); 100 kfd->device_info.num_sdma_queues_per_engine = 8; 101 } 102 103 switch (sdma_version) { 104 case IP_VERSION(6, 0, 0): 105 case IP_VERSION(6, 0, 1): 106 case IP_VERSION(6, 0, 2): 107 /* Reserve 1 for paging and 1 for gfx */ 108 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 109 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */ 110 kfd->device_info.reserved_sdma_queues_bitmap = 0xFULL; 111 break; 112 default: 113 break; 114 } 115 } 116 117 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) 118 { 119 uint32_t gc_version = KFD_GC_VERSION(kfd); 120 121 switch (gc_version) { 122 case IP_VERSION(9, 0, 1): /* VEGA10 */ 123 case IP_VERSION(9, 1, 0): /* RAVEN */ 124 case IP_VERSION(9, 2, 1): /* VEGA12 */ 125 case IP_VERSION(9, 2, 2): /* RAVEN */ 126 case IP_VERSION(9, 3, 0): /* RENOIR */ 127 case IP_VERSION(9, 4, 0): /* VEGA20 */ 128 case IP_VERSION(9, 4, 1): /* ARCTURUS */ 129 case IP_VERSION(9, 4, 2): /* ALDEBARAN */ 130 case IP_VERSION(10, 3, 1): /* VANGOGH */ 131 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */ 132 case IP_VERSION(10, 3, 6): /* GC 10.3.6 */ 133 case IP_VERSION(10, 3, 7): /* GC 10.3.7 */ 134 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */ 135 case IP_VERSION(10, 1, 4): 136 case IP_VERSION(10, 1, 10): /* NAVI10 */ 137 case IP_VERSION(10, 1, 2): /* NAVI12 */ 138 case IP_VERSION(10, 1, 1): /* NAVI14 */ 139 case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */ 140 case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */ 141 case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */ 142 case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */ 143 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 144 break; 145 case IP_VERSION(11, 0, 0): 146 case IP_VERSION(11, 0, 1): 147 case IP_VERSION(11, 0, 2): 148 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 149 break; 150 default: 151 dev_warn(kfd_device, "v9 event interrupt handler is set due to " 152 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version); 153 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 154 } 155 } 156 157 static void kfd_device_info_init(struct kfd_dev *kfd, 158 bool vf, uint32_t gfx_target_version) 159 { 160 uint32_t gc_version = KFD_GC_VERSION(kfd); 161 uint32_t asic_type = kfd->adev->asic_type; 162 163 kfd->device_info.max_pasid_bits = 16; 164 kfd->device_info.max_no_of_hqd = 24; 165 kfd->device_info.num_of_watch_points = 4; 166 kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED; 167 kfd->device_info.gfx_target_version = gfx_target_version; 168 169 if (KFD_IS_SOC15(kfd)) { 170 kfd->device_info.doorbell_size = 8; 171 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t); 172 kfd->device_info.supports_cwsr = true; 173 174 kfd_device_info_set_sdma_info(kfd); 175 176 kfd_device_info_set_event_interrupt_class(kfd); 177 178 /* Raven */ 179 if (gc_version == IP_VERSION(9, 1, 0) || 180 gc_version == IP_VERSION(9, 2, 2)) 181 kfd->device_info.needs_iommu_device = true; 182 183 if (gc_version < IP_VERSION(11, 0, 0)) { 184 /* Navi2x+, Navi1x+ */ 185 if (gc_version == IP_VERSION(10, 3, 6)) 186 kfd->device_info.no_atomic_fw_version = 14; 187 else if (gc_version >= IP_VERSION(10, 3, 0)) 188 kfd->device_info.no_atomic_fw_version = 92; 189 else if (gc_version >= IP_VERSION(10, 1, 1)) 190 kfd->device_info.no_atomic_fw_version = 145; 191 192 /* Navi1x+ */ 193 if (gc_version >= IP_VERSION(10, 1, 1)) 194 kfd->device_info.needs_pci_atomics = true; 195 } 196 } else { 197 kfd->device_info.doorbell_size = 4; 198 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t); 199 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik; 200 kfd->device_info.num_sdma_queues_per_engine = 2; 201 202 if (asic_type != CHIP_KAVERI && 203 asic_type != CHIP_HAWAII && 204 asic_type != CHIP_TONGA) 205 kfd->device_info.supports_cwsr = true; 206 207 if (asic_type == CHIP_KAVERI || 208 asic_type == CHIP_CARRIZO) 209 kfd->device_info.needs_iommu_device = true; 210 211 if (asic_type != CHIP_HAWAII && !vf) 212 kfd->device_info.needs_pci_atomics = true; 213 } 214 } 215 216 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 217 { 218 struct kfd_dev *kfd = NULL; 219 const struct kfd2kgd_calls *f2g = NULL; 220 struct pci_dev *pdev = adev->pdev; 221 uint32_t gfx_target_version = 0; 222 223 switch (adev->asic_type) { 224 #ifdef KFD_SUPPORT_IOMMU_V2 225 #ifdef CONFIG_DRM_AMDGPU_CIK 226 case CHIP_KAVERI: 227 gfx_target_version = 70000; 228 if (!vf) 229 f2g = &gfx_v7_kfd2kgd; 230 break; 231 #endif 232 case CHIP_CARRIZO: 233 gfx_target_version = 80001; 234 if (!vf) 235 f2g = &gfx_v8_kfd2kgd; 236 break; 237 #endif 238 #ifdef CONFIG_DRM_AMDGPU_CIK 239 case CHIP_HAWAII: 240 gfx_target_version = 70001; 241 if (!amdgpu_exp_hw_support) 242 pr_info( 243 "KFD support on Hawaii is experimental. See modparam exp_hw_support\n" 244 ); 245 else if (!vf) 246 f2g = &gfx_v7_kfd2kgd; 247 break; 248 #endif 249 case CHIP_TONGA: 250 gfx_target_version = 80002; 251 if (!vf) 252 f2g = &gfx_v8_kfd2kgd; 253 break; 254 case CHIP_FIJI: 255 gfx_target_version = 80003; 256 f2g = &gfx_v8_kfd2kgd; 257 break; 258 case CHIP_POLARIS10: 259 gfx_target_version = 80003; 260 f2g = &gfx_v8_kfd2kgd; 261 break; 262 case CHIP_POLARIS11: 263 gfx_target_version = 80003; 264 if (!vf) 265 f2g = &gfx_v8_kfd2kgd; 266 break; 267 case CHIP_POLARIS12: 268 gfx_target_version = 80003; 269 if (!vf) 270 f2g = &gfx_v8_kfd2kgd; 271 break; 272 case CHIP_VEGAM: 273 gfx_target_version = 80003; 274 if (!vf) 275 f2g = &gfx_v8_kfd2kgd; 276 break; 277 default: 278 switch (adev->ip_versions[GC_HWIP][0]) { 279 /* Vega 10 */ 280 case IP_VERSION(9, 0, 1): 281 gfx_target_version = 90000; 282 f2g = &gfx_v9_kfd2kgd; 283 break; 284 #ifdef KFD_SUPPORT_IOMMU_V2 285 /* Raven */ 286 case IP_VERSION(9, 1, 0): 287 case IP_VERSION(9, 2, 2): 288 gfx_target_version = 90002; 289 if (!vf) 290 f2g = &gfx_v9_kfd2kgd; 291 break; 292 #endif 293 /* Vega12 */ 294 case IP_VERSION(9, 2, 1): 295 gfx_target_version = 90004; 296 if (!vf) 297 f2g = &gfx_v9_kfd2kgd; 298 break; 299 /* Renoir */ 300 case IP_VERSION(9, 3, 0): 301 gfx_target_version = 90012; 302 if (!vf) 303 f2g = &gfx_v9_kfd2kgd; 304 break; 305 /* Vega20 */ 306 case IP_VERSION(9, 4, 0): 307 gfx_target_version = 90006; 308 if (!vf) 309 f2g = &gfx_v9_kfd2kgd; 310 break; 311 /* Arcturus */ 312 case IP_VERSION(9, 4, 1): 313 gfx_target_version = 90008; 314 f2g = &arcturus_kfd2kgd; 315 break; 316 /* Aldebaran */ 317 case IP_VERSION(9, 4, 2): 318 gfx_target_version = 90010; 319 f2g = &aldebaran_kfd2kgd; 320 break; 321 /* Navi10 */ 322 case IP_VERSION(10, 1, 10): 323 gfx_target_version = 100100; 324 if (!vf) 325 f2g = &gfx_v10_kfd2kgd; 326 break; 327 /* Navi12 */ 328 case IP_VERSION(10, 1, 2): 329 gfx_target_version = 100101; 330 f2g = &gfx_v10_kfd2kgd; 331 break; 332 /* Navi14 */ 333 case IP_VERSION(10, 1, 1): 334 gfx_target_version = 100102; 335 if (!vf) 336 f2g = &gfx_v10_kfd2kgd; 337 break; 338 /* Cyan Skillfish */ 339 case IP_VERSION(10, 1, 3): 340 case IP_VERSION(10, 1, 4): 341 gfx_target_version = 100103; 342 if (!vf) 343 f2g = &gfx_v10_kfd2kgd; 344 break; 345 /* Sienna Cichlid */ 346 case IP_VERSION(10, 3, 0): 347 gfx_target_version = 100300; 348 f2g = &gfx_v10_3_kfd2kgd; 349 break; 350 /* Navy Flounder */ 351 case IP_VERSION(10, 3, 2): 352 gfx_target_version = 100301; 353 f2g = &gfx_v10_3_kfd2kgd; 354 break; 355 /* Van Gogh */ 356 case IP_VERSION(10, 3, 1): 357 gfx_target_version = 100303; 358 if (!vf) 359 f2g = &gfx_v10_3_kfd2kgd; 360 break; 361 /* Dimgrey Cavefish */ 362 case IP_VERSION(10, 3, 4): 363 gfx_target_version = 100302; 364 f2g = &gfx_v10_3_kfd2kgd; 365 break; 366 /* Beige Goby */ 367 case IP_VERSION(10, 3, 5): 368 gfx_target_version = 100304; 369 f2g = &gfx_v10_3_kfd2kgd; 370 break; 371 /* Yellow Carp */ 372 case IP_VERSION(10, 3, 3): 373 gfx_target_version = 100305; 374 if (!vf) 375 f2g = &gfx_v10_3_kfd2kgd; 376 break; 377 case IP_VERSION(10, 3, 6): 378 gfx_target_version = 100306; 379 if (!vf) 380 f2g = &gfx_v10_3_kfd2kgd; 381 break; 382 case IP_VERSION(10, 3, 7): 383 gfx_target_version = 100307; 384 if (!vf) 385 f2g = &gfx_v10_3_kfd2kgd; 386 break; 387 case IP_VERSION(11, 0, 0): 388 gfx_target_version = 110000; 389 f2g = &gfx_v11_kfd2kgd; 390 break; 391 case IP_VERSION(11, 0, 1): 392 gfx_target_version = 110003; 393 f2g = &gfx_v11_kfd2kgd; 394 break; 395 case IP_VERSION(11, 0, 2): 396 gfx_target_version = 110002; 397 f2g = &gfx_v11_kfd2kgd; 398 break; 399 default: 400 break; 401 } 402 break; 403 } 404 405 if (!f2g) { 406 if (adev->ip_versions[GC_HWIP][0]) 407 dev_err(kfd_device, "GC IP %06x %s not supported in kfd\n", 408 adev->ip_versions[GC_HWIP][0], vf ? "VF" : ""); 409 else 410 dev_err(kfd_device, "%s %s not supported in kfd\n", 411 amdgpu_asic_name[adev->asic_type], vf ? "VF" : ""); 412 return NULL; 413 } 414 415 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 416 if (!kfd) 417 return NULL; 418 419 kfd->adev = adev; 420 kfd_device_info_init(kfd, vf, gfx_target_version); 421 kfd->pdev = pdev; 422 kfd->init_complete = false; 423 kfd->kfd2kgd = f2g; 424 atomic_set(&kfd->compute_profile, 0); 425 426 mutex_init(&kfd->doorbell_mutex); 427 memset(&kfd->doorbell_available_index, 0, 428 sizeof(kfd->doorbell_available_index)); 429 430 atomic_set(&kfd->sram_ecc_flag, 0); 431 432 ida_init(&kfd->doorbell_ida); 433 434 return kfd; 435 } 436 437 static void kfd_cwsr_init(struct kfd_dev *kfd) 438 { 439 if (cwsr_enable && kfd->device_info.supports_cwsr) { 440 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) { 441 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE); 442 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 443 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 444 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) { 445 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE); 446 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 447 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 448 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) { 449 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) > PAGE_SIZE); 450 kfd->cwsr_isa = cwsr_trap_aldebaran_hex; 451 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); 452 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) { 453 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE); 454 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 455 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 456 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) { 457 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE); 458 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 459 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 460 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) { 461 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE); 462 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 463 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 464 } else { 465 BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE); 466 kfd->cwsr_isa = cwsr_trap_gfx11_hex; 467 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex); 468 } 469 470 kfd->cwsr_enabled = true; 471 } 472 } 473 474 static int kfd_gws_init(struct kfd_dev *kfd) 475 { 476 int ret = 0; 477 478 if (kfd->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 479 return 0; 480 481 if (hws_gws_support || (KFD_IS_SOC15(kfd) && 482 ((KFD_GC_VERSION(kfd) == IP_VERSION(9, 0, 1) 483 && kfd->mec2_fw_version >= 0x81b3) || 484 (KFD_GC_VERSION(kfd) <= IP_VERSION(9, 4, 0) 485 && kfd->mec2_fw_version >= 0x1b3) || 486 (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1) 487 && kfd->mec2_fw_version >= 0x30) || 488 (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) 489 && kfd->mec2_fw_version >= 0x28)))) 490 ret = amdgpu_amdkfd_alloc_gws(kfd->adev, 491 kfd->adev->gds.gws_size, &kfd->gws); 492 493 return ret; 494 } 495 496 static void kfd_smi_init(struct kfd_dev *dev) 497 { 498 INIT_LIST_HEAD(&dev->smi_clients); 499 spin_lock_init(&dev->smi_lock); 500 } 501 502 bool kgd2kfd_device_init(struct kfd_dev *kfd, 503 struct drm_device *ddev, 504 const struct kgd2kfd_shared_resources *gpu_resources) 505 { 506 unsigned int size, map_process_packet_size; 507 508 kfd->ddev = ddev; 509 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 510 KGD_ENGINE_MEC1); 511 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 512 KGD_ENGINE_MEC2); 513 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 514 KGD_ENGINE_SDMA1); 515 kfd->shared_resources = *gpu_resources; 516 517 kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 518 kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 519 kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd 520 - kfd->vm_info.first_vmid_kfd + 1; 521 522 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 523 * 32 and 64-bit requests are possible and must be 524 * supported. 525 */ 526 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev); 527 if (!kfd->pci_atomic_requested && 528 kfd->device_info.needs_pci_atomics && 529 (!kfd->device_info.no_atomic_fw_version || 530 kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) { 531 dev_info(kfd_device, 532 "skipped device %x:%x, PCI rejects atomics %d<%d\n", 533 kfd->pdev->vendor, kfd->pdev->device, 534 kfd->mec_fw_version, 535 kfd->device_info.no_atomic_fw_version); 536 return false; 537 } 538 539 /* Verify module parameters regarding mapped process number*/ 540 if (hws_max_conc_proc >= 0) 541 kfd->max_proc_per_quantum = min((u32)hws_max_conc_proc, kfd->vm_info.vmid_num_kfd); 542 else 543 kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd; 544 545 /* calculate max size of mqds needed for queues */ 546 size = max_num_of_queues_per_device * 547 kfd->device_info.mqd_size_aligned; 548 549 /* 550 * calculate max size of runlist packet. 551 * There can be only 2 packets at once 552 */ 553 map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ? 554 sizeof(struct pm4_mes_map_process_aldebaran) : 555 sizeof(struct pm4_mes_map_process); 556 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + 557 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 558 + sizeof(struct pm4_mes_runlist)) * 2; 559 560 /* Add size of HIQ & DIQ */ 561 size += KFD_KERNEL_QUEUE_SIZE * 2; 562 563 /* add another 512KB for all other allocations on gart (HPD, fences) */ 564 size += 512 * 1024; 565 566 if (amdgpu_amdkfd_alloc_gtt_mem( 567 kfd->adev, size, &kfd->gtt_mem, 568 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 569 false)) { 570 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 571 goto alloc_gtt_mem_failure; 572 } 573 574 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 575 576 /* Initialize GTT sa with 512 byte chunk size */ 577 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 578 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 579 goto kfd_gtt_sa_init_error; 580 } 581 582 if (kfd_doorbell_init(kfd)) { 583 dev_err(kfd_device, 584 "Error initializing doorbell aperture\n"); 585 goto kfd_doorbell_error; 586 } 587 588 if (amdgpu_use_xgmi_p2p) 589 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id; 590 591 kfd->noretry = kfd->adev->gmc.noretry; 592 593 if (kfd_interrupt_init(kfd)) { 594 dev_err(kfd_device, "Error initializing interrupts\n"); 595 goto kfd_interrupt_error; 596 } 597 598 kfd->dqm = device_queue_manager_init(kfd); 599 if (!kfd->dqm) { 600 dev_err(kfd_device, "Error initializing queue manager\n"); 601 goto device_queue_manager_error; 602 } 603 604 /* If supported on this device, allocate global GWS that is shared 605 * by all KFD processes 606 */ 607 if (kfd_gws_init(kfd)) { 608 dev_err(kfd_device, "Could not allocate %d gws\n", 609 kfd->adev->gds.gws_size); 610 goto gws_error; 611 } 612 613 /* If CRAT is broken, won't set iommu enabled */ 614 kfd_double_confirm_iommu_support(kfd); 615 616 if (kfd_iommu_device_init(kfd)) { 617 kfd->use_iommu_v2 = false; 618 dev_err(kfd_device, "Error initializing iommuv2\n"); 619 goto device_iommu_error; 620 } 621 622 kfd_cwsr_init(kfd); 623 624 svm_migrate_init(kfd->adev); 625 626 if (kgd2kfd_resume_iommu(kfd)) 627 goto device_iommu_error; 628 629 if (kfd_resume(kfd)) 630 goto kfd_resume_error; 631 632 amdgpu_amdkfd_get_local_mem_info(kfd->adev, &kfd->local_mem_info); 633 634 if (kfd_topology_add_device(kfd)) { 635 dev_err(kfd_device, "Error adding device to topology\n"); 636 goto kfd_topology_add_device_error; 637 } 638 639 kfd_smi_init(kfd); 640 641 kfd->init_complete = true; 642 dev_info(kfd_device, "added device %x:%x\n", kfd->pdev->vendor, 643 kfd->pdev->device); 644 645 pr_debug("Starting kfd with the following scheduling policy %d\n", 646 kfd->dqm->sched_policy); 647 648 goto out; 649 650 kfd_topology_add_device_error: 651 kfd_resume_error: 652 device_iommu_error: 653 gws_error: 654 device_queue_manager_uninit(kfd->dqm); 655 device_queue_manager_error: 656 kfd_interrupt_exit(kfd); 657 kfd_interrupt_error: 658 kfd_doorbell_fini(kfd); 659 kfd_doorbell_error: 660 kfd_gtt_sa_fini(kfd); 661 kfd_gtt_sa_init_error: 662 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 663 alloc_gtt_mem_failure: 664 if (kfd->gws) 665 amdgpu_amdkfd_free_gws(kfd->adev, kfd->gws); 666 dev_err(kfd_device, 667 "device %x:%x NOT added due to errors\n", 668 kfd->pdev->vendor, kfd->pdev->device); 669 out: 670 return kfd->init_complete; 671 } 672 673 void kgd2kfd_device_exit(struct kfd_dev *kfd) 674 { 675 if (kfd->init_complete) { 676 device_queue_manager_uninit(kfd->dqm); 677 kfd_interrupt_exit(kfd); 678 kfd_topology_remove_device(kfd); 679 kfd_doorbell_fini(kfd); 680 ida_destroy(&kfd->doorbell_ida); 681 kfd_gtt_sa_fini(kfd); 682 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 683 if (kfd->gws) 684 amdgpu_amdkfd_free_gws(kfd->adev, kfd->gws); 685 } 686 687 kfree(kfd); 688 } 689 690 int kgd2kfd_pre_reset(struct kfd_dev *kfd) 691 { 692 if (!kfd->init_complete) 693 return 0; 694 695 kfd_smi_event_update_gpu_reset(kfd, false); 696 697 kfd->dqm->ops.pre_reset(kfd->dqm); 698 699 kgd2kfd_suspend(kfd, false); 700 701 kfd_signal_reset_event(kfd); 702 return 0; 703 } 704 705 /* 706 * Fix me. KFD won't be able to resume existing process for now. 707 * We will keep all existing process in a evicted state and 708 * wait the process to be terminated. 709 */ 710 711 int kgd2kfd_post_reset(struct kfd_dev *kfd) 712 { 713 int ret; 714 715 if (!kfd->init_complete) 716 return 0; 717 718 ret = kfd_resume(kfd); 719 if (ret) 720 return ret; 721 atomic_dec(&kfd_locked); 722 723 atomic_set(&kfd->sram_ecc_flag, 0); 724 725 kfd_smi_event_update_gpu_reset(kfd, true); 726 727 return 0; 728 } 729 730 bool kfd_is_locked(void) 731 { 732 return (atomic_read(&kfd_locked) > 0); 733 } 734 735 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 736 { 737 if (!kfd->init_complete) 738 return; 739 740 /* for runtime suspend, skip locking kfd */ 741 if (!run_pm) { 742 /* For first KFD device suspend all the KFD processes */ 743 if (atomic_inc_return(&kfd_locked) == 1) 744 kfd_suspend_all_processes(); 745 } 746 747 kfd->dqm->ops.stop(kfd->dqm); 748 kfd_iommu_suspend(kfd); 749 } 750 751 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 752 { 753 int ret, count; 754 755 if (!kfd->init_complete) 756 return 0; 757 758 ret = kfd_resume(kfd); 759 if (ret) 760 return ret; 761 762 /* for runtime resume, skip unlocking kfd */ 763 if (!run_pm) { 764 count = atomic_dec_return(&kfd_locked); 765 WARN_ONCE(count < 0, "KFD suspend / resume ref. error"); 766 if (count == 0) 767 ret = kfd_resume_all_processes(); 768 } 769 770 return ret; 771 } 772 773 int kgd2kfd_resume_iommu(struct kfd_dev *kfd) 774 { 775 int err = 0; 776 777 err = kfd_iommu_resume(kfd); 778 if (err) 779 dev_err(kfd_device, 780 "Failed to resume IOMMU for device %x:%x\n", 781 kfd->pdev->vendor, kfd->pdev->device); 782 return err; 783 } 784 785 static int kfd_resume(struct kfd_dev *kfd) 786 { 787 int err = 0; 788 789 err = kfd->dqm->ops.start(kfd->dqm); 790 if (err) 791 dev_err(kfd_device, 792 "Error starting queue manager for device %x:%x\n", 793 kfd->pdev->vendor, kfd->pdev->device); 794 795 return err; 796 } 797 798 static inline void kfd_queue_work(struct workqueue_struct *wq, 799 struct work_struct *work) 800 { 801 int cpu, new_cpu; 802 803 cpu = new_cpu = smp_processor_id(); 804 do { 805 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids; 806 if (cpu_to_node(new_cpu) == numa_node_id()) 807 break; 808 } while (cpu != new_cpu); 809 810 queue_work_on(new_cpu, wq, work); 811 } 812 813 /* This is called directly from KGD at ISR. */ 814 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 815 { 816 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE]; 817 bool is_patched = false; 818 unsigned long flags; 819 820 if (!kfd->init_complete) 821 return; 822 823 if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) { 824 dev_err_once(kfd_device, "Ring entry too small\n"); 825 return; 826 } 827 828 spin_lock_irqsave(&kfd->interrupt_lock, flags); 829 830 if (kfd->interrupts_active 831 && interrupt_is_wanted(kfd, ih_ring_entry, 832 patched_ihre, &is_patched) 833 && enqueue_ih_ring_entry(kfd, 834 is_patched ? patched_ihre : ih_ring_entry)) 835 kfd_queue_work(kfd->ih_wq, &kfd->interrupt_work); 836 837 spin_unlock_irqrestore(&kfd->interrupt_lock, flags); 838 } 839 840 int kgd2kfd_quiesce_mm(struct mm_struct *mm) 841 { 842 struct kfd_process *p; 843 int r; 844 845 /* Because we are called from arbitrary context (workqueue) as opposed 846 * to process context, kfd_process could attempt to exit while we are 847 * running so the lookup function increments the process ref count. 848 */ 849 p = kfd_lookup_process_by_mm(mm); 850 if (!p) 851 return -ESRCH; 852 853 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 854 r = kfd_process_evict_queues(p); 855 856 kfd_unref_process(p); 857 return r; 858 } 859 860 int kgd2kfd_resume_mm(struct mm_struct *mm) 861 { 862 struct kfd_process *p; 863 int r; 864 865 /* Because we are called from arbitrary context (workqueue) as opposed 866 * to process context, kfd_process could attempt to exit while we are 867 * running so the lookup function increments the process ref count. 868 */ 869 p = kfd_lookup_process_by_mm(mm); 870 if (!p) 871 return -ESRCH; 872 873 r = kfd_process_restore_queues(p); 874 875 kfd_unref_process(p); 876 return r; 877 } 878 879 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 880 * prepare for safe eviction of KFD BOs that belong to the specified 881 * process. 882 * 883 * @mm: mm_struct that identifies the specified KFD process 884 * @fence: eviction fence attached to KFD process BOs 885 * 886 */ 887 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 888 struct dma_fence *fence) 889 { 890 struct kfd_process *p; 891 unsigned long active_time; 892 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 893 894 if (!fence) 895 return -EINVAL; 896 897 if (dma_fence_is_signaled(fence)) 898 return 0; 899 900 p = kfd_lookup_process_by_mm(mm); 901 if (!p) 902 return -ENODEV; 903 904 if (fence->seqno == p->last_eviction_seqno) 905 goto out; 906 907 p->last_eviction_seqno = fence->seqno; 908 909 /* Avoid KFD process starvation. Wait for at least 910 * PROCESS_ACTIVE_TIME_MS before evicting the process again 911 */ 912 active_time = get_jiffies_64() - p->last_restore_timestamp; 913 if (delay_jiffies > active_time) 914 delay_jiffies -= active_time; 915 else 916 delay_jiffies = 0; 917 918 /* During process initialization eviction_work.dwork is initialized 919 * to kfd_evict_bo_worker 920 */ 921 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 922 p->lead_thread->pid, delay_jiffies); 923 schedule_delayed_work(&p->eviction_work, delay_jiffies); 924 out: 925 kfd_unref_process(p); 926 return 0; 927 } 928 929 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 930 unsigned int chunk_size) 931 { 932 if (WARN_ON(buf_size < chunk_size)) 933 return -EINVAL; 934 if (WARN_ON(buf_size == 0)) 935 return -EINVAL; 936 if (WARN_ON(chunk_size == 0)) 937 return -EINVAL; 938 939 kfd->gtt_sa_chunk_size = chunk_size; 940 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 941 942 kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks, 943 GFP_KERNEL); 944 if (!kfd->gtt_sa_bitmap) 945 return -ENOMEM; 946 947 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 948 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 949 950 mutex_init(&kfd->gtt_sa_lock); 951 952 return 0; 953 } 954 955 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 956 { 957 mutex_destroy(&kfd->gtt_sa_lock); 958 bitmap_free(kfd->gtt_sa_bitmap); 959 } 960 961 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 962 unsigned int bit_num, 963 unsigned int chunk_size) 964 { 965 return start_addr + bit_num * chunk_size; 966 } 967 968 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 969 unsigned int bit_num, 970 unsigned int chunk_size) 971 { 972 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 973 } 974 975 int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size, 976 struct kfd_mem_obj **mem_obj) 977 { 978 unsigned int found, start_search, cur_size; 979 980 if (size == 0) 981 return -EINVAL; 982 983 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 984 return -ENOMEM; 985 986 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 987 if (!(*mem_obj)) 988 return -ENOMEM; 989 990 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 991 992 start_search = 0; 993 994 mutex_lock(&kfd->gtt_sa_lock); 995 996 kfd_gtt_restart_search: 997 /* Find the first chunk that is free */ 998 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 999 kfd->gtt_sa_num_of_chunks, 1000 start_search); 1001 1002 pr_debug("Found = %d\n", found); 1003 1004 /* If there wasn't any free chunk, bail out */ 1005 if (found == kfd->gtt_sa_num_of_chunks) 1006 goto kfd_gtt_no_free_chunk; 1007 1008 /* Update fields of mem_obj */ 1009 (*mem_obj)->range_start = found; 1010 (*mem_obj)->range_end = found; 1011 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1012 kfd->gtt_start_gpu_addr, 1013 found, 1014 kfd->gtt_sa_chunk_size); 1015 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1016 kfd->gtt_start_cpu_ptr, 1017 found, 1018 kfd->gtt_sa_chunk_size); 1019 1020 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1021 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1022 1023 /* If we need only one chunk, mark it as allocated and get out */ 1024 if (size <= kfd->gtt_sa_chunk_size) { 1025 pr_debug("Single bit\n"); 1026 __set_bit(found, kfd->gtt_sa_bitmap); 1027 goto kfd_gtt_out; 1028 } 1029 1030 /* Otherwise, try to see if we have enough contiguous chunks */ 1031 cur_size = size - kfd->gtt_sa_chunk_size; 1032 do { 1033 (*mem_obj)->range_end = 1034 find_next_zero_bit(kfd->gtt_sa_bitmap, 1035 kfd->gtt_sa_num_of_chunks, ++found); 1036 /* 1037 * If next free chunk is not contiguous than we need to 1038 * restart our search from the last free chunk we found (which 1039 * wasn't contiguous to the previous ones 1040 */ 1041 if ((*mem_obj)->range_end != found) { 1042 start_search = found; 1043 goto kfd_gtt_restart_search; 1044 } 1045 1046 /* 1047 * If we reached end of buffer, bail out with error 1048 */ 1049 if (found == kfd->gtt_sa_num_of_chunks) 1050 goto kfd_gtt_no_free_chunk; 1051 1052 /* Check if we don't need another chunk */ 1053 if (cur_size <= kfd->gtt_sa_chunk_size) 1054 cur_size = 0; 1055 else 1056 cur_size -= kfd->gtt_sa_chunk_size; 1057 1058 } while (cur_size > 0); 1059 1060 pr_debug("range_start = %d, range_end = %d\n", 1061 (*mem_obj)->range_start, (*mem_obj)->range_end); 1062 1063 /* Mark the chunks as allocated */ 1064 bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start, 1065 (*mem_obj)->range_end - (*mem_obj)->range_start + 1); 1066 1067 kfd_gtt_out: 1068 mutex_unlock(&kfd->gtt_sa_lock); 1069 return 0; 1070 1071 kfd_gtt_no_free_chunk: 1072 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1073 mutex_unlock(&kfd->gtt_sa_lock); 1074 kfree(*mem_obj); 1075 return -ENOMEM; 1076 } 1077 1078 int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj) 1079 { 1080 /* Act like kfree when trying to free a NULL object */ 1081 if (!mem_obj) 1082 return 0; 1083 1084 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1085 mem_obj, mem_obj->range_start, mem_obj->range_end); 1086 1087 mutex_lock(&kfd->gtt_sa_lock); 1088 1089 /* Mark the chunks as free */ 1090 bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start, 1091 mem_obj->range_end - mem_obj->range_start + 1); 1092 1093 mutex_unlock(&kfd->gtt_sa_lock); 1094 1095 kfree(mem_obj); 1096 return 0; 1097 } 1098 1099 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1100 { 1101 if (kfd) 1102 atomic_inc(&kfd->sram_ecc_flag); 1103 } 1104 1105 void kfd_inc_compute_active(struct kfd_dev *kfd) 1106 { 1107 if (atomic_inc_return(&kfd->compute_profile) == 1) 1108 amdgpu_amdkfd_set_compute_idle(kfd->adev, false); 1109 } 1110 1111 void kfd_dec_compute_active(struct kfd_dev *kfd) 1112 { 1113 int count = atomic_dec_return(&kfd->compute_profile); 1114 1115 if (count == 0) 1116 amdgpu_amdkfd_set_compute_idle(kfd->adev, true); 1117 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1118 } 1119 1120 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 1121 { 1122 if (kfd && kfd->init_complete) 1123 kfd_smi_event_update_thermal_throttling(kfd, throttle_bitmask); 1124 } 1125 1126 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and 1127 * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA. 1128 * When the device has more than two engines, we reserve two for PCIe to enable 1129 * full-duplex and the rest are used as XGMI. 1130 */ 1131 unsigned int kfd_get_num_sdma_engines(struct kfd_dev *kdev) 1132 { 1133 /* If XGMI is not supported, all SDMA engines are PCIe */ 1134 if (!kdev->adev->gmc.xgmi.supported) 1135 return kdev->adev->sdma.num_instances; 1136 1137 return min(kdev->adev->sdma.num_instances, 2); 1138 } 1139 1140 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_dev *kdev) 1141 { 1142 /* After reserved for PCIe, the rest of engines are XGMI */ 1143 return kdev->adev->sdma.num_instances - kfd_get_num_sdma_engines(kdev); 1144 } 1145 1146 #if defined(CONFIG_DEBUG_FS) 1147 1148 /* This function will send a package to HIQ to hang the HWS 1149 * which will trigger a GPU reset and bring the HWS back to normal state 1150 */ 1151 int kfd_debugfs_hang_hws(struct kfd_dev *dev) 1152 { 1153 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1154 pr_err("HWS is not enabled"); 1155 return -EINVAL; 1156 } 1157 1158 return dqm_debugfs_hang_hws(dev->dqm); 1159 } 1160 1161 #endif 1162