1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/bsearch.h> 24 #include <linux/pci.h> 25 #include <linux/slab.h> 26 #include "kfd_priv.h" 27 #include "kfd_device_queue_manager.h" 28 #include "kfd_pm4_headers_vi.h" 29 #include "kfd_pm4_headers_aldebaran.h" 30 #include "cwsr_trap_handler.h" 31 #include "kfd_iommu.h" 32 #include "amdgpu_amdkfd.h" 33 #include "kfd_smi_events.h" 34 #include "kfd_migrate.h" 35 36 #define MQD_SIZE_ALIGNED 768 37 38 /* 39 * kfd_locked is used to lock the kfd driver during suspend or reset 40 * once locked, kfd driver will stop any further GPU execution. 41 * create process (open) will return -EAGAIN. 42 */ 43 static atomic_t kfd_locked = ATOMIC_INIT(0); 44 45 #ifdef CONFIG_DRM_AMDGPU_CIK 46 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 47 #endif 48 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 49 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 50 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 51 extern const struct kfd2kgd_calls aldebaran_kfd2kgd; 52 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 53 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 54 55 static const struct kfd2kgd_calls *kfd2kgd_funcs[] = { 56 #ifdef KFD_SUPPORT_IOMMU_V2 57 #ifdef CONFIG_DRM_AMDGPU_CIK 58 [CHIP_KAVERI] = &gfx_v7_kfd2kgd, 59 #endif 60 [CHIP_CARRIZO] = &gfx_v8_kfd2kgd, 61 [CHIP_RAVEN] = &gfx_v9_kfd2kgd, 62 #endif 63 #ifdef CONFIG_DRM_AMDGPU_CIK 64 [CHIP_HAWAII] = &gfx_v7_kfd2kgd, 65 #endif 66 [CHIP_TONGA] = &gfx_v8_kfd2kgd, 67 [CHIP_FIJI] = &gfx_v8_kfd2kgd, 68 [CHIP_POLARIS10] = &gfx_v8_kfd2kgd, 69 [CHIP_POLARIS11] = &gfx_v8_kfd2kgd, 70 [CHIP_POLARIS12] = &gfx_v8_kfd2kgd, 71 [CHIP_VEGAM] = &gfx_v8_kfd2kgd, 72 [CHIP_VEGA10] = &gfx_v9_kfd2kgd, 73 [CHIP_VEGA12] = &gfx_v9_kfd2kgd, 74 [CHIP_VEGA20] = &gfx_v9_kfd2kgd, 75 [CHIP_RENOIR] = &gfx_v9_kfd2kgd, 76 [CHIP_ARCTURUS] = &arcturus_kfd2kgd, 77 [CHIP_ALDEBARAN] = &aldebaran_kfd2kgd, 78 [CHIP_NAVI10] = &gfx_v10_kfd2kgd, 79 [CHIP_NAVI12] = &gfx_v10_kfd2kgd, 80 [CHIP_NAVI14] = &gfx_v10_kfd2kgd, 81 [CHIP_SIENNA_CICHLID] = &gfx_v10_3_kfd2kgd, 82 [CHIP_NAVY_FLOUNDER] = &gfx_v10_3_kfd2kgd, 83 [CHIP_VANGOGH] = &gfx_v10_3_kfd2kgd, 84 [CHIP_DIMGREY_CAVEFISH] = &gfx_v10_3_kfd2kgd, 85 }; 86 87 #ifdef KFD_SUPPORT_IOMMU_V2 88 static const struct kfd_device_info kaveri_device_info = { 89 .asic_family = CHIP_KAVERI, 90 .asic_name = "kaveri", 91 .max_pasid_bits = 16, 92 /* max num of queues for KV.TODO should be a dynamic value */ 93 .max_no_of_hqd = 24, 94 .doorbell_size = 4, 95 .ih_ring_entry_size = 4 * sizeof(uint32_t), 96 .event_interrupt_class = &event_interrupt_class_cik, 97 .num_of_watch_points = 4, 98 .mqd_size_aligned = MQD_SIZE_ALIGNED, 99 .supports_cwsr = false, 100 .needs_iommu_device = true, 101 .needs_pci_atomics = false, 102 .num_sdma_engines = 2, 103 .num_xgmi_sdma_engines = 0, 104 .num_sdma_queues_per_engine = 2, 105 }; 106 107 static const struct kfd_device_info carrizo_device_info = { 108 .asic_family = CHIP_CARRIZO, 109 .asic_name = "carrizo", 110 .max_pasid_bits = 16, 111 /* max num of queues for CZ.TODO should be a dynamic value */ 112 .max_no_of_hqd = 24, 113 .doorbell_size = 4, 114 .ih_ring_entry_size = 4 * sizeof(uint32_t), 115 .event_interrupt_class = &event_interrupt_class_cik, 116 .num_of_watch_points = 4, 117 .mqd_size_aligned = MQD_SIZE_ALIGNED, 118 .supports_cwsr = true, 119 .needs_iommu_device = true, 120 .needs_pci_atomics = false, 121 .num_sdma_engines = 2, 122 .num_xgmi_sdma_engines = 0, 123 .num_sdma_queues_per_engine = 2, 124 }; 125 #endif 126 127 static const struct kfd_device_info raven_device_info = { 128 .asic_family = CHIP_RAVEN, 129 .asic_name = "raven", 130 .max_pasid_bits = 16, 131 .max_no_of_hqd = 24, 132 .doorbell_size = 8, 133 .ih_ring_entry_size = 8 * sizeof(uint32_t), 134 .event_interrupt_class = &event_interrupt_class_v9, 135 .num_of_watch_points = 4, 136 .mqd_size_aligned = MQD_SIZE_ALIGNED, 137 .supports_cwsr = true, 138 .needs_iommu_device = true, 139 .needs_pci_atomics = true, 140 .num_sdma_engines = 1, 141 .num_xgmi_sdma_engines = 0, 142 .num_sdma_queues_per_engine = 2, 143 }; 144 145 static const struct kfd_device_info hawaii_device_info = { 146 .asic_family = CHIP_HAWAII, 147 .asic_name = "hawaii", 148 .max_pasid_bits = 16, 149 /* max num of queues for KV.TODO should be a dynamic value */ 150 .max_no_of_hqd = 24, 151 .doorbell_size = 4, 152 .ih_ring_entry_size = 4 * sizeof(uint32_t), 153 .event_interrupt_class = &event_interrupt_class_cik, 154 .num_of_watch_points = 4, 155 .mqd_size_aligned = MQD_SIZE_ALIGNED, 156 .supports_cwsr = false, 157 .needs_iommu_device = false, 158 .needs_pci_atomics = false, 159 .num_sdma_engines = 2, 160 .num_xgmi_sdma_engines = 0, 161 .num_sdma_queues_per_engine = 2, 162 }; 163 164 static const struct kfd_device_info tonga_device_info = { 165 .asic_family = CHIP_TONGA, 166 .asic_name = "tonga", 167 .max_pasid_bits = 16, 168 .max_no_of_hqd = 24, 169 .doorbell_size = 4, 170 .ih_ring_entry_size = 4 * sizeof(uint32_t), 171 .event_interrupt_class = &event_interrupt_class_cik, 172 .num_of_watch_points = 4, 173 .mqd_size_aligned = MQD_SIZE_ALIGNED, 174 .supports_cwsr = false, 175 .needs_iommu_device = false, 176 .needs_pci_atomics = true, 177 .num_sdma_engines = 2, 178 .num_xgmi_sdma_engines = 0, 179 .num_sdma_queues_per_engine = 2, 180 }; 181 182 static const struct kfd_device_info fiji_device_info = { 183 .asic_family = CHIP_FIJI, 184 .asic_name = "fiji", 185 .max_pasid_bits = 16, 186 .max_no_of_hqd = 24, 187 .doorbell_size = 4, 188 .ih_ring_entry_size = 4 * sizeof(uint32_t), 189 .event_interrupt_class = &event_interrupt_class_cik, 190 .num_of_watch_points = 4, 191 .mqd_size_aligned = MQD_SIZE_ALIGNED, 192 .supports_cwsr = true, 193 .needs_iommu_device = false, 194 .needs_pci_atomics = true, 195 .num_sdma_engines = 2, 196 .num_xgmi_sdma_engines = 0, 197 .num_sdma_queues_per_engine = 2, 198 }; 199 200 static const struct kfd_device_info fiji_vf_device_info = { 201 .asic_family = CHIP_FIJI, 202 .asic_name = "fiji", 203 .max_pasid_bits = 16, 204 .max_no_of_hqd = 24, 205 .doorbell_size = 4, 206 .ih_ring_entry_size = 4 * sizeof(uint32_t), 207 .event_interrupt_class = &event_interrupt_class_cik, 208 .num_of_watch_points = 4, 209 .mqd_size_aligned = MQD_SIZE_ALIGNED, 210 .supports_cwsr = true, 211 .needs_iommu_device = false, 212 .needs_pci_atomics = false, 213 .num_sdma_engines = 2, 214 .num_xgmi_sdma_engines = 0, 215 .num_sdma_queues_per_engine = 2, 216 }; 217 218 219 static const struct kfd_device_info polaris10_device_info = { 220 .asic_family = CHIP_POLARIS10, 221 .asic_name = "polaris10", 222 .max_pasid_bits = 16, 223 .max_no_of_hqd = 24, 224 .doorbell_size = 4, 225 .ih_ring_entry_size = 4 * sizeof(uint32_t), 226 .event_interrupt_class = &event_interrupt_class_cik, 227 .num_of_watch_points = 4, 228 .mqd_size_aligned = MQD_SIZE_ALIGNED, 229 .supports_cwsr = true, 230 .needs_iommu_device = false, 231 .needs_pci_atomics = true, 232 .num_sdma_engines = 2, 233 .num_xgmi_sdma_engines = 0, 234 .num_sdma_queues_per_engine = 2, 235 }; 236 237 static const struct kfd_device_info polaris10_vf_device_info = { 238 .asic_family = CHIP_POLARIS10, 239 .asic_name = "polaris10", 240 .max_pasid_bits = 16, 241 .max_no_of_hqd = 24, 242 .doorbell_size = 4, 243 .ih_ring_entry_size = 4 * sizeof(uint32_t), 244 .event_interrupt_class = &event_interrupt_class_cik, 245 .num_of_watch_points = 4, 246 .mqd_size_aligned = MQD_SIZE_ALIGNED, 247 .supports_cwsr = true, 248 .needs_iommu_device = false, 249 .needs_pci_atomics = false, 250 .num_sdma_engines = 2, 251 .num_xgmi_sdma_engines = 0, 252 .num_sdma_queues_per_engine = 2, 253 }; 254 255 static const struct kfd_device_info polaris11_device_info = { 256 .asic_family = CHIP_POLARIS11, 257 .asic_name = "polaris11", 258 .max_pasid_bits = 16, 259 .max_no_of_hqd = 24, 260 .doorbell_size = 4, 261 .ih_ring_entry_size = 4 * sizeof(uint32_t), 262 .event_interrupt_class = &event_interrupt_class_cik, 263 .num_of_watch_points = 4, 264 .mqd_size_aligned = MQD_SIZE_ALIGNED, 265 .supports_cwsr = true, 266 .needs_iommu_device = false, 267 .needs_pci_atomics = true, 268 .num_sdma_engines = 2, 269 .num_xgmi_sdma_engines = 0, 270 .num_sdma_queues_per_engine = 2, 271 }; 272 273 static const struct kfd_device_info polaris12_device_info = { 274 .asic_family = CHIP_POLARIS12, 275 .asic_name = "polaris12", 276 .max_pasid_bits = 16, 277 .max_no_of_hqd = 24, 278 .doorbell_size = 4, 279 .ih_ring_entry_size = 4 * sizeof(uint32_t), 280 .event_interrupt_class = &event_interrupt_class_cik, 281 .num_of_watch_points = 4, 282 .mqd_size_aligned = MQD_SIZE_ALIGNED, 283 .supports_cwsr = true, 284 .needs_iommu_device = false, 285 .needs_pci_atomics = true, 286 .num_sdma_engines = 2, 287 .num_xgmi_sdma_engines = 0, 288 .num_sdma_queues_per_engine = 2, 289 }; 290 291 static const struct kfd_device_info vegam_device_info = { 292 .asic_family = CHIP_VEGAM, 293 .asic_name = "vegam", 294 .max_pasid_bits = 16, 295 .max_no_of_hqd = 24, 296 .doorbell_size = 4, 297 .ih_ring_entry_size = 4 * sizeof(uint32_t), 298 .event_interrupt_class = &event_interrupt_class_cik, 299 .num_of_watch_points = 4, 300 .mqd_size_aligned = MQD_SIZE_ALIGNED, 301 .supports_cwsr = true, 302 .needs_iommu_device = false, 303 .needs_pci_atomics = true, 304 .num_sdma_engines = 2, 305 .num_xgmi_sdma_engines = 0, 306 .num_sdma_queues_per_engine = 2, 307 }; 308 309 static const struct kfd_device_info vega10_device_info = { 310 .asic_family = CHIP_VEGA10, 311 .asic_name = "vega10", 312 .max_pasid_bits = 16, 313 .max_no_of_hqd = 24, 314 .doorbell_size = 8, 315 .ih_ring_entry_size = 8 * sizeof(uint32_t), 316 .event_interrupt_class = &event_interrupt_class_v9, 317 .num_of_watch_points = 4, 318 .mqd_size_aligned = MQD_SIZE_ALIGNED, 319 .supports_cwsr = true, 320 .needs_iommu_device = false, 321 .needs_pci_atomics = false, 322 .num_sdma_engines = 2, 323 .num_xgmi_sdma_engines = 0, 324 .num_sdma_queues_per_engine = 2, 325 }; 326 327 static const struct kfd_device_info vega10_vf_device_info = { 328 .asic_family = CHIP_VEGA10, 329 .asic_name = "vega10", 330 .max_pasid_bits = 16, 331 .max_no_of_hqd = 24, 332 .doorbell_size = 8, 333 .ih_ring_entry_size = 8 * sizeof(uint32_t), 334 .event_interrupt_class = &event_interrupt_class_v9, 335 .num_of_watch_points = 4, 336 .mqd_size_aligned = MQD_SIZE_ALIGNED, 337 .supports_cwsr = true, 338 .needs_iommu_device = false, 339 .needs_pci_atomics = false, 340 .num_sdma_engines = 2, 341 .num_xgmi_sdma_engines = 0, 342 .num_sdma_queues_per_engine = 2, 343 }; 344 345 static const struct kfd_device_info vega12_device_info = { 346 .asic_family = CHIP_VEGA12, 347 .asic_name = "vega12", 348 .max_pasid_bits = 16, 349 .max_no_of_hqd = 24, 350 .doorbell_size = 8, 351 .ih_ring_entry_size = 8 * sizeof(uint32_t), 352 .event_interrupt_class = &event_interrupt_class_v9, 353 .num_of_watch_points = 4, 354 .mqd_size_aligned = MQD_SIZE_ALIGNED, 355 .supports_cwsr = true, 356 .needs_iommu_device = false, 357 .needs_pci_atomics = false, 358 .num_sdma_engines = 2, 359 .num_xgmi_sdma_engines = 0, 360 .num_sdma_queues_per_engine = 2, 361 }; 362 363 static const struct kfd_device_info vega20_device_info = { 364 .asic_family = CHIP_VEGA20, 365 .asic_name = "vega20", 366 .max_pasid_bits = 16, 367 .max_no_of_hqd = 24, 368 .doorbell_size = 8, 369 .ih_ring_entry_size = 8 * sizeof(uint32_t), 370 .event_interrupt_class = &event_interrupt_class_v9, 371 .num_of_watch_points = 4, 372 .mqd_size_aligned = MQD_SIZE_ALIGNED, 373 .supports_cwsr = true, 374 .needs_iommu_device = false, 375 .needs_pci_atomics = false, 376 .num_sdma_engines = 2, 377 .num_xgmi_sdma_engines = 0, 378 .num_sdma_queues_per_engine = 8, 379 }; 380 381 static const struct kfd_device_info arcturus_device_info = { 382 .asic_family = CHIP_ARCTURUS, 383 .asic_name = "arcturus", 384 .max_pasid_bits = 16, 385 .max_no_of_hqd = 24, 386 .doorbell_size = 8, 387 .ih_ring_entry_size = 8 * sizeof(uint32_t), 388 .event_interrupt_class = &event_interrupt_class_v9, 389 .num_of_watch_points = 4, 390 .mqd_size_aligned = MQD_SIZE_ALIGNED, 391 .supports_cwsr = true, 392 .needs_iommu_device = false, 393 .needs_pci_atomics = false, 394 .num_sdma_engines = 2, 395 .num_xgmi_sdma_engines = 6, 396 .num_sdma_queues_per_engine = 8, 397 }; 398 399 static const struct kfd_device_info aldebaran_device_info = { 400 .asic_family = CHIP_ALDEBARAN, 401 .asic_name = "aldebaran", 402 .max_pasid_bits = 16, 403 .max_no_of_hqd = 24, 404 .doorbell_size = 8, 405 .ih_ring_entry_size = 8 * sizeof(uint32_t), 406 .event_interrupt_class = &event_interrupt_class_v9, 407 .num_of_watch_points = 4, 408 .mqd_size_aligned = MQD_SIZE_ALIGNED, 409 .supports_cwsr = true, 410 .needs_iommu_device = false, 411 .needs_pci_atomics = false, 412 .num_sdma_engines = 2, 413 .num_xgmi_sdma_engines = 3, 414 .num_sdma_queues_per_engine = 8, 415 }; 416 417 static const struct kfd_device_info renoir_device_info = { 418 .asic_family = CHIP_RENOIR, 419 .asic_name = "renoir", 420 .max_pasid_bits = 16, 421 .max_no_of_hqd = 24, 422 .doorbell_size = 8, 423 .ih_ring_entry_size = 8 * sizeof(uint32_t), 424 .event_interrupt_class = &event_interrupt_class_v9, 425 .num_of_watch_points = 4, 426 .mqd_size_aligned = MQD_SIZE_ALIGNED, 427 .supports_cwsr = true, 428 .needs_iommu_device = false, 429 .needs_pci_atomics = false, 430 .num_sdma_engines = 1, 431 .num_xgmi_sdma_engines = 0, 432 .num_sdma_queues_per_engine = 2, 433 }; 434 435 static const struct kfd_device_info navi10_device_info = { 436 .asic_family = CHIP_NAVI10, 437 .asic_name = "navi10", 438 .max_pasid_bits = 16, 439 .max_no_of_hqd = 24, 440 .doorbell_size = 8, 441 .ih_ring_entry_size = 8 * sizeof(uint32_t), 442 .event_interrupt_class = &event_interrupt_class_v9, 443 .num_of_watch_points = 4, 444 .mqd_size_aligned = MQD_SIZE_ALIGNED, 445 .needs_iommu_device = false, 446 .supports_cwsr = true, 447 .needs_pci_atomics = true, 448 .num_sdma_engines = 2, 449 .num_xgmi_sdma_engines = 0, 450 .num_sdma_queues_per_engine = 8, 451 }; 452 453 static const struct kfd_device_info navi12_device_info = { 454 .asic_family = CHIP_NAVI12, 455 .asic_name = "navi12", 456 .max_pasid_bits = 16, 457 .max_no_of_hqd = 24, 458 .doorbell_size = 8, 459 .ih_ring_entry_size = 8 * sizeof(uint32_t), 460 .event_interrupt_class = &event_interrupt_class_v9, 461 .num_of_watch_points = 4, 462 .mqd_size_aligned = MQD_SIZE_ALIGNED, 463 .needs_iommu_device = false, 464 .supports_cwsr = true, 465 .needs_pci_atomics = true, 466 .num_sdma_engines = 2, 467 .num_xgmi_sdma_engines = 0, 468 .num_sdma_queues_per_engine = 8, 469 }; 470 471 static const struct kfd_device_info navi14_device_info = { 472 .asic_family = CHIP_NAVI14, 473 .asic_name = "navi14", 474 .max_pasid_bits = 16, 475 .max_no_of_hqd = 24, 476 .doorbell_size = 8, 477 .ih_ring_entry_size = 8 * sizeof(uint32_t), 478 .event_interrupt_class = &event_interrupt_class_v9, 479 .num_of_watch_points = 4, 480 .mqd_size_aligned = MQD_SIZE_ALIGNED, 481 .needs_iommu_device = false, 482 .supports_cwsr = true, 483 .needs_pci_atomics = true, 484 .num_sdma_engines = 2, 485 .num_xgmi_sdma_engines = 0, 486 .num_sdma_queues_per_engine = 8, 487 }; 488 489 static const struct kfd_device_info sienna_cichlid_device_info = { 490 .asic_family = CHIP_SIENNA_CICHLID, 491 .asic_name = "sienna_cichlid", 492 .max_pasid_bits = 16, 493 .max_no_of_hqd = 24, 494 .doorbell_size = 8, 495 .ih_ring_entry_size = 8 * sizeof(uint32_t), 496 .event_interrupt_class = &event_interrupt_class_v9, 497 .num_of_watch_points = 4, 498 .mqd_size_aligned = MQD_SIZE_ALIGNED, 499 .needs_iommu_device = false, 500 .supports_cwsr = true, 501 .needs_pci_atomics = true, 502 .num_sdma_engines = 4, 503 .num_xgmi_sdma_engines = 0, 504 .num_sdma_queues_per_engine = 8, 505 }; 506 507 static const struct kfd_device_info navy_flounder_device_info = { 508 .asic_family = CHIP_NAVY_FLOUNDER, 509 .asic_name = "navy_flounder", 510 .max_pasid_bits = 16, 511 .max_no_of_hqd = 24, 512 .doorbell_size = 8, 513 .ih_ring_entry_size = 8 * sizeof(uint32_t), 514 .event_interrupt_class = &event_interrupt_class_v9, 515 .num_of_watch_points = 4, 516 .mqd_size_aligned = MQD_SIZE_ALIGNED, 517 .needs_iommu_device = false, 518 .supports_cwsr = true, 519 .needs_pci_atomics = true, 520 .num_sdma_engines = 2, 521 .num_xgmi_sdma_engines = 0, 522 .num_sdma_queues_per_engine = 8, 523 }; 524 525 static const struct kfd_device_info vangogh_device_info = { 526 .asic_family = CHIP_VANGOGH, 527 .asic_name = "vangogh", 528 .max_pasid_bits = 16, 529 .max_no_of_hqd = 24, 530 .doorbell_size = 8, 531 .ih_ring_entry_size = 8 * sizeof(uint32_t), 532 .event_interrupt_class = &event_interrupt_class_v9, 533 .num_of_watch_points = 4, 534 .mqd_size_aligned = MQD_SIZE_ALIGNED, 535 .needs_iommu_device = false, 536 .supports_cwsr = true, 537 .needs_pci_atomics = false, 538 .num_sdma_engines = 1, 539 .num_xgmi_sdma_engines = 0, 540 .num_sdma_queues_per_engine = 2, 541 }; 542 543 static const struct kfd_device_info dimgrey_cavefish_device_info = { 544 .asic_family = CHIP_DIMGREY_CAVEFISH, 545 .asic_name = "dimgrey_cavefish", 546 .max_pasid_bits = 16, 547 .max_no_of_hqd = 24, 548 .doorbell_size = 8, 549 .ih_ring_entry_size = 8 * sizeof(uint32_t), 550 .event_interrupt_class = &event_interrupt_class_v9, 551 .num_of_watch_points = 4, 552 .mqd_size_aligned = MQD_SIZE_ALIGNED, 553 .needs_iommu_device = false, 554 .supports_cwsr = true, 555 .needs_pci_atomics = true, 556 .num_sdma_engines = 2, 557 .num_xgmi_sdma_engines = 0, 558 .num_sdma_queues_per_engine = 8, 559 }; 560 561 562 /* For each entry, [0] is regular and [1] is virtualisation device. */ 563 static const struct kfd_device_info *kfd_supported_devices[][2] = { 564 #ifdef KFD_SUPPORT_IOMMU_V2 565 [CHIP_KAVERI] = {&kaveri_device_info, NULL}, 566 [CHIP_CARRIZO] = {&carrizo_device_info, NULL}, 567 #endif 568 [CHIP_RAVEN] = {&raven_device_info, NULL}, 569 [CHIP_HAWAII] = {&hawaii_device_info, NULL}, 570 [CHIP_TONGA] = {&tonga_device_info, NULL}, 571 [CHIP_FIJI] = {&fiji_device_info, &fiji_vf_device_info}, 572 [CHIP_POLARIS10] = {&polaris10_device_info, &polaris10_vf_device_info}, 573 [CHIP_POLARIS11] = {&polaris11_device_info, NULL}, 574 [CHIP_POLARIS12] = {&polaris12_device_info, NULL}, 575 [CHIP_VEGAM] = {&vegam_device_info, NULL}, 576 [CHIP_VEGA10] = {&vega10_device_info, &vega10_vf_device_info}, 577 [CHIP_VEGA12] = {&vega12_device_info, NULL}, 578 [CHIP_VEGA20] = {&vega20_device_info, NULL}, 579 [CHIP_RENOIR] = {&renoir_device_info, NULL}, 580 [CHIP_ARCTURUS] = {&arcturus_device_info, &arcturus_device_info}, 581 [CHIP_ALDEBARAN] = {&aldebaran_device_info, &aldebaran_device_info}, 582 [CHIP_NAVI10] = {&navi10_device_info, NULL}, 583 [CHIP_NAVI12] = {&navi12_device_info, &navi12_device_info}, 584 [CHIP_NAVI14] = {&navi14_device_info, NULL}, 585 [CHIP_SIENNA_CICHLID] = {&sienna_cichlid_device_info, &sienna_cichlid_device_info}, 586 [CHIP_NAVY_FLOUNDER] = {&navy_flounder_device_info, &navy_flounder_device_info}, 587 [CHIP_VANGOGH] = {&vangogh_device_info, NULL}, 588 [CHIP_DIMGREY_CAVEFISH] = {&dimgrey_cavefish_device_info, &dimgrey_cavefish_device_info}, 589 }; 590 591 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 592 unsigned int chunk_size); 593 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 594 595 static int kfd_resume(struct kfd_dev *kfd); 596 597 struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, 598 struct pci_dev *pdev, unsigned int asic_type, bool vf) 599 { 600 struct kfd_dev *kfd; 601 const struct kfd_device_info *device_info; 602 const struct kfd2kgd_calls *f2g; 603 604 if (asic_type >= sizeof(kfd_supported_devices) / (sizeof(void *) * 2) 605 || asic_type >= sizeof(kfd2kgd_funcs) / sizeof(void *)) { 606 dev_err(kfd_device, "asic_type %d out of range\n", asic_type); 607 return NULL; /* asic_type out of range */ 608 } 609 610 device_info = kfd_supported_devices[asic_type][vf]; 611 f2g = kfd2kgd_funcs[asic_type]; 612 613 if (!device_info || !f2g) { 614 dev_err(kfd_device, "%s %s not supported in kfd\n", 615 amdgpu_asic_name[asic_type], vf ? "VF" : ""); 616 return NULL; 617 } 618 619 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 620 if (!kfd) 621 return NULL; 622 623 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 624 * 32 and 64-bit requests are possible and must be 625 * supported. 626 */ 627 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kgd); 628 if (device_info->needs_pci_atomics && 629 !kfd->pci_atomic_requested) { 630 dev_info(kfd_device, 631 "skipped device %x:%x, PCI rejects atomics\n", 632 pdev->vendor, pdev->device); 633 kfree(kfd); 634 return NULL; 635 } 636 637 kfd->kgd = kgd; 638 kfd->device_info = device_info; 639 kfd->pdev = pdev; 640 kfd->init_complete = false; 641 kfd->kfd2kgd = f2g; 642 atomic_set(&kfd->compute_profile, 0); 643 644 mutex_init(&kfd->doorbell_mutex); 645 memset(&kfd->doorbell_available_index, 0, 646 sizeof(kfd->doorbell_available_index)); 647 648 atomic_set(&kfd->sram_ecc_flag, 0); 649 650 ida_init(&kfd->doorbell_ida); 651 652 return kfd; 653 } 654 655 static void kfd_cwsr_init(struct kfd_dev *kfd) 656 { 657 if (cwsr_enable && kfd->device_info->supports_cwsr) { 658 if (kfd->device_info->asic_family < CHIP_VEGA10) { 659 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE); 660 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 661 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 662 } else if (kfd->device_info->asic_family == CHIP_ARCTURUS) { 663 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE); 664 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 665 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 666 } else if (kfd->device_info->asic_family == CHIP_ALDEBARAN) { 667 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) > PAGE_SIZE); 668 kfd->cwsr_isa = cwsr_trap_aldebaran_hex; 669 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); 670 } else if (kfd->device_info->asic_family < CHIP_NAVI10) { 671 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE); 672 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 673 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 674 } else if (kfd->device_info->asic_family < CHIP_SIENNA_CICHLID) { 675 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE); 676 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 677 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 678 } else { 679 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE); 680 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 681 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 682 } 683 684 kfd->cwsr_enabled = true; 685 } 686 } 687 688 static int kfd_gws_init(struct kfd_dev *kfd) 689 { 690 int ret = 0; 691 692 if (kfd->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 693 return 0; 694 695 if (hws_gws_support 696 || (kfd->device_info->asic_family == CHIP_VEGA10 697 && kfd->mec2_fw_version >= 0x81b3) 698 || (kfd->device_info->asic_family >= CHIP_VEGA12 699 && kfd->device_info->asic_family <= CHIP_RAVEN 700 && kfd->mec2_fw_version >= 0x1b3) 701 || (kfd->device_info->asic_family == CHIP_ARCTURUS 702 && kfd->mec2_fw_version >= 0x30) 703 || (kfd->device_info->asic_family == CHIP_ALDEBARAN 704 && kfd->mec2_fw_version >= 0x28)) 705 ret = amdgpu_amdkfd_alloc_gws(kfd->kgd, 706 amdgpu_amdkfd_get_num_gws(kfd->kgd), &kfd->gws); 707 708 return ret; 709 } 710 711 static void kfd_smi_init(struct kfd_dev *dev) { 712 INIT_LIST_HEAD(&dev->smi_clients); 713 spin_lock_init(&dev->smi_lock); 714 } 715 716 bool kgd2kfd_device_init(struct kfd_dev *kfd, 717 struct drm_device *ddev, 718 const struct kgd2kfd_shared_resources *gpu_resources) 719 { 720 unsigned int size, map_process_packet_size; 721 722 kfd->ddev = ddev; 723 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd, 724 KGD_ENGINE_MEC1); 725 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd, 726 KGD_ENGINE_MEC2); 727 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd, 728 KGD_ENGINE_SDMA1); 729 kfd->shared_resources = *gpu_resources; 730 731 kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 732 kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 733 kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd 734 - kfd->vm_info.first_vmid_kfd + 1; 735 736 /* Verify module parameters regarding mapped process number*/ 737 if ((hws_max_conc_proc < 0) 738 || (hws_max_conc_proc > kfd->vm_info.vmid_num_kfd)) { 739 dev_err(kfd_device, 740 "hws_max_conc_proc %d must be between 0 and %d, use %d instead\n", 741 hws_max_conc_proc, kfd->vm_info.vmid_num_kfd, 742 kfd->vm_info.vmid_num_kfd); 743 kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd; 744 } else 745 kfd->max_proc_per_quantum = hws_max_conc_proc; 746 747 /* calculate max size of mqds needed for queues */ 748 size = max_num_of_queues_per_device * 749 kfd->device_info->mqd_size_aligned; 750 751 /* 752 * calculate max size of runlist packet. 753 * There can be only 2 packets at once 754 */ 755 map_process_packet_size = 756 kfd->device_info->asic_family == CHIP_ALDEBARAN ? 757 sizeof(struct pm4_mes_map_process_aldebaran) : 758 sizeof(struct pm4_mes_map_process); 759 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + 760 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 761 + sizeof(struct pm4_mes_runlist)) * 2; 762 763 /* Add size of HIQ & DIQ */ 764 size += KFD_KERNEL_QUEUE_SIZE * 2; 765 766 /* add another 512KB for all other allocations on gart (HPD, fences) */ 767 size += 512 * 1024; 768 769 if (amdgpu_amdkfd_alloc_gtt_mem( 770 kfd->kgd, size, &kfd->gtt_mem, 771 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 772 false)) { 773 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 774 goto alloc_gtt_mem_failure; 775 } 776 777 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 778 779 /* Initialize GTT sa with 512 byte chunk size */ 780 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 781 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 782 goto kfd_gtt_sa_init_error; 783 } 784 785 if (kfd_doorbell_init(kfd)) { 786 dev_err(kfd_device, 787 "Error initializing doorbell aperture\n"); 788 goto kfd_doorbell_error; 789 } 790 791 kfd->hive_id = amdgpu_amdkfd_get_hive_id(kfd->kgd); 792 793 kfd->noretry = amdgpu_amdkfd_get_noretry(kfd->kgd); 794 795 if (kfd_interrupt_init(kfd)) { 796 dev_err(kfd_device, "Error initializing interrupts\n"); 797 goto kfd_interrupt_error; 798 } 799 800 kfd->dqm = device_queue_manager_init(kfd); 801 if (!kfd->dqm) { 802 dev_err(kfd_device, "Error initializing queue manager\n"); 803 goto device_queue_manager_error; 804 } 805 806 /* If supported on this device, allocate global GWS that is shared 807 * by all KFD processes 808 */ 809 if (kfd_gws_init(kfd)) { 810 dev_err(kfd_device, "Could not allocate %d gws\n", 811 amdgpu_amdkfd_get_num_gws(kfd->kgd)); 812 goto gws_error; 813 } 814 815 /* If CRAT is broken, won't set iommu enabled */ 816 kfd_double_confirm_iommu_support(kfd); 817 818 if (kfd_iommu_device_init(kfd)) { 819 dev_err(kfd_device, "Error initializing iommuv2\n"); 820 goto device_iommu_error; 821 } 822 823 kfd_cwsr_init(kfd); 824 825 svm_migrate_init((struct amdgpu_device *)kfd->kgd); 826 827 if (kfd_resume(kfd)) 828 goto kfd_resume_error; 829 830 kfd->dbgmgr = NULL; 831 832 if (kfd_topology_add_device(kfd)) { 833 dev_err(kfd_device, "Error adding device to topology\n"); 834 goto kfd_topology_add_device_error; 835 } 836 837 kfd_smi_init(kfd); 838 839 kfd->init_complete = true; 840 dev_info(kfd_device, "added device %x:%x\n", kfd->pdev->vendor, 841 kfd->pdev->device); 842 843 pr_debug("Starting kfd with the following scheduling policy %d\n", 844 kfd->dqm->sched_policy); 845 846 goto out; 847 848 kfd_topology_add_device_error: 849 kfd_resume_error: 850 device_iommu_error: 851 gws_error: 852 device_queue_manager_uninit(kfd->dqm); 853 device_queue_manager_error: 854 kfd_interrupt_exit(kfd); 855 kfd_interrupt_error: 856 kfd_doorbell_fini(kfd); 857 kfd_doorbell_error: 858 kfd_gtt_sa_fini(kfd); 859 kfd_gtt_sa_init_error: 860 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem); 861 alloc_gtt_mem_failure: 862 if (kfd->gws) 863 amdgpu_amdkfd_free_gws(kfd->kgd, kfd->gws); 864 dev_err(kfd_device, 865 "device %x:%x NOT added due to errors\n", 866 kfd->pdev->vendor, kfd->pdev->device); 867 out: 868 return kfd->init_complete; 869 } 870 871 void kgd2kfd_device_exit(struct kfd_dev *kfd) 872 { 873 if (kfd->init_complete) { 874 kgd2kfd_suspend(kfd, false); 875 svm_migrate_fini((struct amdgpu_device *)kfd->kgd); 876 device_queue_manager_uninit(kfd->dqm); 877 kfd_interrupt_exit(kfd); 878 kfd_topology_remove_device(kfd); 879 kfd_doorbell_fini(kfd); 880 ida_destroy(&kfd->doorbell_ida); 881 kfd_gtt_sa_fini(kfd); 882 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem); 883 if (kfd->gws) 884 amdgpu_amdkfd_free_gws(kfd->kgd, kfd->gws); 885 } 886 887 kfree(kfd); 888 } 889 890 int kgd2kfd_pre_reset(struct kfd_dev *kfd) 891 { 892 if (!kfd->init_complete) 893 return 0; 894 895 kfd_smi_event_update_gpu_reset(kfd, false); 896 897 kfd->dqm->ops.pre_reset(kfd->dqm); 898 899 kgd2kfd_suspend(kfd, false); 900 901 kfd_signal_reset_event(kfd); 902 return 0; 903 } 904 905 /* 906 * Fix me. KFD won't be able to resume existing process for now. 907 * We will keep all existing process in a evicted state and 908 * wait the process to be terminated. 909 */ 910 911 int kgd2kfd_post_reset(struct kfd_dev *kfd) 912 { 913 int ret; 914 915 if (!kfd->init_complete) 916 return 0; 917 918 ret = kfd_resume(kfd); 919 if (ret) 920 return ret; 921 atomic_dec(&kfd_locked); 922 923 atomic_set(&kfd->sram_ecc_flag, 0); 924 925 kfd_smi_event_update_gpu_reset(kfd, true); 926 927 return 0; 928 } 929 930 bool kfd_is_locked(void) 931 { 932 return (atomic_read(&kfd_locked) > 0); 933 } 934 935 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 936 { 937 if (!kfd->init_complete) 938 return; 939 940 /* for runtime suspend, skip locking kfd */ 941 if (!run_pm) { 942 /* For first KFD device suspend all the KFD processes */ 943 if (atomic_inc_return(&kfd_locked) == 1) 944 kfd_suspend_all_processes(); 945 } 946 947 kfd->dqm->ops.stop(kfd->dqm); 948 kfd_iommu_suspend(kfd); 949 } 950 951 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 952 { 953 int ret, count; 954 955 if (!kfd->init_complete) 956 return 0; 957 958 ret = kfd_resume(kfd); 959 if (ret) 960 return ret; 961 962 /* for runtime resume, skip unlocking kfd */ 963 if (!run_pm) { 964 count = atomic_dec_return(&kfd_locked); 965 WARN_ONCE(count < 0, "KFD suspend / resume ref. error"); 966 if (count == 0) 967 ret = kfd_resume_all_processes(); 968 } 969 970 return ret; 971 } 972 973 static int kfd_resume(struct kfd_dev *kfd) 974 { 975 int err = 0; 976 977 err = kfd_iommu_resume(kfd); 978 if (err) { 979 dev_err(kfd_device, 980 "Failed to resume IOMMU for device %x:%x\n", 981 kfd->pdev->vendor, kfd->pdev->device); 982 return err; 983 } 984 985 err = kfd->dqm->ops.start(kfd->dqm); 986 if (err) { 987 dev_err(kfd_device, 988 "Error starting queue manager for device %x:%x\n", 989 kfd->pdev->vendor, kfd->pdev->device); 990 goto dqm_start_error; 991 } 992 993 return err; 994 995 dqm_start_error: 996 kfd_iommu_suspend(kfd); 997 return err; 998 } 999 1000 static inline void kfd_queue_work(struct workqueue_struct *wq, 1001 struct work_struct *work) 1002 { 1003 int cpu, new_cpu; 1004 1005 cpu = new_cpu = smp_processor_id(); 1006 do { 1007 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids; 1008 if (cpu_to_node(new_cpu) == numa_node_id()) 1009 break; 1010 } while (cpu != new_cpu); 1011 1012 queue_work_on(new_cpu, wq, work); 1013 } 1014 1015 /* This is called directly from KGD at ISR. */ 1016 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 1017 { 1018 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE]; 1019 bool is_patched = false; 1020 unsigned long flags; 1021 1022 if (!kfd->init_complete) 1023 return; 1024 1025 if (kfd->device_info->ih_ring_entry_size > sizeof(patched_ihre)) { 1026 dev_err_once(kfd_device, "Ring entry too small\n"); 1027 return; 1028 } 1029 1030 spin_lock_irqsave(&kfd->interrupt_lock, flags); 1031 1032 if (kfd->interrupts_active 1033 && interrupt_is_wanted(kfd, ih_ring_entry, 1034 patched_ihre, &is_patched) 1035 && enqueue_ih_ring_entry(kfd, 1036 is_patched ? patched_ihre : ih_ring_entry)) 1037 kfd_queue_work(kfd->ih_wq, &kfd->interrupt_work); 1038 1039 spin_unlock_irqrestore(&kfd->interrupt_lock, flags); 1040 } 1041 1042 int kgd2kfd_quiesce_mm(struct mm_struct *mm) 1043 { 1044 struct kfd_process *p; 1045 int r; 1046 1047 /* Because we are called from arbitrary context (workqueue) as opposed 1048 * to process context, kfd_process could attempt to exit while we are 1049 * running so the lookup function increments the process ref count. 1050 */ 1051 p = kfd_lookup_process_by_mm(mm); 1052 if (!p) 1053 return -ESRCH; 1054 1055 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 1056 r = kfd_process_evict_queues(p); 1057 1058 kfd_unref_process(p); 1059 return r; 1060 } 1061 1062 int kgd2kfd_resume_mm(struct mm_struct *mm) 1063 { 1064 struct kfd_process *p; 1065 int r; 1066 1067 /* Because we are called from arbitrary context (workqueue) as opposed 1068 * to process context, kfd_process could attempt to exit while we are 1069 * running so the lookup function increments the process ref count. 1070 */ 1071 p = kfd_lookup_process_by_mm(mm); 1072 if (!p) 1073 return -ESRCH; 1074 1075 r = kfd_process_restore_queues(p); 1076 1077 kfd_unref_process(p); 1078 return r; 1079 } 1080 1081 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 1082 * prepare for safe eviction of KFD BOs that belong to the specified 1083 * process. 1084 * 1085 * @mm: mm_struct that identifies the specified KFD process 1086 * @fence: eviction fence attached to KFD process BOs 1087 * 1088 */ 1089 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 1090 struct dma_fence *fence) 1091 { 1092 struct kfd_process *p; 1093 unsigned long active_time; 1094 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 1095 1096 if (!fence) 1097 return -EINVAL; 1098 1099 if (dma_fence_is_signaled(fence)) 1100 return 0; 1101 1102 p = kfd_lookup_process_by_mm(mm); 1103 if (!p) 1104 return -ENODEV; 1105 1106 if (fence->seqno == p->last_eviction_seqno) 1107 goto out; 1108 1109 p->last_eviction_seqno = fence->seqno; 1110 1111 /* Avoid KFD process starvation. Wait for at least 1112 * PROCESS_ACTIVE_TIME_MS before evicting the process again 1113 */ 1114 active_time = get_jiffies_64() - p->last_restore_timestamp; 1115 if (delay_jiffies > active_time) 1116 delay_jiffies -= active_time; 1117 else 1118 delay_jiffies = 0; 1119 1120 /* During process initialization eviction_work.dwork is initialized 1121 * to kfd_evict_bo_worker 1122 */ 1123 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 1124 p->lead_thread->pid, delay_jiffies); 1125 schedule_delayed_work(&p->eviction_work, delay_jiffies); 1126 out: 1127 kfd_unref_process(p); 1128 return 0; 1129 } 1130 1131 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 1132 unsigned int chunk_size) 1133 { 1134 unsigned int num_of_longs; 1135 1136 if (WARN_ON(buf_size < chunk_size)) 1137 return -EINVAL; 1138 if (WARN_ON(buf_size == 0)) 1139 return -EINVAL; 1140 if (WARN_ON(chunk_size == 0)) 1141 return -EINVAL; 1142 1143 kfd->gtt_sa_chunk_size = chunk_size; 1144 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 1145 1146 num_of_longs = (kfd->gtt_sa_num_of_chunks + BITS_PER_LONG - 1) / 1147 BITS_PER_LONG; 1148 1149 kfd->gtt_sa_bitmap = kcalloc(num_of_longs, sizeof(long), GFP_KERNEL); 1150 1151 if (!kfd->gtt_sa_bitmap) 1152 return -ENOMEM; 1153 1154 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 1155 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 1156 1157 mutex_init(&kfd->gtt_sa_lock); 1158 1159 return 0; 1160 1161 } 1162 1163 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 1164 { 1165 mutex_destroy(&kfd->gtt_sa_lock); 1166 kfree(kfd->gtt_sa_bitmap); 1167 } 1168 1169 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 1170 unsigned int bit_num, 1171 unsigned int chunk_size) 1172 { 1173 return start_addr + bit_num * chunk_size; 1174 } 1175 1176 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 1177 unsigned int bit_num, 1178 unsigned int chunk_size) 1179 { 1180 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 1181 } 1182 1183 int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size, 1184 struct kfd_mem_obj **mem_obj) 1185 { 1186 unsigned int found, start_search, cur_size; 1187 1188 if (size == 0) 1189 return -EINVAL; 1190 1191 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 1192 return -ENOMEM; 1193 1194 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 1195 if (!(*mem_obj)) 1196 return -ENOMEM; 1197 1198 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 1199 1200 start_search = 0; 1201 1202 mutex_lock(&kfd->gtt_sa_lock); 1203 1204 kfd_gtt_restart_search: 1205 /* Find the first chunk that is free */ 1206 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1207 kfd->gtt_sa_num_of_chunks, 1208 start_search); 1209 1210 pr_debug("Found = %d\n", found); 1211 1212 /* If there wasn't any free chunk, bail out */ 1213 if (found == kfd->gtt_sa_num_of_chunks) 1214 goto kfd_gtt_no_free_chunk; 1215 1216 /* Update fields of mem_obj */ 1217 (*mem_obj)->range_start = found; 1218 (*mem_obj)->range_end = found; 1219 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1220 kfd->gtt_start_gpu_addr, 1221 found, 1222 kfd->gtt_sa_chunk_size); 1223 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1224 kfd->gtt_start_cpu_ptr, 1225 found, 1226 kfd->gtt_sa_chunk_size); 1227 1228 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1229 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1230 1231 /* If we need only one chunk, mark it as allocated and get out */ 1232 if (size <= kfd->gtt_sa_chunk_size) { 1233 pr_debug("Single bit\n"); 1234 set_bit(found, kfd->gtt_sa_bitmap); 1235 goto kfd_gtt_out; 1236 } 1237 1238 /* Otherwise, try to see if we have enough contiguous chunks */ 1239 cur_size = size - kfd->gtt_sa_chunk_size; 1240 do { 1241 (*mem_obj)->range_end = 1242 find_next_zero_bit(kfd->gtt_sa_bitmap, 1243 kfd->gtt_sa_num_of_chunks, ++found); 1244 /* 1245 * If next free chunk is not contiguous than we need to 1246 * restart our search from the last free chunk we found (which 1247 * wasn't contiguous to the previous ones 1248 */ 1249 if ((*mem_obj)->range_end != found) { 1250 start_search = found; 1251 goto kfd_gtt_restart_search; 1252 } 1253 1254 /* 1255 * If we reached end of buffer, bail out with error 1256 */ 1257 if (found == kfd->gtt_sa_num_of_chunks) 1258 goto kfd_gtt_no_free_chunk; 1259 1260 /* Check if we don't need another chunk */ 1261 if (cur_size <= kfd->gtt_sa_chunk_size) 1262 cur_size = 0; 1263 else 1264 cur_size -= kfd->gtt_sa_chunk_size; 1265 1266 } while (cur_size > 0); 1267 1268 pr_debug("range_start = %d, range_end = %d\n", 1269 (*mem_obj)->range_start, (*mem_obj)->range_end); 1270 1271 /* Mark the chunks as allocated */ 1272 for (found = (*mem_obj)->range_start; 1273 found <= (*mem_obj)->range_end; 1274 found++) 1275 set_bit(found, kfd->gtt_sa_bitmap); 1276 1277 kfd_gtt_out: 1278 mutex_unlock(&kfd->gtt_sa_lock); 1279 return 0; 1280 1281 kfd_gtt_no_free_chunk: 1282 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1283 mutex_unlock(&kfd->gtt_sa_lock); 1284 kfree(*mem_obj); 1285 return -ENOMEM; 1286 } 1287 1288 int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj) 1289 { 1290 unsigned int bit; 1291 1292 /* Act like kfree when trying to free a NULL object */ 1293 if (!mem_obj) 1294 return 0; 1295 1296 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1297 mem_obj, mem_obj->range_start, mem_obj->range_end); 1298 1299 mutex_lock(&kfd->gtt_sa_lock); 1300 1301 /* Mark the chunks as free */ 1302 for (bit = mem_obj->range_start; 1303 bit <= mem_obj->range_end; 1304 bit++) 1305 clear_bit(bit, kfd->gtt_sa_bitmap); 1306 1307 mutex_unlock(&kfd->gtt_sa_lock); 1308 1309 kfree(mem_obj); 1310 return 0; 1311 } 1312 1313 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1314 { 1315 if (kfd) 1316 atomic_inc(&kfd->sram_ecc_flag); 1317 } 1318 1319 void kfd_inc_compute_active(struct kfd_dev *kfd) 1320 { 1321 if (atomic_inc_return(&kfd->compute_profile) == 1) 1322 amdgpu_amdkfd_set_compute_idle(kfd->kgd, false); 1323 } 1324 1325 void kfd_dec_compute_active(struct kfd_dev *kfd) 1326 { 1327 int count = atomic_dec_return(&kfd->compute_profile); 1328 1329 if (count == 0) 1330 amdgpu_amdkfd_set_compute_idle(kfd->kgd, true); 1331 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1332 } 1333 1334 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint32_t throttle_bitmask) 1335 { 1336 if (kfd && kfd->init_complete) 1337 kfd_smi_event_update_thermal_throttling(kfd, throttle_bitmask); 1338 } 1339 1340 #if defined(CONFIG_DEBUG_FS) 1341 1342 /* This function will send a package to HIQ to hang the HWS 1343 * which will trigger a GPU reset and bring the HWS back to normal state 1344 */ 1345 int kfd_debugfs_hang_hws(struct kfd_dev *dev) 1346 { 1347 int r = 0; 1348 1349 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1350 pr_err("HWS is not enabled"); 1351 return -EINVAL; 1352 } 1353 1354 r = pm_debugfs_hang_hws(&dev->dqm->packets); 1355 if (!r) 1356 r = dqm_debugfs_execute_queues(dev->dqm); 1357 1358 return r; 1359 } 1360 1361 #endif 1362