1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/bsearch.h> 24 #include <linux/pci.h> 25 #include <linux/slab.h> 26 #include "kfd_priv.h" 27 #include "kfd_device_queue_manager.h" 28 #include "kfd_pm4_headers_vi.h" 29 #include "kfd_pm4_headers_aldebaran.h" 30 #include "cwsr_trap_handler.h" 31 #include "kfd_iommu.h" 32 #include "amdgpu_amdkfd.h" 33 #include "kfd_smi_events.h" 34 #include "kfd_migrate.h" 35 36 #define MQD_SIZE_ALIGNED 768 37 38 /* 39 * kfd_locked is used to lock the kfd driver during suspend or reset 40 * once locked, kfd driver will stop any further GPU execution. 41 * create process (open) will return -EAGAIN. 42 */ 43 static atomic_t kfd_locked = ATOMIC_INIT(0); 44 45 #ifdef CONFIG_DRM_AMDGPU_CIK 46 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 47 #endif 48 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 49 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 50 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 51 extern const struct kfd2kgd_calls aldebaran_kfd2kgd; 52 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 53 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 54 55 static const struct kfd2kgd_calls *kfd2kgd_funcs[] = { 56 #ifdef KFD_SUPPORT_IOMMU_V2 57 #ifdef CONFIG_DRM_AMDGPU_CIK 58 [CHIP_KAVERI] = &gfx_v7_kfd2kgd, 59 #endif 60 [CHIP_CARRIZO] = &gfx_v8_kfd2kgd, 61 [CHIP_RAVEN] = &gfx_v9_kfd2kgd, 62 #endif 63 #ifdef CONFIG_DRM_AMDGPU_CIK 64 [CHIP_HAWAII] = &gfx_v7_kfd2kgd, 65 #endif 66 [CHIP_TONGA] = &gfx_v8_kfd2kgd, 67 [CHIP_FIJI] = &gfx_v8_kfd2kgd, 68 [CHIP_POLARIS10] = &gfx_v8_kfd2kgd, 69 [CHIP_POLARIS11] = &gfx_v8_kfd2kgd, 70 [CHIP_POLARIS12] = &gfx_v8_kfd2kgd, 71 [CHIP_VEGAM] = &gfx_v8_kfd2kgd, 72 [CHIP_VEGA10] = &gfx_v9_kfd2kgd, 73 [CHIP_VEGA12] = &gfx_v9_kfd2kgd, 74 [CHIP_VEGA20] = &gfx_v9_kfd2kgd, 75 [CHIP_RENOIR] = &gfx_v9_kfd2kgd, 76 [CHIP_ARCTURUS] = &arcturus_kfd2kgd, 77 [CHIP_ALDEBARAN] = &aldebaran_kfd2kgd, 78 [CHIP_NAVI10] = &gfx_v10_kfd2kgd, 79 [CHIP_NAVI12] = &gfx_v10_kfd2kgd, 80 [CHIP_NAVI14] = &gfx_v10_kfd2kgd, 81 [CHIP_SIENNA_CICHLID] = &gfx_v10_3_kfd2kgd, 82 [CHIP_NAVY_FLOUNDER] = &gfx_v10_3_kfd2kgd, 83 [CHIP_VANGOGH] = &gfx_v10_3_kfd2kgd, 84 [CHIP_DIMGREY_CAVEFISH] = &gfx_v10_3_kfd2kgd, 85 [CHIP_BEIGE_GOBY] = &gfx_v10_3_kfd2kgd, 86 [CHIP_YELLOW_CARP] = &gfx_v10_3_kfd2kgd, 87 [CHIP_CYAN_SKILLFISH] = &gfx_v10_kfd2kgd, 88 }; 89 90 #ifdef KFD_SUPPORT_IOMMU_V2 91 static const struct kfd_device_info kaveri_device_info = { 92 .asic_family = CHIP_KAVERI, 93 .asic_name = "kaveri", 94 .gfx_target_version = 70000, 95 .max_pasid_bits = 16, 96 /* max num of queues for KV.TODO should be a dynamic value */ 97 .max_no_of_hqd = 24, 98 .doorbell_size = 4, 99 .ih_ring_entry_size = 4 * sizeof(uint32_t), 100 .event_interrupt_class = &event_interrupt_class_cik, 101 .num_of_watch_points = 4, 102 .mqd_size_aligned = MQD_SIZE_ALIGNED, 103 .supports_cwsr = false, 104 .needs_iommu_device = true, 105 .needs_pci_atomics = false, 106 .num_sdma_engines = 2, 107 .num_xgmi_sdma_engines = 0, 108 .num_sdma_queues_per_engine = 2, 109 }; 110 111 static const struct kfd_device_info carrizo_device_info = { 112 .asic_family = CHIP_CARRIZO, 113 .asic_name = "carrizo", 114 .gfx_target_version = 80001, 115 .max_pasid_bits = 16, 116 /* max num of queues for CZ.TODO should be a dynamic value */ 117 .max_no_of_hqd = 24, 118 .doorbell_size = 4, 119 .ih_ring_entry_size = 4 * sizeof(uint32_t), 120 .event_interrupt_class = &event_interrupt_class_cik, 121 .num_of_watch_points = 4, 122 .mqd_size_aligned = MQD_SIZE_ALIGNED, 123 .supports_cwsr = true, 124 .needs_iommu_device = true, 125 .needs_pci_atomics = false, 126 .num_sdma_engines = 2, 127 .num_xgmi_sdma_engines = 0, 128 .num_sdma_queues_per_engine = 2, 129 }; 130 #endif 131 132 static const struct kfd_device_info raven_device_info = { 133 .asic_family = CHIP_RAVEN, 134 .asic_name = "raven", 135 .gfx_target_version = 90002, 136 .max_pasid_bits = 16, 137 .max_no_of_hqd = 24, 138 .doorbell_size = 8, 139 .ih_ring_entry_size = 8 * sizeof(uint32_t), 140 .event_interrupt_class = &event_interrupt_class_v9, 141 .num_of_watch_points = 4, 142 .mqd_size_aligned = MQD_SIZE_ALIGNED, 143 .supports_cwsr = true, 144 .needs_iommu_device = true, 145 .needs_pci_atomics = true, 146 .num_sdma_engines = 1, 147 .num_xgmi_sdma_engines = 0, 148 .num_sdma_queues_per_engine = 2, 149 }; 150 151 static const struct kfd_device_info hawaii_device_info = { 152 .asic_family = CHIP_HAWAII, 153 .asic_name = "hawaii", 154 .gfx_target_version = 70001, 155 .max_pasid_bits = 16, 156 /* max num of queues for KV.TODO should be a dynamic value */ 157 .max_no_of_hqd = 24, 158 .doorbell_size = 4, 159 .ih_ring_entry_size = 4 * sizeof(uint32_t), 160 .event_interrupt_class = &event_interrupt_class_cik, 161 .num_of_watch_points = 4, 162 .mqd_size_aligned = MQD_SIZE_ALIGNED, 163 .supports_cwsr = false, 164 .needs_iommu_device = false, 165 .needs_pci_atomics = false, 166 .num_sdma_engines = 2, 167 .num_xgmi_sdma_engines = 0, 168 .num_sdma_queues_per_engine = 2, 169 }; 170 171 static const struct kfd_device_info tonga_device_info = { 172 .asic_family = CHIP_TONGA, 173 .asic_name = "tonga", 174 .gfx_target_version = 80002, 175 .max_pasid_bits = 16, 176 .max_no_of_hqd = 24, 177 .doorbell_size = 4, 178 .ih_ring_entry_size = 4 * sizeof(uint32_t), 179 .event_interrupt_class = &event_interrupt_class_cik, 180 .num_of_watch_points = 4, 181 .mqd_size_aligned = MQD_SIZE_ALIGNED, 182 .supports_cwsr = false, 183 .needs_iommu_device = false, 184 .needs_pci_atomics = true, 185 .num_sdma_engines = 2, 186 .num_xgmi_sdma_engines = 0, 187 .num_sdma_queues_per_engine = 2, 188 }; 189 190 static const struct kfd_device_info fiji_device_info = { 191 .asic_family = CHIP_FIJI, 192 .asic_name = "fiji", 193 .gfx_target_version = 80003, 194 .max_pasid_bits = 16, 195 .max_no_of_hqd = 24, 196 .doorbell_size = 4, 197 .ih_ring_entry_size = 4 * sizeof(uint32_t), 198 .event_interrupt_class = &event_interrupt_class_cik, 199 .num_of_watch_points = 4, 200 .mqd_size_aligned = MQD_SIZE_ALIGNED, 201 .supports_cwsr = true, 202 .needs_iommu_device = false, 203 .needs_pci_atomics = true, 204 .num_sdma_engines = 2, 205 .num_xgmi_sdma_engines = 0, 206 .num_sdma_queues_per_engine = 2, 207 }; 208 209 static const struct kfd_device_info fiji_vf_device_info = { 210 .asic_family = CHIP_FIJI, 211 .asic_name = "fiji", 212 .gfx_target_version = 80003, 213 .max_pasid_bits = 16, 214 .max_no_of_hqd = 24, 215 .doorbell_size = 4, 216 .ih_ring_entry_size = 4 * sizeof(uint32_t), 217 .event_interrupt_class = &event_interrupt_class_cik, 218 .num_of_watch_points = 4, 219 .mqd_size_aligned = MQD_SIZE_ALIGNED, 220 .supports_cwsr = true, 221 .needs_iommu_device = false, 222 .needs_pci_atomics = false, 223 .num_sdma_engines = 2, 224 .num_xgmi_sdma_engines = 0, 225 .num_sdma_queues_per_engine = 2, 226 }; 227 228 229 static const struct kfd_device_info polaris10_device_info = { 230 .asic_family = CHIP_POLARIS10, 231 .asic_name = "polaris10", 232 .gfx_target_version = 80003, 233 .max_pasid_bits = 16, 234 .max_no_of_hqd = 24, 235 .doorbell_size = 4, 236 .ih_ring_entry_size = 4 * sizeof(uint32_t), 237 .event_interrupt_class = &event_interrupt_class_cik, 238 .num_of_watch_points = 4, 239 .mqd_size_aligned = MQD_SIZE_ALIGNED, 240 .supports_cwsr = true, 241 .needs_iommu_device = false, 242 .needs_pci_atomics = true, 243 .num_sdma_engines = 2, 244 .num_xgmi_sdma_engines = 0, 245 .num_sdma_queues_per_engine = 2, 246 }; 247 248 static const struct kfd_device_info polaris10_vf_device_info = { 249 .asic_family = CHIP_POLARIS10, 250 .asic_name = "polaris10", 251 .gfx_target_version = 80003, 252 .max_pasid_bits = 16, 253 .max_no_of_hqd = 24, 254 .doorbell_size = 4, 255 .ih_ring_entry_size = 4 * sizeof(uint32_t), 256 .event_interrupt_class = &event_interrupt_class_cik, 257 .num_of_watch_points = 4, 258 .mqd_size_aligned = MQD_SIZE_ALIGNED, 259 .supports_cwsr = true, 260 .needs_iommu_device = false, 261 .needs_pci_atomics = false, 262 .num_sdma_engines = 2, 263 .num_xgmi_sdma_engines = 0, 264 .num_sdma_queues_per_engine = 2, 265 }; 266 267 static const struct kfd_device_info polaris11_device_info = { 268 .asic_family = CHIP_POLARIS11, 269 .asic_name = "polaris11", 270 .gfx_target_version = 80003, 271 .max_pasid_bits = 16, 272 .max_no_of_hqd = 24, 273 .doorbell_size = 4, 274 .ih_ring_entry_size = 4 * sizeof(uint32_t), 275 .event_interrupt_class = &event_interrupt_class_cik, 276 .num_of_watch_points = 4, 277 .mqd_size_aligned = MQD_SIZE_ALIGNED, 278 .supports_cwsr = true, 279 .needs_iommu_device = false, 280 .needs_pci_atomics = true, 281 .num_sdma_engines = 2, 282 .num_xgmi_sdma_engines = 0, 283 .num_sdma_queues_per_engine = 2, 284 }; 285 286 static const struct kfd_device_info polaris12_device_info = { 287 .asic_family = CHIP_POLARIS12, 288 .asic_name = "polaris12", 289 .gfx_target_version = 80003, 290 .max_pasid_bits = 16, 291 .max_no_of_hqd = 24, 292 .doorbell_size = 4, 293 .ih_ring_entry_size = 4 * sizeof(uint32_t), 294 .event_interrupt_class = &event_interrupt_class_cik, 295 .num_of_watch_points = 4, 296 .mqd_size_aligned = MQD_SIZE_ALIGNED, 297 .supports_cwsr = true, 298 .needs_iommu_device = false, 299 .needs_pci_atomics = true, 300 .num_sdma_engines = 2, 301 .num_xgmi_sdma_engines = 0, 302 .num_sdma_queues_per_engine = 2, 303 }; 304 305 static const struct kfd_device_info vegam_device_info = { 306 .asic_family = CHIP_VEGAM, 307 .asic_name = "vegam", 308 .gfx_target_version = 80003, 309 .max_pasid_bits = 16, 310 .max_no_of_hqd = 24, 311 .doorbell_size = 4, 312 .ih_ring_entry_size = 4 * sizeof(uint32_t), 313 .event_interrupt_class = &event_interrupt_class_cik, 314 .num_of_watch_points = 4, 315 .mqd_size_aligned = MQD_SIZE_ALIGNED, 316 .supports_cwsr = true, 317 .needs_iommu_device = false, 318 .needs_pci_atomics = true, 319 .num_sdma_engines = 2, 320 .num_xgmi_sdma_engines = 0, 321 .num_sdma_queues_per_engine = 2, 322 }; 323 324 static const struct kfd_device_info vega10_device_info = { 325 .asic_family = CHIP_VEGA10, 326 .asic_name = "vega10", 327 .gfx_target_version = 90000, 328 .max_pasid_bits = 16, 329 .max_no_of_hqd = 24, 330 .doorbell_size = 8, 331 .ih_ring_entry_size = 8 * sizeof(uint32_t), 332 .event_interrupt_class = &event_interrupt_class_v9, 333 .num_of_watch_points = 4, 334 .mqd_size_aligned = MQD_SIZE_ALIGNED, 335 .supports_cwsr = true, 336 .needs_iommu_device = false, 337 .needs_pci_atomics = false, 338 .num_sdma_engines = 2, 339 .num_xgmi_sdma_engines = 0, 340 .num_sdma_queues_per_engine = 2, 341 }; 342 343 static const struct kfd_device_info vega10_vf_device_info = { 344 .asic_family = CHIP_VEGA10, 345 .asic_name = "vega10", 346 .gfx_target_version = 90000, 347 .max_pasid_bits = 16, 348 .max_no_of_hqd = 24, 349 .doorbell_size = 8, 350 .ih_ring_entry_size = 8 * sizeof(uint32_t), 351 .event_interrupt_class = &event_interrupt_class_v9, 352 .num_of_watch_points = 4, 353 .mqd_size_aligned = MQD_SIZE_ALIGNED, 354 .supports_cwsr = true, 355 .needs_iommu_device = false, 356 .needs_pci_atomics = false, 357 .num_sdma_engines = 2, 358 .num_xgmi_sdma_engines = 0, 359 .num_sdma_queues_per_engine = 2, 360 }; 361 362 static const struct kfd_device_info vega12_device_info = { 363 .asic_family = CHIP_VEGA12, 364 .asic_name = "vega12", 365 .gfx_target_version = 90004, 366 .max_pasid_bits = 16, 367 .max_no_of_hqd = 24, 368 .doorbell_size = 8, 369 .ih_ring_entry_size = 8 * sizeof(uint32_t), 370 .event_interrupt_class = &event_interrupt_class_v9, 371 .num_of_watch_points = 4, 372 .mqd_size_aligned = MQD_SIZE_ALIGNED, 373 .supports_cwsr = true, 374 .needs_iommu_device = false, 375 .needs_pci_atomics = false, 376 .num_sdma_engines = 2, 377 .num_xgmi_sdma_engines = 0, 378 .num_sdma_queues_per_engine = 2, 379 }; 380 381 static const struct kfd_device_info vega20_device_info = { 382 .asic_family = CHIP_VEGA20, 383 .asic_name = "vega20", 384 .gfx_target_version = 90006, 385 .max_pasid_bits = 16, 386 .max_no_of_hqd = 24, 387 .doorbell_size = 8, 388 .ih_ring_entry_size = 8 * sizeof(uint32_t), 389 .event_interrupt_class = &event_interrupt_class_v9, 390 .num_of_watch_points = 4, 391 .mqd_size_aligned = MQD_SIZE_ALIGNED, 392 .supports_cwsr = true, 393 .needs_iommu_device = false, 394 .needs_pci_atomics = false, 395 .num_sdma_engines = 2, 396 .num_xgmi_sdma_engines = 0, 397 .num_sdma_queues_per_engine = 8, 398 }; 399 400 static const struct kfd_device_info arcturus_device_info = { 401 .asic_family = CHIP_ARCTURUS, 402 .asic_name = "arcturus", 403 .gfx_target_version = 90008, 404 .max_pasid_bits = 16, 405 .max_no_of_hqd = 24, 406 .doorbell_size = 8, 407 .ih_ring_entry_size = 8 * sizeof(uint32_t), 408 .event_interrupt_class = &event_interrupt_class_v9, 409 .num_of_watch_points = 4, 410 .mqd_size_aligned = MQD_SIZE_ALIGNED, 411 .supports_cwsr = true, 412 .needs_iommu_device = false, 413 .needs_pci_atomics = false, 414 .num_sdma_engines = 2, 415 .num_xgmi_sdma_engines = 6, 416 .num_sdma_queues_per_engine = 8, 417 }; 418 419 static const struct kfd_device_info aldebaran_device_info = { 420 .asic_family = CHIP_ALDEBARAN, 421 .asic_name = "aldebaran", 422 .gfx_target_version = 90010, 423 .max_pasid_bits = 16, 424 .max_no_of_hqd = 24, 425 .doorbell_size = 8, 426 .ih_ring_entry_size = 8 * sizeof(uint32_t), 427 .event_interrupt_class = &event_interrupt_class_v9, 428 .num_of_watch_points = 4, 429 .mqd_size_aligned = MQD_SIZE_ALIGNED, 430 .supports_cwsr = true, 431 .needs_iommu_device = false, 432 .needs_pci_atomics = false, 433 .num_sdma_engines = 2, 434 .num_xgmi_sdma_engines = 3, 435 .num_sdma_queues_per_engine = 8, 436 }; 437 438 static const struct kfd_device_info renoir_device_info = { 439 .asic_family = CHIP_RENOIR, 440 .asic_name = "renoir", 441 .gfx_target_version = 90002, 442 .max_pasid_bits = 16, 443 .max_no_of_hqd = 24, 444 .doorbell_size = 8, 445 .ih_ring_entry_size = 8 * sizeof(uint32_t), 446 .event_interrupt_class = &event_interrupt_class_v9, 447 .num_of_watch_points = 4, 448 .mqd_size_aligned = MQD_SIZE_ALIGNED, 449 .supports_cwsr = true, 450 .needs_iommu_device = false, 451 .needs_pci_atomics = false, 452 .num_sdma_engines = 1, 453 .num_xgmi_sdma_engines = 0, 454 .num_sdma_queues_per_engine = 2, 455 }; 456 457 static const struct kfd_device_info navi10_device_info = { 458 .asic_family = CHIP_NAVI10, 459 .asic_name = "navi10", 460 .gfx_target_version = 100100, 461 .max_pasid_bits = 16, 462 .max_no_of_hqd = 24, 463 .doorbell_size = 8, 464 .ih_ring_entry_size = 8 * sizeof(uint32_t), 465 .event_interrupt_class = &event_interrupt_class_v9, 466 .num_of_watch_points = 4, 467 .mqd_size_aligned = MQD_SIZE_ALIGNED, 468 .needs_iommu_device = false, 469 .supports_cwsr = true, 470 .needs_pci_atomics = true, 471 .no_atomic_fw_version = 145, 472 .num_sdma_engines = 2, 473 .num_xgmi_sdma_engines = 0, 474 .num_sdma_queues_per_engine = 8, 475 }; 476 477 static const struct kfd_device_info navi12_device_info = { 478 .asic_family = CHIP_NAVI12, 479 .asic_name = "navi12", 480 .gfx_target_version = 100101, 481 .max_pasid_bits = 16, 482 .max_no_of_hqd = 24, 483 .doorbell_size = 8, 484 .ih_ring_entry_size = 8 * sizeof(uint32_t), 485 .event_interrupt_class = &event_interrupt_class_v9, 486 .num_of_watch_points = 4, 487 .mqd_size_aligned = MQD_SIZE_ALIGNED, 488 .needs_iommu_device = false, 489 .supports_cwsr = true, 490 .needs_pci_atomics = true, 491 .no_atomic_fw_version = 145, 492 .num_sdma_engines = 2, 493 .num_xgmi_sdma_engines = 0, 494 .num_sdma_queues_per_engine = 8, 495 }; 496 497 static const struct kfd_device_info navi14_device_info = { 498 .asic_family = CHIP_NAVI14, 499 .asic_name = "navi14", 500 .gfx_target_version = 100102, 501 .max_pasid_bits = 16, 502 .max_no_of_hqd = 24, 503 .doorbell_size = 8, 504 .ih_ring_entry_size = 8 * sizeof(uint32_t), 505 .event_interrupt_class = &event_interrupt_class_v9, 506 .num_of_watch_points = 4, 507 .mqd_size_aligned = MQD_SIZE_ALIGNED, 508 .needs_iommu_device = false, 509 .supports_cwsr = true, 510 .needs_pci_atomics = true, 511 .no_atomic_fw_version = 145, 512 .num_sdma_engines = 2, 513 .num_xgmi_sdma_engines = 0, 514 .num_sdma_queues_per_engine = 8, 515 }; 516 517 static const struct kfd_device_info sienna_cichlid_device_info = { 518 .asic_family = CHIP_SIENNA_CICHLID, 519 .asic_name = "sienna_cichlid", 520 .gfx_target_version = 100300, 521 .max_pasid_bits = 16, 522 .max_no_of_hqd = 24, 523 .doorbell_size = 8, 524 .ih_ring_entry_size = 8 * sizeof(uint32_t), 525 .event_interrupt_class = &event_interrupt_class_v9, 526 .num_of_watch_points = 4, 527 .mqd_size_aligned = MQD_SIZE_ALIGNED, 528 .needs_iommu_device = false, 529 .supports_cwsr = true, 530 .needs_pci_atomics = true, 531 .no_atomic_fw_version = 92, 532 .num_sdma_engines = 4, 533 .num_xgmi_sdma_engines = 0, 534 .num_sdma_queues_per_engine = 8, 535 }; 536 537 static const struct kfd_device_info navy_flounder_device_info = { 538 .asic_family = CHIP_NAVY_FLOUNDER, 539 .asic_name = "navy_flounder", 540 .gfx_target_version = 100301, 541 .max_pasid_bits = 16, 542 .max_no_of_hqd = 24, 543 .doorbell_size = 8, 544 .ih_ring_entry_size = 8 * sizeof(uint32_t), 545 .event_interrupt_class = &event_interrupt_class_v9, 546 .num_of_watch_points = 4, 547 .mqd_size_aligned = MQD_SIZE_ALIGNED, 548 .needs_iommu_device = false, 549 .supports_cwsr = true, 550 .needs_pci_atomics = true, 551 .no_atomic_fw_version = 92, 552 .num_sdma_engines = 2, 553 .num_xgmi_sdma_engines = 0, 554 .num_sdma_queues_per_engine = 8, 555 }; 556 557 static const struct kfd_device_info vangogh_device_info = { 558 .asic_family = CHIP_VANGOGH, 559 .asic_name = "vangogh", 560 .gfx_target_version = 100303, 561 .max_pasid_bits = 16, 562 .max_no_of_hqd = 24, 563 .doorbell_size = 8, 564 .ih_ring_entry_size = 8 * sizeof(uint32_t), 565 .event_interrupt_class = &event_interrupt_class_v9, 566 .num_of_watch_points = 4, 567 .mqd_size_aligned = MQD_SIZE_ALIGNED, 568 .needs_iommu_device = false, 569 .supports_cwsr = true, 570 .needs_pci_atomics = true, 571 .no_atomic_fw_version = 92, 572 .num_sdma_engines = 1, 573 .num_xgmi_sdma_engines = 0, 574 .num_sdma_queues_per_engine = 2, 575 }; 576 577 static const struct kfd_device_info dimgrey_cavefish_device_info = { 578 .asic_family = CHIP_DIMGREY_CAVEFISH, 579 .asic_name = "dimgrey_cavefish", 580 .gfx_target_version = 100302, 581 .max_pasid_bits = 16, 582 .max_no_of_hqd = 24, 583 .doorbell_size = 8, 584 .ih_ring_entry_size = 8 * sizeof(uint32_t), 585 .event_interrupt_class = &event_interrupt_class_v9, 586 .num_of_watch_points = 4, 587 .mqd_size_aligned = MQD_SIZE_ALIGNED, 588 .needs_iommu_device = false, 589 .supports_cwsr = true, 590 .needs_pci_atomics = true, 591 .no_atomic_fw_version = 92, 592 .num_sdma_engines = 2, 593 .num_xgmi_sdma_engines = 0, 594 .num_sdma_queues_per_engine = 8, 595 }; 596 597 static const struct kfd_device_info beige_goby_device_info = { 598 .asic_family = CHIP_BEIGE_GOBY, 599 .asic_name = "beige_goby", 600 .gfx_target_version = 100304, 601 .max_pasid_bits = 16, 602 .max_no_of_hqd = 24, 603 .doorbell_size = 8, 604 .ih_ring_entry_size = 8 * sizeof(uint32_t), 605 .event_interrupt_class = &event_interrupt_class_v9, 606 .num_of_watch_points = 4, 607 .mqd_size_aligned = MQD_SIZE_ALIGNED, 608 .needs_iommu_device = false, 609 .supports_cwsr = true, 610 .needs_pci_atomics = true, 611 .no_atomic_fw_version = 92, 612 .num_sdma_engines = 1, 613 .num_xgmi_sdma_engines = 0, 614 .num_sdma_queues_per_engine = 8, 615 }; 616 617 static const struct kfd_device_info yellow_carp_device_info = { 618 .asic_family = CHIP_YELLOW_CARP, 619 .asic_name = "yellow_carp", 620 .gfx_target_version = 100305, 621 .max_pasid_bits = 16, 622 .max_no_of_hqd = 24, 623 .doorbell_size = 8, 624 .ih_ring_entry_size = 8 * sizeof(uint32_t), 625 .event_interrupt_class = &event_interrupt_class_v9, 626 .num_of_watch_points = 4, 627 .mqd_size_aligned = MQD_SIZE_ALIGNED, 628 .needs_iommu_device = false, 629 .supports_cwsr = true, 630 .needs_pci_atomics = true, 631 .no_atomic_fw_version = 92, 632 .num_sdma_engines = 1, 633 .num_xgmi_sdma_engines = 0, 634 .num_sdma_queues_per_engine = 2, 635 }; 636 637 static const struct kfd_device_info cyan_skillfish_device_info = { 638 .asic_family = CHIP_CYAN_SKILLFISH, 639 .asic_name = "cyan_skillfish", 640 .gfx_target_version = 100103, 641 .max_pasid_bits = 16, 642 .max_no_of_hqd = 24, 643 .doorbell_size = 8, 644 .ih_ring_entry_size = 8 * sizeof(uint32_t), 645 .event_interrupt_class = &event_interrupt_class_v9, 646 .num_of_watch_points = 4, 647 .mqd_size_aligned = MQD_SIZE_ALIGNED, 648 .needs_iommu_device = false, 649 .supports_cwsr = true, 650 .needs_pci_atomics = true, 651 .num_sdma_engines = 2, 652 .num_xgmi_sdma_engines = 0, 653 .num_sdma_queues_per_engine = 8, 654 }; 655 656 /* For each entry, [0] is regular and [1] is virtualisation device. */ 657 static const struct kfd_device_info *kfd_supported_devices[][2] = { 658 #ifdef KFD_SUPPORT_IOMMU_V2 659 [CHIP_KAVERI] = {&kaveri_device_info, NULL}, 660 [CHIP_CARRIZO] = {&carrizo_device_info, NULL}, 661 #endif 662 [CHIP_RAVEN] = {&raven_device_info, NULL}, 663 [CHIP_HAWAII] = {&hawaii_device_info, NULL}, 664 [CHIP_TONGA] = {&tonga_device_info, NULL}, 665 [CHIP_FIJI] = {&fiji_device_info, &fiji_vf_device_info}, 666 [CHIP_POLARIS10] = {&polaris10_device_info, &polaris10_vf_device_info}, 667 [CHIP_POLARIS11] = {&polaris11_device_info, NULL}, 668 [CHIP_POLARIS12] = {&polaris12_device_info, NULL}, 669 [CHIP_VEGAM] = {&vegam_device_info, NULL}, 670 [CHIP_VEGA10] = {&vega10_device_info, &vega10_vf_device_info}, 671 [CHIP_VEGA12] = {&vega12_device_info, NULL}, 672 [CHIP_VEGA20] = {&vega20_device_info, NULL}, 673 [CHIP_RENOIR] = {&renoir_device_info, NULL}, 674 [CHIP_ARCTURUS] = {&arcturus_device_info, &arcturus_device_info}, 675 [CHIP_ALDEBARAN] = {&aldebaran_device_info, &aldebaran_device_info}, 676 [CHIP_NAVI10] = {&navi10_device_info, NULL}, 677 [CHIP_NAVI12] = {&navi12_device_info, &navi12_device_info}, 678 [CHIP_NAVI14] = {&navi14_device_info, NULL}, 679 [CHIP_SIENNA_CICHLID] = {&sienna_cichlid_device_info, &sienna_cichlid_device_info}, 680 [CHIP_NAVY_FLOUNDER] = {&navy_flounder_device_info, &navy_flounder_device_info}, 681 [CHIP_VANGOGH] = {&vangogh_device_info, NULL}, 682 [CHIP_DIMGREY_CAVEFISH] = {&dimgrey_cavefish_device_info, &dimgrey_cavefish_device_info}, 683 [CHIP_BEIGE_GOBY] = {&beige_goby_device_info, &beige_goby_device_info}, 684 [CHIP_YELLOW_CARP] = {&yellow_carp_device_info, NULL}, 685 [CHIP_CYAN_SKILLFISH] = {&cyan_skillfish_device_info, NULL}, 686 }; 687 688 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 689 unsigned int chunk_size); 690 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 691 692 static int kfd_resume(struct kfd_dev *kfd); 693 694 struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, 695 struct pci_dev *pdev, unsigned int asic_type, bool vf) 696 { 697 struct kfd_dev *kfd; 698 const struct kfd_device_info *device_info; 699 const struct kfd2kgd_calls *f2g; 700 701 if (asic_type >= sizeof(kfd_supported_devices) / (sizeof(void *) * 2) 702 || asic_type >= sizeof(kfd2kgd_funcs) / sizeof(void *)) { 703 dev_err(kfd_device, "asic_type %d out of range\n", asic_type); 704 return NULL; /* asic_type out of range */ 705 } 706 707 device_info = kfd_supported_devices[asic_type][vf]; 708 f2g = kfd2kgd_funcs[asic_type]; 709 710 if (!device_info || !f2g) { 711 dev_err(kfd_device, "%s %s not supported in kfd\n", 712 amdgpu_asic_name[asic_type], vf ? "VF" : ""); 713 return NULL; 714 } 715 716 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 717 if (!kfd) 718 return NULL; 719 720 kfd->kgd = kgd; 721 kfd->device_info = device_info; 722 kfd->pdev = pdev; 723 kfd->init_complete = false; 724 kfd->kfd2kgd = f2g; 725 atomic_set(&kfd->compute_profile, 0); 726 727 mutex_init(&kfd->doorbell_mutex); 728 memset(&kfd->doorbell_available_index, 0, 729 sizeof(kfd->doorbell_available_index)); 730 731 atomic_set(&kfd->sram_ecc_flag, 0); 732 733 ida_init(&kfd->doorbell_ida); 734 735 return kfd; 736 } 737 738 static void kfd_cwsr_init(struct kfd_dev *kfd) 739 { 740 if (cwsr_enable && kfd->device_info->supports_cwsr) { 741 if (kfd->device_info->asic_family < CHIP_VEGA10) { 742 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE); 743 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 744 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 745 } else if (kfd->device_info->asic_family == CHIP_ARCTURUS) { 746 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE); 747 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 748 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 749 } else if (kfd->device_info->asic_family == CHIP_ALDEBARAN) { 750 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) > PAGE_SIZE); 751 kfd->cwsr_isa = cwsr_trap_aldebaran_hex; 752 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); 753 } else if (kfd->device_info->asic_family < CHIP_NAVI10) { 754 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE); 755 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 756 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 757 } else if (kfd->device_info->asic_family < CHIP_SIENNA_CICHLID) { 758 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE); 759 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 760 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 761 } else { 762 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE); 763 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 764 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 765 } 766 767 kfd->cwsr_enabled = true; 768 } 769 } 770 771 static int kfd_gws_init(struct kfd_dev *kfd) 772 { 773 int ret = 0; 774 775 if (kfd->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 776 return 0; 777 778 if (hws_gws_support 779 || (kfd->device_info->asic_family == CHIP_VEGA10 780 && kfd->mec2_fw_version >= 0x81b3) 781 || (kfd->device_info->asic_family >= CHIP_VEGA12 782 && kfd->device_info->asic_family <= CHIP_RAVEN 783 && kfd->mec2_fw_version >= 0x1b3) 784 || (kfd->device_info->asic_family == CHIP_ARCTURUS 785 && kfd->mec2_fw_version >= 0x30) 786 || (kfd->device_info->asic_family == CHIP_ALDEBARAN 787 && kfd->mec2_fw_version >= 0x28)) 788 ret = amdgpu_amdkfd_alloc_gws(kfd->kgd, 789 amdgpu_amdkfd_get_num_gws(kfd->kgd), &kfd->gws); 790 791 return ret; 792 } 793 794 static void kfd_smi_init(struct kfd_dev *dev) { 795 INIT_LIST_HEAD(&dev->smi_clients); 796 spin_lock_init(&dev->smi_lock); 797 } 798 799 bool kgd2kfd_device_init(struct kfd_dev *kfd, 800 struct drm_device *ddev, 801 const struct kgd2kfd_shared_resources *gpu_resources) 802 { 803 unsigned int size, map_process_packet_size; 804 805 kfd->ddev = ddev; 806 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd, 807 KGD_ENGINE_MEC1); 808 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd, 809 KGD_ENGINE_MEC2); 810 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd, 811 KGD_ENGINE_SDMA1); 812 kfd->shared_resources = *gpu_resources; 813 814 kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 815 kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 816 kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd 817 - kfd->vm_info.first_vmid_kfd + 1; 818 819 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 820 * 32 and 64-bit requests are possible and must be 821 * supported. 822 */ 823 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->kgd); 824 if (!kfd->pci_atomic_requested && 825 kfd->device_info->needs_pci_atomics && 826 (!kfd->device_info->no_atomic_fw_version || 827 kfd->mec_fw_version < kfd->device_info->no_atomic_fw_version)) { 828 dev_info(kfd_device, 829 "skipped device %x:%x, PCI rejects atomics %d<%d\n", 830 kfd->pdev->vendor, kfd->pdev->device, 831 kfd->mec_fw_version, 832 kfd->device_info->no_atomic_fw_version); 833 return false; 834 } 835 836 /* Verify module parameters regarding mapped process number*/ 837 if ((hws_max_conc_proc < 0) 838 || (hws_max_conc_proc > kfd->vm_info.vmid_num_kfd)) { 839 dev_err(kfd_device, 840 "hws_max_conc_proc %d must be between 0 and %d, use %d instead\n", 841 hws_max_conc_proc, kfd->vm_info.vmid_num_kfd, 842 kfd->vm_info.vmid_num_kfd); 843 kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd; 844 } else 845 kfd->max_proc_per_quantum = hws_max_conc_proc; 846 847 /* calculate max size of mqds needed for queues */ 848 size = max_num_of_queues_per_device * 849 kfd->device_info->mqd_size_aligned; 850 851 /* 852 * calculate max size of runlist packet. 853 * There can be only 2 packets at once 854 */ 855 map_process_packet_size = 856 kfd->device_info->asic_family == CHIP_ALDEBARAN ? 857 sizeof(struct pm4_mes_map_process_aldebaran) : 858 sizeof(struct pm4_mes_map_process); 859 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + 860 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 861 + sizeof(struct pm4_mes_runlist)) * 2; 862 863 /* Add size of HIQ & DIQ */ 864 size += KFD_KERNEL_QUEUE_SIZE * 2; 865 866 /* add another 512KB for all other allocations on gart (HPD, fences) */ 867 size += 512 * 1024; 868 869 if (amdgpu_amdkfd_alloc_gtt_mem( 870 kfd->kgd, size, &kfd->gtt_mem, 871 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 872 false)) { 873 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 874 goto alloc_gtt_mem_failure; 875 } 876 877 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 878 879 /* Initialize GTT sa with 512 byte chunk size */ 880 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 881 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 882 goto kfd_gtt_sa_init_error; 883 } 884 885 if (kfd_doorbell_init(kfd)) { 886 dev_err(kfd_device, 887 "Error initializing doorbell aperture\n"); 888 goto kfd_doorbell_error; 889 } 890 891 kfd->hive_id = amdgpu_amdkfd_get_hive_id(kfd->kgd); 892 893 kfd->noretry = amdgpu_amdkfd_get_noretry(kfd->kgd); 894 895 if (kfd_interrupt_init(kfd)) { 896 dev_err(kfd_device, "Error initializing interrupts\n"); 897 goto kfd_interrupt_error; 898 } 899 900 kfd->dqm = device_queue_manager_init(kfd); 901 if (!kfd->dqm) { 902 dev_err(kfd_device, "Error initializing queue manager\n"); 903 goto device_queue_manager_error; 904 } 905 906 /* If supported on this device, allocate global GWS that is shared 907 * by all KFD processes 908 */ 909 if (kfd_gws_init(kfd)) { 910 dev_err(kfd_device, "Could not allocate %d gws\n", 911 amdgpu_amdkfd_get_num_gws(kfd->kgd)); 912 goto gws_error; 913 } 914 915 /* If CRAT is broken, won't set iommu enabled */ 916 kfd_double_confirm_iommu_support(kfd); 917 918 if (kfd_iommu_device_init(kfd)) { 919 dev_err(kfd_device, "Error initializing iommuv2\n"); 920 goto device_iommu_error; 921 } 922 923 kfd_cwsr_init(kfd); 924 925 svm_migrate_init((struct amdgpu_device *)kfd->kgd); 926 927 if (kfd_resume(kfd)) 928 goto kfd_resume_error; 929 930 kfd->dbgmgr = NULL; 931 932 if (kfd_topology_add_device(kfd)) { 933 dev_err(kfd_device, "Error adding device to topology\n"); 934 goto kfd_topology_add_device_error; 935 } 936 937 kfd_smi_init(kfd); 938 939 kfd->init_complete = true; 940 dev_info(kfd_device, "added device %x:%x\n", kfd->pdev->vendor, 941 kfd->pdev->device); 942 943 pr_debug("Starting kfd with the following scheduling policy %d\n", 944 kfd->dqm->sched_policy); 945 946 goto out; 947 948 kfd_topology_add_device_error: 949 kfd_resume_error: 950 device_iommu_error: 951 gws_error: 952 device_queue_manager_uninit(kfd->dqm); 953 device_queue_manager_error: 954 kfd_interrupt_exit(kfd); 955 kfd_interrupt_error: 956 kfd_doorbell_fini(kfd); 957 kfd_doorbell_error: 958 kfd_gtt_sa_fini(kfd); 959 kfd_gtt_sa_init_error: 960 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem); 961 alloc_gtt_mem_failure: 962 if (kfd->gws) 963 amdgpu_amdkfd_free_gws(kfd->kgd, kfd->gws); 964 dev_err(kfd_device, 965 "device %x:%x NOT added due to errors\n", 966 kfd->pdev->vendor, kfd->pdev->device); 967 out: 968 return kfd->init_complete; 969 } 970 971 void kgd2kfd_device_exit(struct kfd_dev *kfd) 972 { 973 if (kfd->init_complete) { 974 device_queue_manager_uninit(kfd->dqm); 975 kfd_interrupt_exit(kfd); 976 kfd_topology_remove_device(kfd); 977 kfd_doorbell_fini(kfd); 978 ida_destroy(&kfd->doorbell_ida); 979 kfd_gtt_sa_fini(kfd); 980 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem); 981 if (kfd->gws) 982 amdgpu_amdkfd_free_gws(kfd->kgd, kfd->gws); 983 } 984 985 kfree(kfd); 986 } 987 988 int kgd2kfd_pre_reset(struct kfd_dev *kfd) 989 { 990 if (!kfd->init_complete) 991 return 0; 992 993 kfd_smi_event_update_gpu_reset(kfd, false); 994 995 kfd->dqm->ops.pre_reset(kfd->dqm); 996 997 kgd2kfd_suspend(kfd, false); 998 999 kfd_signal_reset_event(kfd); 1000 return 0; 1001 } 1002 1003 /* 1004 * Fix me. KFD won't be able to resume existing process for now. 1005 * We will keep all existing process in a evicted state and 1006 * wait the process to be terminated. 1007 */ 1008 1009 int kgd2kfd_post_reset(struct kfd_dev *kfd) 1010 { 1011 int ret; 1012 1013 if (!kfd->init_complete) 1014 return 0; 1015 1016 ret = kfd_resume(kfd); 1017 if (ret) 1018 return ret; 1019 atomic_dec(&kfd_locked); 1020 1021 atomic_set(&kfd->sram_ecc_flag, 0); 1022 1023 kfd_smi_event_update_gpu_reset(kfd, true); 1024 1025 return 0; 1026 } 1027 1028 bool kfd_is_locked(void) 1029 { 1030 return (atomic_read(&kfd_locked) > 0); 1031 } 1032 1033 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 1034 { 1035 if (!kfd->init_complete) 1036 return; 1037 1038 /* for runtime suspend, skip locking kfd */ 1039 if (!run_pm) { 1040 /* For first KFD device suspend all the KFD processes */ 1041 if (atomic_inc_return(&kfd_locked) == 1) 1042 kfd_suspend_all_processes(); 1043 } 1044 1045 kfd->dqm->ops.stop(kfd->dqm); 1046 kfd_iommu_suspend(kfd); 1047 } 1048 1049 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 1050 { 1051 int ret, count; 1052 1053 if (!kfd->init_complete) 1054 return 0; 1055 1056 ret = kfd_resume(kfd); 1057 if (ret) 1058 return ret; 1059 1060 /* for runtime resume, skip unlocking kfd */ 1061 if (!run_pm) { 1062 count = atomic_dec_return(&kfd_locked); 1063 WARN_ONCE(count < 0, "KFD suspend / resume ref. error"); 1064 if (count == 0) 1065 ret = kfd_resume_all_processes(); 1066 } 1067 1068 return ret; 1069 } 1070 1071 int kgd2kfd_resume_iommu(struct kfd_dev *kfd) 1072 { 1073 int err = 0; 1074 1075 err = kfd_iommu_resume(kfd); 1076 if (err) 1077 dev_err(kfd_device, 1078 "Failed to resume IOMMU for device %x:%x\n", 1079 kfd->pdev->vendor, kfd->pdev->device); 1080 return err; 1081 } 1082 1083 static int kfd_resume(struct kfd_dev *kfd) 1084 { 1085 int err = 0; 1086 1087 err = kfd->dqm->ops.start(kfd->dqm); 1088 if (err) 1089 dev_err(kfd_device, 1090 "Error starting queue manager for device %x:%x\n", 1091 kfd->pdev->vendor, kfd->pdev->device); 1092 1093 return err; 1094 } 1095 1096 static inline void kfd_queue_work(struct workqueue_struct *wq, 1097 struct work_struct *work) 1098 { 1099 int cpu, new_cpu; 1100 1101 cpu = new_cpu = smp_processor_id(); 1102 do { 1103 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids; 1104 if (cpu_to_node(new_cpu) == numa_node_id()) 1105 break; 1106 } while (cpu != new_cpu); 1107 1108 queue_work_on(new_cpu, wq, work); 1109 } 1110 1111 /* This is called directly from KGD at ISR. */ 1112 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 1113 { 1114 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE]; 1115 bool is_patched = false; 1116 unsigned long flags; 1117 1118 if (!kfd->init_complete) 1119 return; 1120 1121 if (kfd->device_info->ih_ring_entry_size > sizeof(patched_ihre)) { 1122 dev_err_once(kfd_device, "Ring entry too small\n"); 1123 return; 1124 } 1125 1126 spin_lock_irqsave(&kfd->interrupt_lock, flags); 1127 1128 if (kfd->interrupts_active 1129 && interrupt_is_wanted(kfd, ih_ring_entry, 1130 patched_ihre, &is_patched) 1131 && enqueue_ih_ring_entry(kfd, 1132 is_patched ? patched_ihre : ih_ring_entry)) 1133 kfd_queue_work(kfd->ih_wq, &kfd->interrupt_work); 1134 1135 spin_unlock_irqrestore(&kfd->interrupt_lock, flags); 1136 } 1137 1138 int kgd2kfd_quiesce_mm(struct mm_struct *mm) 1139 { 1140 struct kfd_process *p; 1141 int r; 1142 1143 /* Because we are called from arbitrary context (workqueue) as opposed 1144 * to process context, kfd_process could attempt to exit while we are 1145 * running so the lookup function increments the process ref count. 1146 */ 1147 p = kfd_lookup_process_by_mm(mm); 1148 if (!p) 1149 return -ESRCH; 1150 1151 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 1152 r = kfd_process_evict_queues(p); 1153 1154 kfd_unref_process(p); 1155 return r; 1156 } 1157 1158 int kgd2kfd_resume_mm(struct mm_struct *mm) 1159 { 1160 struct kfd_process *p; 1161 int r; 1162 1163 /* Because we are called from arbitrary context (workqueue) as opposed 1164 * to process context, kfd_process could attempt to exit while we are 1165 * running so the lookup function increments the process ref count. 1166 */ 1167 p = kfd_lookup_process_by_mm(mm); 1168 if (!p) 1169 return -ESRCH; 1170 1171 r = kfd_process_restore_queues(p); 1172 1173 kfd_unref_process(p); 1174 return r; 1175 } 1176 1177 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 1178 * prepare for safe eviction of KFD BOs that belong to the specified 1179 * process. 1180 * 1181 * @mm: mm_struct that identifies the specified KFD process 1182 * @fence: eviction fence attached to KFD process BOs 1183 * 1184 */ 1185 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 1186 struct dma_fence *fence) 1187 { 1188 struct kfd_process *p; 1189 unsigned long active_time; 1190 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 1191 1192 if (!fence) 1193 return -EINVAL; 1194 1195 if (dma_fence_is_signaled(fence)) 1196 return 0; 1197 1198 p = kfd_lookup_process_by_mm(mm); 1199 if (!p) 1200 return -ENODEV; 1201 1202 if (fence->seqno == p->last_eviction_seqno) 1203 goto out; 1204 1205 p->last_eviction_seqno = fence->seqno; 1206 1207 /* Avoid KFD process starvation. Wait for at least 1208 * PROCESS_ACTIVE_TIME_MS before evicting the process again 1209 */ 1210 active_time = get_jiffies_64() - p->last_restore_timestamp; 1211 if (delay_jiffies > active_time) 1212 delay_jiffies -= active_time; 1213 else 1214 delay_jiffies = 0; 1215 1216 /* During process initialization eviction_work.dwork is initialized 1217 * to kfd_evict_bo_worker 1218 */ 1219 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 1220 p->lead_thread->pid, delay_jiffies); 1221 schedule_delayed_work(&p->eviction_work, delay_jiffies); 1222 out: 1223 kfd_unref_process(p); 1224 return 0; 1225 } 1226 1227 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 1228 unsigned int chunk_size) 1229 { 1230 unsigned int num_of_longs; 1231 1232 if (WARN_ON(buf_size < chunk_size)) 1233 return -EINVAL; 1234 if (WARN_ON(buf_size == 0)) 1235 return -EINVAL; 1236 if (WARN_ON(chunk_size == 0)) 1237 return -EINVAL; 1238 1239 kfd->gtt_sa_chunk_size = chunk_size; 1240 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 1241 1242 num_of_longs = (kfd->gtt_sa_num_of_chunks + BITS_PER_LONG - 1) / 1243 BITS_PER_LONG; 1244 1245 kfd->gtt_sa_bitmap = kcalloc(num_of_longs, sizeof(long), GFP_KERNEL); 1246 1247 if (!kfd->gtt_sa_bitmap) 1248 return -ENOMEM; 1249 1250 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 1251 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 1252 1253 mutex_init(&kfd->gtt_sa_lock); 1254 1255 return 0; 1256 1257 } 1258 1259 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 1260 { 1261 mutex_destroy(&kfd->gtt_sa_lock); 1262 kfree(kfd->gtt_sa_bitmap); 1263 } 1264 1265 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 1266 unsigned int bit_num, 1267 unsigned int chunk_size) 1268 { 1269 return start_addr + bit_num * chunk_size; 1270 } 1271 1272 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 1273 unsigned int bit_num, 1274 unsigned int chunk_size) 1275 { 1276 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 1277 } 1278 1279 int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size, 1280 struct kfd_mem_obj **mem_obj) 1281 { 1282 unsigned int found, start_search, cur_size; 1283 1284 if (size == 0) 1285 return -EINVAL; 1286 1287 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 1288 return -ENOMEM; 1289 1290 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 1291 if (!(*mem_obj)) 1292 return -ENOMEM; 1293 1294 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 1295 1296 start_search = 0; 1297 1298 mutex_lock(&kfd->gtt_sa_lock); 1299 1300 kfd_gtt_restart_search: 1301 /* Find the first chunk that is free */ 1302 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1303 kfd->gtt_sa_num_of_chunks, 1304 start_search); 1305 1306 pr_debug("Found = %d\n", found); 1307 1308 /* If there wasn't any free chunk, bail out */ 1309 if (found == kfd->gtt_sa_num_of_chunks) 1310 goto kfd_gtt_no_free_chunk; 1311 1312 /* Update fields of mem_obj */ 1313 (*mem_obj)->range_start = found; 1314 (*mem_obj)->range_end = found; 1315 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1316 kfd->gtt_start_gpu_addr, 1317 found, 1318 kfd->gtt_sa_chunk_size); 1319 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1320 kfd->gtt_start_cpu_ptr, 1321 found, 1322 kfd->gtt_sa_chunk_size); 1323 1324 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1325 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1326 1327 /* If we need only one chunk, mark it as allocated and get out */ 1328 if (size <= kfd->gtt_sa_chunk_size) { 1329 pr_debug("Single bit\n"); 1330 set_bit(found, kfd->gtt_sa_bitmap); 1331 goto kfd_gtt_out; 1332 } 1333 1334 /* Otherwise, try to see if we have enough contiguous chunks */ 1335 cur_size = size - kfd->gtt_sa_chunk_size; 1336 do { 1337 (*mem_obj)->range_end = 1338 find_next_zero_bit(kfd->gtt_sa_bitmap, 1339 kfd->gtt_sa_num_of_chunks, ++found); 1340 /* 1341 * If next free chunk is not contiguous than we need to 1342 * restart our search from the last free chunk we found (which 1343 * wasn't contiguous to the previous ones 1344 */ 1345 if ((*mem_obj)->range_end != found) { 1346 start_search = found; 1347 goto kfd_gtt_restart_search; 1348 } 1349 1350 /* 1351 * If we reached end of buffer, bail out with error 1352 */ 1353 if (found == kfd->gtt_sa_num_of_chunks) 1354 goto kfd_gtt_no_free_chunk; 1355 1356 /* Check if we don't need another chunk */ 1357 if (cur_size <= kfd->gtt_sa_chunk_size) 1358 cur_size = 0; 1359 else 1360 cur_size -= kfd->gtt_sa_chunk_size; 1361 1362 } while (cur_size > 0); 1363 1364 pr_debug("range_start = %d, range_end = %d\n", 1365 (*mem_obj)->range_start, (*mem_obj)->range_end); 1366 1367 /* Mark the chunks as allocated */ 1368 for (found = (*mem_obj)->range_start; 1369 found <= (*mem_obj)->range_end; 1370 found++) 1371 set_bit(found, kfd->gtt_sa_bitmap); 1372 1373 kfd_gtt_out: 1374 mutex_unlock(&kfd->gtt_sa_lock); 1375 return 0; 1376 1377 kfd_gtt_no_free_chunk: 1378 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1379 mutex_unlock(&kfd->gtt_sa_lock); 1380 kfree(*mem_obj); 1381 return -ENOMEM; 1382 } 1383 1384 int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj) 1385 { 1386 unsigned int bit; 1387 1388 /* Act like kfree when trying to free a NULL object */ 1389 if (!mem_obj) 1390 return 0; 1391 1392 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1393 mem_obj, mem_obj->range_start, mem_obj->range_end); 1394 1395 mutex_lock(&kfd->gtt_sa_lock); 1396 1397 /* Mark the chunks as free */ 1398 for (bit = mem_obj->range_start; 1399 bit <= mem_obj->range_end; 1400 bit++) 1401 clear_bit(bit, kfd->gtt_sa_bitmap); 1402 1403 mutex_unlock(&kfd->gtt_sa_lock); 1404 1405 kfree(mem_obj); 1406 return 0; 1407 } 1408 1409 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1410 { 1411 if (kfd) 1412 atomic_inc(&kfd->sram_ecc_flag); 1413 } 1414 1415 void kfd_inc_compute_active(struct kfd_dev *kfd) 1416 { 1417 if (atomic_inc_return(&kfd->compute_profile) == 1) 1418 amdgpu_amdkfd_set_compute_idle(kfd->kgd, false); 1419 } 1420 1421 void kfd_dec_compute_active(struct kfd_dev *kfd) 1422 { 1423 int count = atomic_dec_return(&kfd->compute_profile); 1424 1425 if (count == 0) 1426 amdgpu_amdkfd_set_compute_idle(kfd->kgd, true); 1427 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1428 } 1429 1430 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 1431 { 1432 if (kfd && kfd->init_complete) 1433 kfd_smi_event_update_thermal_throttling(kfd, throttle_bitmask); 1434 } 1435 1436 #if defined(CONFIG_DEBUG_FS) 1437 1438 /* This function will send a package to HIQ to hang the HWS 1439 * which will trigger a GPU reset and bring the HWS back to normal state 1440 */ 1441 int kfd_debugfs_hang_hws(struct kfd_dev *dev) 1442 { 1443 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1444 pr_err("HWS is not enabled"); 1445 return -EINVAL; 1446 } 1447 1448 return dqm_debugfs_hang_hws(dev->dqm); 1449 } 1450 1451 #endif 1452