1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/bsearch.h> 25 #include <linux/pci.h> 26 #include <linux/slab.h> 27 #include "kfd_priv.h" 28 #include "kfd_device_queue_manager.h" 29 #include "kfd_pm4_headers_vi.h" 30 #include "kfd_pm4_headers_aldebaran.h" 31 #include "cwsr_trap_handler.h" 32 #include "kfd_iommu.h" 33 #include "amdgpu_amdkfd.h" 34 #include "kfd_smi_events.h" 35 #include "kfd_svm.h" 36 #include "kfd_migrate.h" 37 #include "amdgpu.h" 38 #include "amdgpu_xcp.h" 39 40 #define MQD_SIZE_ALIGNED 768 41 42 /* 43 * kfd_locked is used to lock the kfd driver during suspend or reset 44 * once locked, kfd driver will stop any further GPU execution. 45 * create process (open) will return -EAGAIN. 46 */ 47 static int kfd_locked; 48 49 #ifdef CONFIG_DRM_AMDGPU_CIK 50 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 51 #endif 52 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 53 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 54 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 55 extern const struct kfd2kgd_calls aldebaran_kfd2kgd; 56 extern const struct kfd2kgd_calls gc_9_4_3_kfd2kgd; 57 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 58 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 59 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd; 60 61 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 62 unsigned int chunk_size); 63 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 64 65 static int kfd_resume_iommu(struct kfd_dev *kfd); 66 static int kfd_resume(struct kfd_node *kfd); 67 68 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) 69 { 70 uint32_t sdma_version = kfd->adev->ip_versions[SDMA0_HWIP][0]; 71 72 switch (sdma_version) { 73 case IP_VERSION(4, 0, 0):/* VEGA10 */ 74 case IP_VERSION(4, 0, 1):/* VEGA12 */ 75 case IP_VERSION(4, 1, 0):/* RAVEN */ 76 case IP_VERSION(4, 1, 1):/* RAVEN */ 77 case IP_VERSION(4, 1, 2):/* RENOIR */ 78 case IP_VERSION(5, 2, 1):/* VANGOGH */ 79 case IP_VERSION(5, 2, 3):/* YELLOW_CARP */ 80 case IP_VERSION(5, 2, 6):/* GC 10.3.6 */ 81 case IP_VERSION(5, 2, 7):/* GC 10.3.7 */ 82 kfd->device_info.num_sdma_queues_per_engine = 2; 83 break; 84 case IP_VERSION(4, 2, 0):/* VEGA20 */ 85 case IP_VERSION(4, 2, 2):/* ARCTURUS */ 86 case IP_VERSION(4, 4, 0):/* ALDEBARAN */ 87 case IP_VERSION(4, 4, 2): 88 case IP_VERSION(5, 0, 0):/* NAVI10 */ 89 case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */ 90 case IP_VERSION(5, 0, 2):/* NAVI14 */ 91 case IP_VERSION(5, 0, 5):/* NAVI12 */ 92 case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */ 93 case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */ 94 case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */ 95 case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */ 96 case IP_VERSION(6, 0, 0): 97 case IP_VERSION(6, 0, 1): 98 case IP_VERSION(6, 0, 2): 99 case IP_VERSION(6, 0, 3): 100 kfd->device_info.num_sdma_queues_per_engine = 8; 101 break; 102 default: 103 dev_warn(kfd_device, 104 "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n", 105 sdma_version); 106 kfd->device_info.num_sdma_queues_per_engine = 8; 107 } 108 109 bitmap_zero(kfd->device_info.reserved_sdma_queues_bitmap, KFD_MAX_SDMA_QUEUES); 110 111 switch (sdma_version) { 112 case IP_VERSION(6, 0, 0): 113 case IP_VERSION(6, 0, 1): 114 case IP_VERSION(6, 0, 2): 115 case IP_VERSION(6, 0, 3): 116 /* Reserve 1 for paging and 1 for gfx */ 117 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 118 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */ 119 bitmap_set(kfd->device_info.reserved_sdma_queues_bitmap, 0, 120 kfd->adev->sdma.num_instances * 121 kfd->device_info.num_reserved_sdma_queues_per_engine); 122 break; 123 default: 124 break; 125 } 126 } 127 128 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) 129 { 130 uint32_t gc_version = KFD_GC_VERSION(kfd); 131 132 switch (gc_version) { 133 case IP_VERSION(9, 0, 1): /* VEGA10 */ 134 case IP_VERSION(9, 1, 0): /* RAVEN */ 135 case IP_VERSION(9, 2, 1): /* VEGA12 */ 136 case IP_VERSION(9, 2, 2): /* RAVEN */ 137 case IP_VERSION(9, 3, 0): /* RENOIR */ 138 case IP_VERSION(9, 4, 0): /* VEGA20 */ 139 case IP_VERSION(9, 4, 1): /* ARCTURUS */ 140 case IP_VERSION(9, 4, 2): /* ALDEBARAN */ 141 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 142 break; 143 case IP_VERSION(9, 4, 3): /* GC 9.4.3 */ 144 kfd->device_info.event_interrupt_class = 145 &event_interrupt_class_v9_4_3; 146 break; 147 case IP_VERSION(10, 3, 1): /* VANGOGH */ 148 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */ 149 case IP_VERSION(10, 3, 6): /* GC 10.3.6 */ 150 case IP_VERSION(10, 3, 7): /* GC 10.3.7 */ 151 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */ 152 case IP_VERSION(10, 1, 4): 153 case IP_VERSION(10, 1, 10): /* NAVI10 */ 154 case IP_VERSION(10, 1, 2): /* NAVI12 */ 155 case IP_VERSION(10, 1, 1): /* NAVI14 */ 156 case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */ 157 case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */ 158 case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */ 159 case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */ 160 kfd->device_info.event_interrupt_class = &event_interrupt_class_v10; 161 break; 162 case IP_VERSION(11, 0, 0): 163 case IP_VERSION(11, 0, 1): 164 case IP_VERSION(11, 0, 2): 165 case IP_VERSION(11, 0, 3): 166 case IP_VERSION(11, 0, 4): 167 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 168 break; 169 default: 170 dev_warn(kfd_device, "v9 event interrupt handler is set due to " 171 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version); 172 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 173 } 174 } 175 176 static void kfd_device_info_init(struct kfd_dev *kfd, 177 bool vf, uint32_t gfx_target_version) 178 { 179 uint32_t gc_version = KFD_GC_VERSION(kfd); 180 uint32_t asic_type = kfd->adev->asic_type; 181 182 kfd->device_info.max_pasid_bits = 16; 183 kfd->device_info.max_no_of_hqd = 24; 184 kfd->device_info.num_of_watch_points = 4; 185 kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED; 186 kfd->device_info.gfx_target_version = gfx_target_version; 187 188 if (KFD_IS_SOC15(kfd)) { 189 kfd->device_info.doorbell_size = 8; 190 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t); 191 kfd->device_info.supports_cwsr = true; 192 193 kfd_device_info_set_sdma_info(kfd); 194 195 kfd_device_info_set_event_interrupt_class(kfd); 196 197 /* Raven */ 198 if (gc_version == IP_VERSION(9, 1, 0) || 199 gc_version == IP_VERSION(9, 2, 2)) 200 kfd->device_info.needs_iommu_device = true; 201 202 if (gc_version < IP_VERSION(11, 0, 0)) { 203 /* Navi2x+, Navi1x+ */ 204 if (gc_version == IP_VERSION(10, 3, 6)) 205 kfd->device_info.no_atomic_fw_version = 14; 206 else if (gc_version == IP_VERSION(10, 3, 7)) 207 kfd->device_info.no_atomic_fw_version = 3; 208 else if (gc_version >= IP_VERSION(10, 3, 0)) 209 kfd->device_info.no_atomic_fw_version = 92; 210 else if (gc_version >= IP_VERSION(10, 1, 1)) 211 kfd->device_info.no_atomic_fw_version = 145; 212 213 /* Navi1x+ */ 214 if (gc_version >= IP_VERSION(10, 1, 1)) 215 kfd->device_info.needs_pci_atomics = true; 216 } else if (gc_version < IP_VERSION(12, 0, 0)) { 217 /* 218 * PCIe atomics support acknowledgment in GFX11 RS64 CPFW requires 219 * MEC version >= 509. Prior RS64 CPFW versions (and all F32) require 220 * PCIe atomics support. 221 */ 222 kfd->device_info.needs_pci_atomics = true; 223 kfd->device_info.no_atomic_fw_version = kfd->adev->gfx.rs64_enable ? 509 : 0; 224 } 225 } else { 226 kfd->device_info.doorbell_size = 4; 227 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t); 228 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik; 229 kfd->device_info.num_sdma_queues_per_engine = 2; 230 231 if (asic_type != CHIP_KAVERI && 232 asic_type != CHIP_HAWAII && 233 asic_type != CHIP_TONGA) 234 kfd->device_info.supports_cwsr = true; 235 236 if (asic_type == CHIP_KAVERI || 237 asic_type == CHIP_CARRIZO) 238 kfd->device_info.needs_iommu_device = true; 239 240 if (asic_type != CHIP_HAWAII && !vf) 241 kfd->device_info.needs_pci_atomics = true; 242 } 243 } 244 245 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 246 { 247 struct kfd_dev *kfd = NULL; 248 const struct kfd2kgd_calls *f2g = NULL; 249 uint32_t gfx_target_version = 0; 250 251 switch (adev->asic_type) { 252 #ifdef KFD_SUPPORT_IOMMU_V2 253 #ifdef CONFIG_DRM_AMDGPU_CIK 254 case CHIP_KAVERI: 255 gfx_target_version = 70000; 256 if (!vf) 257 f2g = &gfx_v7_kfd2kgd; 258 break; 259 #endif 260 case CHIP_CARRIZO: 261 gfx_target_version = 80001; 262 if (!vf) 263 f2g = &gfx_v8_kfd2kgd; 264 break; 265 #endif 266 #ifdef CONFIG_DRM_AMDGPU_CIK 267 case CHIP_HAWAII: 268 gfx_target_version = 70001; 269 if (!amdgpu_exp_hw_support) 270 pr_info( 271 "KFD support on Hawaii is experimental. See modparam exp_hw_support\n" 272 ); 273 else if (!vf) 274 f2g = &gfx_v7_kfd2kgd; 275 break; 276 #endif 277 case CHIP_TONGA: 278 gfx_target_version = 80002; 279 if (!vf) 280 f2g = &gfx_v8_kfd2kgd; 281 break; 282 case CHIP_FIJI: 283 case CHIP_POLARIS10: 284 gfx_target_version = 80003; 285 f2g = &gfx_v8_kfd2kgd; 286 break; 287 case CHIP_POLARIS11: 288 case CHIP_POLARIS12: 289 case CHIP_VEGAM: 290 gfx_target_version = 80003; 291 if (!vf) 292 f2g = &gfx_v8_kfd2kgd; 293 break; 294 default: 295 switch (adev->ip_versions[GC_HWIP][0]) { 296 /* Vega 10 */ 297 case IP_VERSION(9, 0, 1): 298 gfx_target_version = 90000; 299 f2g = &gfx_v9_kfd2kgd; 300 break; 301 #ifdef KFD_SUPPORT_IOMMU_V2 302 /* Raven */ 303 case IP_VERSION(9, 1, 0): 304 case IP_VERSION(9, 2, 2): 305 gfx_target_version = 90002; 306 if (!vf) 307 f2g = &gfx_v9_kfd2kgd; 308 break; 309 #endif 310 /* Vega12 */ 311 case IP_VERSION(9, 2, 1): 312 gfx_target_version = 90004; 313 if (!vf) 314 f2g = &gfx_v9_kfd2kgd; 315 break; 316 /* Renoir */ 317 case IP_VERSION(9, 3, 0): 318 gfx_target_version = 90012; 319 if (!vf) 320 f2g = &gfx_v9_kfd2kgd; 321 break; 322 /* Vega20 */ 323 case IP_VERSION(9, 4, 0): 324 gfx_target_version = 90006; 325 if (!vf) 326 f2g = &gfx_v9_kfd2kgd; 327 break; 328 /* Arcturus */ 329 case IP_VERSION(9, 4, 1): 330 gfx_target_version = 90008; 331 f2g = &arcturus_kfd2kgd; 332 break; 333 /* Aldebaran */ 334 case IP_VERSION(9, 4, 2): 335 gfx_target_version = 90010; 336 f2g = &aldebaran_kfd2kgd; 337 break; 338 case IP_VERSION(9, 4, 3): 339 gfx_target_version = adev->rev_id >= 1 ? 90402 340 : adev->flags & AMD_IS_APU ? 90400 341 : 90401; 342 f2g = &gc_9_4_3_kfd2kgd; 343 break; 344 /* Navi10 */ 345 case IP_VERSION(10, 1, 10): 346 gfx_target_version = 100100; 347 if (!vf) 348 f2g = &gfx_v10_kfd2kgd; 349 break; 350 /* Navi12 */ 351 case IP_VERSION(10, 1, 2): 352 gfx_target_version = 100101; 353 f2g = &gfx_v10_kfd2kgd; 354 break; 355 /* Navi14 */ 356 case IP_VERSION(10, 1, 1): 357 gfx_target_version = 100102; 358 if (!vf) 359 f2g = &gfx_v10_kfd2kgd; 360 break; 361 /* Cyan Skillfish */ 362 case IP_VERSION(10, 1, 3): 363 case IP_VERSION(10, 1, 4): 364 gfx_target_version = 100103; 365 if (!vf) 366 f2g = &gfx_v10_kfd2kgd; 367 break; 368 /* Sienna Cichlid */ 369 case IP_VERSION(10, 3, 0): 370 gfx_target_version = 100300; 371 f2g = &gfx_v10_3_kfd2kgd; 372 break; 373 /* Navy Flounder */ 374 case IP_VERSION(10, 3, 2): 375 gfx_target_version = 100301; 376 f2g = &gfx_v10_3_kfd2kgd; 377 break; 378 /* Van Gogh */ 379 case IP_VERSION(10, 3, 1): 380 gfx_target_version = 100303; 381 if (!vf) 382 f2g = &gfx_v10_3_kfd2kgd; 383 break; 384 /* Dimgrey Cavefish */ 385 case IP_VERSION(10, 3, 4): 386 gfx_target_version = 100302; 387 f2g = &gfx_v10_3_kfd2kgd; 388 break; 389 /* Beige Goby */ 390 case IP_VERSION(10, 3, 5): 391 gfx_target_version = 100304; 392 f2g = &gfx_v10_3_kfd2kgd; 393 break; 394 /* Yellow Carp */ 395 case IP_VERSION(10, 3, 3): 396 gfx_target_version = 100305; 397 if (!vf) 398 f2g = &gfx_v10_3_kfd2kgd; 399 break; 400 case IP_VERSION(10, 3, 6): 401 case IP_VERSION(10, 3, 7): 402 gfx_target_version = 100306; 403 if (!vf) 404 f2g = &gfx_v10_3_kfd2kgd; 405 break; 406 case IP_VERSION(11, 0, 0): 407 gfx_target_version = 110000; 408 f2g = &gfx_v11_kfd2kgd; 409 break; 410 case IP_VERSION(11, 0, 1): 411 case IP_VERSION(11, 0, 4): 412 gfx_target_version = 110003; 413 f2g = &gfx_v11_kfd2kgd; 414 break; 415 case IP_VERSION(11, 0, 2): 416 gfx_target_version = 110002; 417 f2g = &gfx_v11_kfd2kgd; 418 break; 419 case IP_VERSION(11, 0, 3): 420 if ((adev->pdev->device == 0x7460 && 421 adev->pdev->revision == 0x00) || 422 (adev->pdev->device == 0x7461 && 423 adev->pdev->revision == 0x00)) 424 /* Note: Compiler version is 11.0.5 while HW version is 11.0.3 */ 425 gfx_target_version = 110005; 426 else 427 /* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */ 428 gfx_target_version = 110001; 429 f2g = &gfx_v11_kfd2kgd; 430 break; 431 default: 432 break; 433 } 434 break; 435 } 436 437 if (!f2g) { 438 if (adev->ip_versions[GC_HWIP][0]) 439 dev_err(kfd_device, "GC IP %06x %s not supported in kfd\n", 440 adev->ip_versions[GC_HWIP][0], vf ? "VF" : ""); 441 else 442 dev_err(kfd_device, "%s %s not supported in kfd\n", 443 amdgpu_asic_name[adev->asic_type], vf ? "VF" : ""); 444 return NULL; 445 } 446 447 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 448 if (!kfd) 449 return NULL; 450 451 kfd->adev = adev; 452 kfd_device_info_init(kfd, vf, gfx_target_version); 453 kfd->init_complete = false; 454 kfd->kfd2kgd = f2g; 455 atomic_set(&kfd->compute_profile, 0); 456 457 mutex_init(&kfd->doorbell_mutex); 458 memset(&kfd->doorbell_available_index, 0, 459 sizeof(kfd->doorbell_available_index)); 460 461 ida_init(&kfd->doorbell_ida); 462 463 return kfd; 464 } 465 466 static void kfd_cwsr_init(struct kfd_dev *kfd) 467 { 468 if (cwsr_enable && kfd->device_info.supports_cwsr) { 469 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) { 470 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE); 471 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 472 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 473 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) { 474 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE); 475 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 476 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 477 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) { 478 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) > PAGE_SIZE); 479 kfd->cwsr_isa = cwsr_trap_aldebaran_hex; 480 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); 481 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3)) { 482 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_4_3_hex) > PAGE_SIZE); 483 kfd->cwsr_isa = cwsr_trap_gfx9_4_3_hex; 484 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_4_3_hex); 485 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) { 486 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE); 487 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 488 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 489 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) { 490 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE); 491 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 492 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 493 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) { 494 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE); 495 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 496 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 497 } else { 498 BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE); 499 kfd->cwsr_isa = cwsr_trap_gfx11_hex; 500 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex); 501 } 502 503 kfd->cwsr_enabled = true; 504 } 505 } 506 507 static int kfd_gws_init(struct kfd_node *node) 508 { 509 int ret = 0; 510 struct kfd_dev *kfd = node->kfd; 511 uint32_t mes_rev = node->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; 512 513 if (node->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 514 return 0; 515 516 if (hws_gws_support || (KFD_IS_SOC15(node) && 517 ((KFD_GC_VERSION(node) == IP_VERSION(9, 0, 1) 518 && kfd->mec2_fw_version >= 0x81b3) || 519 (KFD_GC_VERSION(node) <= IP_VERSION(9, 4, 0) 520 && kfd->mec2_fw_version >= 0x1b3) || 521 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 1) 522 && kfd->mec2_fw_version >= 0x30) || 523 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 2) 524 && kfd->mec2_fw_version >= 0x28) || 525 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 3)) || 526 (KFD_GC_VERSION(node) >= IP_VERSION(10, 3, 0) 527 && KFD_GC_VERSION(node) < IP_VERSION(11, 0, 0) 528 && kfd->mec2_fw_version >= 0x6b) || 529 (KFD_GC_VERSION(node) >= IP_VERSION(11, 0, 0) 530 && KFD_GC_VERSION(node) < IP_VERSION(12, 0, 0) 531 && mes_rev >= 68)))) 532 ret = amdgpu_amdkfd_alloc_gws(node->adev, 533 node->adev->gds.gws_size, &node->gws); 534 535 return ret; 536 } 537 538 static void kfd_smi_init(struct kfd_node *dev) 539 { 540 INIT_LIST_HEAD(&dev->smi_clients); 541 spin_lock_init(&dev->smi_lock); 542 } 543 544 static int kfd_init_node(struct kfd_node *node) 545 { 546 int err = -1; 547 548 if (kfd_interrupt_init(node)) { 549 dev_err(kfd_device, "Error initializing interrupts\n"); 550 goto kfd_interrupt_error; 551 } 552 553 node->dqm = device_queue_manager_init(node); 554 if (!node->dqm) { 555 dev_err(kfd_device, "Error initializing queue manager\n"); 556 goto device_queue_manager_error; 557 } 558 559 if (kfd_gws_init(node)) { 560 dev_err(kfd_device, "Could not allocate %d gws\n", 561 node->adev->gds.gws_size); 562 goto gws_error; 563 } 564 565 if (kfd_resume(node)) 566 goto kfd_resume_error; 567 568 if (kfd_topology_add_device(node)) { 569 dev_err(kfd_device, "Error adding device to topology\n"); 570 goto kfd_topology_add_device_error; 571 } 572 573 kfd_smi_init(node); 574 575 return 0; 576 577 kfd_topology_add_device_error: 578 kfd_resume_error: 579 gws_error: 580 device_queue_manager_uninit(node->dqm); 581 device_queue_manager_error: 582 kfd_interrupt_exit(node); 583 kfd_interrupt_error: 584 if (node->gws) 585 amdgpu_amdkfd_free_gws(node->adev, node->gws); 586 587 /* Cleanup the node memory here */ 588 kfree(node); 589 return err; 590 } 591 592 static void kfd_cleanup_nodes(struct kfd_dev *kfd, unsigned int num_nodes) 593 { 594 struct kfd_node *knode; 595 unsigned int i; 596 597 for (i = 0; i < num_nodes; i++) { 598 knode = kfd->nodes[i]; 599 device_queue_manager_uninit(knode->dqm); 600 kfd_interrupt_exit(knode); 601 kfd_topology_remove_device(knode); 602 if (knode->gws) 603 amdgpu_amdkfd_free_gws(knode->adev, knode->gws); 604 kfree(knode); 605 kfd->nodes[i] = NULL; 606 } 607 } 608 609 static void kfd_setup_interrupt_bitmap(struct kfd_node *node, 610 unsigned int kfd_node_idx) 611 { 612 struct amdgpu_device *adev = node->adev; 613 uint32_t xcc_mask = node->xcc_mask; 614 uint32_t xcc, mapped_xcc; 615 /* 616 * Interrupt bitmap is setup for processing interrupts from 617 * different XCDs and AIDs. 618 * Interrupt bitmap is defined as follows: 619 * 1. Bits 0-15 - correspond to the NodeId field. 620 * Each bit corresponds to NodeId number. For example, if 621 * a KFD node has interrupt bitmap set to 0x7, then this 622 * KFD node will process interrupts with NodeId = 0, 1 and 2 623 * in the IH cookie. 624 * 2. Bits 16-31 - unused. 625 * 626 * Please note that the kfd_node_idx argument passed to this 627 * function is not related to NodeId field received in the 628 * IH cookie. 629 * 630 * In CPX mode, a KFD node will process an interrupt if: 631 * - the Node Id matches the corresponding bit set in 632 * Bits 0-15. 633 * - AND VMID reported in the interrupt lies within the 634 * VMID range of the node. 635 */ 636 for_each_inst(xcc, xcc_mask) { 637 mapped_xcc = GET_INST(GC, xcc); 638 node->interrupt_bitmap |= (mapped_xcc % 2 ? 5 : 3) << (4 * (mapped_xcc / 2)); 639 } 640 dev_info(kfd_device, "Node: %d, interrupt_bitmap: %x\n", kfd_node_idx, 641 node->interrupt_bitmap); 642 } 643 644 bool kgd2kfd_device_init(struct kfd_dev *kfd, 645 const struct kgd2kfd_shared_resources *gpu_resources) 646 { 647 unsigned int size, map_process_packet_size, i; 648 struct kfd_node *node; 649 uint32_t first_vmid_kfd, last_vmid_kfd, vmid_num_kfd; 650 unsigned int max_proc_per_quantum; 651 int partition_mode; 652 int xcp_idx; 653 654 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 655 KGD_ENGINE_MEC1); 656 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 657 KGD_ENGINE_MEC2); 658 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 659 KGD_ENGINE_SDMA1); 660 kfd->shared_resources = *gpu_resources; 661 662 kfd->num_nodes = amdgpu_xcp_get_num_xcp(kfd->adev->xcp_mgr); 663 664 if (kfd->num_nodes == 0) { 665 dev_err(kfd_device, 666 "KFD num nodes cannot be 0, num_xcc_in_node: %d\n", 667 kfd->adev->gfx.num_xcc_per_xcp); 668 goto out; 669 } 670 671 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 672 * 32 and 64-bit requests are possible and must be 673 * supported. 674 */ 675 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev); 676 if (!kfd->pci_atomic_requested && 677 kfd->device_info.needs_pci_atomics && 678 (!kfd->device_info.no_atomic_fw_version || 679 kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) { 680 dev_info(kfd_device, 681 "skipped device %x:%x, PCI rejects atomics %d<%d\n", 682 kfd->adev->pdev->vendor, kfd->adev->pdev->device, 683 kfd->mec_fw_version, 684 kfd->device_info.no_atomic_fw_version); 685 return false; 686 } 687 688 first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 689 last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 690 vmid_num_kfd = last_vmid_kfd - first_vmid_kfd + 1; 691 692 /* For GFX9.4.3, we need special handling for VMIDs depending on 693 * partition mode. 694 * In CPX mode, the VMID range needs to be shared between XCDs. 695 * Additionally, there are 13 VMIDs (3-15) available for KFD. To 696 * divide them equally, we change starting VMID to 4 and not use 697 * VMID 3. 698 * If the VMID range changes for GFX9.4.3, then this code MUST be 699 * revisited. 700 */ 701 if (kfd->adev->xcp_mgr) { 702 partition_mode = amdgpu_xcp_query_partition_mode(kfd->adev->xcp_mgr, 703 AMDGPU_XCP_FL_LOCKED); 704 if (partition_mode == AMDGPU_CPX_PARTITION_MODE && 705 kfd->num_nodes != 1) { 706 vmid_num_kfd /= 2; 707 first_vmid_kfd = last_vmid_kfd + 1 - vmid_num_kfd*2; 708 } 709 } 710 711 /* Verify module parameters regarding mapped process number*/ 712 if (hws_max_conc_proc >= 0) 713 max_proc_per_quantum = min((u32)hws_max_conc_proc, vmid_num_kfd); 714 else 715 max_proc_per_quantum = vmid_num_kfd; 716 717 /* calculate max size of mqds needed for queues */ 718 size = max_num_of_queues_per_device * 719 kfd->device_info.mqd_size_aligned; 720 721 /* 722 * calculate max size of runlist packet. 723 * There can be only 2 packets at once 724 */ 725 map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ? 726 sizeof(struct pm4_mes_map_process_aldebaran) : 727 sizeof(struct pm4_mes_map_process); 728 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + 729 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 730 + sizeof(struct pm4_mes_runlist)) * 2; 731 732 /* Add size of HIQ & DIQ */ 733 size += KFD_KERNEL_QUEUE_SIZE * 2; 734 735 /* add another 512KB for all other allocations on gart (HPD, fences) */ 736 size += 512 * 1024; 737 738 if (amdgpu_amdkfd_alloc_gtt_mem( 739 kfd->adev, size, &kfd->gtt_mem, 740 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 741 false)) { 742 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 743 goto alloc_gtt_mem_failure; 744 } 745 746 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 747 748 /* Initialize GTT sa with 512 byte chunk size */ 749 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 750 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 751 goto kfd_gtt_sa_init_error; 752 } 753 754 if (kfd_doorbell_init(kfd)) { 755 dev_err(kfd_device, 756 "Error initializing doorbell aperture\n"); 757 goto kfd_doorbell_error; 758 } 759 760 if (amdgpu_use_xgmi_p2p) 761 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id; 762 763 /* 764 * For GFX9.4.3, the KFD abstracts all partitions within a socket as 765 * xGMI connected in the topology so assign a unique hive id per 766 * device based on the pci device location if device is in PCIe mode. 767 */ 768 if (!kfd->hive_id && (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3)) && kfd->num_nodes > 1) 769 kfd->hive_id = pci_dev_id(kfd->adev->pdev); 770 771 kfd->noretry = kfd->adev->gmc.noretry; 772 773 /* If CRAT is broken, won't set iommu enabled */ 774 kfd_double_confirm_iommu_support(kfd); 775 776 if (kfd_iommu_device_init(kfd)) { 777 kfd->use_iommu_v2 = false; 778 dev_err(kfd_device, "Error initializing iommuv2\n"); 779 goto device_iommu_error; 780 } 781 782 kfd_cwsr_init(kfd); 783 784 dev_info(kfd_device, "Total number of KFD nodes to be created: %d\n", 785 kfd->num_nodes); 786 787 /* Allocate the KFD nodes */ 788 for (i = 0, xcp_idx = 0; i < kfd->num_nodes; i++) { 789 node = kzalloc(sizeof(struct kfd_node), GFP_KERNEL); 790 if (!node) 791 goto node_alloc_error; 792 793 node->node_id = i; 794 node->adev = kfd->adev; 795 node->kfd = kfd; 796 node->kfd2kgd = kfd->kfd2kgd; 797 node->vm_info.vmid_num_kfd = vmid_num_kfd; 798 node->xcp = amdgpu_get_next_xcp(kfd->adev->xcp_mgr, &xcp_idx); 799 /* TODO : Check if error handling is needed */ 800 if (node->xcp) { 801 amdgpu_xcp_get_inst_details(node->xcp, AMDGPU_XCP_GFX, 802 &node->xcc_mask); 803 ++xcp_idx; 804 } else { 805 node->xcc_mask = 806 (1U << NUM_XCC(kfd->adev->gfx.xcc_mask)) - 1; 807 } 808 809 if (node->xcp) { 810 dev_info(kfd_device, "KFD node %d partition %d size %lldM\n", 811 node->node_id, node->xcp->mem_id, 812 KFD_XCP_MEMORY_SIZE(node->adev, node->node_id) >> 20); 813 } 814 815 if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) && 816 partition_mode == AMDGPU_CPX_PARTITION_MODE && 817 kfd->num_nodes != 1) { 818 /* For GFX9.4.3 and CPX mode, first XCD gets VMID range 819 * 4-9 and second XCD gets VMID range 10-15. 820 */ 821 822 node->vm_info.first_vmid_kfd = (i%2 == 0) ? 823 first_vmid_kfd : 824 first_vmid_kfd+vmid_num_kfd; 825 node->vm_info.last_vmid_kfd = (i%2 == 0) ? 826 last_vmid_kfd-vmid_num_kfd : 827 last_vmid_kfd; 828 node->compute_vmid_bitmap = 829 ((0x1 << (node->vm_info.last_vmid_kfd + 1)) - 1) - 830 ((0x1 << (node->vm_info.first_vmid_kfd)) - 1); 831 } else { 832 node->vm_info.first_vmid_kfd = first_vmid_kfd; 833 node->vm_info.last_vmid_kfd = last_vmid_kfd; 834 node->compute_vmid_bitmap = 835 gpu_resources->compute_vmid_bitmap; 836 } 837 node->max_proc_per_quantum = max_proc_per_quantum; 838 atomic_set(&node->sram_ecc_flag, 0); 839 840 amdgpu_amdkfd_get_local_mem_info(kfd->adev, 841 &node->local_mem_info, node->xcp); 842 843 if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3)) 844 kfd_setup_interrupt_bitmap(node, i); 845 846 /* Initialize the KFD node */ 847 if (kfd_init_node(node)) { 848 dev_err(kfd_device, "Error initializing KFD node\n"); 849 goto node_init_error; 850 } 851 kfd->nodes[i] = node; 852 } 853 854 svm_range_set_max_pages(kfd->adev); 855 856 if (kfd_resume_iommu(kfd)) 857 goto kfd_resume_iommu_error; 858 859 spin_lock_init(&kfd->watch_points_lock); 860 861 kfd->init_complete = true; 862 dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, 863 kfd->adev->pdev->device); 864 865 pr_debug("Starting kfd with the following scheduling policy %d\n", 866 node->dqm->sched_policy); 867 868 goto out; 869 870 kfd_resume_iommu_error: 871 node_init_error: 872 node_alloc_error: 873 kfd_cleanup_nodes(kfd, i); 874 device_iommu_error: 875 kfd_doorbell_fini(kfd); 876 kfd_doorbell_error: 877 kfd_gtt_sa_fini(kfd); 878 kfd_gtt_sa_init_error: 879 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 880 alloc_gtt_mem_failure: 881 dev_err(kfd_device, 882 "device %x:%x NOT added due to errors\n", 883 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 884 out: 885 return kfd->init_complete; 886 } 887 888 void kgd2kfd_device_exit(struct kfd_dev *kfd) 889 { 890 if (kfd->init_complete) { 891 /* Cleanup KFD nodes */ 892 kfd_cleanup_nodes(kfd, kfd->num_nodes); 893 /* Cleanup common/shared resources */ 894 kfd_doorbell_fini(kfd); 895 ida_destroy(&kfd->doorbell_ida); 896 kfd_gtt_sa_fini(kfd); 897 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 898 } 899 900 kfree(kfd); 901 } 902 903 int kgd2kfd_pre_reset(struct kfd_dev *kfd) 904 { 905 struct kfd_node *node; 906 int i; 907 908 if (!kfd->init_complete) 909 return 0; 910 911 for (i = 0; i < kfd->num_nodes; i++) { 912 node = kfd->nodes[i]; 913 kfd_smi_event_update_gpu_reset(node, false); 914 node->dqm->ops.pre_reset(node->dqm); 915 } 916 917 kgd2kfd_suspend(kfd, false); 918 919 for (i = 0; i < kfd->num_nodes; i++) 920 kfd_signal_reset_event(kfd->nodes[i]); 921 922 return 0; 923 } 924 925 /* 926 * Fix me. KFD won't be able to resume existing process for now. 927 * We will keep all existing process in a evicted state and 928 * wait the process to be terminated. 929 */ 930 931 int kgd2kfd_post_reset(struct kfd_dev *kfd) 932 { 933 int ret; 934 struct kfd_node *node; 935 int i; 936 937 if (!kfd->init_complete) 938 return 0; 939 940 for (i = 0; i < kfd->num_nodes; i++) { 941 ret = kfd_resume(kfd->nodes[i]); 942 if (ret) 943 return ret; 944 } 945 946 mutex_lock(&kfd_processes_mutex); 947 --kfd_locked; 948 mutex_unlock(&kfd_processes_mutex); 949 950 for (i = 0; i < kfd->num_nodes; i++) { 951 node = kfd->nodes[i]; 952 atomic_set(&node->sram_ecc_flag, 0); 953 kfd_smi_event_update_gpu_reset(node, true); 954 } 955 956 return 0; 957 } 958 959 bool kfd_is_locked(void) 960 { 961 lockdep_assert_held(&kfd_processes_mutex); 962 return (kfd_locked > 0); 963 } 964 965 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 966 { 967 struct kfd_node *node; 968 int i; 969 int count; 970 971 if (!kfd->init_complete) 972 return; 973 974 /* for runtime suspend, skip locking kfd */ 975 if (!run_pm) { 976 mutex_lock(&kfd_processes_mutex); 977 count = ++kfd_locked; 978 mutex_unlock(&kfd_processes_mutex); 979 980 /* For first KFD device suspend all the KFD processes */ 981 if (count == 1) 982 kfd_suspend_all_processes(); 983 } 984 985 for (i = 0; i < kfd->num_nodes; i++) { 986 node = kfd->nodes[i]; 987 node->dqm->ops.stop(node->dqm); 988 } 989 kfd_iommu_suspend(kfd); 990 } 991 992 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 993 { 994 int ret, count, i; 995 996 if (!kfd->init_complete) 997 return 0; 998 999 for (i = 0; i < kfd->num_nodes; i++) { 1000 ret = kfd_resume(kfd->nodes[i]); 1001 if (ret) 1002 return ret; 1003 } 1004 1005 /* for runtime resume, skip unlocking kfd */ 1006 if (!run_pm) { 1007 mutex_lock(&kfd_processes_mutex); 1008 count = --kfd_locked; 1009 mutex_unlock(&kfd_processes_mutex); 1010 1011 WARN_ONCE(count < 0, "KFD suspend / resume ref. error"); 1012 if (count == 0) 1013 ret = kfd_resume_all_processes(); 1014 } 1015 1016 return ret; 1017 } 1018 1019 int kgd2kfd_resume_iommu(struct kfd_dev *kfd) 1020 { 1021 if (!kfd->init_complete) 1022 return 0; 1023 1024 return kfd_resume_iommu(kfd); 1025 } 1026 1027 static int kfd_resume_iommu(struct kfd_dev *kfd) 1028 { 1029 int err = 0; 1030 1031 err = kfd_iommu_resume(kfd); 1032 if (err) 1033 dev_err(kfd_device, 1034 "Failed to resume IOMMU for device %x:%x\n", 1035 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 1036 return err; 1037 } 1038 1039 static int kfd_resume(struct kfd_node *node) 1040 { 1041 int err = 0; 1042 1043 err = node->dqm->ops.start(node->dqm); 1044 if (err) 1045 dev_err(kfd_device, 1046 "Error starting queue manager for device %x:%x\n", 1047 node->adev->pdev->vendor, node->adev->pdev->device); 1048 1049 return err; 1050 } 1051 1052 static inline void kfd_queue_work(struct workqueue_struct *wq, 1053 struct work_struct *work) 1054 { 1055 int cpu, new_cpu; 1056 1057 cpu = new_cpu = smp_processor_id(); 1058 do { 1059 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids; 1060 if (cpu_to_node(new_cpu) == numa_node_id()) 1061 break; 1062 } while (cpu != new_cpu); 1063 1064 queue_work_on(new_cpu, wq, work); 1065 } 1066 1067 /* This is called directly from KGD at ISR. */ 1068 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 1069 { 1070 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE], i; 1071 bool is_patched = false; 1072 unsigned long flags; 1073 struct kfd_node *node; 1074 1075 if (!kfd->init_complete) 1076 return; 1077 1078 if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) { 1079 dev_err_once(kfd_device, "Ring entry too small\n"); 1080 return; 1081 } 1082 1083 for (i = 0; i < kfd->num_nodes; i++) { 1084 node = kfd->nodes[i]; 1085 spin_lock_irqsave(&node->interrupt_lock, flags); 1086 1087 if (node->interrupts_active 1088 && interrupt_is_wanted(node, ih_ring_entry, 1089 patched_ihre, &is_patched) 1090 && enqueue_ih_ring_entry(node, 1091 is_patched ? patched_ihre : ih_ring_entry)) { 1092 kfd_queue_work(node->ih_wq, &node->interrupt_work); 1093 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1094 return; 1095 } 1096 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1097 } 1098 1099 } 1100 1101 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger) 1102 { 1103 struct kfd_process *p; 1104 int r; 1105 1106 /* Because we are called from arbitrary context (workqueue) as opposed 1107 * to process context, kfd_process could attempt to exit while we are 1108 * running so the lookup function increments the process ref count. 1109 */ 1110 p = kfd_lookup_process_by_mm(mm); 1111 if (!p) 1112 return -ESRCH; 1113 1114 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 1115 r = kfd_process_evict_queues(p, trigger); 1116 1117 kfd_unref_process(p); 1118 return r; 1119 } 1120 1121 int kgd2kfd_resume_mm(struct mm_struct *mm) 1122 { 1123 struct kfd_process *p; 1124 int r; 1125 1126 /* Because we are called from arbitrary context (workqueue) as opposed 1127 * to process context, kfd_process could attempt to exit while we are 1128 * running so the lookup function increments the process ref count. 1129 */ 1130 p = kfd_lookup_process_by_mm(mm); 1131 if (!p) 1132 return -ESRCH; 1133 1134 r = kfd_process_restore_queues(p); 1135 1136 kfd_unref_process(p); 1137 return r; 1138 } 1139 1140 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 1141 * prepare for safe eviction of KFD BOs that belong to the specified 1142 * process. 1143 * 1144 * @mm: mm_struct that identifies the specified KFD process 1145 * @fence: eviction fence attached to KFD process BOs 1146 * 1147 */ 1148 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 1149 struct dma_fence *fence) 1150 { 1151 struct kfd_process *p; 1152 unsigned long active_time; 1153 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 1154 1155 if (!fence) 1156 return -EINVAL; 1157 1158 if (dma_fence_is_signaled(fence)) 1159 return 0; 1160 1161 p = kfd_lookup_process_by_mm(mm); 1162 if (!p) 1163 return -ENODEV; 1164 1165 if (fence->seqno == p->last_eviction_seqno) 1166 goto out; 1167 1168 p->last_eviction_seqno = fence->seqno; 1169 1170 /* Avoid KFD process starvation. Wait for at least 1171 * PROCESS_ACTIVE_TIME_MS before evicting the process again 1172 */ 1173 active_time = get_jiffies_64() - p->last_restore_timestamp; 1174 if (delay_jiffies > active_time) 1175 delay_jiffies -= active_time; 1176 else 1177 delay_jiffies = 0; 1178 1179 /* During process initialization eviction_work.dwork is initialized 1180 * to kfd_evict_bo_worker 1181 */ 1182 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 1183 p->lead_thread->pid, delay_jiffies); 1184 schedule_delayed_work(&p->eviction_work, delay_jiffies); 1185 out: 1186 kfd_unref_process(p); 1187 return 0; 1188 } 1189 1190 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 1191 unsigned int chunk_size) 1192 { 1193 if (WARN_ON(buf_size < chunk_size)) 1194 return -EINVAL; 1195 if (WARN_ON(buf_size == 0)) 1196 return -EINVAL; 1197 if (WARN_ON(chunk_size == 0)) 1198 return -EINVAL; 1199 1200 kfd->gtt_sa_chunk_size = chunk_size; 1201 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 1202 1203 kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks, 1204 GFP_KERNEL); 1205 if (!kfd->gtt_sa_bitmap) 1206 return -ENOMEM; 1207 1208 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 1209 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 1210 1211 mutex_init(&kfd->gtt_sa_lock); 1212 1213 return 0; 1214 } 1215 1216 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 1217 { 1218 mutex_destroy(&kfd->gtt_sa_lock); 1219 bitmap_free(kfd->gtt_sa_bitmap); 1220 } 1221 1222 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 1223 unsigned int bit_num, 1224 unsigned int chunk_size) 1225 { 1226 return start_addr + bit_num * chunk_size; 1227 } 1228 1229 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 1230 unsigned int bit_num, 1231 unsigned int chunk_size) 1232 { 1233 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 1234 } 1235 1236 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size, 1237 struct kfd_mem_obj **mem_obj) 1238 { 1239 unsigned int found, start_search, cur_size; 1240 struct kfd_dev *kfd = node->kfd; 1241 1242 if (size == 0) 1243 return -EINVAL; 1244 1245 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 1246 return -ENOMEM; 1247 1248 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 1249 if (!(*mem_obj)) 1250 return -ENOMEM; 1251 1252 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 1253 1254 start_search = 0; 1255 1256 mutex_lock(&kfd->gtt_sa_lock); 1257 1258 kfd_gtt_restart_search: 1259 /* Find the first chunk that is free */ 1260 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1261 kfd->gtt_sa_num_of_chunks, 1262 start_search); 1263 1264 pr_debug("Found = %d\n", found); 1265 1266 /* If there wasn't any free chunk, bail out */ 1267 if (found == kfd->gtt_sa_num_of_chunks) 1268 goto kfd_gtt_no_free_chunk; 1269 1270 /* Update fields of mem_obj */ 1271 (*mem_obj)->range_start = found; 1272 (*mem_obj)->range_end = found; 1273 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1274 kfd->gtt_start_gpu_addr, 1275 found, 1276 kfd->gtt_sa_chunk_size); 1277 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1278 kfd->gtt_start_cpu_ptr, 1279 found, 1280 kfd->gtt_sa_chunk_size); 1281 1282 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1283 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1284 1285 /* If we need only one chunk, mark it as allocated and get out */ 1286 if (size <= kfd->gtt_sa_chunk_size) { 1287 pr_debug("Single bit\n"); 1288 __set_bit(found, kfd->gtt_sa_bitmap); 1289 goto kfd_gtt_out; 1290 } 1291 1292 /* Otherwise, try to see if we have enough contiguous chunks */ 1293 cur_size = size - kfd->gtt_sa_chunk_size; 1294 do { 1295 (*mem_obj)->range_end = 1296 find_next_zero_bit(kfd->gtt_sa_bitmap, 1297 kfd->gtt_sa_num_of_chunks, ++found); 1298 /* 1299 * If next free chunk is not contiguous than we need to 1300 * restart our search from the last free chunk we found (which 1301 * wasn't contiguous to the previous ones 1302 */ 1303 if ((*mem_obj)->range_end != found) { 1304 start_search = found; 1305 goto kfd_gtt_restart_search; 1306 } 1307 1308 /* 1309 * If we reached end of buffer, bail out with error 1310 */ 1311 if (found == kfd->gtt_sa_num_of_chunks) 1312 goto kfd_gtt_no_free_chunk; 1313 1314 /* Check if we don't need another chunk */ 1315 if (cur_size <= kfd->gtt_sa_chunk_size) 1316 cur_size = 0; 1317 else 1318 cur_size -= kfd->gtt_sa_chunk_size; 1319 1320 } while (cur_size > 0); 1321 1322 pr_debug("range_start = %d, range_end = %d\n", 1323 (*mem_obj)->range_start, (*mem_obj)->range_end); 1324 1325 /* Mark the chunks as allocated */ 1326 bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start, 1327 (*mem_obj)->range_end - (*mem_obj)->range_start + 1); 1328 1329 kfd_gtt_out: 1330 mutex_unlock(&kfd->gtt_sa_lock); 1331 return 0; 1332 1333 kfd_gtt_no_free_chunk: 1334 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1335 mutex_unlock(&kfd->gtt_sa_lock); 1336 kfree(*mem_obj); 1337 return -ENOMEM; 1338 } 1339 1340 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj) 1341 { 1342 struct kfd_dev *kfd = node->kfd; 1343 1344 /* Act like kfree when trying to free a NULL object */ 1345 if (!mem_obj) 1346 return 0; 1347 1348 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1349 mem_obj, mem_obj->range_start, mem_obj->range_end); 1350 1351 mutex_lock(&kfd->gtt_sa_lock); 1352 1353 /* Mark the chunks as free */ 1354 bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start, 1355 mem_obj->range_end - mem_obj->range_start + 1); 1356 1357 mutex_unlock(&kfd->gtt_sa_lock); 1358 1359 kfree(mem_obj); 1360 return 0; 1361 } 1362 1363 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1364 { 1365 /* 1366 * TODO: Currently update SRAM ECC flag for first node. 1367 * This needs to be updated later when we can 1368 * identify SRAM ECC error on other nodes also. 1369 */ 1370 if (kfd) 1371 atomic_inc(&kfd->nodes[0]->sram_ecc_flag); 1372 } 1373 1374 void kfd_inc_compute_active(struct kfd_node *node) 1375 { 1376 if (atomic_inc_return(&node->kfd->compute_profile) == 1) 1377 amdgpu_amdkfd_set_compute_idle(node->adev, false); 1378 } 1379 1380 void kfd_dec_compute_active(struct kfd_node *node) 1381 { 1382 int count = atomic_dec_return(&node->kfd->compute_profile); 1383 1384 if (count == 0) 1385 amdgpu_amdkfd_set_compute_idle(node->adev, true); 1386 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1387 } 1388 1389 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 1390 { 1391 /* 1392 * TODO: For now, raise the throttling event only on first node. 1393 * This will need to change after we are able to determine 1394 * which node raised the throttling event. 1395 */ 1396 if (kfd && kfd->init_complete) 1397 kfd_smi_event_update_thermal_throttling(kfd->nodes[0], 1398 throttle_bitmask); 1399 } 1400 1401 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and 1402 * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA. 1403 * When the device has more than two engines, we reserve two for PCIe to enable 1404 * full-duplex and the rest are used as XGMI. 1405 */ 1406 unsigned int kfd_get_num_sdma_engines(struct kfd_node *node) 1407 { 1408 /* If XGMI is not supported, all SDMA engines are PCIe */ 1409 if (!node->adev->gmc.xgmi.supported) 1410 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes; 1411 1412 return min(node->adev->sdma.num_instances/(int)node->kfd->num_nodes, 2); 1413 } 1414 1415 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *node) 1416 { 1417 /* After reserved for PCIe, the rest of engines are XGMI */ 1418 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes - 1419 kfd_get_num_sdma_engines(node); 1420 } 1421 1422 int kgd2kfd_check_and_lock_kfd(void) 1423 { 1424 mutex_lock(&kfd_processes_mutex); 1425 if (!hash_empty(kfd_processes_table) || kfd_is_locked()) { 1426 mutex_unlock(&kfd_processes_mutex); 1427 return -EBUSY; 1428 } 1429 1430 ++kfd_locked; 1431 mutex_unlock(&kfd_processes_mutex); 1432 1433 return 0; 1434 } 1435 1436 void kgd2kfd_unlock_kfd(void) 1437 { 1438 mutex_lock(&kfd_processes_mutex); 1439 --kfd_locked; 1440 mutex_unlock(&kfd_processes_mutex); 1441 } 1442 1443 #if defined(CONFIG_DEBUG_FS) 1444 1445 /* This function will send a package to HIQ to hang the HWS 1446 * which will trigger a GPU reset and bring the HWS back to normal state 1447 */ 1448 int kfd_debugfs_hang_hws(struct kfd_node *dev) 1449 { 1450 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1451 pr_err("HWS is not enabled"); 1452 return -EINVAL; 1453 } 1454 1455 return dqm_debugfs_hang_hws(dev->dqm); 1456 } 1457 1458 #endif 1459