1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/bsearch.h> 25 #include <linux/pci.h> 26 #include <linux/slab.h> 27 #include "kfd_priv.h" 28 #include "kfd_device_queue_manager.h" 29 #include "kfd_pm4_headers_vi.h" 30 #include "kfd_pm4_headers_aldebaran.h" 31 #include "cwsr_trap_handler.h" 32 #include "kfd_iommu.h" 33 #include "amdgpu_amdkfd.h" 34 #include "kfd_smi_events.h" 35 #include "kfd_migrate.h" 36 #include "amdgpu.h" 37 38 #define MQD_SIZE_ALIGNED 768 39 40 /* 41 * kfd_locked is used to lock the kfd driver during suspend or reset 42 * once locked, kfd driver will stop any further GPU execution. 43 * create process (open) will return -EAGAIN. 44 */ 45 static atomic_t kfd_locked = ATOMIC_INIT(0); 46 47 #ifdef CONFIG_DRM_AMDGPU_CIK 48 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 49 #endif 50 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 51 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 52 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 53 extern const struct kfd2kgd_calls aldebaran_kfd2kgd; 54 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 55 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 56 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd; 57 58 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 59 unsigned int chunk_size); 60 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 61 62 static int kfd_resume(struct kfd_dev *kfd); 63 64 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) 65 { 66 uint32_t sdma_version = kfd->adev->ip_versions[SDMA0_HWIP][0]; 67 68 switch (sdma_version) { 69 case IP_VERSION(4, 0, 0):/* VEGA10 */ 70 case IP_VERSION(4, 0, 1):/* VEGA12 */ 71 case IP_VERSION(4, 1, 0):/* RAVEN */ 72 case IP_VERSION(4, 1, 1):/* RAVEN */ 73 case IP_VERSION(4, 1, 2):/* RENOIR */ 74 case IP_VERSION(5, 2, 1):/* VANGOGH */ 75 case IP_VERSION(5, 2, 3):/* YELLOW_CARP */ 76 case IP_VERSION(5, 2, 6):/* GC 10.3.6 */ 77 case IP_VERSION(5, 2, 7):/* GC 10.3.7 */ 78 kfd->device_info.num_sdma_queues_per_engine = 2; 79 break; 80 case IP_VERSION(4, 2, 0):/* VEGA20 */ 81 case IP_VERSION(4, 2, 2):/* ARCTURUS */ 82 case IP_VERSION(4, 4, 0):/* ALDEBARAN */ 83 case IP_VERSION(5, 0, 0):/* NAVI10 */ 84 case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */ 85 case IP_VERSION(5, 0, 2):/* NAVI14 */ 86 case IP_VERSION(5, 0, 5):/* NAVI12 */ 87 case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */ 88 case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */ 89 case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */ 90 case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */ 91 case IP_VERSION(6, 0, 0): 92 case IP_VERSION(6, 0, 1): 93 case IP_VERSION(6, 0, 2): 94 kfd->device_info.num_sdma_queues_per_engine = 8; 95 break; 96 default: 97 dev_warn(kfd_device, 98 "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n", 99 sdma_version); 100 kfd->device_info.num_sdma_queues_per_engine = 8; 101 } 102 103 switch (sdma_version) { 104 case IP_VERSION(6, 0, 0): 105 case IP_VERSION(6, 0, 2): 106 /* Reserve 1 for paging and 1 for gfx */ 107 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 108 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */ 109 kfd->device_info.reserved_sdma_queues_bitmap = 0xFULL; 110 break; 111 case IP_VERSION(6, 0, 1): 112 /* Reserve 1 for paging and 1 for gfx */ 113 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 114 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-0 queue-1; ... */ 115 kfd->device_info.reserved_sdma_queues_bitmap = 0x3ULL; 116 break; 117 default: 118 break; 119 } 120 } 121 122 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) 123 { 124 uint32_t gc_version = KFD_GC_VERSION(kfd); 125 126 switch (gc_version) { 127 case IP_VERSION(9, 0, 1): /* VEGA10 */ 128 case IP_VERSION(9, 1, 0): /* RAVEN */ 129 case IP_VERSION(9, 2, 1): /* VEGA12 */ 130 case IP_VERSION(9, 2, 2): /* RAVEN */ 131 case IP_VERSION(9, 3, 0): /* RENOIR */ 132 case IP_VERSION(9, 4, 0): /* VEGA20 */ 133 case IP_VERSION(9, 4, 1): /* ARCTURUS */ 134 case IP_VERSION(9, 4, 2): /* ALDEBARAN */ 135 case IP_VERSION(10, 3, 1): /* VANGOGH */ 136 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */ 137 case IP_VERSION(10, 3, 6): /* GC 10.3.6 */ 138 case IP_VERSION(10, 3, 7): /* GC 10.3.7 */ 139 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */ 140 case IP_VERSION(10, 1, 4): 141 case IP_VERSION(10, 1, 10): /* NAVI10 */ 142 case IP_VERSION(10, 1, 2): /* NAVI12 */ 143 case IP_VERSION(10, 1, 1): /* NAVI14 */ 144 case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */ 145 case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */ 146 case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */ 147 case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */ 148 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 149 break; 150 case IP_VERSION(11, 0, 0): 151 case IP_VERSION(11, 0, 1): 152 case IP_VERSION(11, 0, 2): 153 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 154 break; 155 default: 156 dev_warn(kfd_device, "v9 event interrupt handler is set due to " 157 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version); 158 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 159 } 160 } 161 162 static void kfd_device_info_init(struct kfd_dev *kfd, 163 bool vf, uint32_t gfx_target_version) 164 { 165 uint32_t gc_version = KFD_GC_VERSION(kfd); 166 uint32_t asic_type = kfd->adev->asic_type; 167 168 kfd->device_info.max_pasid_bits = 16; 169 kfd->device_info.max_no_of_hqd = 24; 170 kfd->device_info.num_of_watch_points = 4; 171 kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED; 172 kfd->device_info.gfx_target_version = gfx_target_version; 173 174 if (KFD_IS_SOC15(kfd)) { 175 kfd->device_info.doorbell_size = 8; 176 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t); 177 kfd->device_info.supports_cwsr = true; 178 179 kfd_device_info_set_sdma_info(kfd); 180 181 kfd_device_info_set_event_interrupt_class(kfd); 182 183 /* Raven */ 184 if (gc_version == IP_VERSION(9, 1, 0) || 185 gc_version == IP_VERSION(9, 2, 2)) 186 kfd->device_info.needs_iommu_device = true; 187 188 if (gc_version < IP_VERSION(11, 0, 0)) { 189 /* Navi2x+, Navi1x+ */ 190 if (gc_version == IP_VERSION(10, 3, 6)) 191 kfd->device_info.no_atomic_fw_version = 14; 192 else if (gc_version == IP_VERSION(10, 3, 7)) 193 kfd->device_info.no_atomic_fw_version = 3; 194 else if (gc_version >= IP_VERSION(10, 3, 0)) 195 kfd->device_info.no_atomic_fw_version = 92; 196 else if (gc_version >= IP_VERSION(10, 1, 1)) 197 kfd->device_info.no_atomic_fw_version = 145; 198 199 /* Navi1x+ */ 200 if (gc_version >= IP_VERSION(10, 1, 1)) 201 kfd->device_info.needs_pci_atomics = true; 202 } 203 } else { 204 kfd->device_info.doorbell_size = 4; 205 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t); 206 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik; 207 kfd->device_info.num_sdma_queues_per_engine = 2; 208 209 if (asic_type != CHIP_KAVERI && 210 asic_type != CHIP_HAWAII && 211 asic_type != CHIP_TONGA) 212 kfd->device_info.supports_cwsr = true; 213 214 if (asic_type == CHIP_KAVERI || 215 asic_type == CHIP_CARRIZO) 216 kfd->device_info.needs_iommu_device = true; 217 218 if (asic_type != CHIP_HAWAII && !vf) 219 kfd->device_info.needs_pci_atomics = true; 220 } 221 } 222 223 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 224 { 225 struct kfd_dev *kfd = NULL; 226 const struct kfd2kgd_calls *f2g = NULL; 227 struct pci_dev *pdev = adev->pdev; 228 uint32_t gfx_target_version = 0; 229 230 switch (adev->asic_type) { 231 #ifdef KFD_SUPPORT_IOMMU_V2 232 #ifdef CONFIG_DRM_AMDGPU_CIK 233 case CHIP_KAVERI: 234 gfx_target_version = 70000; 235 if (!vf) 236 f2g = &gfx_v7_kfd2kgd; 237 break; 238 #endif 239 case CHIP_CARRIZO: 240 gfx_target_version = 80001; 241 if (!vf) 242 f2g = &gfx_v8_kfd2kgd; 243 break; 244 #endif 245 #ifdef CONFIG_DRM_AMDGPU_CIK 246 case CHIP_HAWAII: 247 gfx_target_version = 70001; 248 if (!amdgpu_exp_hw_support) 249 pr_info( 250 "KFD support on Hawaii is experimental. See modparam exp_hw_support\n" 251 ); 252 else if (!vf) 253 f2g = &gfx_v7_kfd2kgd; 254 break; 255 #endif 256 case CHIP_TONGA: 257 gfx_target_version = 80002; 258 if (!vf) 259 f2g = &gfx_v8_kfd2kgd; 260 break; 261 case CHIP_FIJI: 262 gfx_target_version = 80003; 263 f2g = &gfx_v8_kfd2kgd; 264 break; 265 case CHIP_POLARIS10: 266 gfx_target_version = 80003; 267 f2g = &gfx_v8_kfd2kgd; 268 break; 269 case CHIP_POLARIS11: 270 gfx_target_version = 80003; 271 if (!vf) 272 f2g = &gfx_v8_kfd2kgd; 273 break; 274 case CHIP_POLARIS12: 275 gfx_target_version = 80003; 276 if (!vf) 277 f2g = &gfx_v8_kfd2kgd; 278 break; 279 case CHIP_VEGAM: 280 gfx_target_version = 80003; 281 if (!vf) 282 f2g = &gfx_v8_kfd2kgd; 283 break; 284 default: 285 switch (adev->ip_versions[GC_HWIP][0]) { 286 /* Vega 10 */ 287 case IP_VERSION(9, 0, 1): 288 gfx_target_version = 90000; 289 f2g = &gfx_v9_kfd2kgd; 290 break; 291 #ifdef KFD_SUPPORT_IOMMU_V2 292 /* Raven */ 293 case IP_VERSION(9, 1, 0): 294 case IP_VERSION(9, 2, 2): 295 gfx_target_version = 90002; 296 if (!vf) 297 f2g = &gfx_v9_kfd2kgd; 298 break; 299 #endif 300 /* Vega12 */ 301 case IP_VERSION(9, 2, 1): 302 gfx_target_version = 90004; 303 if (!vf) 304 f2g = &gfx_v9_kfd2kgd; 305 break; 306 /* Renoir */ 307 case IP_VERSION(9, 3, 0): 308 gfx_target_version = 90012; 309 if (!vf) 310 f2g = &gfx_v9_kfd2kgd; 311 break; 312 /* Vega20 */ 313 case IP_VERSION(9, 4, 0): 314 gfx_target_version = 90006; 315 if (!vf) 316 f2g = &gfx_v9_kfd2kgd; 317 break; 318 /* Arcturus */ 319 case IP_VERSION(9, 4, 1): 320 gfx_target_version = 90008; 321 f2g = &arcturus_kfd2kgd; 322 break; 323 /* Aldebaran */ 324 case IP_VERSION(9, 4, 2): 325 gfx_target_version = 90010; 326 f2g = &aldebaran_kfd2kgd; 327 break; 328 /* Navi10 */ 329 case IP_VERSION(10, 1, 10): 330 gfx_target_version = 100100; 331 if (!vf) 332 f2g = &gfx_v10_kfd2kgd; 333 break; 334 /* Navi12 */ 335 case IP_VERSION(10, 1, 2): 336 gfx_target_version = 100101; 337 f2g = &gfx_v10_kfd2kgd; 338 break; 339 /* Navi14 */ 340 case IP_VERSION(10, 1, 1): 341 gfx_target_version = 100102; 342 if (!vf) 343 f2g = &gfx_v10_kfd2kgd; 344 break; 345 /* Cyan Skillfish */ 346 case IP_VERSION(10, 1, 3): 347 case IP_VERSION(10, 1, 4): 348 gfx_target_version = 100103; 349 if (!vf) 350 f2g = &gfx_v10_kfd2kgd; 351 break; 352 /* Sienna Cichlid */ 353 case IP_VERSION(10, 3, 0): 354 gfx_target_version = 100300; 355 f2g = &gfx_v10_3_kfd2kgd; 356 break; 357 /* Navy Flounder */ 358 case IP_VERSION(10, 3, 2): 359 gfx_target_version = 100301; 360 f2g = &gfx_v10_3_kfd2kgd; 361 break; 362 /* Van Gogh */ 363 case IP_VERSION(10, 3, 1): 364 gfx_target_version = 100303; 365 if (!vf) 366 f2g = &gfx_v10_3_kfd2kgd; 367 break; 368 /* Dimgrey Cavefish */ 369 case IP_VERSION(10, 3, 4): 370 gfx_target_version = 100302; 371 f2g = &gfx_v10_3_kfd2kgd; 372 break; 373 /* Beige Goby */ 374 case IP_VERSION(10, 3, 5): 375 gfx_target_version = 100304; 376 f2g = &gfx_v10_3_kfd2kgd; 377 break; 378 /* Yellow Carp */ 379 case IP_VERSION(10, 3, 3): 380 gfx_target_version = 100305; 381 if (!vf) 382 f2g = &gfx_v10_3_kfd2kgd; 383 break; 384 case IP_VERSION(10, 3, 6): 385 gfx_target_version = 100306; 386 if (!vf) 387 f2g = &gfx_v10_3_kfd2kgd; 388 break; 389 case IP_VERSION(10, 3, 7): 390 gfx_target_version = 100307; 391 if (!vf) 392 f2g = &gfx_v10_3_kfd2kgd; 393 break; 394 case IP_VERSION(11, 0, 0): 395 gfx_target_version = 110000; 396 f2g = &gfx_v11_kfd2kgd; 397 break; 398 case IP_VERSION(11, 0, 1): 399 gfx_target_version = 110003; 400 f2g = &gfx_v11_kfd2kgd; 401 break; 402 case IP_VERSION(11, 0, 2): 403 gfx_target_version = 110002; 404 f2g = &gfx_v11_kfd2kgd; 405 break; 406 default: 407 break; 408 } 409 break; 410 } 411 412 if (!f2g) { 413 if (adev->ip_versions[GC_HWIP][0]) 414 dev_err(kfd_device, "GC IP %06x %s not supported in kfd\n", 415 adev->ip_versions[GC_HWIP][0], vf ? "VF" : ""); 416 else 417 dev_err(kfd_device, "%s %s not supported in kfd\n", 418 amdgpu_asic_name[adev->asic_type], vf ? "VF" : ""); 419 return NULL; 420 } 421 422 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 423 if (!kfd) 424 return NULL; 425 426 kfd->adev = adev; 427 kfd_device_info_init(kfd, vf, gfx_target_version); 428 kfd->pdev = pdev; 429 kfd->init_complete = false; 430 kfd->kfd2kgd = f2g; 431 atomic_set(&kfd->compute_profile, 0); 432 433 mutex_init(&kfd->doorbell_mutex); 434 memset(&kfd->doorbell_available_index, 0, 435 sizeof(kfd->doorbell_available_index)); 436 437 atomic_set(&kfd->sram_ecc_flag, 0); 438 439 ida_init(&kfd->doorbell_ida); 440 441 return kfd; 442 } 443 444 static void kfd_cwsr_init(struct kfd_dev *kfd) 445 { 446 if (cwsr_enable && kfd->device_info.supports_cwsr) { 447 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) { 448 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE); 449 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 450 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 451 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) { 452 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE); 453 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 454 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 455 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) { 456 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) > PAGE_SIZE); 457 kfd->cwsr_isa = cwsr_trap_aldebaran_hex; 458 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); 459 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) { 460 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE); 461 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 462 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 463 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) { 464 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE); 465 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 466 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 467 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) { 468 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE); 469 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 470 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 471 } else { 472 BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE); 473 kfd->cwsr_isa = cwsr_trap_gfx11_hex; 474 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex); 475 } 476 477 kfd->cwsr_enabled = true; 478 } 479 } 480 481 static int kfd_gws_init(struct kfd_dev *kfd) 482 { 483 int ret = 0; 484 485 if (kfd->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 486 return 0; 487 488 if (hws_gws_support || (KFD_IS_SOC15(kfd) && 489 ((KFD_GC_VERSION(kfd) == IP_VERSION(9, 0, 1) 490 && kfd->mec2_fw_version >= 0x81b3) || 491 (KFD_GC_VERSION(kfd) <= IP_VERSION(9, 4, 0) 492 && kfd->mec2_fw_version >= 0x1b3) || 493 (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1) 494 && kfd->mec2_fw_version >= 0x30) || 495 (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) 496 && kfd->mec2_fw_version >= 0x28)))) 497 ret = amdgpu_amdkfd_alloc_gws(kfd->adev, 498 kfd->adev->gds.gws_size, &kfd->gws); 499 500 return ret; 501 } 502 503 static void kfd_smi_init(struct kfd_dev *dev) 504 { 505 INIT_LIST_HEAD(&dev->smi_clients); 506 spin_lock_init(&dev->smi_lock); 507 } 508 509 bool kgd2kfd_device_init(struct kfd_dev *kfd, 510 struct drm_device *ddev, 511 const struct kgd2kfd_shared_resources *gpu_resources) 512 { 513 unsigned int size, map_process_packet_size; 514 515 kfd->ddev = ddev; 516 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 517 KGD_ENGINE_MEC1); 518 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 519 KGD_ENGINE_MEC2); 520 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 521 KGD_ENGINE_SDMA1); 522 kfd->shared_resources = *gpu_resources; 523 524 kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 525 kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 526 kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd 527 - kfd->vm_info.first_vmid_kfd + 1; 528 529 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 530 * 32 and 64-bit requests are possible and must be 531 * supported. 532 */ 533 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev); 534 if (!kfd->pci_atomic_requested && 535 kfd->device_info.needs_pci_atomics && 536 (!kfd->device_info.no_atomic_fw_version || 537 kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) { 538 dev_info(kfd_device, 539 "skipped device %x:%x, PCI rejects atomics %d<%d\n", 540 kfd->pdev->vendor, kfd->pdev->device, 541 kfd->mec_fw_version, 542 kfd->device_info.no_atomic_fw_version); 543 return false; 544 } 545 546 /* Verify module parameters regarding mapped process number*/ 547 if (hws_max_conc_proc >= 0) 548 kfd->max_proc_per_quantum = min((u32)hws_max_conc_proc, kfd->vm_info.vmid_num_kfd); 549 else 550 kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd; 551 552 /* calculate max size of mqds needed for queues */ 553 size = max_num_of_queues_per_device * 554 kfd->device_info.mqd_size_aligned; 555 556 /* 557 * calculate max size of runlist packet. 558 * There can be only 2 packets at once 559 */ 560 map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ? 561 sizeof(struct pm4_mes_map_process_aldebaran) : 562 sizeof(struct pm4_mes_map_process); 563 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + 564 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 565 + sizeof(struct pm4_mes_runlist)) * 2; 566 567 /* Add size of HIQ & DIQ */ 568 size += KFD_KERNEL_QUEUE_SIZE * 2; 569 570 /* add another 512KB for all other allocations on gart (HPD, fences) */ 571 size += 512 * 1024; 572 573 if (amdgpu_amdkfd_alloc_gtt_mem( 574 kfd->adev, size, &kfd->gtt_mem, 575 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 576 false)) { 577 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 578 goto alloc_gtt_mem_failure; 579 } 580 581 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 582 583 /* Initialize GTT sa with 512 byte chunk size */ 584 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 585 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 586 goto kfd_gtt_sa_init_error; 587 } 588 589 if (kfd_doorbell_init(kfd)) { 590 dev_err(kfd_device, 591 "Error initializing doorbell aperture\n"); 592 goto kfd_doorbell_error; 593 } 594 595 if (amdgpu_use_xgmi_p2p) 596 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id; 597 598 kfd->noretry = kfd->adev->gmc.noretry; 599 600 if (kfd_interrupt_init(kfd)) { 601 dev_err(kfd_device, "Error initializing interrupts\n"); 602 goto kfd_interrupt_error; 603 } 604 605 kfd->dqm = device_queue_manager_init(kfd); 606 if (!kfd->dqm) { 607 dev_err(kfd_device, "Error initializing queue manager\n"); 608 goto device_queue_manager_error; 609 } 610 611 /* If supported on this device, allocate global GWS that is shared 612 * by all KFD processes 613 */ 614 if (kfd_gws_init(kfd)) { 615 dev_err(kfd_device, "Could not allocate %d gws\n", 616 kfd->adev->gds.gws_size); 617 goto gws_error; 618 } 619 620 /* If CRAT is broken, won't set iommu enabled */ 621 kfd_double_confirm_iommu_support(kfd); 622 623 if (kfd_iommu_device_init(kfd)) { 624 kfd->use_iommu_v2 = false; 625 dev_err(kfd_device, "Error initializing iommuv2\n"); 626 goto device_iommu_error; 627 } 628 629 kfd_cwsr_init(kfd); 630 631 svm_migrate_init(kfd->adev); 632 633 if (kgd2kfd_resume_iommu(kfd)) 634 goto device_iommu_error; 635 636 if (kfd_resume(kfd)) 637 goto kfd_resume_error; 638 639 amdgpu_amdkfd_get_local_mem_info(kfd->adev, &kfd->local_mem_info); 640 641 if (kfd_topology_add_device(kfd)) { 642 dev_err(kfd_device, "Error adding device to topology\n"); 643 goto kfd_topology_add_device_error; 644 } 645 646 kfd_smi_init(kfd); 647 648 kfd->init_complete = true; 649 dev_info(kfd_device, "added device %x:%x\n", kfd->pdev->vendor, 650 kfd->pdev->device); 651 652 pr_debug("Starting kfd with the following scheduling policy %d\n", 653 kfd->dqm->sched_policy); 654 655 goto out; 656 657 kfd_topology_add_device_error: 658 kfd_resume_error: 659 device_iommu_error: 660 gws_error: 661 device_queue_manager_uninit(kfd->dqm); 662 device_queue_manager_error: 663 kfd_interrupt_exit(kfd); 664 kfd_interrupt_error: 665 kfd_doorbell_fini(kfd); 666 kfd_doorbell_error: 667 kfd_gtt_sa_fini(kfd); 668 kfd_gtt_sa_init_error: 669 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 670 alloc_gtt_mem_failure: 671 if (kfd->gws) 672 amdgpu_amdkfd_free_gws(kfd->adev, kfd->gws); 673 dev_err(kfd_device, 674 "device %x:%x NOT added due to errors\n", 675 kfd->pdev->vendor, kfd->pdev->device); 676 out: 677 return kfd->init_complete; 678 } 679 680 void kgd2kfd_device_exit(struct kfd_dev *kfd) 681 { 682 if (kfd->init_complete) { 683 device_queue_manager_uninit(kfd->dqm); 684 kfd_interrupt_exit(kfd); 685 kfd_topology_remove_device(kfd); 686 kfd_doorbell_fini(kfd); 687 ida_destroy(&kfd->doorbell_ida); 688 kfd_gtt_sa_fini(kfd); 689 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 690 if (kfd->gws) 691 amdgpu_amdkfd_free_gws(kfd->adev, kfd->gws); 692 } 693 694 kfree(kfd); 695 } 696 697 int kgd2kfd_pre_reset(struct kfd_dev *kfd) 698 { 699 if (!kfd->init_complete) 700 return 0; 701 702 kfd_smi_event_update_gpu_reset(kfd, false); 703 704 kfd->dqm->ops.pre_reset(kfd->dqm); 705 706 kgd2kfd_suspend(kfd, false); 707 708 kfd_signal_reset_event(kfd); 709 return 0; 710 } 711 712 /* 713 * Fix me. KFD won't be able to resume existing process for now. 714 * We will keep all existing process in a evicted state and 715 * wait the process to be terminated. 716 */ 717 718 int kgd2kfd_post_reset(struct kfd_dev *kfd) 719 { 720 int ret; 721 722 if (!kfd->init_complete) 723 return 0; 724 725 ret = kfd_resume(kfd); 726 if (ret) 727 return ret; 728 atomic_dec(&kfd_locked); 729 730 atomic_set(&kfd->sram_ecc_flag, 0); 731 732 kfd_smi_event_update_gpu_reset(kfd, true); 733 734 return 0; 735 } 736 737 bool kfd_is_locked(void) 738 { 739 return (atomic_read(&kfd_locked) > 0); 740 } 741 742 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 743 { 744 if (!kfd->init_complete) 745 return; 746 747 /* for runtime suspend, skip locking kfd */ 748 if (!run_pm) { 749 /* For first KFD device suspend all the KFD processes */ 750 if (atomic_inc_return(&kfd_locked) == 1) 751 kfd_suspend_all_processes(); 752 } 753 754 kfd->dqm->ops.stop(kfd->dqm); 755 kfd_iommu_suspend(kfd); 756 } 757 758 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 759 { 760 int ret, count; 761 762 if (!kfd->init_complete) 763 return 0; 764 765 ret = kfd_resume(kfd); 766 if (ret) 767 return ret; 768 769 /* for runtime resume, skip unlocking kfd */ 770 if (!run_pm) { 771 count = atomic_dec_return(&kfd_locked); 772 WARN_ONCE(count < 0, "KFD suspend / resume ref. error"); 773 if (count == 0) 774 ret = kfd_resume_all_processes(); 775 } 776 777 return ret; 778 } 779 780 int kgd2kfd_resume_iommu(struct kfd_dev *kfd) 781 { 782 int err = 0; 783 784 err = kfd_iommu_resume(kfd); 785 if (err) 786 dev_err(kfd_device, 787 "Failed to resume IOMMU for device %x:%x\n", 788 kfd->pdev->vendor, kfd->pdev->device); 789 return err; 790 } 791 792 static int kfd_resume(struct kfd_dev *kfd) 793 { 794 int err = 0; 795 796 err = kfd->dqm->ops.start(kfd->dqm); 797 if (err) 798 dev_err(kfd_device, 799 "Error starting queue manager for device %x:%x\n", 800 kfd->pdev->vendor, kfd->pdev->device); 801 802 return err; 803 } 804 805 static inline void kfd_queue_work(struct workqueue_struct *wq, 806 struct work_struct *work) 807 { 808 int cpu, new_cpu; 809 810 cpu = new_cpu = smp_processor_id(); 811 do { 812 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids; 813 if (cpu_to_node(new_cpu) == numa_node_id()) 814 break; 815 } while (cpu != new_cpu); 816 817 queue_work_on(new_cpu, wq, work); 818 } 819 820 /* This is called directly from KGD at ISR. */ 821 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 822 { 823 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE]; 824 bool is_patched = false; 825 unsigned long flags; 826 827 if (!kfd->init_complete) 828 return; 829 830 if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) { 831 dev_err_once(kfd_device, "Ring entry too small\n"); 832 return; 833 } 834 835 spin_lock_irqsave(&kfd->interrupt_lock, flags); 836 837 if (kfd->interrupts_active 838 && interrupt_is_wanted(kfd, ih_ring_entry, 839 patched_ihre, &is_patched) 840 && enqueue_ih_ring_entry(kfd, 841 is_patched ? patched_ihre : ih_ring_entry)) 842 kfd_queue_work(kfd->ih_wq, &kfd->interrupt_work); 843 844 spin_unlock_irqrestore(&kfd->interrupt_lock, flags); 845 } 846 847 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger) 848 { 849 struct kfd_process *p; 850 int r; 851 852 /* Because we are called from arbitrary context (workqueue) as opposed 853 * to process context, kfd_process could attempt to exit while we are 854 * running so the lookup function increments the process ref count. 855 */ 856 p = kfd_lookup_process_by_mm(mm); 857 if (!p) 858 return -ESRCH; 859 860 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 861 r = kfd_process_evict_queues(p, trigger); 862 863 kfd_unref_process(p); 864 return r; 865 } 866 867 int kgd2kfd_resume_mm(struct mm_struct *mm) 868 { 869 struct kfd_process *p; 870 int r; 871 872 /* Because we are called from arbitrary context (workqueue) as opposed 873 * to process context, kfd_process could attempt to exit while we are 874 * running so the lookup function increments the process ref count. 875 */ 876 p = kfd_lookup_process_by_mm(mm); 877 if (!p) 878 return -ESRCH; 879 880 r = kfd_process_restore_queues(p); 881 882 kfd_unref_process(p); 883 return r; 884 } 885 886 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 887 * prepare for safe eviction of KFD BOs that belong to the specified 888 * process. 889 * 890 * @mm: mm_struct that identifies the specified KFD process 891 * @fence: eviction fence attached to KFD process BOs 892 * 893 */ 894 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 895 struct dma_fence *fence) 896 { 897 struct kfd_process *p; 898 unsigned long active_time; 899 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 900 901 if (!fence) 902 return -EINVAL; 903 904 if (dma_fence_is_signaled(fence)) 905 return 0; 906 907 p = kfd_lookup_process_by_mm(mm); 908 if (!p) 909 return -ENODEV; 910 911 if (fence->seqno == p->last_eviction_seqno) 912 goto out; 913 914 p->last_eviction_seqno = fence->seqno; 915 916 /* Avoid KFD process starvation. Wait for at least 917 * PROCESS_ACTIVE_TIME_MS before evicting the process again 918 */ 919 active_time = get_jiffies_64() - p->last_restore_timestamp; 920 if (delay_jiffies > active_time) 921 delay_jiffies -= active_time; 922 else 923 delay_jiffies = 0; 924 925 /* During process initialization eviction_work.dwork is initialized 926 * to kfd_evict_bo_worker 927 */ 928 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 929 p->lead_thread->pid, delay_jiffies); 930 schedule_delayed_work(&p->eviction_work, delay_jiffies); 931 out: 932 kfd_unref_process(p); 933 return 0; 934 } 935 936 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 937 unsigned int chunk_size) 938 { 939 if (WARN_ON(buf_size < chunk_size)) 940 return -EINVAL; 941 if (WARN_ON(buf_size == 0)) 942 return -EINVAL; 943 if (WARN_ON(chunk_size == 0)) 944 return -EINVAL; 945 946 kfd->gtt_sa_chunk_size = chunk_size; 947 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 948 949 kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks, 950 GFP_KERNEL); 951 if (!kfd->gtt_sa_bitmap) 952 return -ENOMEM; 953 954 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 955 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 956 957 mutex_init(&kfd->gtt_sa_lock); 958 959 return 0; 960 } 961 962 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 963 { 964 mutex_destroy(&kfd->gtt_sa_lock); 965 bitmap_free(kfd->gtt_sa_bitmap); 966 } 967 968 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 969 unsigned int bit_num, 970 unsigned int chunk_size) 971 { 972 return start_addr + bit_num * chunk_size; 973 } 974 975 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 976 unsigned int bit_num, 977 unsigned int chunk_size) 978 { 979 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 980 } 981 982 int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size, 983 struct kfd_mem_obj **mem_obj) 984 { 985 unsigned int found, start_search, cur_size; 986 987 if (size == 0) 988 return -EINVAL; 989 990 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 991 return -ENOMEM; 992 993 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 994 if (!(*mem_obj)) 995 return -ENOMEM; 996 997 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 998 999 start_search = 0; 1000 1001 mutex_lock(&kfd->gtt_sa_lock); 1002 1003 kfd_gtt_restart_search: 1004 /* Find the first chunk that is free */ 1005 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1006 kfd->gtt_sa_num_of_chunks, 1007 start_search); 1008 1009 pr_debug("Found = %d\n", found); 1010 1011 /* If there wasn't any free chunk, bail out */ 1012 if (found == kfd->gtt_sa_num_of_chunks) 1013 goto kfd_gtt_no_free_chunk; 1014 1015 /* Update fields of mem_obj */ 1016 (*mem_obj)->range_start = found; 1017 (*mem_obj)->range_end = found; 1018 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1019 kfd->gtt_start_gpu_addr, 1020 found, 1021 kfd->gtt_sa_chunk_size); 1022 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1023 kfd->gtt_start_cpu_ptr, 1024 found, 1025 kfd->gtt_sa_chunk_size); 1026 1027 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1028 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1029 1030 /* If we need only one chunk, mark it as allocated and get out */ 1031 if (size <= kfd->gtt_sa_chunk_size) { 1032 pr_debug("Single bit\n"); 1033 __set_bit(found, kfd->gtt_sa_bitmap); 1034 goto kfd_gtt_out; 1035 } 1036 1037 /* Otherwise, try to see if we have enough contiguous chunks */ 1038 cur_size = size - kfd->gtt_sa_chunk_size; 1039 do { 1040 (*mem_obj)->range_end = 1041 find_next_zero_bit(kfd->gtt_sa_bitmap, 1042 kfd->gtt_sa_num_of_chunks, ++found); 1043 /* 1044 * If next free chunk is not contiguous than we need to 1045 * restart our search from the last free chunk we found (which 1046 * wasn't contiguous to the previous ones 1047 */ 1048 if ((*mem_obj)->range_end != found) { 1049 start_search = found; 1050 goto kfd_gtt_restart_search; 1051 } 1052 1053 /* 1054 * If we reached end of buffer, bail out with error 1055 */ 1056 if (found == kfd->gtt_sa_num_of_chunks) 1057 goto kfd_gtt_no_free_chunk; 1058 1059 /* Check if we don't need another chunk */ 1060 if (cur_size <= kfd->gtt_sa_chunk_size) 1061 cur_size = 0; 1062 else 1063 cur_size -= kfd->gtt_sa_chunk_size; 1064 1065 } while (cur_size > 0); 1066 1067 pr_debug("range_start = %d, range_end = %d\n", 1068 (*mem_obj)->range_start, (*mem_obj)->range_end); 1069 1070 /* Mark the chunks as allocated */ 1071 bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start, 1072 (*mem_obj)->range_end - (*mem_obj)->range_start + 1); 1073 1074 kfd_gtt_out: 1075 mutex_unlock(&kfd->gtt_sa_lock); 1076 return 0; 1077 1078 kfd_gtt_no_free_chunk: 1079 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1080 mutex_unlock(&kfd->gtt_sa_lock); 1081 kfree(*mem_obj); 1082 return -ENOMEM; 1083 } 1084 1085 int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj) 1086 { 1087 /* Act like kfree when trying to free a NULL object */ 1088 if (!mem_obj) 1089 return 0; 1090 1091 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1092 mem_obj, mem_obj->range_start, mem_obj->range_end); 1093 1094 mutex_lock(&kfd->gtt_sa_lock); 1095 1096 /* Mark the chunks as free */ 1097 bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start, 1098 mem_obj->range_end - mem_obj->range_start + 1); 1099 1100 mutex_unlock(&kfd->gtt_sa_lock); 1101 1102 kfree(mem_obj); 1103 return 0; 1104 } 1105 1106 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1107 { 1108 if (kfd) 1109 atomic_inc(&kfd->sram_ecc_flag); 1110 } 1111 1112 void kfd_inc_compute_active(struct kfd_dev *kfd) 1113 { 1114 if (atomic_inc_return(&kfd->compute_profile) == 1) 1115 amdgpu_amdkfd_set_compute_idle(kfd->adev, false); 1116 } 1117 1118 void kfd_dec_compute_active(struct kfd_dev *kfd) 1119 { 1120 int count = atomic_dec_return(&kfd->compute_profile); 1121 1122 if (count == 0) 1123 amdgpu_amdkfd_set_compute_idle(kfd->adev, true); 1124 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1125 } 1126 1127 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 1128 { 1129 if (kfd && kfd->init_complete) 1130 kfd_smi_event_update_thermal_throttling(kfd, throttle_bitmask); 1131 } 1132 1133 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and 1134 * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA. 1135 * When the device has more than two engines, we reserve two for PCIe to enable 1136 * full-duplex and the rest are used as XGMI. 1137 */ 1138 unsigned int kfd_get_num_sdma_engines(struct kfd_dev *kdev) 1139 { 1140 /* If XGMI is not supported, all SDMA engines are PCIe */ 1141 if (!kdev->adev->gmc.xgmi.supported) 1142 return kdev->adev->sdma.num_instances; 1143 1144 return min(kdev->adev->sdma.num_instances, 2); 1145 } 1146 1147 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_dev *kdev) 1148 { 1149 /* After reserved for PCIe, the rest of engines are XGMI */ 1150 return kdev->adev->sdma.num_instances - kfd_get_num_sdma_engines(kdev); 1151 } 1152 1153 #if defined(CONFIG_DEBUG_FS) 1154 1155 /* This function will send a package to HIQ to hang the HWS 1156 * which will trigger a GPU reset and bring the HWS back to normal state 1157 */ 1158 int kfd_debugfs_hang_hws(struct kfd_dev *dev) 1159 { 1160 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1161 pr_err("HWS is not enabled"); 1162 return -EINVAL; 1163 } 1164 1165 return dqm_debugfs_hang_hws(dev->dqm); 1166 } 1167 1168 #endif 1169