1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/bsearch.h> 25 #include <linux/pci.h> 26 #include <linux/slab.h> 27 #include "kfd_priv.h" 28 #include "kfd_device_queue_manager.h" 29 #include "kfd_pm4_headers_vi.h" 30 #include "kfd_pm4_headers_aldebaran.h" 31 #include "cwsr_trap_handler.h" 32 #include "kfd_iommu.h" 33 #include "amdgpu_amdkfd.h" 34 #include "kfd_smi_events.h" 35 #include "kfd_migrate.h" 36 #include "amdgpu.h" 37 38 #define MQD_SIZE_ALIGNED 768 39 40 /* 41 * kfd_locked is used to lock the kfd driver during suspend or reset 42 * once locked, kfd driver will stop any further GPU execution. 43 * create process (open) will return -EAGAIN. 44 */ 45 static atomic_t kfd_locked = ATOMIC_INIT(0); 46 47 #ifdef CONFIG_DRM_AMDGPU_CIK 48 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 49 #endif 50 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 51 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 52 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 53 extern const struct kfd2kgd_calls aldebaran_kfd2kgd; 54 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 55 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 56 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd; 57 58 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 59 unsigned int chunk_size); 60 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 61 62 static int kfd_resume_iommu(struct kfd_dev *kfd); 63 static int kfd_resume(struct kfd_dev *kfd); 64 65 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) 66 { 67 uint32_t sdma_version = kfd->adev->ip_versions[SDMA0_HWIP][0]; 68 69 switch (sdma_version) { 70 case IP_VERSION(4, 0, 0):/* VEGA10 */ 71 case IP_VERSION(4, 0, 1):/* VEGA12 */ 72 case IP_VERSION(4, 1, 0):/* RAVEN */ 73 case IP_VERSION(4, 1, 1):/* RAVEN */ 74 case IP_VERSION(4, 1, 2):/* RENOIR */ 75 case IP_VERSION(5, 2, 1):/* VANGOGH */ 76 case IP_VERSION(5, 2, 3):/* YELLOW_CARP */ 77 case IP_VERSION(5, 2, 6):/* GC 10.3.6 */ 78 case IP_VERSION(5, 2, 7):/* GC 10.3.7 */ 79 kfd->device_info.num_sdma_queues_per_engine = 2; 80 break; 81 case IP_VERSION(4, 2, 0):/* VEGA20 */ 82 case IP_VERSION(4, 2, 2):/* ARCTURUS */ 83 case IP_VERSION(4, 4, 0):/* ALDEBARAN */ 84 case IP_VERSION(5, 0, 0):/* NAVI10 */ 85 case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */ 86 case IP_VERSION(5, 0, 2):/* NAVI14 */ 87 case IP_VERSION(5, 0, 5):/* NAVI12 */ 88 case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */ 89 case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */ 90 case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */ 91 case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */ 92 case IP_VERSION(6, 0, 0): 93 case IP_VERSION(6, 0, 1): 94 case IP_VERSION(6, 0, 2): 95 case IP_VERSION(6, 0, 3): 96 kfd->device_info.num_sdma_queues_per_engine = 8; 97 break; 98 default: 99 dev_warn(kfd_device, 100 "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n", 101 sdma_version); 102 kfd->device_info.num_sdma_queues_per_engine = 8; 103 } 104 105 switch (sdma_version) { 106 case IP_VERSION(6, 0, 0): 107 case IP_VERSION(6, 0, 2): 108 case IP_VERSION(6, 0, 3): 109 /* Reserve 1 for paging and 1 for gfx */ 110 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 111 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */ 112 kfd->device_info.reserved_sdma_queues_bitmap = 0xFULL; 113 break; 114 case IP_VERSION(6, 0, 1): 115 /* Reserve 1 for paging and 1 for gfx */ 116 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 117 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-0 queue-1; ... */ 118 kfd->device_info.reserved_sdma_queues_bitmap = 0x3ULL; 119 break; 120 default: 121 break; 122 } 123 } 124 125 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) 126 { 127 uint32_t gc_version = KFD_GC_VERSION(kfd); 128 129 switch (gc_version) { 130 case IP_VERSION(9, 0, 1): /* VEGA10 */ 131 case IP_VERSION(9, 1, 0): /* RAVEN */ 132 case IP_VERSION(9, 2, 1): /* VEGA12 */ 133 case IP_VERSION(9, 2, 2): /* RAVEN */ 134 case IP_VERSION(9, 3, 0): /* RENOIR */ 135 case IP_VERSION(9, 4, 0): /* VEGA20 */ 136 case IP_VERSION(9, 4, 1): /* ARCTURUS */ 137 case IP_VERSION(9, 4, 2): /* ALDEBARAN */ 138 case IP_VERSION(10, 3, 1): /* VANGOGH */ 139 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */ 140 case IP_VERSION(10, 3, 6): /* GC 10.3.6 */ 141 case IP_VERSION(10, 3, 7): /* GC 10.3.7 */ 142 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */ 143 case IP_VERSION(10, 1, 4): 144 case IP_VERSION(10, 1, 10): /* NAVI10 */ 145 case IP_VERSION(10, 1, 2): /* NAVI12 */ 146 case IP_VERSION(10, 1, 1): /* NAVI14 */ 147 case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */ 148 case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */ 149 case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */ 150 case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */ 151 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 152 break; 153 case IP_VERSION(11, 0, 0): 154 case IP_VERSION(11, 0, 1): 155 case IP_VERSION(11, 0, 2): 156 case IP_VERSION(11, 0, 3): 157 case IP_VERSION(11, 0, 4): 158 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 159 break; 160 default: 161 dev_warn(kfd_device, "v9 event interrupt handler is set due to " 162 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version); 163 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 164 } 165 } 166 167 static void kfd_device_info_init(struct kfd_dev *kfd, 168 bool vf, uint32_t gfx_target_version) 169 { 170 uint32_t gc_version = KFD_GC_VERSION(kfd); 171 uint32_t asic_type = kfd->adev->asic_type; 172 173 kfd->device_info.max_pasid_bits = 16; 174 kfd->device_info.max_no_of_hqd = 24; 175 kfd->device_info.num_of_watch_points = 4; 176 kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED; 177 kfd->device_info.gfx_target_version = gfx_target_version; 178 179 if (KFD_IS_SOC15(kfd)) { 180 kfd->device_info.doorbell_size = 8; 181 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t); 182 kfd->device_info.supports_cwsr = true; 183 184 kfd_device_info_set_sdma_info(kfd); 185 186 kfd_device_info_set_event_interrupt_class(kfd); 187 188 /* Raven */ 189 if (gc_version == IP_VERSION(9, 1, 0) || 190 gc_version == IP_VERSION(9, 2, 2)) 191 kfd->device_info.needs_iommu_device = true; 192 193 if (gc_version < IP_VERSION(11, 0, 0)) { 194 /* Navi2x+, Navi1x+ */ 195 if (gc_version == IP_VERSION(10, 3, 6)) 196 kfd->device_info.no_atomic_fw_version = 14; 197 else if (gc_version == IP_VERSION(10, 3, 7)) 198 kfd->device_info.no_atomic_fw_version = 3; 199 else if (gc_version >= IP_VERSION(10, 3, 0)) 200 kfd->device_info.no_atomic_fw_version = 92; 201 else if (gc_version >= IP_VERSION(10, 1, 1)) 202 kfd->device_info.no_atomic_fw_version = 145; 203 204 /* Navi1x+ */ 205 if (gc_version >= IP_VERSION(10, 1, 1)) 206 kfd->device_info.needs_pci_atomics = true; 207 } 208 } else { 209 kfd->device_info.doorbell_size = 4; 210 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t); 211 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik; 212 kfd->device_info.num_sdma_queues_per_engine = 2; 213 214 if (asic_type != CHIP_KAVERI && 215 asic_type != CHIP_HAWAII && 216 asic_type != CHIP_TONGA) 217 kfd->device_info.supports_cwsr = true; 218 219 if (asic_type == CHIP_KAVERI || 220 asic_type == CHIP_CARRIZO) 221 kfd->device_info.needs_iommu_device = true; 222 223 if (asic_type != CHIP_HAWAII && !vf) 224 kfd->device_info.needs_pci_atomics = true; 225 } 226 } 227 228 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 229 { 230 struct kfd_dev *kfd = NULL; 231 const struct kfd2kgd_calls *f2g = NULL; 232 uint32_t gfx_target_version = 0; 233 234 switch (adev->asic_type) { 235 #ifdef KFD_SUPPORT_IOMMU_V2 236 #ifdef CONFIG_DRM_AMDGPU_CIK 237 case CHIP_KAVERI: 238 gfx_target_version = 70000; 239 if (!vf) 240 f2g = &gfx_v7_kfd2kgd; 241 break; 242 #endif 243 case CHIP_CARRIZO: 244 gfx_target_version = 80001; 245 if (!vf) 246 f2g = &gfx_v8_kfd2kgd; 247 break; 248 #endif 249 #ifdef CONFIG_DRM_AMDGPU_CIK 250 case CHIP_HAWAII: 251 gfx_target_version = 70001; 252 if (!amdgpu_exp_hw_support) 253 pr_info( 254 "KFD support on Hawaii is experimental. See modparam exp_hw_support\n" 255 ); 256 else if (!vf) 257 f2g = &gfx_v7_kfd2kgd; 258 break; 259 #endif 260 case CHIP_TONGA: 261 gfx_target_version = 80002; 262 if (!vf) 263 f2g = &gfx_v8_kfd2kgd; 264 break; 265 case CHIP_FIJI: 266 case CHIP_POLARIS10: 267 gfx_target_version = 80003; 268 f2g = &gfx_v8_kfd2kgd; 269 break; 270 case CHIP_POLARIS11: 271 case CHIP_POLARIS12: 272 case CHIP_VEGAM: 273 gfx_target_version = 80003; 274 if (!vf) 275 f2g = &gfx_v8_kfd2kgd; 276 break; 277 default: 278 switch (adev->ip_versions[GC_HWIP][0]) { 279 /* Vega 10 */ 280 case IP_VERSION(9, 0, 1): 281 gfx_target_version = 90000; 282 f2g = &gfx_v9_kfd2kgd; 283 break; 284 #ifdef KFD_SUPPORT_IOMMU_V2 285 /* Raven */ 286 case IP_VERSION(9, 1, 0): 287 case IP_VERSION(9, 2, 2): 288 gfx_target_version = 90002; 289 if (!vf) 290 f2g = &gfx_v9_kfd2kgd; 291 break; 292 #endif 293 /* Vega12 */ 294 case IP_VERSION(9, 2, 1): 295 gfx_target_version = 90004; 296 if (!vf) 297 f2g = &gfx_v9_kfd2kgd; 298 break; 299 /* Renoir */ 300 case IP_VERSION(9, 3, 0): 301 gfx_target_version = 90012; 302 if (!vf) 303 f2g = &gfx_v9_kfd2kgd; 304 break; 305 /* Vega20 */ 306 case IP_VERSION(9, 4, 0): 307 gfx_target_version = 90006; 308 if (!vf) 309 f2g = &gfx_v9_kfd2kgd; 310 break; 311 /* Arcturus */ 312 case IP_VERSION(9, 4, 1): 313 gfx_target_version = 90008; 314 f2g = &arcturus_kfd2kgd; 315 break; 316 /* Aldebaran */ 317 case IP_VERSION(9, 4, 2): 318 gfx_target_version = 90010; 319 f2g = &aldebaran_kfd2kgd; 320 break; 321 /* Navi10 */ 322 case IP_VERSION(10, 1, 10): 323 gfx_target_version = 100100; 324 if (!vf) 325 f2g = &gfx_v10_kfd2kgd; 326 break; 327 /* Navi12 */ 328 case IP_VERSION(10, 1, 2): 329 gfx_target_version = 100101; 330 f2g = &gfx_v10_kfd2kgd; 331 break; 332 /* Navi14 */ 333 case IP_VERSION(10, 1, 1): 334 gfx_target_version = 100102; 335 if (!vf) 336 f2g = &gfx_v10_kfd2kgd; 337 break; 338 /* Cyan Skillfish */ 339 case IP_VERSION(10, 1, 3): 340 case IP_VERSION(10, 1, 4): 341 gfx_target_version = 100103; 342 if (!vf) 343 f2g = &gfx_v10_kfd2kgd; 344 break; 345 /* Sienna Cichlid */ 346 case IP_VERSION(10, 3, 0): 347 gfx_target_version = 100300; 348 f2g = &gfx_v10_3_kfd2kgd; 349 break; 350 /* Navy Flounder */ 351 case IP_VERSION(10, 3, 2): 352 gfx_target_version = 100301; 353 f2g = &gfx_v10_3_kfd2kgd; 354 break; 355 /* Van Gogh */ 356 case IP_VERSION(10, 3, 1): 357 gfx_target_version = 100303; 358 if (!vf) 359 f2g = &gfx_v10_3_kfd2kgd; 360 break; 361 /* Dimgrey Cavefish */ 362 case IP_VERSION(10, 3, 4): 363 gfx_target_version = 100302; 364 f2g = &gfx_v10_3_kfd2kgd; 365 break; 366 /* Beige Goby */ 367 case IP_VERSION(10, 3, 5): 368 gfx_target_version = 100304; 369 f2g = &gfx_v10_3_kfd2kgd; 370 break; 371 /* Yellow Carp */ 372 case IP_VERSION(10, 3, 3): 373 gfx_target_version = 100305; 374 if (!vf) 375 f2g = &gfx_v10_3_kfd2kgd; 376 break; 377 case IP_VERSION(10, 3, 6): 378 case IP_VERSION(10, 3, 7): 379 gfx_target_version = 100306; 380 if (!vf) 381 f2g = &gfx_v10_3_kfd2kgd; 382 break; 383 case IP_VERSION(11, 0, 0): 384 gfx_target_version = 110000; 385 f2g = &gfx_v11_kfd2kgd; 386 break; 387 case IP_VERSION(11, 0, 1): 388 case IP_VERSION(11, 0, 4): 389 gfx_target_version = 110003; 390 f2g = &gfx_v11_kfd2kgd; 391 break; 392 case IP_VERSION(11, 0, 2): 393 gfx_target_version = 110002; 394 f2g = &gfx_v11_kfd2kgd; 395 break; 396 case IP_VERSION(11, 0, 3): 397 /* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */ 398 gfx_target_version = 110001; 399 f2g = &gfx_v11_kfd2kgd; 400 break; 401 default: 402 break; 403 } 404 break; 405 } 406 407 if (!f2g) { 408 if (adev->ip_versions[GC_HWIP][0]) 409 dev_err(kfd_device, "GC IP %06x %s not supported in kfd\n", 410 adev->ip_versions[GC_HWIP][0], vf ? "VF" : ""); 411 else 412 dev_err(kfd_device, "%s %s not supported in kfd\n", 413 amdgpu_asic_name[adev->asic_type], vf ? "VF" : ""); 414 return NULL; 415 } 416 417 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 418 if (!kfd) 419 return NULL; 420 421 kfd->adev = adev; 422 kfd_device_info_init(kfd, vf, gfx_target_version); 423 kfd->init_complete = false; 424 kfd->kfd2kgd = f2g; 425 atomic_set(&kfd->compute_profile, 0); 426 427 mutex_init(&kfd->doorbell_mutex); 428 memset(&kfd->doorbell_available_index, 0, 429 sizeof(kfd->doorbell_available_index)); 430 431 atomic_set(&kfd->sram_ecc_flag, 0); 432 433 ida_init(&kfd->doorbell_ida); 434 435 return kfd; 436 } 437 438 static void kfd_cwsr_init(struct kfd_dev *kfd) 439 { 440 if (cwsr_enable && kfd->device_info.supports_cwsr) { 441 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) { 442 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE); 443 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 444 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 445 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) { 446 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE); 447 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 448 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 449 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) { 450 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) > PAGE_SIZE); 451 kfd->cwsr_isa = cwsr_trap_aldebaran_hex; 452 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); 453 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) { 454 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE); 455 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 456 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 457 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) { 458 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE); 459 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 460 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 461 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) { 462 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE); 463 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 464 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 465 } else { 466 BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE); 467 kfd->cwsr_isa = cwsr_trap_gfx11_hex; 468 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex); 469 } 470 471 kfd->cwsr_enabled = true; 472 } 473 } 474 475 static int kfd_gws_init(struct kfd_dev *kfd) 476 { 477 int ret = 0; 478 479 if (kfd->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 480 return 0; 481 482 if (hws_gws_support || (KFD_IS_SOC15(kfd) && 483 ((KFD_GC_VERSION(kfd) == IP_VERSION(9, 0, 1) 484 && kfd->mec2_fw_version >= 0x81b3) || 485 (KFD_GC_VERSION(kfd) <= IP_VERSION(9, 4, 0) 486 && kfd->mec2_fw_version >= 0x1b3) || 487 (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1) 488 && kfd->mec2_fw_version >= 0x30) || 489 (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) 490 && kfd->mec2_fw_version >= 0x28) || 491 (KFD_GC_VERSION(kfd) >= IP_VERSION(10, 3, 0) 492 && KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0) 493 && kfd->mec2_fw_version >= 0x6b)))) 494 ret = amdgpu_amdkfd_alloc_gws(kfd->adev, 495 kfd->adev->gds.gws_size, &kfd->gws); 496 497 return ret; 498 } 499 500 static void kfd_smi_init(struct kfd_dev *dev) 501 { 502 INIT_LIST_HEAD(&dev->smi_clients); 503 spin_lock_init(&dev->smi_lock); 504 } 505 506 bool kgd2kfd_device_init(struct kfd_dev *kfd, 507 const struct kgd2kfd_shared_resources *gpu_resources) 508 { 509 unsigned int size, map_process_packet_size; 510 511 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 512 KGD_ENGINE_MEC1); 513 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 514 KGD_ENGINE_MEC2); 515 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 516 KGD_ENGINE_SDMA1); 517 kfd->shared_resources = *gpu_resources; 518 519 kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 520 kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 521 kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd 522 - kfd->vm_info.first_vmid_kfd + 1; 523 524 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 525 * 32 and 64-bit requests are possible and must be 526 * supported. 527 */ 528 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev); 529 if (!kfd->pci_atomic_requested && 530 kfd->device_info.needs_pci_atomics && 531 (!kfd->device_info.no_atomic_fw_version || 532 kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) { 533 dev_info(kfd_device, 534 "skipped device %x:%x, PCI rejects atomics %d<%d\n", 535 kfd->adev->pdev->vendor, kfd->adev->pdev->device, 536 kfd->mec_fw_version, 537 kfd->device_info.no_atomic_fw_version); 538 return false; 539 } 540 541 /* Verify module parameters regarding mapped process number*/ 542 if (hws_max_conc_proc >= 0) 543 kfd->max_proc_per_quantum = min((u32)hws_max_conc_proc, kfd->vm_info.vmid_num_kfd); 544 else 545 kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd; 546 547 /* calculate max size of mqds needed for queues */ 548 size = max_num_of_queues_per_device * 549 kfd->device_info.mqd_size_aligned; 550 551 /* 552 * calculate max size of runlist packet. 553 * There can be only 2 packets at once 554 */ 555 map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ? 556 sizeof(struct pm4_mes_map_process_aldebaran) : 557 sizeof(struct pm4_mes_map_process); 558 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + 559 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 560 + sizeof(struct pm4_mes_runlist)) * 2; 561 562 /* Add size of HIQ & DIQ */ 563 size += KFD_KERNEL_QUEUE_SIZE * 2; 564 565 /* add another 512KB for all other allocations on gart (HPD, fences) */ 566 size += 512 * 1024; 567 568 if (amdgpu_amdkfd_alloc_gtt_mem( 569 kfd->adev, size, &kfd->gtt_mem, 570 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 571 false)) { 572 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 573 goto alloc_gtt_mem_failure; 574 } 575 576 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 577 578 /* Initialize GTT sa with 512 byte chunk size */ 579 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 580 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 581 goto kfd_gtt_sa_init_error; 582 } 583 584 if (kfd_doorbell_init(kfd)) { 585 dev_err(kfd_device, 586 "Error initializing doorbell aperture\n"); 587 goto kfd_doorbell_error; 588 } 589 590 if (amdgpu_use_xgmi_p2p) 591 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id; 592 593 kfd->noretry = kfd->adev->gmc.noretry; 594 595 if (kfd_interrupt_init(kfd)) { 596 dev_err(kfd_device, "Error initializing interrupts\n"); 597 goto kfd_interrupt_error; 598 } 599 600 kfd->dqm = device_queue_manager_init(kfd); 601 if (!kfd->dqm) { 602 dev_err(kfd_device, "Error initializing queue manager\n"); 603 goto device_queue_manager_error; 604 } 605 606 /* If supported on this device, allocate global GWS that is shared 607 * by all KFD processes 608 */ 609 if (kfd_gws_init(kfd)) { 610 dev_err(kfd_device, "Could not allocate %d gws\n", 611 kfd->adev->gds.gws_size); 612 goto gws_error; 613 } 614 615 /* If CRAT is broken, won't set iommu enabled */ 616 kfd_double_confirm_iommu_support(kfd); 617 618 if (kfd_iommu_device_init(kfd)) { 619 kfd->use_iommu_v2 = false; 620 dev_err(kfd_device, "Error initializing iommuv2\n"); 621 goto device_iommu_error; 622 } 623 624 kfd_cwsr_init(kfd); 625 626 svm_migrate_init(kfd->adev); 627 628 if (kfd_resume_iommu(kfd)) 629 goto device_iommu_error; 630 631 if (kfd_resume(kfd)) 632 goto kfd_resume_error; 633 634 amdgpu_amdkfd_get_local_mem_info(kfd->adev, &kfd->local_mem_info); 635 636 if (kfd_topology_add_device(kfd)) { 637 dev_err(kfd_device, "Error adding device to topology\n"); 638 goto kfd_topology_add_device_error; 639 } 640 641 kfd_smi_init(kfd); 642 643 kfd->init_complete = true; 644 dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, 645 kfd->adev->pdev->device); 646 647 pr_debug("Starting kfd with the following scheduling policy %d\n", 648 kfd->dqm->sched_policy); 649 650 goto out; 651 652 kfd_topology_add_device_error: 653 kfd_resume_error: 654 device_iommu_error: 655 gws_error: 656 device_queue_manager_uninit(kfd->dqm); 657 device_queue_manager_error: 658 kfd_interrupt_exit(kfd); 659 kfd_interrupt_error: 660 kfd_doorbell_fini(kfd); 661 kfd_doorbell_error: 662 kfd_gtt_sa_fini(kfd); 663 kfd_gtt_sa_init_error: 664 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 665 alloc_gtt_mem_failure: 666 if (kfd->gws) 667 amdgpu_amdkfd_free_gws(kfd->adev, kfd->gws); 668 dev_err(kfd_device, 669 "device %x:%x NOT added due to errors\n", 670 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 671 out: 672 return kfd->init_complete; 673 } 674 675 void kgd2kfd_device_exit(struct kfd_dev *kfd) 676 { 677 if (kfd->init_complete) { 678 device_queue_manager_uninit(kfd->dqm); 679 kfd_interrupt_exit(kfd); 680 kfd_topology_remove_device(kfd); 681 kfd_doorbell_fini(kfd); 682 ida_destroy(&kfd->doorbell_ida); 683 kfd_gtt_sa_fini(kfd); 684 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 685 if (kfd->gws) 686 amdgpu_amdkfd_free_gws(kfd->adev, kfd->gws); 687 } 688 689 kfree(kfd); 690 } 691 692 int kgd2kfd_pre_reset(struct kfd_dev *kfd) 693 { 694 if (!kfd->init_complete) 695 return 0; 696 697 kfd_smi_event_update_gpu_reset(kfd, false); 698 699 kfd->dqm->ops.pre_reset(kfd->dqm); 700 701 kgd2kfd_suspend(kfd, false); 702 703 kfd_signal_reset_event(kfd); 704 return 0; 705 } 706 707 /* 708 * Fix me. KFD won't be able to resume existing process for now. 709 * We will keep all existing process in a evicted state and 710 * wait the process to be terminated. 711 */ 712 713 int kgd2kfd_post_reset(struct kfd_dev *kfd) 714 { 715 int ret; 716 717 if (!kfd->init_complete) 718 return 0; 719 720 ret = kfd_resume(kfd); 721 if (ret) 722 return ret; 723 atomic_dec(&kfd_locked); 724 725 atomic_set(&kfd->sram_ecc_flag, 0); 726 727 kfd_smi_event_update_gpu_reset(kfd, true); 728 729 return 0; 730 } 731 732 bool kfd_is_locked(void) 733 { 734 return (atomic_read(&kfd_locked) > 0); 735 } 736 737 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 738 { 739 if (!kfd->init_complete) 740 return; 741 742 /* for runtime suspend, skip locking kfd */ 743 if (!run_pm) { 744 /* For first KFD device suspend all the KFD processes */ 745 if (atomic_inc_return(&kfd_locked) == 1) 746 kfd_suspend_all_processes(); 747 } 748 749 kfd->dqm->ops.stop(kfd->dqm); 750 kfd_iommu_suspend(kfd); 751 } 752 753 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 754 { 755 int ret, count; 756 757 if (!kfd->init_complete) 758 return 0; 759 760 ret = kfd_resume(kfd); 761 if (ret) 762 return ret; 763 764 /* for runtime resume, skip unlocking kfd */ 765 if (!run_pm) { 766 count = atomic_dec_return(&kfd_locked); 767 WARN_ONCE(count < 0, "KFD suspend / resume ref. error"); 768 if (count == 0) 769 ret = kfd_resume_all_processes(); 770 } 771 772 return ret; 773 } 774 775 int kgd2kfd_resume_iommu(struct kfd_dev *kfd) 776 { 777 if (!kfd->init_complete) 778 return 0; 779 780 return kfd_resume_iommu(kfd); 781 } 782 783 static int kfd_resume_iommu(struct kfd_dev *kfd) 784 { 785 int err = 0; 786 787 err = kfd_iommu_resume(kfd); 788 if (err) 789 dev_err(kfd_device, 790 "Failed to resume IOMMU for device %x:%x\n", 791 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 792 return err; 793 } 794 795 static int kfd_resume(struct kfd_dev *kfd) 796 { 797 int err = 0; 798 799 err = kfd->dqm->ops.start(kfd->dqm); 800 if (err) 801 dev_err(kfd_device, 802 "Error starting queue manager for device %x:%x\n", 803 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 804 805 return err; 806 } 807 808 static inline void kfd_queue_work(struct workqueue_struct *wq, 809 struct work_struct *work) 810 { 811 int cpu, new_cpu; 812 813 cpu = new_cpu = smp_processor_id(); 814 do { 815 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids; 816 if (cpu_to_node(new_cpu) == numa_node_id()) 817 break; 818 } while (cpu != new_cpu); 819 820 queue_work_on(new_cpu, wq, work); 821 } 822 823 /* This is called directly from KGD at ISR. */ 824 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 825 { 826 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE]; 827 bool is_patched = false; 828 unsigned long flags; 829 830 if (!kfd->init_complete) 831 return; 832 833 if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) { 834 dev_err_once(kfd_device, "Ring entry too small\n"); 835 return; 836 } 837 838 spin_lock_irqsave(&kfd->interrupt_lock, flags); 839 840 if (kfd->interrupts_active 841 && interrupt_is_wanted(kfd, ih_ring_entry, 842 patched_ihre, &is_patched) 843 && enqueue_ih_ring_entry(kfd, 844 is_patched ? patched_ihre : ih_ring_entry)) 845 kfd_queue_work(kfd->ih_wq, &kfd->interrupt_work); 846 847 spin_unlock_irqrestore(&kfd->interrupt_lock, flags); 848 } 849 850 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger) 851 { 852 struct kfd_process *p; 853 int r; 854 855 /* Because we are called from arbitrary context (workqueue) as opposed 856 * to process context, kfd_process could attempt to exit while we are 857 * running so the lookup function increments the process ref count. 858 */ 859 p = kfd_lookup_process_by_mm(mm); 860 if (!p) 861 return -ESRCH; 862 863 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 864 r = kfd_process_evict_queues(p, trigger); 865 866 kfd_unref_process(p); 867 return r; 868 } 869 870 int kgd2kfd_resume_mm(struct mm_struct *mm) 871 { 872 struct kfd_process *p; 873 int r; 874 875 /* Because we are called from arbitrary context (workqueue) as opposed 876 * to process context, kfd_process could attempt to exit while we are 877 * running so the lookup function increments the process ref count. 878 */ 879 p = kfd_lookup_process_by_mm(mm); 880 if (!p) 881 return -ESRCH; 882 883 r = kfd_process_restore_queues(p); 884 885 kfd_unref_process(p); 886 return r; 887 } 888 889 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 890 * prepare for safe eviction of KFD BOs that belong to the specified 891 * process. 892 * 893 * @mm: mm_struct that identifies the specified KFD process 894 * @fence: eviction fence attached to KFD process BOs 895 * 896 */ 897 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 898 struct dma_fence *fence) 899 { 900 struct kfd_process *p; 901 unsigned long active_time; 902 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 903 904 if (!fence) 905 return -EINVAL; 906 907 if (dma_fence_is_signaled(fence)) 908 return 0; 909 910 p = kfd_lookup_process_by_mm(mm); 911 if (!p) 912 return -ENODEV; 913 914 if (fence->seqno == p->last_eviction_seqno) 915 goto out; 916 917 p->last_eviction_seqno = fence->seqno; 918 919 /* Avoid KFD process starvation. Wait for at least 920 * PROCESS_ACTIVE_TIME_MS before evicting the process again 921 */ 922 active_time = get_jiffies_64() - p->last_restore_timestamp; 923 if (delay_jiffies > active_time) 924 delay_jiffies -= active_time; 925 else 926 delay_jiffies = 0; 927 928 /* During process initialization eviction_work.dwork is initialized 929 * to kfd_evict_bo_worker 930 */ 931 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 932 p->lead_thread->pid, delay_jiffies); 933 schedule_delayed_work(&p->eviction_work, delay_jiffies); 934 out: 935 kfd_unref_process(p); 936 return 0; 937 } 938 939 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 940 unsigned int chunk_size) 941 { 942 if (WARN_ON(buf_size < chunk_size)) 943 return -EINVAL; 944 if (WARN_ON(buf_size == 0)) 945 return -EINVAL; 946 if (WARN_ON(chunk_size == 0)) 947 return -EINVAL; 948 949 kfd->gtt_sa_chunk_size = chunk_size; 950 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 951 952 kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks, 953 GFP_KERNEL); 954 if (!kfd->gtt_sa_bitmap) 955 return -ENOMEM; 956 957 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 958 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 959 960 mutex_init(&kfd->gtt_sa_lock); 961 962 return 0; 963 } 964 965 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 966 { 967 mutex_destroy(&kfd->gtt_sa_lock); 968 bitmap_free(kfd->gtt_sa_bitmap); 969 } 970 971 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 972 unsigned int bit_num, 973 unsigned int chunk_size) 974 { 975 return start_addr + bit_num * chunk_size; 976 } 977 978 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 979 unsigned int bit_num, 980 unsigned int chunk_size) 981 { 982 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 983 } 984 985 int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size, 986 struct kfd_mem_obj **mem_obj) 987 { 988 unsigned int found, start_search, cur_size; 989 990 if (size == 0) 991 return -EINVAL; 992 993 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 994 return -ENOMEM; 995 996 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 997 if (!(*mem_obj)) 998 return -ENOMEM; 999 1000 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 1001 1002 start_search = 0; 1003 1004 mutex_lock(&kfd->gtt_sa_lock); 1005 1006 kfd_gtt_restart_search: 1007 /* Find the first chunk that is free */ 1008 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1009 kfd->gtt_sa_num_of_chunks, 1010 start_search); 1011 1012 pr_debug("Found = %d\n", found); 1013 1014 /* If there wasn't any free chunk, bail out */ 1015 if (found == kfd->gtt_sa_num_of_chunks) 1016 goto kfd_gtt_no_free_chunk; 1017 1018 /* Update fields of mem_obj */ 1019 (*mem_obj)->range_start = found; 1020 (*mem_obj)->range_end = found; 1021 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1022 kfd->gtt_start_gpu_addr, 1023 found, 1024 kfd->gtt_sa_chunk_size); 1025 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1026 kfd->gtt_start_cpu_ptr, 1027 found, 1028 kfd->gtt_sa_chunk_size); 1029 1030 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1031 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1032 1033 /* If we need only one chunk, mark it as allocated and get out */ 1034 if (size <= kfd->gtt_sa_chunk_size) { 1035 pr_debug("Single bit\n"); 1036 __set_bit(found, kfd->gtt_sa_bitmap); 1037 goto kfd_gtt_out; 1038 } 1039 1040 /* Otherwise, try to see if we have enough contiguous chunks */ 1041 cur_size = size - kfd->gtt_sa_chunk_size; 1042 do { 1043 (*mem_obj)->range_end = 1044 find_next_zero_bit(kfd->gtt_sa_bitmap, 1045 kfd->gtt_sa_num_of_chunks, ++found); 1046 /* 1047 * If next free chunk is not contiguous than we need to 1048 * restart our search from the last free chunk we found (which 1049 * wasn't contiguous to the previous ones 1050 */ 1051 if ((*mem_obj)->range_end != found) { 1052 start_search = found; 1053 goto kfd_gtt_restart_search; 1054 } 1055 1056 /* 1057 * If we reached end of buffer, bail out with error 1058 */ 1059 if (found == kfd->gtt_sa_num_of_chunks) 1060 goto kfd_gtt_no_free_chunk; 1061 1062 /* Check if we don't need another chunk */ 1063 if (cur_size <= kfd->gtt_sa_chunk_size) 1064 cur_size = 0; 1065 else 1066 cur_size -= kfd->gtt_sa_chunk_size; 1067 1068 } while (cur_size > 0); 1069 1070 pr_debug("range_start = %d, range_end = %d\n", 1071 (*mem_obj)->range_start, (*mem_obj)->range_end); 1072 1073 /* Mark the chunks as allocated */ 1074 bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start, 1075 (*mem_obj)->range_end - (*mem_obj)->range_start + 1); 1076 1077 kfd_gtt_out: 1078 mutex_unlock(&kfd->gtt_sa_lock); 1079 return 0; 1080 1081 kfd_gtt_no_free_chunk: 1082 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1083 mutex_unlock(&kfd->gtt_sa_lock); 1084 kfree(*mem_obj); 1085 return -ENOMEM; 1086 } 1087 1088 int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj) 1089 { 1090 /* Act like kfree when trying to free a NULL object */ 1091 if (!mem_obj) 1092 return 0; 1093 1094 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1095 mem_obj, mem_obj->range_start, mem_obj->range_end); 1096 1097 mutex_lock(&kfd->gtt_sa_lock); 1098 1099 /* Mark the chunks as free */ 1100 bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start, 1101 mem_obj->range_end - mem_obj->range_start + 1); 1102 1103 mutex_unlock(&kfd->gtt_sa_lock); 1104 1105 kfree(mem_obj); 1106 return 0; 1107 } 1108 1109 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1110 { 1111 if (kfd) 1112 atomic_inc(&kfd->sram_ecc_flag); 1113 } 1114 1115 void kfd_inc_compute_active(struct kfd_dev *kfd) 1116 { 1117 if (atomic_inc_return(&kfd->compute_profile) == 1) 1118 amdgpu_amdkfd_set_compute_idle(kfd->adev, false); 1119 } 1120 1121 void kfd_dec_compute_active(struct kfd_dev *kfd) 1122 { 1123 int count = atomic_dec_return(&kfd->compute_profile); 1124 1125 if (count == 0) 1126 amdgpu_amdkfd_set_compute_idle(kfd->adev, true); 1127 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1128 } 1129 1130 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 1131 { 1132 if (kfd && kfd->init_complete) 1133 kfd_smi_event_update_thermal_throttling(kfd, throttle_bitmask); 1134 } 1135 1136 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and 1137 * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA. 1138 * When the device has more than two engines, we reserve two for PCIe to enable 1139 * full-duplex and the rest are used as XGMI. 1140 */ 1141 unsigned int kfd_get_num_sdma_engines(struct kfd_dev *kdev) 1142 { 1143 /* If XGMI is not supported, all SDMA engines are PCIe */ 1144 if (!kdev->adev->gmc.xgmi.supported) 1145 return kdev->adev->sdma.num_instances; 1146 1147 return min(kdev->adev->sdma.num_instances, 2); 1148 } 1149 1150 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_dev *kdev) 1151 { 1152 /* After reserved for PCIe, the rest of engines are XGMI */ 1153 return kdev->adev->sdma.num_instances - kfd_get_num_sdma_engines(kdev); 1154 } 1155 1156 #if defined(CONFIG_DEBUG_FS) 1157 1158 /* This function will send a package to HIQ to hang the HWS 1159 * which will trigger a GPU reset and bring the HWS back to normal state 1160 */ 1161 int kfd_debugfs_hang_hws(struct kfd_dev *dev) 1162 { 1163 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1164 pr_err("HWS is not enabled"); 1165 return -EINVAL; 1166 } 1167 1168 return dqm_debugfs_hang_hws(dev->dqm); 1169 } 1170 1171 #endif 1172