1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/bsearch.h> 25 #include <linux/pci.h> 26 #include <linux/slab.h> 27 #include "kfd_priv.h" 28 #include "kfd_device_queue_manager.h" 29 #include "kfd_pm4_headers_vi.h" 30 #include "kfd_pm4_headers_aldebaran.h" 31 #include "cwsr_trap_handler.h" 32 #include "kfd_iommu.h" 33 #include "amdgpu_amdkfd.h" 34 #include "kfd_smi_events.h" 35 #include "kfd_migrate.h" 36 #include "amdgpu.h" 37 #include "amdgpu_xcp.h" 38 39 #define MQD_SIZE_ALIGNED 768 40 41 /* 42 * kfd_locked is used to lock the kfd driver during suspend or reset 43 * once locked, kfd driver will stop any further GPU execution. 44 * create process (open) will return -EAGAIN. 45 */ 46 static int kfd_locked; 47 48 #ifdef CONFIG_DRM_AMDGPU_CIK 49 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 50 #endif 51 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 52 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 53 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 54 extern const struct kfd2kgd_calls aldebaran_kfd2kgd; 55 extern const struct kfd2kgd_calls gc_9_4_3_kfd2kgd; 56 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 57 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 58 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd; 59 60 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 61 unsigned int chunk_size); 62 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 63 64 static int kfd_resume_iommu(struct kfd_dev *kfd); 65 static int kfd_resume(struct kfd_node *kfd); 66 67 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) 68 { 69 uint32_t sdma_version = kfd->adev->ip_versions[SDMA0_HWIP][0]; 70 71 switch (sdma_version) { 72 case IP_VERSION(4, 0, 0):/* VEGA10 */ 73 case IP_VERSION(4, 0, 1):/* VEGA12 */ 74 case IP_VERSION(4, 1, 0):/* RAVEN */ 75 case IP_VERSION(4, 1, 1):/* RAVEN */ 76 case IP_VERSION(4, 1, 2):/* RENOIR */ 77 case IP_VERSION(5, 2, 1):/* VANGOGH */ 78 case IP_VERSION(5, 2, 3):/* YELLOW_CARP */ 79 case IP_VERSION(5, 2, 6):/* GC 10.3.6 */ 80 case IP_VERSION(5, 2, 7):/* GC 10.3.7 */ 81 kfd->device_info.num_sdma_queues_per_engine = 2; 82 break; 83 case IP_VERSION(4, 2, 0):/* VEGA20 */ 84 case IP_VERSION(4, 2, 2):/* ARCTURUS */ 85 case IP_VERSION(4, 4, 0):/* ALDEBARAN */ 86 case IP_VERSION(4, 4, 2): 87 case IP_VERSION(5, 0, 0):/* NAVI10 */ 88 case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */ 89 case IP_VERSION(5, 0, 2):/* NAVI14 */ 90 case IP_VERSION(5, 0, 5):/* NAVI12 */ 91 case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */ 92 case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */ 93 case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */ 94 case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */ 95 case IP_VERSION(6, 0, 0): 96 case IP_VERSION(6, 0, 1): 97 case IP_VERSION(6, 0, 2): 98 case IP_VERSION(6, 0, 3): 99 kfd->device_info.num_sdma_queues_per_engine = 8; 100 break; 101 default: 102 dev_warn(kfd_device, 103 "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n", 104 sdma_version); 105 kfd->device_info.num_sdma_queues_per_engine = 8; 106 } 107 108 switch (sdma_version) { 109 case IP_VERSION(6, 0, 0): 110 case IP_VERSION(6, 0, 2): 111 case IP_VERSION(6, 0, 3): 112 /* Reserve 1 for paging and 1 for gfx */ 113 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 114 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */ 115 kfd->device_info.reserved_sdma_queues_bitmap = 0xFULL; 116 break; 117 case IP_VERSION(6, 0, 1): 118 /* Reserve 1 for paging and 1 for gfx */ 119 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 120 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-0 queue-1; ... */ 121 kfd->device_info.reserved_sdma_queues_bitmap = 0x3ULL; 122 break; 123 default: 124 break; 125 } 126 } 127 128 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) 129 { 130 uint32_t gc_version = KFD_GC_VERSION(kfd); 131 132 switch (gc_version) { 133 case IP_VERSION(9, 0, 1): /* VEGA10 */ 134 case IP_VERSION(9, 1, 0): /* RAVEN */ 135 case IP_VERSION(9, 2, 1): /* VEGA12 */ 136 case IP_VERSION(9, 2, 2): /* RAVEN */ 137 case IP_VERSION(9, 3, 0): /* RENOIR */ 138 case IP_VERSION(9, 4, 0): /* VEGA20 */ 139 case IP_VERSION(9, 4, 1): /* ARCTURUS */ 140 case IP_VERSION(9, 4, 2): /* ALDEBARAN */ 141 case IP_VERSION(10, 3, 1): /* VANGOGH */ 142 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */ 143 case IP_VERSION(10, 3, 6): /* GC 10.3.6 */ 144 case IP_VERSION(10, 3, 7): /* GC 10.3.7 */ 145 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */ 146 case IP_VERSION(10, 1, 4): 147 case IP_VERSION(10, 1, 10): /* NAVI10 */ 148 case IP_VERSION(10, 1, 2): /* NAVI12 */ 149 case IP_VERSION(10, 1, 1): /* NAVI14 */ 150 case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */ 151 case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */ 152 case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */ 153 case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */ 154 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 155 break; 156 case IP_VERSION(11, 0, 0): 157 case IP_VERSION(11, 0, 1): 158 case IP_VERSION(11, 0, 2): 159 case IP_VERSION(11, 0, 3): 160 case IP_VERSION(11, 0, 4): 161 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 162 break; 163 default: 164 dev_warn(kfd_device, "v9 event interrupt handler is set due to " 165 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version); 166 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 167 } 168 } 169 170 static void kfd_device_info_init(struct kfd_dev *kfd, 171 bool vf, uint32_t gfx_target_version) 172 { 173 uint32_t gc_version = KFD_GC_VERSION(kfd); 174 uint32_t asic_type = kfd->adev->asic_type; 175 176 kfd->device_info.max_pasid_bits = 16; 177 kfd->device_info.max_no_of_hqd = 24; 178 kfd->device_info.num_of_watch_points = 4; 179 kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED; 180 kfd->device_info.gfx_target_version = gfx_target_version; 181 182 if (KFD_IS_SOC15(kfd)) { 183 kfd->device_info.doorbell_size = 8; 184 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t); 185 kfd->device_info.supports_cwsr = true; 186 187 kfd_device_info_set_sdma_info(kfd); 188 189 kfd_device_info_set_event_interrupt_class(kfd); 190 191 /* Raven */ 192 if (gc_version == IP_VERSION(9, 1, 0) || 193 gc_version == IP_VERSION(9, 2, 2)) 194 kfd->device_info.needs_iommu_device = true; 195 196 if (gc_version < IP_VERSION(11, 0, 0)) { 197 /* Navi2x+, Navi1x+ */ 198 if (gc_version == IP_VERSION(10, 3, 6)) 199 kfd->device_info.no_atomic_fw_version = 14; 200 else if (gc_version == IP_VERSION(10, 3, 7)) 201 kfd->device_info.no_atomic_fw_version = 3; 202 else if (gc_version >= IP_VERSION(10, 3, 0)) 203 kfd->device_info.no_atomic_fw_version = 92; 204 else if (gc_version >= IP_VERSION(10, 1, 1)) 205 kfd->device_info.no_atomic_fw_version = 145; 206 207 /* Navi1x+ */ 208 if (gc_version >= IP_VERSION(10, 1, 1)) 209 kfd->device_info.needs_pci_atomics = true; 210 } else if (gc_version < IP_VERSION(12, 0, 0)) { 211 /* 212 * PCIe atomics support acknowledgment in GFX11 RS64 CPFW requires 213 * MEC version >= 509. Prior RS64 CPFW versions (and all F32) require 214 * PCIe atomics support. 215 */ 216 kfd->device_info.needs_pci_atomics = true; 217 kfd->device_info.no_atomic_fw_version = kfd->adev->gfx.rs64_enable ? 509 : 0; 218 } 219 } else { 220 kfd->device_info.doorbell_size = 4; 221 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t); 222 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik; 223 kfd->device_info.num_sdma_queues_per_engine = 2; 224 225 if (asic_type != CHIP_KAVERI && 226 asic_type != CHIP_HAWAII && 227 asic_type != CHIP_TONGA) 228 kfd->device_info.supports_cwsr = true; 229 230 if (asic_type == CHIP_KAVERI || 231 asic_type == CHIP_CARRIZO) 232 kfd->device_info.needs_iommu_device = true; 233 234 if (asic_type != CHIP_HAWAII && !vf) 235 kfd->device_info.needs_pci_atomics = true; 236 } 237 } 238 239 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 240 { 241 struct kfd_dev *kfd = NULL; 242 const struct kfd2kgd_calls *f2g = NULL; 243 uint32_t gfx_target_version = 0; 244 245 switch (adev->asic_type) { 246 #ifdef KFD_SUPPORT_IOMMU_V2 247 #ifdef CONFIG_DRM_AMDGPU_CIK 248 case CHIP_KAVERI: 249 gfx_target_version = 70000; 250 if (!vf) 251 f2g = &gfx_v7_kfd2kgd; 252 break; 253 #endif 254 case CHIP_CARRIZO: 255 gfx_target_version = 80001; 256 if (!vf) 257 f2g = &gfx_v8_kfd2kgd; 258 break; 259 #endif 260 #ifdef CONFIG_DRM_AMDGPU_CIK 261 case CHIP_HAWAII: 262 gfx_target_version = 70001; 263 if (!amdgpu_exp_hw_support) 264 pr_info( 265 "KFD support on Hawaii is experimental. See modparam exp_hw_support\n" 266 ); 267 else if (!vf) 268 f2g = &gfx_v7_kfd2kgd; 269 break; 270 #endif 271 case CHIP_TONGA: 272 gfx_target_version = 80002; 273 if (!vf) 274 f2g = &gfx_v8_kfd2kgd; 275 break; 276 case CHIP_FIJI: 277 case CHIP_POLARIS10: 278 gfx_target_version = 80003; 279 f2g = &gfx_v8_kfd2kgd; 280 break; 281 case CHIP_POLARIS11: 282 case CHIP_POLARIS12: 283 case CHIP_VEGAM: 284 gfx_target_version = 80003; 285 if (!vf) 286 f2g = &gfx_v8_kfd2kgd; 287 break; 288 default: 289 switch (adev->ip_versions[GC_HWIP][0]) { 290 /* Vega 10 */ 291 case IP_VERSION(9, 0, 1): 292 gfx_target_version = 90000; 293 f2g = &gfx_v9_kfd2kgd; 294 break; 295 #ifdef KFD_SUPPORT_IOMMU_V2 296 /* Raven */ 297 case IP_VERSION(9, 1, 0): 298 case IP_VERSION(9, 2, 2): 299 gfx_target_version = 90002; 300 if (!vf) 301 f2g = &gfx_v9_kfd2kgd; 302 break; 303 #endif 304 /* Vega12 */ 305 case IP_VERSION(9, 2, 1): 306 gfx_target_version = 90004; 307 if (!vf) 308 f2g = &gfx_v9_kfd2kgd; 309 break; 310 /* Renoir */ 311 case IP_VERSION(9, 3, 0): 312 gfx_target_version = 90012; 313 if (!vf) 314 f2g = &gfx_v9_kfd2kgd; 315 break; 316 /* Vega20 */ 317 case IP_VERSION(9, 4, 0): 318 gfx_target_version = 90006; 319 if (!vf) 320 f2g = &gfx_v9_kfd2kgd; 321 break; 322 /* Arcturus */ 323 case IP_VERSION(9, 4, 1): 324 gfx_target_version = 90008; 325 f2g = &arcturus_kfd2kgd; 326 break; 327 /* Aldebaran */ 328 case IP_VERSION(9, 4, 2): 329 gfx_target_version = 90010; 330 f2g = &aldebaran_kfd2kgd; 331 break; 332 case IP_VERSION(9, 4, 3): 333 gfx_target_version = 90400; 334 f2g = &gc_9_4_3_kfd2kgd; 335 break; 336 /* Navi10 */ 337 case IP_VERSION(10, 1, 10): 338 gfx_target_version = 100100; 339 if (!vf) 340 f2g = &gfx_v10_kfd2kgd; 341 break; 342 /* Navi12 */ 343 case IP_VERSION(10, 1, 2): 344 gfx_target_version = 100101; 345 f2g = &gfx_v10_kfd2kgd; 346 break; 347 /* Navi14 */ 348 case IP_VERSION(10, 1, 1): 349 gfx_target_version = 100102; 350 if (!vf) 351 f2g = &gfx_v10_kfd2kgd; 352 break; 353 /* Cyan Skillfish */ 354 case IP_VERSION(10, 1, 3): 355 case IP_VERSION(10, 1, 4): 356 gfx_target_version = 100103; 357 if (!vf) 358 f2g = &gfx_v10_kfd2kgd; 359 break; 360 /* Sienna Cichlid */ 361 case IP_VERSION(10, 3, 0): 362 gfx_target_version = 100300; 363 f2g = &gfx_v10_3_kfd2kgd; 364 break; 365 /* Navy Flounder */ 366 case IP_VERSION(10, 3, 2): 367 gfx_target_version = 100301; 368 f2g = &gfx_v10_3_kfd2kgd; 369 break; 370 /* Van Gogh */ 371 case IP_VERSION(10, 3, 1): 372 gfx_target_version = 100303; 373 if (!vf) 374 f2g = &gfx_v10_3_kfd2kgd; 375 break; 376 /* Dimgrey Cavefish */ 377 case IP_VERSION(10, 3, 4): 378 gfx_target_version = 100302; 379 f2g = &gfx_v10_3_kfd2kgd; 380 break; 381 /* Beige Goby */ 382 case IP_VERSION(10, 3, 5): 383 gfx_target_version = 100304; 384 f2g = &gfx_v10_3_kfd2kgd; 385 break; 386 /* Yellow Carp */ 387 case IP_VERSION(10, 3, 3): 388 gfx_target_version = 100305; 389 if (!vf) 390 f2g = &gfx_v10_3_kfd2kgd; 391 break; 392 case IP_VERSION(10, 3, 6): 393 case IP_VERSION(10, 3, 7): 394 gfx_target_version = 100306; 395 if (!vf) 396 f2g = &gfx_v10_3_kfd2kgd; 397 break; 398 case IP_VERSION(11, 0, 0): 399 gfx_target_version = 110000; 400 f2g = &gfx_v11_kfd2kgd; 401 break; 402 case IP_VERSION(11, 0, 1): 403 case IP_VERSION(11, 0, 4): 404 gfx_target_version = 110003; 405 f2g = &gfx_v11_kfd2kgd; 406 break; 407 case IP_VERSION(11, 0, 2): 408 gfx_target_version = 110002; 409 f2g = &gfx_v11_kfd2kgd; 410 break; 411 case IP_VERSION(11, 0, 3): 412 /* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */ 413 gfx_target_version = 110001; 414 f2g = &gfx_v11_kfd2kgd; 415 break; 416 default: 417 break; 418 } 419 break; 420 } 421 422 if (!f2g) { 423 if (adev->ip_versions[GC_HWIP][0]) 424 dev_err(kfd_device, "GC IP %06x %s not supported in kfd\n", 425 adev->ip_versions[GC_HWIP][0], vf ? "VF" : ""); 426 else 427 dev_err(kfd_device, "%s %s not supported in kfd\n", 428 amdgpu_asic_name[adev->asic_type], vf ? "VF" : ""); 429 return NULL; 430 } 431 432 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 433 if (!kfd) 434 return NULL; 435 436 kfd->adev = adev; 437 kfd_device_info_init(kfd, vf, gfx_target_version); 438 kfd->init_complete = false; 439 kfd->kfd2kgd = f2g; 440 atomic_set(&kfd->compute_profile, 0); 441 442 mutex_init(&kfd->doorbell_mutex); 443 memset(&kfd->doorbell_available_index, 0, 444 sizeof(kfd->doorbell_available_index)); 445 446 ida_init(&kfd->doorbell_ida); 447 448 return kfd; 449 } 450 451 static void kfd_cwsr_init(struct kfd_dev *kfd) 452 { 453 if (cwsr_enable && kfd->device_info.supports_cwsr) { 454 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) { 455 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE); 456 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 457 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 458 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) { 459 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE); 460 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 461 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 462 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) { 463 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) > PAGE_SIZE); 464 kfd->cwsr_isa = cwsr_trap_aldebaran_hex; 465 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); 466 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3)) { 467 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_4_3_hex) > PAGE_SIZE); 468 kfd->cwsr_isa = cwsr_trap_gfx9_4_3_hex; 469 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_4_3_hex); 470 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) { 471 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE); 472 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 473 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 474 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) { 475 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE); 476 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 477 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 478 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) { 479 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE); 480 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 481 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 482 } else { 483 BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE); 484 kfd->cwsr_isa = cwsr_trap_gfx11_hex; 485 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex); 486 } 487 488 kfd->cwsr_enabled = true; 489 } 490 } 491 492 static int kfd_gws_init(struct kfd_node *node) 493 { 494 int ret = 0; 495 struct kfd_dev *kfd = node->kfd; 496 497 if (node->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 498 return 0; 499 500 if (hws_gws_support || (KFD_IS_SOC15(node) && 501 ((KFD_GC_VERSION(node) == IP_VERSION(9, 0, 1) 502 && kfd->mec2_fw_version >= 0x81b3) || 503 (KFD_GC_VERSION(node) <= IP_VERSION(9, 4, 0) 504 && kfd->mec2_fw_version >= 0x1b3) || 505 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 1) 506 && kfd->mec2_fw_version >= 0x30) || 507 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 2) 508 && kfd->mec2_fw_version >= 0x28) || 509 (KFD_GC_VERSION(node) >= IP_VERSION(10, 3, 0) 510 && KFD_GC_VERSION(node) < IP_VERSION(11, 0, 0) 511 && kfd->mec2_fw_version >= 0x6b)))) 512 ret = amdgpu_amdkfd_alloc_gws(node->adev, 513 node->adev->gds.gws_size, &node->gws); 514 515 return ret; 516 } 517 518 static void kfd_smi_init(struct kfd_node *dev) 519 { 520 INIT_LIST_HEAD(&dev->smi_clients); 521 spin_lock_init(&dev->smi_lock); 522 } 523 524 static int kfd_init_node(struct kfd_node *node) 525 { 526 int err = -1; 527 528 if (kfd_interrupt_init(node)) { 529 dev_err(kfd_device, "Error initializing interrupts\n"); 530 goto kfd_interrupt_error; 531 } 532 533 node->dqm = device_queue_manager_init(node); 534 if (!node->dqm) { 535 dev_err(kfd_device, "Error initializing queue manager\n"); 536 goto device_queue_manager_error; 537 } 538 539 if (kfd_gws_init(node)) { 540 dev_err(kfd_device, "Could not allocate %d gws\n", 541 node->adev->gds.gws_size); 542 goto gws_error; 543 } 544 545 if (kfd_resume(node)) 546 goto kfd_resume_error; 547 548 if (kfd_topology_add_device(node)) { 549 dev_err(kfd_device, "Error adding device to topology\n"); 550 goto kfd_topology_add_device_error; 551 } 552 553 kfd_smi_init(node); 554 555 return 0; 556 557 kfd_topology_add_device_error: 558 kfd_resume_error: 559 gws_error: 560 device_queue_manager_uninit(node->dqm); 561 device_queue_manager_error: 562 kfd_interrupt_exit(node); 563 kfd_interrupt_error: 564 if (node->gws) 565 amdgpu_amdkfd_free_gws(node->adev, node->gws); 566 567 /* Cleanup the node memory here */ 568 kfree(node); 569 return err; 570 } 571 572 static void kfd_cleanup_nodes(struct kfd_dev *kfd, unsigned int num_nodes) 573 { 574 struct kfd_node *knode; 575 unsigned int i; 576 577 for (i = 0; i < num_nodes; i++) { 578 knode = kfd->nodes[i]; 579 device_queue_manager_uninit(knode->dqm); 580 kfd_interrupt_exit(knode); 581 kfd_topology_remove_device(knode); 582 if (knode->gws) 583 amdgpu_amdkfd_free_gws(knode->adev, knode->gws); 584 kfree(knode); 585 kfd->nodes[i] = NULL; 586 } 587 } 588 589 bool kgd2kfd_device_init(struct kfd_dev *kfd, 590 const struct kgd2kfd_shared_resources *gpu_resources) 591 { 592 unsigned int size, map_process_packet_size, i; 593 struct kfd_node *node; 594 uint32_t first_vmid_kfd, last_vmid_kfd, vmid_num_kfd; 595 unsigned int max_proc_per_quantum; 596 int num_xcd, partition_mode; 597 598 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 599 KGD_ENGINE_MEC1); 600 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 601 KGD_ENGINE_MEC2); 602 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 603 KGD_ENGINE_SDMA1); 604 kfd->shared_resources = *gpu_resources; 605 606 num_xcd = NUM_XCC(kfd->adev->gfx.xcc_mask); 607 if (num_xcd == 0 || num_xcd == 1 || kfd->adev->gfx.num_xcc_per_xcp == 0) 608 kfd->num_nodes = 1; 609 else 610 kfd->num_nodes = num_xcd / kfd->adev->gfx.num_xcc_per_xcp; 611 if (kfd->num_nodes == 0) { 612 dev_err(kfd_device, 613 "KFD num nodes cannot be 0, GC inst: %d, num_xcc_in_node: %d\n", 614 num_xcd, kfd->adev->gfx.num_xcc_per_xcp); 615 goto out; 616 } 617 618 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 619 * 32 and 64-bit requests are possible and must be 620 * supported. 621 */ 622 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev); 623 if (!kfd->pci_atomic_requested && 624 kfd->device_info.needs_pci_atomics && 625 (!kfd->device_info.no_atomic_fw_version || 626 kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) { 627 dev_info(kfd_device, 628 "skipped device %x:%x, PCI rejects atomics %d<%d\n", 629 kfd->adev->pdev->vendor, kfd->adev->pdev->device, 630 kfd->mec_fw_version, 631 kfd->device_info.no_atomic_fw_version); 632 return false; 633 } 634 635 first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 636 last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 637 vmid_num_kfd = last_vmid_kfd - first_vmid_kfd + 1; 638 639 /* For GFX9.4.3, we need special handling for VMIDs depending on 640 * partition mode. 641 * In CPX mode, the VMID range needs to be shared between XCDs. 642 * Additionally, there are 13 VMIDs (3-15) available for KFD. To 643 * divide them equally, we change starting VMID to 4 and not use 644 * VMID 3. 645 * If the VMID range changes for GFX9.4.3, then this code MUST be 646 * revisited. 647 */ 648 partition_mode = amdgpu_xcp_query_partition_mode(kfd->adev->xcp_mgr); 649 if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) && 650 partition_mode == AMDGPU_CPX_PARTITION_MODE && 651 kfd->num_nodes != 1) { 652 vmid_num_kfd /= 2; 653 first_vmid_kfd = last_vmid_kfd + 1 - vmid_num_kfd*2; 654 } 655 656 /* Verify module parameters regarding mapped process number*/ 657 if (hws_max_conc_proc >= 0) 658 max_proc_per_quantum = min((u32)hws_max_conc_proc, vmid_num_kfd); 659 else 660 max_proc_per_quantum = vmid_num_kfd; 661 662 /* calculate max size of mqds needed for queues */ 663 size = max_num_of_queues_per_device * 664 kfd->device_info.mqd_size_aligned; 665 666 /* 667 * calculate max size of runlist packet. 668 * There can be only 2 packets at once 669 */ 670 map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ? 671 sizeof(struct pm4_mes_map_process_aldebaran) : 672 sizeof(struct pm4_mes_map_process); 673 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + 674 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 675 + sizeof(struct pm4_mes_runlist)) * 2; 676 677 /* Add size of HIQ & DIQ */ 678 size += KFD_KERNEL_QUEUE_SIZE * 2; 679 680 /* add another 512KB for all other allocations on gart (HPD, fences) */ 681 size += 512 * 1024; 682 683 if (amdgpu_amdkfd_alloc_gtt_mem( 684 kfd->adev, size, &kfd->gtt_mem, 685 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 686 false)) { 687 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 688 goto alloc_gtt_mem_failure; 689 } 690 691 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 692 693 /* Initialize GTT sa with 512 byte chunk size */ 694 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 695 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 696 goto kfd_gtt_sa_init_error; 697 } 698 699 if (kfd_doorbell_init(kfd)) { 700 dev_err(kfd_device, 701 "Error initializing doorbell aperture\n"); 702 goto kfd_doorbell_error; 703 } 704 705 if (amdgpu_use_xgmi_p2p) 706 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id; 707 708 /* 709 * For GFX9.4.3, the KFD abstracts all partitions within a socket as 710 * xGMI connected in the topology so assign a unique hive id per 711 * device based on the pci device location if device is in PCIe mode. 712 */ 713 if (!kfd->hive_id && (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3)) && kfd->num_nodes > 1) 714 kfd->hive_id = pci_dev_id(kfd->adev->pdev); 715 716 kfd->noretry = kfd->adev->gmc.noretry; 717 718 /* If CRAT is broken, won't set iommu enabled */ 719 kfd_double_confirm_iommu_support(kfd); 720 721 if (kfd_iommu_device_init(kfd)) { 722 kfd->use_iommu_v2 = false; 723 dev_err(kfd_device, "Error initializing iommuv2\n"); 724 goto device_iommu_error; 725 } 726 727 kfd_cwsr_init(kfd); 728 729 /* TODO: Needs to be updated for memory partitioning */ 730 svm_migrate_init(kfd->adev); 731 732 amdgpu_amdkfd_get_local_mem_info(kfd->adev, &kfd->local_mem_info); 733 734 dev_info(kfd_device, "Total number of KFD nodes to be created: %d\n", 735 kfd->num_nodes); 736 737 /* Allocate the KFD nodes */ 738 for (i = 0; i < kfd->num_nodes; i++) { 739 node = kzalloc(sizeof(struct kfd_node), GFP_KERNEL); 740 if (!node) 741 goto node_alloc_error; 742 743 node->node_id = i; 744 node->adev = kfd->adev; 745 node->kfd = kfd; 746 node->kfd2kgd = kfd->kfd2kgd; 747 node->vm_info.vmid_num_kfd = vmid_num_kfd; 748 node->num_xcc_per_node = max(1U, kfd->adev->gfx.num_xcc_per_xcp); 749 node->start_xcc_id = node->num_xcc_per_node * i; 750 751 if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) && 752 partition_mode == AMDGPU_CPX_PARTITION_MODE && 753 kfd->num_nodes != 1) { 754 /* For GFX9.4.3 and CPX mode, first XCD gets VMID range 755 * 4-9 and second XCD gets VMID range 10-15. 756 */ 757 758 node->vm_info.first_vmid_kfd = (i%2 == 0) ? 759 first_vmid_kfd : 760 first_vmid_kfd+vmid_num_kfd; 761 node->vm_info.last_vmid_kfd = (i%2 == 0) ? 762 last_vmid_kfd-vmid_num_kfd : 763 last_vmid_kfd; 764 node->compute_vmid_bitmap = 765 ((0x1 << (node->vm_info.last_vmid_kfd + 1)) - 1) - 766 ((0x1 << (node->vm_info.first_vmid_kfd)) - 1); 767 } else { 768 node->vm_info.first_vmid_kfd = first_vmid_kfd; 769 node->vm_info.last_vmid_kfd = last_vmid_kfd; 770 node->compute_vmid_bitmap = 771 gpu_resources->compute_vmid_bitmap; 772 } 773 node->max_proc_per_quantum = max_proc_per_quantum; 774 atomic_set(&node->sram_ecc_flag, 0); 775 /* Initialize the KFD node */ 776 if (kfd_init_node(node)) { 777 dev_err(kfd_device, "Error initializing KFD node\n"); 778 goto node_init_error; 779 } 780 kfd->nodes[i] = node; 781 } 782 783 if (kfd_resume_iommu(kfd)) 784 goto kfd_resume_iommu_error; 785 786 kfd->init_complete = true; 787 dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, 788 kfd->adev->pdev->device); 789 790 pr_debug("Starting kfd with the following scheduling policy %d\n", 791 node->dqm->sched_policy); 792 793 goto out; 794 795 kfd_resume_iommu_error: 796 node_init_error: 797 node_alloc_error: 798 kfd_cleanup_nodes(kfd, i); 799 device_iommu_error: 800 kfd_doorbell_fini(kfd); 801 kfd_doorbell_error: 802 kfd_gtt_sa_fini(kfd); 803 kfd_gtt_sa_init_error: 804 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 805 alloc_gtt_mem_failure: 806 dev_err(kfd_device, 807 "device %x:%x NOT added due to errors\n", 808 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 809 out: 810 return kfd->init_complete; 811 } 812 813 void kgd2kfd_device_exit(struct kfd_dev *kfd) 814 { 815 if (kfd->init_complete) { 816 /* Cleanup KFD nodes */ 817 kfd_cleanup_nodes(kfd, kfd->num_nodes); 818 /* Cleanup common/shared resources */ 819 kfd_doorbell_fini(kfd); 820 ida_destroy(&kfd->doorbell_ida); 821 kfd_gtt_sa_fini(kfd); 822 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 823 } 824 825 kfree(kfd); 826 } 827 828 int kgd2kfd_pre_reset(struct kfd_dev *kfd) 829 { 830 struct kfd_node *node; 831 int i; 832 833 if (!kfd->init_complete) 834 return 0; 835 836 for (i = 0; i < kfd->num_nodes; i++) { 837 node = kfd->nodes[i]; 838 kfd_smi_event_update_gpu_reset(node, false); 839 node->dqm->ops.pre_reset(node->dqm); 840 } 841 842 kgd2kfd_suspend(kfd, false); 843 844 for (i = 0; i < kfd->num_nodes; i++) 845 kfd_signal_reset_event(kfd->nodes[i]); 846 847 return 0; 848 } 849 850 /* 851 * Fix me. KFD won't be able to resume existing process for now. 852 * We will keep all existing process in a evicted state and 853 * wait the process to be terminated. 854 */ 855 856 int kgd2kfd_post_reset(struct kfd_dev *kfd) 857 { 858 int ret; 859 struct kfd_node *node; 860 int i; 861 862 if (!kfd->init_complete) 863 return 0; 864 865 for (i = 0; i < kfd->num_nodes; i++) { 866 ret = kfd_resume(kfd->nodes[i]); 867 if (ret) 868 return ret; 869 } 870 871 mutex_lock(&kfd_processes_mutex); 872 --kfd_locked; 873 mutex_unlock(&kfd_processes_mutex); 874 875 for (i = 0; i < kfd->num_nodes; i++) { 876 node = kfd->nodes[i]; 877 atomic_set(&node->sram_ecc_flag, 0); 878 kfd_smi_event_update_gpu_reset(node, true); 879 } 880 881 return 0; 882 } 883 884 bool kfd_is_locked(void) 885 { 886 lockdep_assert_held(&kfd_processes_mutex); 887 return (kfd_locked > 0); 888 } 889 890 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 891 { 892 struct kfd_node *node; 893 int i; 894 int count; 895 896 if (!kfd->init_complete) 897 return; 898 899 /* for runtime suspend, skip locking kfd */ 900 if (!run_pm) { 901 mutex_lock(&kfd_processes_mutex); 902 count = ++kfd_locked; 903 mutex_unlock(&kfd_processes_mutex); 904 905 /* For first KFD device suspend all the KFD processes */ 906 if (count == 1) 907 kfd_suspend_all_processes(); 908 } 909 910 for (i = 0; i < kfd->num_nodes; i++) { 911 node = kfd->nodes[i]; 912 node->dqm->ops.stop(node->dqm); 913 } 914 kfd_iommu_suspend(kfd); 915 } 916 917 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 918 { 919 int ret, count, i; 920 921 if (!kfd->init_complete) 922 return 0; 923 924 for (i = 0; i < kfd->num_nodes; i++) { 925 ret = kfd_resume(kfd->nodes[i]); 926 if (ret) 927 return ret; 928 } 929 930 /* for runtime resume, skip unlocking kfd */ 931 if (!run_pm) { 932 mutex_lock(&kfd_processes_mutex); 933 count = --kfd_locked; 934 mutex_unlock(&kfd_processes_mutex); 935 936 WARN_ONCE(count < 0, "KFD suspend / resume ref. error"); 937 if (count == 0) 938 ret = kfd_resume_all_processes(); 939 } 940 941 return ret; 942 } 943 944 int kgd2kfd_resume_iommu(struct kfd_dev *kfd) 945 { 946 if (!kfd->init_complete) 947 return 0; 948 949 return kfd_resume_iommu(kfd); 950 } 951 952 static int kfd_resume_iommu(struct kfd_dev *kfd) 953 { 954 int err = 0; 955 956 err = kfd_iommu_resume(kfd); 957 if (err) 958 dev_err(kfd_device, 959 "Failed to resume IOMMU for device %x:%x\n", 960 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 961 return err; 962 } 963 964 static int kfd_resume(struct kfd_node *node) 965 { 966 int err = 0; 967 968 err = node->dqm->ops.start(node->dqm); 969 if (err) 970 dev_err(kfd_device, 971 "Error starting queue manager for device %x:%x\n", 972 node->adev->pdev->vendor, node->adev->pdev->device); 973 974 return err; 975 } 976 977 static inline void kfd_queue_work(struct workqueue_struct *wq, 978 struct work_struct *work) 979 { 980 int cpu, new_cpu; 981 982 cpu = new_cpu = smp_processor_id(); 983 do { 984 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids; 985 if (cpu_to_node(new_cpu) == numa_node_id()) 986 break; 987 } while (cpu != new_cpu); 988 989 queue_work_on(new_cpu, wq, work); 990 } 991 992 /* This is called directly from KGD at ISR. */ 993 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 994 { 995 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE], i; 996 bool is_patched = false; 997 unsigned long flags; 998 struct kfd_node *node; 999 1000 if (!kfd->init_complete) 1001 return; 1002 1003 if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) { 1004 dev_err_once(kfd_device, "Ring entry too small\n"); 1005 return; 1006 } 1007 1008 for (i = 0; i < kfd->num_nodes; i++) { 1009 node = kfd->nodes[i]; 1010 spin_lock_irqsave(&node->interrupt_lock, flags); 1011 1012 if (node->interrupts_active 1013 && interrupt_is_wanted(node, ih_ring_entry, 1014 patched_ihre, &is_patched) 1015 && enqueue_ih_ring_entry(node, 1016 is_patched ? patched_ihre : ih_ring_entry)) { 1017 kfd_queue_work(node->ih_wq, &node->interrupt_work); 1018 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1019 return; 1020 } 1021 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1022 } 1023 1024 } 1025 1026 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger) 1027 { 1028 struct kfd_process *p; 1029 int r; 1030 1031 /* Because we are called from arbitrary context (workqueue) as opposed 1032 * to process context, kfd_process could attempt to exit while we are 1033 * running so the lookup function increments the process ref count. 1034 */ 1035 p = kfd_lookup_process_by_mm(mm); 1036 if (!p) 1037 return -ESRCH; 1038 1039 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 1040 r = kfd_process_evict_queues(p, trigger); 1041 1042 kfd_unref_process(p); 1043 return r; 1044 } 1045 1046 int kgd2kfd_resume_mm(struct mm_struct *mm) 1047 { 1048 struct kfd_process *p; 1049 int r; 1050 1051 /* Because we are called from arbitrary context (workqueue) as opposed 1052 * to process context, kfd_process could attempt to exit while we are 1053 * running so the lookup function increments the process ref count. 1054 */ 1055 p = kfd_lookup_process_by_mm(mm); 1056 if (!p) 1057 return -ESRCH; 1058 1059 r = kfd_process_restore_queues(p); 1060 1061 kfd_unref_process(p); 1062 return r; 1063 } 1064 1065 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 1066 * prepare for safe eviction of KFD BOs that belong to the specified 1067 * process. 1068 * 1069 * @mm: mm_struct that identifies the specified KFD process 1070 * @fence: eviction fence attached to KFD process BOs 1071 * 1072 */ 1073 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 1074 struct dma_fence *fence) 1075 { 1076 struct kfd_process *p; 1077 unsigned long active_time; 1078 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 1079 1080 if (!fence) 1081 return -EINVAL; 1082 1083 if (dma_fence_is_signaled(fence)) 1084 return 0; 1085 1086 p = kfd_lookup_process_by_mm(mm); 1087 if (!p) 1088 return -ENODEV; 1089 1090 if (fence->seqno == p->last_eviction_seqno) 1091 goto out; 1092 1093 p->last_eviction_seqno = fence->seqno; 1094 1095 /* Avoid KFD process starvation. Wait for at least 1096 * PROCESS_ACTIVE_TIME_MS before evicting the process again 1097 */ 1098 active_time = get_jiffies_64() - p->last_restore_timestamp; 1099 if (delay_jiffies > active_time) 1100 delay_jiffies -= active_time; 1101 else 1102 delay_jiffies = 0; 1103 1104 /* During process initialization eviction_work.dwork is initialized 1105 * to kfd_evict_bo_worker 1106 */ 1107 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 1108 p->lead_thread->pid, delay_jiffies); 1109 schedule_delayed_work(&p->eviction_work, delay_jiffies); 1110 out: 1111 kfd_unref_process(p); 1112 return 0; 1113 } 1114 1115 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 1116 unsigned int chunk_size) 1117 { 1118 if (WARN_ON(buf_size < chunk_size)) 1119 return -EINVAL; 1120 if (WARN_ON(buf_size == 0)) 1121 return -EINVAL; 1122 if (WARN_ON(chunk_size == 0)) 1123 return -EINVAL; 1124 1125 kfd->gtt_sa_chunk_size = chunk_size; 1126 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 1127 1128 kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks, 1129 GFP_KERNEL); 1130 if (!kfd->gtt_sa_bitmap) 1131 return -ENOMEM; 1132 1133 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 1134 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 1135 1136 mutex_init(&kfd->gtt_sa_lock); 1137 1138 return 0; 1139 } 1140 1141 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 1142 { 1143 mutex_destroy(&kfd->gtt_sa_lock); 1144 bitmap_free(kfd->gtt_sa_bitmap); 1145 } 1146 1147 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 1148 unsigned int bit_num, 1149 unsigned int chunk_size) 1150 { 1151 return start_addr + bit_num * chunk_size; 1152 } 1153 1154 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 1155 unsigned int bit_num, 1156 unsigned int chunk_size) 1157 { 1158 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 1159 } 1160 1161 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size, 1162 struct kfd_mem_obj **mem_obj) 1163 { 1164 unsigned int found, start_search, cur_size; 1165 struct kfd_dev *kfd = node->kfd; 1166 1167 if (size == 0) 1168 return -EINVAL; 1169 1170 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 1171 return -ENOMEM; 1172 1173 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 1174 if (!(*mem_obj)) 1175 return -ENOMEM; 1176 1177 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 1178 1179 start_search = 0; 1180 1181 mutex_lock(&kfd->gtt_sa_lock); 1182 1183 kfd_gtt_restart_search: 1184 /* Find the first chunk that is free */ 1185 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1186 kfd->gtt_sa_num_of_chunks, 1187 start_search); 1188 1189 pr_debug("Found = %d\n", found); 1190 1191 /* If there wasn't any free chunk, bail out */ 1192 if (found == kfd->gtt_sa_num_of_chunks) 1193 goto kfd_gtt_no_free_chunk; 1194 1195 /* Update fields of mem_obj */ 1196 (*mem_obj)->range_start = found; 1197 (*mem_obj)->range_end = found; 1198 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1199 kfd->gtt_start_gpu_addr, 1200 found, 1201 kfd->gtt_sa_chunk_size); 1202 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1203 kfd->gtt_start_cpu_ptr, 1204 found, 1205 kfd->gtt_sa_chunk_size); 1206 1207 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1208 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1209 1210 /* If we need only one chunk, mark it as allocated and get out */ 1211 if (size <= kfd->gtt_sa_chunk_size) { 1212 pr_debug("Single bit\n"); 1213 __set_bit(found, kfd->gtt_sa_bitmap); 1214 goto kfd_gtt_out; 1215 } 1216 1217 /* Otherwise, try to see if we have enough contiguous chunks */ 1218 cur_size = size - kfd->gtt_sa_chunk_size; 1219 do { 1220 (*mem_obj)->range_end = 1221 find_next_zero_bit(kfd->gtt_sa_bitmap, 1222 kfd->gtt_sa_num_of_chunks, ++found); 1223 /* 1224 * If next free chunk is not contiguous than we need to 1225 * restart our search from the last free chunk we found (which 1226 * wasn't contiguous to the previous ones 1227 */ 1228 if ((*mem_obj)->range_end != found) { 1229 start_search = found; 1230 goto kfd_gtt_restart_search; 1231 } 1232 1233 /* 1234 * If we reached end of buffer, bail out with error 1235 */ 1236 if (found == kfd->gtt_sa_num_of_chunks) 1237 goto kfd_gtt_no_free_chunk; 1238 1239 /* Check if we don't need another chunk */ 1240 if (cur_size <= kfd->gtt_sa_chunk_size) 1241 cur_size = 0; 1242 else 1243 cur_size -= kfd->gtt_sa_chunk_size; 1244 1245 } while (cur_size > 0); 1246 1247 pr_debug("range_start = %d, range_end = %d\n", 1248 (*mem_obj)->range_start, (*mem_obj)->range_end); 1249 1250 /* Mark the chunks as allocated */ 1251 bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start, 1252 (*mem_obj)->range_end - (*mem_obj)->range_start + 1); 1253 1254 kfd_gtt_out: 1255 mutex_unlock(&kfd->gtt_sa_lock); 1256 return 0; 1257 1258 kfd_gtt_no_free_chunk: 1259 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1260 mutex_unlock(&kfd->gtt_sa_lock); 1261 kfree(*mem_obj); 1262 return -ENOMEM; 1263 } 1264 1265 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj) 1266 { 1267 struct kfd_dev *kfd = node->kfd; 1268 1269 /* Act like kfree when trying to free a NULL object */ 1270 if (!mem_obj) 1271 return 0; 1272 1273 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1274 mem_obj, mem_obj->range_start, mem_obj->range_end); 1275 1276 mutex_lock(&kfd->gtt_sa_lock); 1277 1278 /* Mark the chunks as free */ 1279 bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start, 1280 mem_obj->range_end - mem_obj->range_start + 1); 1281 1282 mutex_unlock(&kfd->gtt_sa_lock); 1283 1284 kfree(mem_obj); 1285 return 0; 1286 } 1287 1288 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1289 { 1290 /* 1291 * TODO: Currently update SRAM ECC flag for first node. 1292 * This needs to be updated later when we can 1293 * identify SRAM ECC error on other nodes also. 1294 */ 1295 if (kfd) 1296 atomic_inc(&kfd->nodes[0]->sram_ecc_flag); 1297 } 1298 1299 void kfd_inc_compute_active(struct kfd_node *node) 1300 { 1301 if (atomic_inc_return(&node->kfd->compute_profile) == 1) 1302 amdgpu_amdkfd_set_compute_idle(node->adev, false); 1303 } 1304 1305 void kfd_dec_compute_active(struct kfd_node *node) 1306 { 1307 int count = atomic_dec_return(&node->kfd->compute_profile); 1308 1309 if (count == 0) 1310 amdgpu_amdkfd_set_compute_idle(node->adev, true); 1311 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1312 } 1313 1314 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 1315 { 1316 /* 1317 * TODO: For now, raise the throttling event only on first node. 1318 * This will need to change after we are able to determine 1319 * which node raised the throttling event. 1320 */ 1321 if (kfd && kfd->init_complete) 1322 kfd_smi_event_update_thermal_throttling(kfd->nodes[0], 1323 throttle_bitmask); 1324 } 1325 1326 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and 1327 * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA. 1328 * When the device has more than two engines, we reserve two for PCIe to enable 1329 * full-duplex and the rest are used as XGMI. 1330 */ 1331 unsigned int kfd_get_num_sdma_engines(struct kfd_node *node) 1332 { 1333 /* If XGMI is not supported, all SDMA engines are PCIe */ 1334 if (!node->adev->gmc.xgmi.supported) 1335 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes; 1336 1337 return min(node->adev->sdma.num_instances/(int)node->kfd->num_nodes, 2); 1338 } 1339 1340 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *node) 1341 { 1342 /* After reserved for PCIe, the rest of engines are XGMI */ 1343 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes - 1344 kfd_get_num_sdma_engines(node); 1345 } 1346 1347 int kgd2kfd_check_and_lock_kfd(void) 1348 { 1349 mutex_lock(&kfd_processes_mutex); 1350 if (!hash_empty(kfd_processes_table) || kfd_is_locked()) { 1351 mutex_unlock(&kfd_processes_mutex); 1352 return -EBUSY; 1353 } 1354 1355 ++kfd_locked; 1356 mutex_unlock(&kfd_processes_mutex); 1357 1358 return 0; 1359 } 1360 1361 void kgd2kfd_unlock_kfd(void) 1362 { 1363 mutex_lock(&kfd_processes_mutex); 1364 --kfd_locked; 1365 mutex_unlock(&kfd_processes_mutex); 1366 } 1367 1368 #if defined(CONFIG_DEBUG_FS) 1369 1370 /* This function will send a package to HIQ to hang the HWS 1371 * which will trigger a GPU reset and bring the HWS back to normal state 1372 */ 1373 int kfd_debugfs_hang_hws(struct kfd_node *dev) 1374 { 1375 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1376 pr_err("HWS is not enabled"); 1377 return -EINVAL; 1378 } 1379 1380 return dqm_debugfs_hang_hws(dev->dqm); 1381 } 1382 1383 #endif 1384