1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/bsearch.h> 24 #include <linux/pci.h> 25 #include <linux/slab.h> 26 #include "kfd_priv.h" 27 #include "kfd_device_queue_manager.h" 28 #include "kfd_pm4_headers_vi.h" 29 #include "cwsr_trap_handler.h" 30 #include "kfd_iommu.h" 31 #include "amdgpu_amdkfd.h" 32 33 #define MQD_SIZE_ALIGNED 768 34 35 /* 36 * kfd_locked is used to lock the kfd driver during suspend or reset 37 * once locked, kfd driver will stop any further GPU execution. 38 * create process (open) will return -EAGAIN. 39 */ 40 static atomic_t kfd_locked = ATOMIC_INIT(0); 41 42 #ifdef KFD_SUPPORT_IOMMU_V2 43 static const struct kfd_device_info kaveri_device_info = { 44 .asic_family = CHIP_KAVERI, 45 .max_pasid_bits = 16, 46 /* max num of queues for KV.TODO should be a dynamic value */ 47 .max_no_of_hqd = 24, 48 .doorbell_size = 4, 49 .ih_ring_entry_size = 4 * sizeof(uint32_t), 50 .event_interrupt_class = &event_interrupt_class_cik, 51 .num_of_watch_points = 4, 52 .mqd_size_aligned = MQD_SIZE_ALIGNED, 53 .supports_cwsr = false, 54 .needs_iommu_device = true, 55 .needs_pci_atomics = false, 56 .num_sdma_engines = 2, 57 .num_sdma_queues_per_engine = 2, 58 }; 59 60 static const struct kfd_device_info carrizo_device_info = { 61 .asic_family = CHIP_CARRIZO, 62 .max_pasid_bits = 16, 63 /* max num of queues for CZ.TODO should be a dynamic value */ 64 .max_no_of_hqd = 24, 65 .doorbell_size = 4, 66 .ih_ring_entry_size = 4 * sizeof(uint32_t), 67 .event_interrupt_class = &event_interrupt_class_cik, 68 .num_of_watch_points = 4, 69 .mqd_size_aligned = MQD_SIZE_ALIGNED, 70 .supports_cwsr = true, 71 .needs_iommu_device = true, 72 .needs_pci_atomics = false, 73 .num_sdma_engines = 2, 74 .num_sdma_queues_per_engine = 2, 75 }; 76 77 static const struct kfd_device_info raven_device_info = { 78 .asic_family = CHIP_RAVEN, 79 .max_pasid_bits = 16, 80 .max_no_of_hqd = 24, 81 .doorbell_size = 8, 82 .ih_ring_entry_size = 8 * sizeof(uint32_t), 83 .event_interrupt_class = &event_interrupt_class_v9, 84 .num_of_watch_points = 4, 85 .mqd_size_aligned = MQD_SIZE_ALIGNED, 86 .supports_cwsr = true, 87 .needs_iommu_device = true, 88 .needs_pci_atomics = true, 89 .num_sdma_engines = 1, 90 .num_sdma_queues_per_engine = 2, 91 }; 92 #endif 93 94 static const struct kfd_device_info hawaii_device_info = { 95 .asic_family = CHIP_HAWAII, 96 .max_pasid_bits = 16, 97 /* max num of queues for KV.TODO should be a dynamic value */ 98 .max_no_of_hqd = 24, 99 .doorbell_size = 4, 100 .ih_ring_entry_size = 4 * sizeof(uint32_t), 101 .event_interrupt_class = &event_interrupt_class_cik, 102 .num_of_watch_points = 4, 103 .mqd_size_aligned = MQD_SIZE_ALIGNED, 104 .supports_cwsr = false, 105 .needs_iommu_device = false, 106 .needs_pci_atomics = false, 107 .num_sdma_engines = 2, 108 .num_sdma_queues_per_engine = 2, 109 }; 110 111 static const struct kfd_device_info tonga_device_info = { 112 .asic_family = CHIP_TONGA, 113 .max_pasid_bits = 16, 114 .max_no_of_hqd = 24, 115 .doorbell_size = 4, 116 .ih_ring_entry_size = 4 * sizeof(uint32_t), 117 .event_interrupt_class = &event_interrupt_class_cik, 118 .num_of_watch_points = 4, 119 .mqd_size_aligned = MQD_SIZE_ALIGNED, 120 .supports_cwsr = false, 121 .needs_iommu_device = false, 122 .needs_pci_atomics = true, 123 .num_sdma_engines = 2, 124 .num_sdma_queues_per_engine = 2, 125 }; 126 127 static const struct kfd_device_info fiji_device_info = { 128 .asic_family = CHIP_FIJI, 129 .max_pasid_bits = 16, 130 .max_no_of_hqd = 24, 131 .doorbell_size = 4, 132 .ih_ring_entry_size = 4 * sizeof(uint32_t), 133 .event_interrupt_class = &event_interrupt_class_cik, 134 .num_of_watch_points = 4, 135 .mqd_size_aligned = MQD_SIZE_ALIGNED, 136 .supports_cwsr = true, 137 .needs_iommu_device = false, 138 .needs_pci_atomics = true, 139 .num_sdma_engines = 2, 140 .num_sdma_queues_per_engine = 2, 141 }; 142 143 static const struct kfd_device_info fiji_vf_device_info = { 144 .asic_family = CHIP_FIJI, 145 .max_pasid_bits = 16, 146 .max_no_of_hqd = 24, 147 .doorbell_size = 4, 148 .ih_ring_entry_size = 4 * sizeof(uint32_t), 149 .event_interrupt_class = &event_interrupt_class_cik, 150 .num_of_watch_points = 4, 151 .mqd_size_aligned = MQD_SIZE_ALIGNED, 152 .supports_cwsr = true, 153 .needs_iommu_device = false, 154 .needs_pci_atomics = false, 155 .num_sdma_engines = 2, 156 .num_sdma_queues_per_engine = 2, 157 }; 158 159 160 static const struct kfd_device_info polaris10_device_info = { 161 .asic_family = CHIP_POLARIS10, 162 .max_pasid_bits = 16, 163 .max_no_of_hqd = 24, 164 .doorbell_size = 4, 165 .ih_ring_entry_size = 4 * sizeof(uint32_t), 166 .event_interrupt_class = &event_interrupt_class_cik, 167 .num_of_watch_points = 4, 168 .mqd_size_aligned = MQD_SIZE_ALIGNED, 169 .supports_cwsr = true, 170 .needs_iommu_device = false, 171 .needs_pci_atomics = true, 172 .num_sdma_engines = 2, 173 .num_sdma_queues_per_engine = 2, 174 }; 175 176 static const struct kfd_device_info polaris10_vf_device_info = { 177 .asic_family = CHIP_POLARIS10, 178 .max_pasid_bits = 16, 179 .max_no_of_hqd = 24, 180 .doorbell_size = 4, 181 .ih_ring_entry_size = 4 * sizeof(uint32_t), 182 .event_interrupt_class = &event_interrupt_class_cik, 183 .num_of_watch_points = 4, 184 .mqd_size_aligned = MQD_SIZE_ALIGNED, 185 .supports_cwsr = true, 186 .needs_iommu_device = false, 187 .needs_pci_atomics = false, 188 .num_sdma_engines = 2, 189 .num_sdma_queues_per_engine = 2, 190 }; 191 192 static const struct kfd_device_info polaris11_device_info = { 193 .asic_family = CHIP_POLARIS11, 194 .max_pasid_bits = 16, 195 .max_no_of_hqd = 24, 196 .doorbell_size = 4, 197 .ih_ring_entry_size = 4 * sizeof(uint32_t), 198 .event_interrupt_class = &event_interrupt_class_cik, 199 .num_of_watch_points = 4, 200 .mqd_size_aligned = MQD_SIZE_ALIGNED, 201 .supports_cwsr = true, 202 .needs_iommu_device = false, 203 .needs_pci_atomics = true, 204 .num_sdma_engines = 2, 205 .num_sdma_queues_per_engine = 2, 206 }; 207 208 static const struct kfd_device_info vega10_device_info = { 209 .asic_family = CHIP_VEGA10, 210 .max_pasid_bits = 16, 211 .max_no_of_hqd = 24, 212 .doorbell_size = 8, 213 .ih_ring_entry_size = 8 * sizeof(uint32_t), 214 .event_interrupt_class = &event_interrupt_class_v9, 215 .num_of_watch_points = 4, 216 .mqd_size_aligned = MQD_SIZE_ALIGNED, 217 .supports_cwsr = true, 218 .needs_iommu_device = false, 219 .needs_pci_atomics = false, 220 .num_sdma_engines = 2, 221 .num_sdma_queues_per_engine = 2, 222 }; 223 224 static const struct kfd_device_info vega10_vf_device_info = { 225 .asic_family = CHIP_VEGA10, 226 .max_pasid_bits = 16, 227 .max_no_of_hqd = 24, 228 .doorbell_size = 8, 229 .ih_ring_entry_size = 8 * sizeof(uint32_t), 230 .event_interrupt_class = &event_interrupt_class_v9, 231 .num_of_watch_points = 4, 232 .mqd_size_aligned = MQD_SIZE_ALIGNED, 233 .supports_cwsr = true, 234 .needs_iommu_device = false, 235 .needs_pci_atomics = false, 236 .num_sdma_engines = 2, 237 .num_sdma_queues_per_engine = 2, 238 }; 239 240 static const struct kfd_device_info vega20_device_info = { 241 .asic_family = CHIP_VEGA20, 242 .max_pasid_bits = 16, 243 .max_no_of_hqd = 24, 244 .doorbell_size = 8, 245 .ih_ring_entry_size = 8 * sizeof(uint32_t), 246 .event_interrupt_class = &event_interrupt_class_v9, 247 .num_of_watch_points = 4, 248 .mqd_size_aligned = MQD_SIZE_ALIGNED, 249 .supports_cwsr = true, 250 .needs_iommu_device = false, 251 .needs_pci_atomics = false, 252 .num_sdma_engines = 2, 253 .num_sdma_queues_per_engine = 8, 254 }; 255 256 struct kfd_deviceid { 257 unsigned short did; 258 const struct kfd_device_info *device_info; 259 }; 260 261 static const struct kfd_deviceid supported_devices[] = { 262 #ifdef KFD_SUPPORT_IOMMU_V2 263 { 0x1304, &kaveri_device_info }, /* Kaveri */ 264 { 0x1305, &kaveri_device_info }, /* Kaveri */ 265 { 0x1306, &kaveri_device_info }, /* Kaveri */ 266 { 0x1307, &kaveri_device_info }, /* Kaveri */ 267 { 0x1309, &kaveri_device_info }, /* Kaveri */ 268 { 0x130A, &kaveri_device_info }, /* Kaveri */ 269 { 0x130B, &kaveri_device_info }, /* Kaveri */ 270 { 0x130C, &kaveri_device_info }, /* Kaveri */ 271 { 0x130D, &kaveri_device_info }, /* Kaveri */ 272 { 0x130E, &kaveri_device_info }, /* Kaveri */ 273 { 0x130F, &kaveri_device_info }, /* Kaveri */ 274 { 0x1310, &kaveri_device_info }, /* Kaveri */ 275 { 0x1311, &kaveri_device_info }, /* Kaveri */ 276 { 0x1312, &kaveri_device_info }, /* Kaveri */ 277 { 0x1313, &kaveri_device_info }, /* Kaveri */ 278 { 0x1315, &kaveri_device_info }, /* Kaveri */ 279 { 0x1316, &kaveri_device_info }, /* Kaveri */ 280 { 0x1317, &kaveri_device_info }, /* Kaveri */ 281 { 0x1318, &kaveri_device_info }, /* Kaveri */ 282 { 0x131B, &kaveri_device_info }, /* Kaveri */ 283 { 0x131C, &kaveri_device_info }, /* Kaveri */ 284 { 0x131D, &kaveri_device_info }, /* Kaveri */ 285 { 0x9870, &carrizo_device_info }, /* Carrizo */ 286 { 0x9874, &carrizo_device_info }, /* Carrizo */ 287 { 0x9875, &carrizo_device_info }, /* Carrizo */ 288 { 0x9876, &carrizo_device_info }, /* Carrizo */ 289 { 0x9877, &carrizo_device_info }, /* Carrizo */ 290 { 0x15DD, &raven_device_info }, /* Raven */ 291 #endif 292 { 0x67A0, &hawaii_device_info }, /* Hawaii */ 293 { 0x67A1, &hawaii_device_info }, /* Hawaii */ 294 { 0x67A2, &hawaii_device_info }, /* Hawaii */ 295 { 0x67A8, &hawaii_device_info }, /* Hawaii */ 296 { 0x67A9, &hawaii_device_info }, /* Hawaii */ 297 { 0x67AA, &hawaii_device_info }, /* Hawaii */ 298 { 0x67B0, &hawaii_device_info }, /* Hawaii */ 299 { 0x67B1, &hawaii_device_info }, /* Hawaii */ 300 { 0x67B8, &hawaii_device_info }, /* Hawaii */ 301 { 0x67B9, &hawaii_device_info }, /* Hawaii */ 302 { 0x67BA, &hawaii_device_info }, /* Hawaii */ 303 { 0x67BE, &hawaii_device_info }, /* Hawaii */ 304 { 0x6920, &tonga_device_info }, /* Tonga */ 305 { 0x6921, &tonga_device_info }, /* Tonga */ 306 { 0x6928, &tonga_device_info }, /* Tonga */ 307 { 0x6929, &tonga_device_info }, /* Tonga */ 308 { 0x692B, &tonga_device_info }, /* Tonga */ 309 { 0x6938, &tonga_device_info }, /* Tonga */ 310 { 0x6939, &tonga_device_info }, /* Tonga */ 311 { 0x7300, &fiji_device_info }, /* Fiji */ 312 { 0x730F, &fiji_vf_device_info }, /* Fiji vf*/ 313 { 0x67C0, &polaris10_device_info }, /* Polaris10 */ 314 { 0x67C1, &polaris10_device_info }, /* Polaris10 */ 315 { 0x67C2, &polaris10_device_info }, /* Polaris10 */ 316 { 0x67C4, &polaris10_device_info }, /* Polaris10 */ 317 { 0x67C7, &polaris10_device_info }, /* Polaris10 */ 318 { 0x67C8, &polaris10_device_info }, /* Polaris10 */ 319 { 0x67C9, &polaris10_device_info }, /* Polaris10 */ 320 { 0x67CA, &polaris10_device_info }, /* Polaris10 */ 321 { 0x67CC, &polaris10_device_info }, /* Polaris10 */ 322 { 0x67CF, &polaris10_device_info }, /* Polaris10 */ 323 { 0x67D0, &polaris10_vf_device_info }, /* Polaris10 vf*/ 324 { 0x67DF, &polaris10_device_info }, /* Polaris10 */ 325 { 0x67E0, &polaris11_device_info }, /* Polaris11 */ 326 { 0x67E1, &polaris11_device_info }, /* Polaris11 */ 327 { 0x67E3, &polaris11_device_info }, /* Polaris11 */ 328 { 0x67E7, &polaris11_device_info }, /* Polaris11 */ 329 { 0x67E8, &polaris11_device_info }, /* Polaris11 */ 330 { 0x67E9, &polaris11_device_info }, /* Polaris11 */ 331 { 0x67EB, &polaris11_device_info }, /* Polaris11 */ 332 { 0x67EF, &polaris11_device_info }, /* Polaris11 */ 333 { 0x67FF, &polaris11_device_info }, /* Polaris11 */ 334 { 0x6860, &vega10_device_info }, /* Vega10 */ 335 { 0x6861, &vega10_device_info }, /* Vega10 */ 336 { 0x6862, &vega10_device_info }, /* Vega10 */ 337 { 0x6863, &vega10_device_info }, /* Vega10 */ 338 { 0x6864, &vega10_device_info }, /* Vega10 */ 339 { 0x6867, &vega10_device_info }, /* Vega10 */ 340 { 0x6868, &vega10_device_info }, /* Vega10 */ 341 { 0x686C, &vega10_vf_device_info }, /* Vega10 vf*/ 342 { 0x687F, &vega10_device_info }, /* Vega10 */ 343 { 0x66a0, &vega20_device_info }, /* Vega20 */ 344 { 0x66a1, &vega20_device_info }, /* Vega20 */ 345 { 0x66a2, &vega20_device_info }, /* Vega20 */ 346 { 0x66a3, &vega20_device_info }, /* Vega20 */ 347 { 0x66a7, &vega20_device_info }, /* Vega20 */ 348 { 0x66af, &vega20_device_info } /* Vega20 */ 349 }; 350 351 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 352 unsigned int chunk_size); 353 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 354 355 static int kfd_resume(struct kfd_dev *kfd); 356 357 static const struct kfd_device_info *lookup_device_info(unsigned short did) 358 { 359 size_t i; 360 361 for (i = 0; i < ARRAY_SIZE(supported_devices); i++) { 362 if (supported_devices[i].did == did) { 363 WARN_ON(!supported_devices[i].device_info); 364 return supported_devices[i].device_info; 365 } 366 } 367 368 dev_warn(kfd_device, "DID %04x is missing in supported_devices\n", 369 did); 370 371 return NULL; 372 } 373 374 struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, 375 struct pci_dev *pdev, const struct kfd2kgd_calls *f2g) 376 { 377 struct kfd_dev *kfd; 378 int ret; 379 const struct kfd_device_info *device_info = 380 lookup_device_info(pdev->device); 381 382 if (!device_info) { 383 dev_err(kfd_device, "kgd2kfd_probe failed\n"); 384 return NULL; 385 } 386 387 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 388 if (!kfd) 389 return NULL; 390 391 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 392 * 32 and 64-bit requests are possible and must be 393 * supported. 394 */ 395 ret = pci_enable_atomic_ops_to_root(pdev, 396 PCI_EXP_DEVCAP2_ATOMIC_COMP32 | 397 PCI_EXP_DEVCAP2_ATOMIC_COMP64); 398 if (device_info->needs_pci_atomics && ret < 0) { 399 dev_info(kfd_device, 400 "skipped device %x:%x, PCI rejects atomics\n", 401 pdev->vendor, pdev->device); 402 kfree(kfd); 403 return NULL; 404 } else if (!ret) 405 kfd->pci_atomic_requested = true; 406 407 kfd->kgd = kgd; 408 kfd->device_info = device_info; 409 kfd->pdev = pdev; 410 kfd->init_complete = false; 411 kfd->kfd2kgd = f2g; 412 413 mutex_init(&kfd->doorbell_mutex); 414 memset(&kfd->doorbell_available_index, 0, 415 sizeof(kfd->doorbell_available_index)); 416 417 return kfd; 418 } 419 420 static void kfd_cwsr_init(struct kfd_dev *kfd) 421 { 422 if (cwsr_enable && kfd->device_info->supports_cwsr) { 423 if (kfd->device_info->asic_family < CHIP_VEGA10) { 424 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE); 425 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 426 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 427 } else { 428 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE); 429 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 430 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 431 } 432 433 kfd->cwsr_enabled = true; 434 } 435 } 436 437 bool kgd2kfd_device_init(struct kfd_dev *kfd, 438 const struct kgd2kfd_shared_resources *gpu_resources) 439 { 440 unsigned int size; 441 442 kfd->mec_fw_version = kfd->kfd2kgd->get_fw_version(kfd->kgd, 443 KGD_ENGINE_MEC1); 444 kfd->sdma_fw_version = kfd->kfd2kgd->get_fw_version(kfd->kgd, 445 KGD_ENGINE_SDMA1); 446 kfd->shared_resources = *gpu_resources; 447 448 kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 449 kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 450 kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd 451 - kfd->vm_info.first_vmid_kfd + 1; 452 453 /* Verify module parameters regarding mapped process number*/ 454 if ((hws_max_conc_proc < 0) 455 || (hws_max_conc_proc > kfd->vm_info.vmid_num_kfd)) { 456 dev_err(kfd_device, 457 "hws_max_conc_proc %d must be between 0 and %d, use %d instead\n", 458 hws_max_conc_proc, kfd->vm_info.vmid_num_kfd, 459 kfd->vm_info.vmid_num_kfd); 460 kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd; 461 } else 462 kfd->max_proc_per_quantum = hws_max_conc_proc; 463 464 /* calculate max size of mqds needed for queues */ 465 size = max_num_of_queues_per_device * 466 kfd->device_info->mqd_size_aligned; 467 468 /* 469 * calculate max size of runlist packet. 470 * There can be only 2 packets at once 471 */ 472 size += (KFD_MAX_NUM_OF_PROCESSES * sizeof(struct pm4_mes_map_process) + 473 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 474 + sizeof(struct pm4_mes_runlist)) * 2; 475 476 /* Add size of HIQ & DIQ */ 477 size += KFD_KERNEL_QUEUE_SIZE * 2; 478 479 /* add another 512KB for all other allocations on gart (HPD, fences) */ 480 size += 512 * 1024; 481 482 if (amdgpu_amdkfd_alloc_gtt_mem( 483 kfd->kgd, size, &kfd->gtt_mem, 484 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 485 false)) { 486 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 487 goto out; 488 } 489 490 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 491 492 /* Initialize GTT sa with 512 byte chunk size */ 493 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 494 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 495 goto kfd_gtt_sa_init_error; 496 } 497 498 if (kfd_doorbell_init(kfd)) { 499 dev_err(kfd_device, 500 "Error initializing doorbell aperture\n"); 501 goto kfd_doorbell_error; 502 } 503 504 if (kfd->kfd2kgd->get_hive_id) 505 kfd->hive_id = kfd->kfd2kgd->get_hive_id(kfd->kgd); 506 507 if (kfd_topology_add_device(kfd)) { 508 dev_err(kfd_device, "Error adding device to topology\n"); 509 goto kfd_topology_add_device_error; 510 } 511 512 if (kfd_interrupt_init(kfd)) { 513 dev_err(kfd_device, "Error initializing interrupts\n"); 514 goto kfd_interrupt_error; 515 } 516 517 kfd->dqm = device_queue_manager_init(kfd); 518 if (!kfd->dqm) { 519 dev_err(kfd_device, "Error initializing queue manager\n"); 520 goto device_queue_manager_error; 521 } 522 523 if (kfd_iommu_device_init(kfd)) { 524 dev_err(kfd_device, "Error initializing iommuv2\n"); 525 goto device_iommu_error; 526 } 527 528 kfd_cwsr_init(kfd); 529 530 if (kfd_resume(kfd)) 531 goto kfd_resume_error; 532 533 kfd->dbgmgr = NULL; 534 535 kfd->init_complete = true; 536 dev_info(kfd_device, "added device %x:%x\n", kfd->pdev->vendor, 537 kfd->pdev->device); 538 539 pr_debug("Starting kfd with the following scheduling policy %d\n", 540 kfd->dqm->sched_policy); 541 542 goto out; 543 544 kfd_resume_error: 545 device_iommu_error: 546 device_queue_manager_uninit(kfd->dqm); 547 device_queue_manager_error: 548 kfd_interrupt_exit(kfd); 549 kfd_interrupt_error: 550 kfd_topology_remove_device(kfd); 551 kfd_topology_add_device_error: 552 kfd_doorbell_fini(kfd); 553 kfd_doorbell_error: 554 kfd_gtt_sa_fini(kfd); 555 kfd_gtt_sa_init_error: 556 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem); 557 dev_err(kfd_device, 558 "device %x:%x NOT added due to errors\n", 559 kfd->pdev->vendor, kfd->pdev->device); 560 out: 561 return kfd->init_complete; 562 } 563 564 void kgd2kfd_device_exit(struct kfd_dev *kfd) 565 { 566 if (kfd->init_complete) { 567 kgd2kfd_suspend(kfd); 568 device_queue_manager_uninit(kfd->dqm); 569 kfd_interrupt_exit(kfd); 570 kfd_topology_remove_device(kfd); 571 kfd_doorbell_fini(kfd); 572 kfd_gtt_sa_fini(kfd); 573 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem); 574 } 575 576 kfree(kfd); 577 } 578 579 int kgd2kfd_pre_reset(struct kfd_dev *kfd) 580 { 581 if (!kfd->init_complete) 582 return 0; 583 kgd2kfd_suspend(kfd); 584 585 /* hold dqm->lock to prevent further execution*/ 586 dqm_lock(kfd->dqm); 587 588 kfd_signal_reset_event(kfd); 589 return 0; 590 } 591 592 /* 593 * Fix me. KFD won't be able to resume existing process for now. 594 * We will keep all existing process in a evicted state and 595 * wait the process to be terminated. 596 */ 597 598 int kgd2kfd_post_reset(struct kfd_dev *kfd) 599 { 600 int ret, count; 601 602 if (!kfd->init_complete) 603 return 0; 604 605 dqm_unlock(kfd->dqm); 606 607 ret = kfd_resume(kfd); 608 if (ret) 609 return ret; 610 count = atomic_dec_return(&kfd_locked); 611 WARN_ONCE(count != 0, "KFD reset ref. error"); 612 return 0; 613 } 614 615 bool kfd_is_locked(void) 616 { 617 return (atomic_read(&kfd_locked) > 0); 618 } 619 620 void kgd2kfd_suspend(struct kfd_dev *kfd) 621 { 622 if (!kfd->init_complete) 623 return; 624 625 /* For first KFD device suspend all the KFD processes */ 626 if (atomic_inc_return(&kfd_locked) == 1) 627 kfd_suspend_all_processes(); 628 629 kfd->dqm->ops.stop(kfd->dqm); 630 631 kfd_iommu_suspend(kfd); 632 } 633 634 int kgd2kfd_resume(struct kfd_dev *kfd) 635 { 636 int ret, count; 637 638 if (!kfd->init_complete) 639 return 0; 640 641 ret = kfd_resume(kfd); 642 if (ret) 643 return ret; 644 645 count = atomic_dec_return(&kfd_locked); 646 WARN_ONCE(count < 0, "KFD suspend / resume ref. error"); 647 if (count == 0) 648 ret = kfd_resume_all_processes(); 649 650 return ret; 651 } 652 653 static int kfd_resume(struct kfd_dev *kfd) 654 { 655 int err = 0; 656 657 err = kfd_iommu_resume(kfd); 658 if (err) { 659 dev_err(kfd_device, 660 "Failed to resume IOMMU for device %x:%x\n", 661 kfd->pdev->vendor, kfd->pdev->device); 662 return err; 663 } 664 665 err = kfd->dqm->ops.start(kfd->dqm); 666 if (err) { 667 dev_err(kfd_device, 668 "Error starting queue manager for device %x:%x\n", 669 kfd->pdev->vendor, kfd->pdev->device); 670 goto dqm_start_error; 671 } 672 673 return err; 674 675 dqm_start_error: 676 kfd_iommu_suspend(kfd); 677 return err; 678 } 679 680 /* This is called directly from KGD at ISR. */ 681 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 682 { 683 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE]; 684 bool is_patched = false; 685 unsigned long flags; 686 687 if (!kfd->init_complete) 688 return; 689 690 if (kfd->device_info->ih_ring_entry_size > sizeof(patched_ihre)) { 691 dev_err_once(kfd_device, "Ring entry too small\n"); 692 return; 693 } 694 695 spin_lock_irqsave(&kfd->interrupt_lock, flags); 696 697 if (kfd->interrupts_active 698 && interrupt_is_wanted(kfd, ih_ring_entry, 699 patched_ihre, &is_patched) 700 && enqueue_ih_ring_entry(kfd, 701 is_patched ? patched_ihre : ih_ring_entry)) 702 queue_work(kfd->ih_wq, &kfd->interrupt_work); 703 704 spin_unlock_irqrestore(&kfd->interrupt_lock, flags); 705 } 706 707 int kgd2kfd_quiesce_mm(struct mm_struct *mm) 708 { 709 struct kfd_process *p; 710 int r; 711 712 /* Because we are called from arbitrary context (workqueue) as opposed 713 * to process context, kfd_process could attempt to exit while we are 714 * running so the lookup function increments the process ref count. 715 */ 716 p = kfd_lookup_process_by_mm(mm); 717 if (!p) 718 return -ESRCH; 719 720 r = kfd_process_evict_queues(p); 721 722 kfd_unref_process(p); 723 return r; 724 } 725 726 int kgd2kfd_resume_mm(struct mm_struct *mm) 727 { 728 struct kfd_process *p; 729 int r; 730 731 /* Because we are called from arbitrary context (workqueue) as opposed 732 * to process context, kfd_process could attempt to exit while we are 733 * running so the lookup function increments the process ref count. 734 */ 735 p = kfd_lookup_process_by_mm(mm); 736 if (!p) 737 return -ESRCH; 738 739 r = kfd_process_restore_queues(p); 740 741 kfd_unref_process(p); 742 return r; 743 } 744 745 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 746 * prepare for safe eviction of KFD BOs that belong to the specified 747 * process. 748 * 749 * @mm: mm_struct that identifies the specified KFD process 750 * @fence: eviction fence attached to KFD process BOs 751 * 752 */ 753 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 754 struct dma_fence *fence) 755 { 756 struct kfd_process *p; 757 unsigned long active_time; 758 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 759 760 if (!fence) 761 return -EINVAL; 762 763 if (dma_fence_is_signaled(fence)) 764 return 0; 765 766 p = kfd_lookup_process_by_mm(mm); 767 if (!p) 768 return -ENODEV; 769 770 if (fence->seqno == p->last_eviction_seqno) 771 goto out; 772 773 p->last_eviction_seqno = fence->seqno; 774 775 /* Avoid KFD process starvation. Wait for at least 776 * PROCESS_ACTIVE_TIME_MS before evicting the process again 777 */ 778 active_time = get_jiffies_64() - p->last_restore_timestamp; 779 if (delay_jiffies > active_time) 780 delay_jiffies -= active_time; 781 else 782 delay_jiffies = 0; 783 784 /* During process initialization eviction_work.dwork is initialized 785 * to kfd_evict_bo_worker 786 */ 787 schedule_delayed_work(&p->eviction_work, delay_jiffies); 788 out: 789 kfd_unref_process(p); 790 return 0; 791 } 792 793 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 794 unsigned int chunk_size) 795 { 796 unsigned int num_of_longs; 797 798 if (WARN_ON(buf_size < chunk_size)) 799 return -EINVAL; 800 if (WARN_ON(buf_size == 0)) 801 return -EINVAL; 802 if (WARN_ON(chunk_size == 0)) 803 return -EINVAL; 804 805 kfd->gtt_sa_chunk_size = chunk_size; 806 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 807 808 num_of_longs = (kfd->gtt_sa_num_of_chunks + BITS_PER_LONG - 1) / 809 BITS_PER_LONG; 810 811 kfd->gtt_sa_bitmap = kcalloc(num_of_longs, sizeof(long), GFP_KERNEL); 812 813 if (!kfd->gtt_sa_bitmap) 814 return -ENOMEM; 815 816 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 817 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 818 819 mutex_init(&kfd->gtt_sa_lock); 820 821 return 0; 822 823 } 824 825 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 826 { 827 mutex_destroy(&kfd->gtt_sa_lock); 828 kfree(kfd->gtt_sa_bitmap); 829 } 830 831 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 832 unsigned int bit_num, 833 unsigned int chunk_size) 834 { 835 return start_addr + bit_num * chunk_size; 836 } 837 838 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 839 unsigned int bit_num, 840 unsigned int chunk_size) 841 { 842 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 843 } 844 845 int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size, 846 struct kfd_mem_obj **mem_obj) 847 { 848 unsigned int found, start_search, cur_size; 849 850 if (size == 0) 851 return -EINVAL; 852 853 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 854 return -ENOMEM; 855 856 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 857 if (!(*mem_obj)) 858 return -ENOMEM; 859 860 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 861 862 start_search = 0; 863 864 mutex_lock(&kfd->gtt_sa_lock); 865 866 kfd_gtt_restart_search: 867 /* Find the first chunk that is free */ 868 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 869 kfd->gtt_sa_num_of_chunks, 870 start_search); 871 872 pr_debug("Found = %d\n", found); 873 874 /* If there wasn't any free chunk, bail out */ 875 if (found == kfd->gtt_sa_num_of_chunks) 876 goto kfd_gtt_no_free_chunk; 877 878 /* Update fields of mem_obj */ 879 (*mem_obj)->range_start = found; 880 (*mem_obj)->range_end = found; 881 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 882 kfd->gtt_start_gpu_addr, 883 found, 884 kfd->gtt_sa_chunk_size); 885 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 886 kfd->gtt_start_cpu_ptr, 887 found, 888 kfd->gtt_sa_chunk_size); 889 890 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 891 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 892 893 /* If we need only one chunk, mark it as allocated and get out */ 894 if (size <= kfd->gtt_sa_chunk_size) { 895 pr_debug("Single bit\n"); 896 set_bit(found, kfd->gtt_sa_bitmap); 897 goto kfd_gtt_out; 898 } 899 900 /* Otherwise, try to see if we have enough contiguous chunks */ 901 cur_size = size - kfd->gtt_sa_chunk_size; 902 do { 903 (*mem_obj)->range_end = 904 find_next_zero_bit(kfd->gtt_sa_bitmap, 905 kfd->gtt_sa_num_of_chunks, ++found); 906 /* 907 * If next free chunk is not contiguous than we need to 908 * restart our search from the last free chunk we found (which 909 * wasn't contiguous to the previous ones 910 */ 911 if ((*mem_obj)->range_end != found) { 912 start_search = found; 913 goto kfd_gtt_restart_search; 914 } 915 916 /* 917 * If we reached end of buffer, bail out with error 918 */ 919 if (found == kfd->gtt_sa_num_of_chunks) 920 goto kfd_gtt_no_free_chunk; 921 922 /* Check if we don't need another chunk */ 923 if (cur_size <= kfd->gtt_sa_chunk_size) 924 cur_size = 0; 925 else 926 cur_size -= kfd->gtt_sa_chunk_size; 927 928 } while (cur_size > 0); 929 930 pr_debug("range_start = %d, range_end = %d\n", 931 (*mem_obj)->range_start, (*mem_obj)->range_end); 932 933 /* Mark the chunks as allocated */ 934 for (found = (*mem_obj)->range_start; 935 found <= (*mem_obj)->range_end; 936 found++) 937 set_bit(found, kfd->gtt_sa_bitmap); 938 939 kfd_gtt_out: 940 mutex_unlock(&kfd->gtt_sa_lock); 941 return 0; 942 943 kfd_gtt_no_free_chunk: 944 pr_debug("Allocation failed with mem_obj = %p\n", mem_obj); 945 mutex_unlock(&kfd->gtt_sa_lock); 946 kfree(mem_obj); 947 return -ENOMEM; 948 } 949 950 int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj) 951 { 952 unsigned int bit; 953 954 /* Act like kfree when trying to free a NULL object */ 955 if (!mem_obj) 956 return 0; 957 958 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 959 mem_obj, mem_obj->range_start, mem_obj->range_end); 960 961 mutex_lock(&kfd->gtt_sa_lock); 962 963 /* Mark the chunks as free */ 964 for (bit = mem_obj->range_start; 965 bit <= mem_obj->range_end; 966 bit++) 967 clear_bit(bit, kfd->gtt_sa_bitmap); 968 969 mutex_unlock(&kfd->gtt_sa_lock); 970 971 kfree(mem_obj); 972 return 0; 973 } 974 975 #if defined(CONFIG_DEBUG_FS) 976 977 /* This function will send a package to HIQ to hang the HWS 978 * which will trigger a GPU reset and bring the HWS back to normal state 979 */ 980 int kfd_debugfs_hang_hws(struct kfd_dev *dev) 981 { 982 int r = 0; 983 984 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 985 pr_err("HWS is not enabled"); 986 return -EINVAL; 987 } 988 989 r = pm_debugfs_hang_hws(&dev->dqm->packets); 990 if (!r) 991 r = dqm_debugfs_execute_queues(dev->dqm); 992 993 return r; 994 } 995 996 #endif 997