1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/bsearch.h> 24 #include <linux/pci.h> 25 #include <linux/slab.h> 26 #include "kfd_priv.h" 27 #include "kfd_device_queue_manager.h" 28 #include "kfd_pm4_headers_vi.h" 29 #include "cwsr_trap_handler.h" 30 #include "kfd_iommu.h" 31 #include "amdgpu_amdkfd.h" 32 33 #define MQD_SIZE_ALIGNED 768 34 35 /* 36 * kfd_locked is used to lock the kfd driver during suspend or reset 37 * once locked, kfd driver will stop any further GPU execution. 38 * create process (open) will return -EAGAIN. 39 */ 40 static atomic_t kfd_locked = ATOMIC_INIT(0); 41 42 #ifdef KFD_SUPPORT_IOMMU_V2 43 static const struct kfd_device_info kaveri_device_info = { 44 .asic_family = CHIP_KAVERI, 45 .max_pasid_bits = 16, 46 /* max num of queues for KV.TODO should be a dynamic value */ 47 .max_no_of_hqd = 24, 48 .doorbell_size = 4, 49 .ih_ring_entry_size = 4 * sizeof(uint32_t), 50 .event_interrupt_class = &event_interrupt_class_cik, 51 .num_of_watch_points = 4, 52 .mqd_size_aligned = MQD_SIZE_ALIGNED, 53 .supports_cwsr = false, 54 .needs_iommu_device = true, 55 .needs_pci_atomics = false, 56 .num_sdma_engines = 2, 57 .num_sdma_queues_per_engine = 2, 58 }; 59 60 static const struct kfd_device_info carrizo_device_info = { 61 .asic_family = CHIP_CARRIZO, 62 .max_pasid_bits = 16, 63 /* max num of queues for CZ.TODO should be a dynamic value */ 64 .max_no_of_hqd = 24, 65 .doorbell_size = 4, 66 .ih_ring_entry_size = 4 * sizeof(uint32_t), 67 .event_interrupt_class = &event_interrupt_class_cik, 68 .num_of_watch_points = 4, 69 .mqd_size_aligned = MQD_SIZE_ALIGNED, 70 .supports_cwsr = true, 71 .needs_iommu_device = true, 72 .needs_pci_atomics = false, 73 .num_sdma_engines = 2, 74 .num_sdma_queues_per_engine = 2, 75 }; 76 77 static const struct kfd_device_info raven_device_info = { 78 .asic_family = CHIP_RAVEN, 79 .max_pasid_bits = 16, 80 .max_no_of_hqd = 24, 81 .doorbell_size = 8, 82 .ih_ring_entry_size = 8 * sizeof(uint32_t), 83 .event_interrupt_class = &event_interrupt_class_v9, 84 .num_of_watch_points = 4, 85 .mqd_size_aligned = MQD_SIZE_ALIGNED, 86 .supports_cwsr = true, 87 .needs_iommu_device = true, 88 .needs_pci_atomics = true, 89 .num_sdma_engines = 1, 90 .num_sdma_queues_per_engine = 2, 91 }; 92 #endif 93 94 static const struct kfd_device_info hawaii_device_info = { 95 .asic_family = CHIP_HAWAII, 96 .max_pasid_bits = 16, 97 /* max num of queues for KV.TODO should be a dynamic value */ 98 .max_no_of_hqd = 24, 99 .doorbell_size = 4, 100 .ih_ring_entry_size = 4 * sizeof(uint32_t), 101 .event_interrupt_class = &event_interrupt_class_cik, 102 .num_of_watch_points = 4, 103 .mqd_size_aligned = MQD_SIZE_ALIGNED, 104 .supports_cwsr = false, 105 .needs_iommu_device = false, 106 .needs_pci_atomics = false, 107 .num_sdma_engines = 2, 108 .num_sdma_queues_per_engine = 2, 109 }; 110 111 static const struct kfd_device_info tonga_device_info = { 112 .asic_family = CHIP_TONGA, 113 .max_pasid_bits = 16, 114 .max_no_of_hqd = 24, 115 .doorbell_size = 4, 116 .ih_ring_entry_size = 4 * sizeof(uint32_t), 117 .event_interrupt_class = &event_interrupt_class_cik, 118 .num_of_watch_points = 4, 119 .mqd_size_aligned = MQD_SIZE_ALIGNED, 120 .supports_cwsr = false, 121 .needs_iommu_device = false, 122 .needs_pci_atomics = true, 123 .num_sdma_engines = 2, 124 .num_sdma_queues_per_engine = 2, 125 }; 126 127 static const struct kfd_device_info fiji_device_info = { 128 .asic_family = CHIP_FIJI, 129 .max_pasid_bits = 16, 130 .max_no_of_hqd = 24, 131 .doorbell_size = 4, 132 .ih_ring_entry_size = 4 * sizeof(uint32_t), 133 .event_interrupt_class = &event_interrupt_class_cik, 134 .num_of_watch_points = 4, 135 .mqd_size_aligned = MQD_SIZE_ALIGNED, 136 .supports_cwsr = true, 137 .needs_iommu_device = false, 138 .needs_pci_atomics = true, 139 .num_sdma_engines = 2, 140 .num_sdma_queues_per_engine = 2, 141 }; 142 143 static const struct kfd_device_info fiji_vf_device_info = { 144 .asic_family = CHIP_FIJI, 145 .max_pasid_bits = 16, 146 .max_no_of_hqd = 24, 147 .doorbell_size = 4, 148 .ih_ring_entry_size = 4 * sizeof(uint32_t), 149 .event_interrupt_class = &event_interrupt_class_cik, 150 .num_of_watch_points = 4, 151 .mqd_size_aligned = MQD_SIZE_ALIGNED, 152 .supports_cwsr = true, 153 .needs_iommu_device = false, 154 .needs_pci_atomics = false, 155 .num_sdma_engines = 2, 156 .num_sdma_queues_per_engine = 2, 157 }; 158 159 160 static const struct kfd_device_info polaris10_device_info = { 161 .asic_family = CHIP_POLARIS10, 162 .max_pasid_bits = 16, 163 .max_no_of_hqd = 24, 164 .doorbell_size = 4, 165 .ih_ring_entry_size = 4 * sizeof(uint32_t), 166 .event_interrupt_class = &event_interrupt_class_cik, 167 .num_of_watch_points = 4, 168 .mqd_size_aligned = MQD_SIZE_ALIGNED, 169 .supports_cwsr = true, 170 .needs_iommu_device = false, 171 .needs_pci_atomics = true, 172 .num_sdma_engines = 2, 173 .num_sdma_queues_per_engine = 2, 174 }; 175 176 static const struct kfd_device_info polaris10_vf_device_info = { 177 .asic_family = CHIP_POLARIS10, 178 .max_pasid_bits = 16, 179 .max_no_of_hqd = 24, 180 .doorbell_size = 4, 181 .ih_ring_entry_size = 4 * sizeof(uint32_t), 182 .event_interrupt_class = &event_interrupt_class_cik, 183 .num_of_watch_points = 4, 184 .mqd_size_aligned = MQD_SIZE_ALIGNED, 185 .supports_cwsr = true, 186 .needs_iommu_device = false, 187 .needs_pci_atomics = false, 188 .num_sdma_engines = 2, 189 .num_sdma_queues_per_engine = 2, 190 }; 191 192 static const struct kfd_device_info polaris11_device_info = { 193 .asic_family = CHIP_POLARIS11, 194 .max_pasid_bits = 16, 195 .max_no_of_hqd = 24, 196 .doorbell_size = 4, 197 .ih_ring_entry_size = 4 * sizeof(uint32_t), 198 .event_interrupt_class = &event_interrupt_class_cik, 199 .num_of_watch_points = 4, 200 .mqd_size_aligned = MQD_SIZE_ALIGNED, 201 .supports_cwsr = true, 202 .needs_iommu_device = false, 203 .needs_pci_atomics = true, 204 .num_sdma_engines = 2, 205 .num_sdma_queues_per_engine = 2, 206 }; 207 208 static const struct kfd_device_info polaris12_device_info = { 209 .asic_family = CHIP_POLARIS12, 210 .max_pasid_bits = 16, 211 .max_no_of_hqd = 24, 212 .doorbell_size = 4, 213 .ih_ring_entry_size = 4 * sizeof(uint32_t), 214 .event_interrupt_class = &event_interrupt_class_cik, 215 .num_of_watch_points = 4, 216 .mqd_size_aligned = MQD_SIZE_ALIGNED, 217 .supports_cwsr = true, 218 .needs_iommu_device = false, 219 .needs_pci_atomics = true, 220 .num_sdma_engines = 2, 221 .num_sdma_queues_per_engine = 2, 222 }; 223 224 static const struct kfd_device_info vega10_device_info = { 225 .asic_family = CHIP_VEGA10, 226 .max_pasid_bits = 16, 227 .max_no_of_hqd = 24, 228 .doorbell_size = 8, 229 .ih_ring_entry_size = 8 * sizeof(uint32_t), 230 .event_interrupt_class = &event_interrupt_class_v9, 231 .num_of_watch_points = 4, 232 .mqd_size_aligned = MQD_SIZE_ALIGNED, 233 .supports_cwsr = true, 234 .needs_iommu_device = false, 235 .needs_pci_atomics = false, 236 .num_sdma_engines = 2, 237 .num_sdma_queues_per_engine = 2, 238 }; 239 240 static const struct kfd_device_info vega10_vf_device_info = { 241 .asic_family = CHIP_VEGA10, 242 .max_pasid_bits = 16, 243 .max_no_of_hqd = 24, 244 .doorbell_size = 8, 245 .ih_ring_entry_size = 8 * sizeof(uint32_t), 246 .event_interrupt_class = &event_interrupt_class_v9, 247 .num_of_watch_points = 4, 248 .mqd_size_aligned = MQD_SIZE_ALIGNED, 249 .supports_cwsr = true, 250 .needs_iommu_device = false, 251 .needs_pci_atomics = false, 252 .num_sdma_engines = 2, 253 .num_sdma_queues_per_engine = 2, 254 }; 255 256 static const struct kfd_device_info vega12_device_info = { 257 .asic_family = CHIP_VEGA12, 258 .max_pasid_bits = 16, 259 .max_no_of_hqd = 24, 260 .doorbell_size = 8, 261 .ih_ring_entry_size = 8 * sizeof(uint32_t), 262 .event_interrupt_class = &event_interrupt_class_v9, 263 .num_of_watch_points = 4, 264 .mqd_size_aligned = MQD_SIZE_ALIGNED, 265 .supports_cwsr = true, 266 .needs_iommu_device = false, 267 .needs_pci_atomics = false, 268 .num_sdma_engines = 2, 269 .num_sdma_queues_per_engine = 2, 270 }; 271 272 static const struct kfd_device_info vega20_device_info = { 273 .asic_family = CHIP_VEGA20, 274 .max_pasid_bits = 16, 275 .max_no_of_hqd = 24, 276 .doorbell_size = 8, 277 .ih_ring_entry_size = 8 * sizeof(uint32_t), 278 .event_interrupt_class = &event_interrupt_class_v9, 279 .num_of_watch_points = 4, 280 .mqd_size_aligned = MQD_SIZE_ALIGNED, 281 .supports_cwsr = true, 282 .needs_iommu_device = false, 283 .needs_pci_atomics = false, 284 .num_sdma_engines = 2, 285 .num_sdma_queues_per_engine = 8, 286 }; 287 288 struct kfd_deviceid { 289 unsigned short did; 290 const struct kfd_device_info *device_info; 291 }; 292 293 static const struct kfd_deviceid supported_devices[] = { 294 #ifdef KFD_SUPPORT_IOMMU_V2 295 { 0x1304, &kaveri_device_info }, /* Kaveri */ 296 { 0x1305, &kaveri_device_info }, /* Kaveri */ 297 { 0x1306, &kaveri_device_info }, /* Kaveri */ 298 { 0x1307, &kaveri_device_info }, /* Kaveri */ 299 { 0x1309, &kaveri_device_info }, /* Kaveri */ 300 { 0x130A, &kaveri_device_info }, /* Kaveri */ 301 { 0x130B, &kaveri_device_info }, /* Kaveri */ 302 { 0x130C, &kaveri_device_info }, /* Kaveri */ 303 { 0x130D, &kaveri_device_info }, /* Kaveri */ 304 { 0x130E, &kaveri_device_info }, /* Kaveri */ 305 { 0x130F, &kaveri_device_info }, /* Kaveri */ 306 { 0x1310, &kaveri_device_info }, /* Kaveri */ 307 { 0x1311, &kaveri_device_info }, /* Kaveri */ 308 { 0x1312, &kaveri_device_info }, /* Kaveri */ 309 { 0x1313, &kaveri_device_info }, /* Kaveri */ 310 { 0x1315, &kaveri_device_info }, /* Kaveri */ 311 { 0x1316, &kaveri_device_info }, /* Kaveri */ 312 { 0x1317, &kaveri_device_info }, /* Kaveri */ 313 { 0x1318, &kaveri_device_info }, /* Kaveri */ 314 { 0x131B, &kaveri_device_info }, /* Kaveri */ 315 { 0x131C, &kaveri_device_info }, /* Kaveri */ 316 { 0x131D, &kaveri_device_info }, /* Kaveri */ 317 { 0x9870, &carrizo_device_info }, /* Carrizo */ 318 { 0x9874, &carrizo_device_info }, /* Carrizo */ 319 { 0x9875, &carrizo_device_info }, /* Carrizo */ 320 { 0x9876, &carrizo_device_info }, /* Carrizo */ 321 { 0x9877, &carrizo_device_info }, /* Carrizo */ 322 { 0x15DD, &raven_device_info }, /* Raven */ 323 { 0x15D8, &raven_device_info }, /* Raven */ 324 #endif 325 { 0x67A0, &hawaii_device_info }, /* Hawaii */ 326 { 0x67A1, &hawaii_device_info }, /* Hawaii */ 327 { 0x67A2, &hawaii_device_info }, /* Hawaii */ 328 { 0x67A8, &hawaii_device_info }, /* Hawaii */ 329 { 0x67A9, &hawaii_device_info }, /* Hawaii */ 330 { 0x67AA, &hawaii_device_info }, /* Hawaii */ 331 { 0x67B0, &hawaii_device_info }, /* Hawaii */ 332 { 0x67B1, &hawaii_device_info }, /* Hawaii */ 333 { 0x67B8, &hawaii_device_info }, /* Hawaii */ 334 { 0x67B9, &hawaii_device_info }, /* Hawaii */ 335 { 0x67BA, &hawaii_device_info }, /* Hawaii */ 336 { 0x67BE, &hawaii_device_info }, /* Hawaii */ 337 { 0x6920, &tonga_device_info }, /* Tonga */ 338 { 0x6921, &tonga_device_info }, /* Tonga */ 339 { 0x6928, &tonga_device_info }, /* Tonga */ 340 { 0x6929, &tonga_device_info }, /* Tonga */ 341 { 0x692B, &tonga_device_info }, /* Tonga */ 342 { 0x6938, &tonga_device_info }, /* Tonga */ 343 { 0x6939, &tonga_device_info }, /* Tonga */ 344 { 0x7300, &fiji_device_info }, /* Fiji */ 345 { 0x730F, &fiji_vf_device_info }, /* Fiji vf*/ 346 { 0x67C0, &polaris10_device_info }, /* Polaris10 */ 347 { 0x67C1, &polaris10_device_info }, /* Polaris10 */ 348 { 0x67C2, &polaris10_device_info }, /* Polaris10 */ 349 { 0x67C4, &polaris10_device_info }, /* Polaris10 */ 350 { 0x67C7, &polaris10_device_info }, /* Polaris10 */ 351 { 0x67C8, &polaris10_device_info }, /* Polaris10 */ 352 { 0x67C9, &polaris10_device_info }, /* Polaris10 */ 353 { 0x67CA, &polaris10_device_info }, /* Polaris10 */ 354 { 0x67CC, &polaris10_device_info }, /* Polaris10 */ 355 { 0x67CF, &polaris10_device_info }, /* Polaris10 */ 356 { 0x67D0, &polaris10_vf_device_info }, /* Polaris10 vf*/ 357 { 0x67DF, &polaris10_device_info }, /* Polaris10 */ 358 { 0x6FDF, &polaris10_device_info }, /* Polaris10 */ 359 { 0x67E0, &polaris11_device_info }, /* Polaris11 */ 360 { 0x67E1, &polaris11_device_info }, /* Polaris11 */ 361 { 0x67E3, &polaris11_device_info }, /* Polaris11 */ 362 { 0x67E7, &polaris11_device_info }, /* Polaris11 */ 363 { 0x67E8, &polaris11_device_info }, /* Polaris11 */ 364 { 0x67E9, &polaris11_device_info }, /* Polaris11 */ 365 { 0x67EB, &polaris11_device_info }, /* Polaris11 */ 366 { 0x67EF, &polaris11_device_info }, /* Polaris11 */ 367 { 0x67FF, &polaris11_device_info }, /* Polaris11 */ 368 { 0x6980, &polaris12_device_info }, /* Polaris12 */ 369 { 0x6981, &polaris12_device_info }, /* Polaris12 */ 370 { 0x6985, &polaris12_device_info }, /* Polaris12 */ 371 { 0x6986, &polaris12_device_info }, /* Polaris12 */ 372 { 0x6987, &polaris12_device_info }, /* Polaris12 */ 373 { 0x6995, &polaris12_device_info }, /* Polaris12 */ 374 { 0x6997, &polaris12_device_info }, /* Polaris12 */ 375 { 0x699F, &polaris12_device_info }, /* Polaris12 */ 376 { 0x6860, &vega10_device_info }, /* Vega10 */ 377 { 0x6861, &vega10_device_info }, /* Vega10 */ 378 { 0x6862, &vega10_device_info }, /* Vega10 */ 379 { 0x6863, &vega10_device_info }, /* Vega10 */ 380 { 0x6864, &vega10_device_info }, /* Vega10 */ 381 { 0x6867, &vega10_device_info }, /* Vega10 */ 382 { 0x6868, &vega10_device_info }, /* Vega10 */ 383 { 0x6869, &vega10_device_info }, /* Vega10 */ 384 { 0x686A, &vega10_device_info }, /* Vega10 */ 385 { 0x686B, &vega10_device_info }, /* Vega10 */ 386 { 0x686C, &vega10_vf_device_info }, /* Vega10 vf*/ 387 { 0x686D, &vega10_device_info }, /* Vega10 */ 388 { 0x686E, &vega10_device_info }, /* Vega10 */ 389 { 0x686F, &vega10_device_info }, /* Vega10 */ 390 { 0x687F, &vega10_device_info }, /* Vega10 */ 391 { 0x69A0, &vega12_device_info }, /* Vega12 */ 392 { 0x69A1, &vega12_device_info }, /* Vega12 */ 393 { 0x69A2, &vega12_device_info }, /* Vega12 */ 394 { 0x69A3, &vega12_device_info }, /* Vega12 */ 395 { 0x69AF, &vega12_device_info }, /* Vega12 */ 396 { 0x66a0, &vega20_device_info }, /* Vega20 */ 397 { 0x66a1, &vega20_device_info }, /* Vega20 */ 398 { 0x66a2, &vega20_device_info }, /* Vega20 */ 399 { 0x66a3, &vega20_device_info }, /* Vega20 */ 400 { 0x66a4, &vega20_device_info }, /* Vega20 */ 401 { 0x66a7, &vega20_device_info }, /* Vega20 */ 402 { 0x66af, &vega20_device_info } /* Vega20 */ 403 }; 404 405 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 406 unsigned int chunk_size); 407 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 408 409 static int kfd_resume(struct kfd_dev *kfd); 410 411 static const struct kfd_device_info *lookup_device_info(unsigned short did) 412 { 413 size_t i; 414 415 for (i = 0; i < ARRAY_SIZE(supported_devices); i++) { 416 if (supported_devices[i].did == did) { 417 WARN_ON(!supported_devices[i].device_info); 418 return supported_devices[i].device_info; 419 } 420 } 421 422 dev_warn(kfd_device, "DID %04x is missing in supported_devices\n", 423 did); 424 425 return NULL; 426 } 427 428 struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, 429 struct pci_dev *pdev, const struct kfd2kgd_calls *f2g) 430 { 431 struct kfd_dev *kfd; 432 int ret; 433 const struct kfd_device_info *device_info = 434 lookup_device_info(pdev->device); 435 436 if (!device_info) { 437 dev_err(kfd_device, "kgd2kfd_probe failed\n"); 438 return NULL; 439 } 440 441 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 442 if (!kfd) 443 return NULL; 444 445 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 446 * 32 and 64-bit requests are possible and must be 447 * supported. 448 */ 449 ret = pci_enable_atomic_ops_to_root(pdev, 450 PCI_EXP_DEVCAP2_ATOMIC_COMP32 | 451 PCI_EXP_DEVCAP2_ATOMIC_COMP64); 452 if (device_info->needs_pci_atomics && ret < 0) { 453 dev_info(kfd_device, 454 "skipped device %x:%x, PCI rejects atomics\n", 455 pdev->vendor, pdev->device); 456 kfree(kfd); 457 return NULL; 458 } else if (!ret) 459 kfd->pci_atomic_requested = true; 460 461 kfd->kgd = kgd; 462 kfd->device_info = device_info; 463 kfd->pdev = pdev; 464 kfd->init_complete = false; 465 kfd->kfd2kgd = f2g; 466 atomic_set(&kfd->compute_profile, 0); 467 468 mutex_init(&kfd->doorbell_mutex); 469 memset(&kfd->doorbell_available_index, 0, 470 sizeof(kfd->doorbell_available_index)); 471 472 atomic_set(&kfd->sram_ecc_flag, 0); 473 474 return kfd; 475 } 476 477 static void kfd_cwsr_init(struct kfd_dev *kfd) 478 { 479 if (cwsr_enable && kfd->device_info->supports_cwsr) { 480 if (kfd->device_info->asic_family < CHIP_VEGA10) { 481 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE); 482 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 483 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 484 } else { 485 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE); 486 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 487 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 488 } 489 490 kfd->cwsr_enabled = true; 491 } 492 } 493 494 bool kgd2kfd_device_init(struct kfd_dev *kfd, 495 const struct kgd2kfd_shared_resources *gpu_resources) 496 { 497 unsigned int size; 498 499 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd, 500 KGD_ENGINE_MEC1); 501 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd, 502 KGD_ENGINE_SDMA1); 503 kfd->shared_resources = *gpu_resources; 504 505 kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 506 kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 507 kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd 508 - kfd->vm_info.first_vmid_kfd + 1; 509 510 /* Verify module parameters regarding mapped process number*/ 511 if ((hws_max_conc_proc < 0) 512 || (hws_max_conc_proc > kfd->vm_info.vmid_num_kfd)) { 513 dev_err(kfd_device, 514 "hws_max_conc_proc %d must be between 0 and %d, use %d instead\n", 515 hws_max_conc_proc, kfd->vm_info.vmid_num_kfd, 516 kfd->vm_info.vmid_num_kfd); 517 kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd; 518 } else 519 kfd->max_proc_per_quantum = hws_max_conc_proc; 520 521 /* calculate max size of mqds needed for queues */ 522 size = max_num_of_queues_per_device * 523 kfd->device_info->mqd_size_aligned; 524 525 /* 526 * calculate max size of runlist packet. 527 * There can be only 2 packets at once 528 */ 529 size += (KFD_MAX_NUM_OF_PROCESSES * sizeof(struct pm4_mes_map_process) + 530 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 531 + sizeof(struct pm4_mes_runlist)) * 2; 532 533 /* Add size of HIQ & DIQ */ 534 size += KFD_KERNEL_QUEUE_SIZE * 2; 535 536 /* add another 512KB for all other allocations on gart (HPD, fences) */ 537 size += 512 * 1024; 538 539 if (amdgpu_amdkfd_alloc_gtt_mem( 540 kfd->kgd, size, &kfd->gtt_mem, 541 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 542 false)) { 543 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 544 goto out; 545 } 546 547 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 548 549 /* Initialize GTT sa with 512 byte chunk size */ 550 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 551 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 552 goto kfd_gtt_sa_init_error; 553 } 554 555 if (kfd_doorbell_init(kfd)) { 556 dev_err(kfd_device, 557 "Error initializing doorbell aperture\n"); 558 goto kfd_doorbell_error; 559 } 560 561 if (kfd->kfd2kgd->get_hive_id) 562 kfd->hive_id = kfd->kfd2kgd->get_hive_id(kfd->kgd); 563 564 if (kfd_topology_add_device(kfd)) { 565 dev_err(kfd_device, "Error adding device to topology\n"); 566 goto kfd_topology_add_device_error; 567 } 568 569 if (kfd_interrupt_init(kfd)) { 570 dev_err(kfd_device, "Error initializing interrupts\n"); 571 goto kfd_interrupt_error; 572 } 573 574 kfd->dqm = device_queue_manager_init(kfd); 575 if (!kfd->dqm) { 576 dev_err(kfd_device, "Error initializing queue manager\n"); 577 goto device_queue_manager_error; 578 } 579 580 if (kfd_iommu_device_init(kfd)) { 581 dev_err(kfd_device, "Error initializing iommuv2\n"); 582 goto device_iommu_error; 583 } 584 585 kfd_cwsr_init(kfd); 586 587 if (kfd_resume(kfd)) 588 goto kfd_resume_error; 589 590 kfd->dbgmgr = NULL; 591 592 kfd->init_complete = true; 593 dev_info(kfd_device, "added device %x:%x\n", kfd->pdev->vendor, 594 kfd->pdev->device); 595 596 pr_debug("Starting kfd with the following scheduling policy %d\n", 597 kfd->dqm->sched_policy); 598 599 goto out; 600 601 kfd_resume_error: 602 device_iommu_error: 603 device_queue_manager_uninit(kfd->dqm); 604 device_queue_manager_error: 605 kfd_interrupt_exit(kfd); 606 kfd_interrupt_error: 607 kfd_topology_remove_device(kfd); 608 kfd_topology_add_device_error: 609 kfd_doorbell_fini(kfd); 610 kfd_doorbell_error: 611 kfd_gtt_sa_fini(kfd); 612 kfd_gtt_sa_init_error: 613 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem); 614 dev_err(kfd_device, 615 "device %x:%x NOT added due to errors\n", 616 kfd->pdev->vendor, kfd->pdev->device); 617 out: 618 return kfd->init_complete; 619 } 620 621 void kgd2kfd_device_exit(struct kfd_dev *kfd) 622 { 623 if (kfd->init_complete) { 624 kgd2kfd_suspend(kfd); 625 device_queue_manager_uninit(kfd->dqm); 626 kfd_interrupt_exit(kfd); 627 kfd_topology_remove_device(kfd); 628 kfd_doorbell_fini(kfd); 629 kfd_gtt_sa_fini(kfd); 630 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem); 631 } 632 633 kfree(kfd); 634 } 635 636 int kgd2kfd_pre_reset(struct kfd_dev *kfd) 637 { 638 if (!kfd->init_complete) 639 return 0; 640 kgd2kfd_suspend(kfd); 641 642 /* hold dqm->lock to prevent further execution*/ 643 dqm_lock(kfd->dqm); 644 645 kfd_signal_reset_event(kfd); 646 return 0; 647 } 648 649 /* 650 * Fix me. KFD won't be able to resume existing process for now. 651 * We will keep all existing process in a evicted state and 652 * wait the process to be terminated. 653 */ 654 655 int kgd2kfd_post_reset(struct kfd_dev *kfd) 656 { 657 int ret, count; 658 659 if (!kfd->init_complete) 660 return 0; 661 662 dqm_unlock(kfd->dqm); 663 664 ret = kfd_resume(kfd); 665 if (ret) 666 return ret; 667 count = atomic_dec_return(&kfd_locked); 668 WARN_ONCE(count != 0, "KFD reset ref. error"); 669 670 atomic_set(&kfd->sram_ecc_flag, 0); 671 672 return 0; 673 } 674 675 bool kfd_is_locked(void) 676 { 677 return (atomic_read(&kfd_locked) > 0); 678 } 679 680 void kgd2kfd_suspend(struct kfd_dev *kfd) 681 { 682 if (!kfd->init_complete) 683 return; 684 685 /* For first KFD device suspend all the KFD processes */ 686 if (atomic_inc_return(&kfd_locked) == 1) 687 kfd_suspend_all_processes(); 688 689 kfd->dqm->ops.stop(kfd->dqm); 690 691 kfd_iommu_suspend(kfd); 692 } 693 694 int kgd2kfd_resume(struct kfd_dev *kfd) 695 { 696 int ret, count; 697 698 if (!kfd->init_complete) 699 return 0; 700 701 ret = kfd_resume(kfd); 702 if (ret) 703 return ret; 704 705 count = atomic_dec_return(&kfd_locked); 706 WARN_ONCE(count < 0, "KFD suspend / resume ref. error"); 707 if (count == 0) 708 ret = kfd_resume_all_processes(); 709 710 return ret; 711 } 712 713 static int kfd_resume(struct kfd_dev *kfd) 714 { 715 int err = 0; 716 717 err = kfd_iommu_resume(kfd); 718 if (err) { 719 dev_err(kfd_device, 720 "Failed to resume IOMMU for device %x:%x\n", 721 kfd->pdev->vendor, kfd->pdev->device); 722 return err; 723 } 724 725 err = kfd->dqm->ops.start(kfd->dqm); 726 if (err) { 727 dev_err(kfd_device, 728 "Error starting queue manager for device %x:%x\n", 729 kfd->pdev->vendor, kfd->pdev->device); 730 goto dqm_start_error; 731 } 732 733 return err; 734 735 dqm_start_error: 736 kfd_iommu_suspend(kfd); 737 return err; 738 } 739 740 /* This is called directly from KGD at ISR. */ 741 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 742 { 743 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE]; 744 bool is_patched = false; 745 unsigned long flags; 746 747 if (!kfd->init_complete) 748 return; 749 750 if (kfd->device_info->ih_ring_entry_size > sizeof(patched_ihre)) { 751 dev_err_once(kfd_device, "Ring entry too small\n"); 752 return; 753 } 754 755 spin_lock_irqsave(&kfd->interrupt_lock, flags); 756 757 if (kfd->interrupts_active 758 && interrupt_is_wanted(kfd, ih_ring_entry, 759 patched_ihre, &is_patched) 760 && enqueue_ih_ring_entry(kfd, 761 is_patched ? patched_ihre : ih_ring_entry)) 762 queue_work(kfd->ih_wq, &kfd->interrupt_work); 763 764 spin_unlock_irqrestore(&kfd->interrupt_lock, flags); 765 } 766 767 int kgd2kfd_quiesce_mm(struct mm_struct *mm) 768 { 769 struct kfd_process *p; 770 int r; 771 772 /* Because we are called from arbitrary context (workqueue) as opposed 773 * to process context, kfd_process could attempt to exit while we are 774 * running so the lookup function increments the process ref count. 775 */ 776 p = kfd_lookup_process_by_mm(mm); 777 if (!p) 778 return -ESRCH; 779 780 r = kfd_process_evict_queues(p); 781 782 kfd_unref_process(p); 783 return r; 784 } 785 786 int kgd2kfd_resume_mm(struct mm_struct *mm) 787 { 788 struct kfd_process *p; 789 int r; 790 791 /* Because we are called from arbitrary context (workqueue) as opposed 792 * to process context, kfd_process could attempt to exit while we are 793 * running so the lookup function increments the process ref count. 794 */ 795 p = kfd_lookup_process_by_mm(mm); 796 if (!p) 797 return -ESRCH; 798 799 r = kfd_process_restore_queues(p); 800 801 kfd_unref_process(p); 802 return r; 803 } 804 805 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 806 * prepare for safe eviction of KFD BOs that belong to the specified 807 * process. 808 * 809 * @mm: mm_struct that identifies the specified KFD process 810 * @fence: eviction fence attached to KFD process BOs 811 * 812 */ 813 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 814 struct dma_fence *fence) 815 { 816 struct kfd_process *p; 817 unsigned long active_time; 818 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 819 820 if (!fence) 821 return -EINVAL; 822 823 if (dma_fence_is_signaled(fence)) 824 return 0; 825 826 p = kfd_lookup_process_by_mm(mm); 827 if (!p) 828 return -ENODEV; 829 830 if (fence->seqno == p->last_eviction_seqno) 831 goto out; 832 833 p->last_eviction_seqno = fence->seqno; 834 835 /* Avoid KFD process starvation. Wait for at least 836 * PROCESS_ACTIVE_TIME_MS before evicting the process again 837 */ 838 active_time = get_jiffies_64() - p->last_restore_timestamp; 839 if (delay_jiffies > active_time) 840 delay_jiffies -= active_time; 841 else 842 delay_jiffies = 0; 843 844 /* During process initialization eviction_work.dwork is initialized 845 * to kfd_evict_bo_worker 846 */ 847 schedule_delayed_work(&p->eviction_work, delay_jiffies); 848 out: 849 kfd_unref_process(p); 850 return 0; 851 } 852 853 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 854 unsigned int chunk_size) 855 { 856 unsigned int num_of_longs; 857 858 if (WARN_ON(buf_size < chunk_size)) 859 return -EINVAL; 860 if (WARN_ON(buf_size == 0)) 861 return -EINVAL; 862 if (WARN_ON(chunk_size == 0)) 863 return -EINVAL; 864 865 kfd->gtt_sa_chunk_size = chunk_size; 866 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 867 868 num_of_longs = (kfd->gtt_sa_num_of_chunks + BITS_PER_LONG - 1) / 869 BITS_PER_LONG; 870 871 kfd->gtt_sa_bitmap = kcalloc(num_of_longs, sizeof(long), GFP_KERNEL); 872 873 if (!kfd->gtt_sa_bitmap) 874 return -ENOMEM; 875 876 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 877 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 878 879 mutex_init(&kfd->gtt_sa_lock); 880 881 return 0; 882 883 } 884 885 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 886 { 887 mutex_destroy(&kfd->gtt_sa_lock); 888 kfree(kfd->gtt_sa_bitmap); 889 } 890 891 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 892 unsigned int bit_num, 893 unsigned int chunk_size) 894 { 895 return start_addr + bit_num * chunk_size; 896 } 897 898 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 899 unsigned int bit_num, 900 unsigned int chunk_size) 901 { 902 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 903 } 904 905 int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size, 906 struct kfd_mem_obj **mem_obj) 907 { 908 unsigned int found, start_search, cur_size; 909 910 if (size == 0) 911 return -EINVAL; 912 913 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 914 return -ENOMEM; 915 916 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 917 if (!(*mem_obj)) 918 return -ENOMEM; 919 920 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 921 922 start_search = 0; 923 924 mutex_lock(&kfd->gtt_sa_lock); 925 926 kfd_gtt_restart_search: 927 /* Find the first chunk that is free */ 928 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 929 kfd->gtt_sa_num_of_chunks, 930 start_search); 931 932 pr_debug("Found = %d\n", found); 933 934 /* If there wasn't any free chunk, bail out */ 935 if (found == kfd->gtt_sa_num_of_chunks) 936 goto kfd_gtt_no_free_chunk; 937 938 /* Update fields of mem_obj */ 939 (*mem_obj)->range_start = found; 940 (*mem_obj)->range_end = found; 941 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 942 kfd->gtt_start_gpu_addr, 943 found, 944 kfd->gtt_sa_chunk_size); 945 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 946 kfd->gtt_start_cpu_ptr, 947 found, 948 kfd->gtt_sa_chunk_size); 949 950 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 951 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 952 953 /* If we need only one chunk, mark it as allocated and get out */ 954 if (size <= kfd->gtt_sa_chunk_size) { 955 pr_debug("Single bit\n"); 956 set_bit(found, kfd->gtt_sa_bitmap); 957 goto kfd_gtt_out; 958 } 959 960 /* Otherwise, try to see if we have enough contiguous chunks */ 961 cur_size = size - kfd->gtt_sa_chunk_size; 962 do { 963 (*mem_obj)->range_end = 964 find_next_zero_bit(kfd->gtt_sa_bitmap, 965 kfd->gtt_sa_num_of_chunks, ++found); 966 /* 967 * If next free chunk is not contiguous than we need to 968 * restart our search from the last free chunk we found (which 969 * wasn't contiguous to the previous ones 970 */ 971 if ((*mem_obj)->range_end != found) { 972 start_search = found; 973 goto kfd_gtt_restart_search; 974 } 975 976 /* 977 * If we reached end of buffer, bail out with error 978 */ 979 if (found == kfd->gtt_sa_num_of_chunks) 980 goto kfd_gtt_no_free_chunk; 981 982 /* Check if we don't need another chunk */ 983 if (cur_size <= kfd->gtt_sa_chunk_size) 984 cur_size = 0; 985 else 986 cur_size -= kfd->gtt_sa_chunk_size; 987 988 } while (cur_size > 0); 989 990 pr_debug("range_start = %d, range_end = %d\n", 991 (*mem_obj)->range_start, (*mem_obj)->range_end); 992 993 /* Mark the chunks as allocated */ 994 for (found = (*mem_obj)->range_start; 995 found <= (*mem_obj)->range_end; 996 found++) 997 set_bit(found, kfd->gtt_sa_bitmap); 998 999 kfd_gtt_out: 1000 mutex_unlock(&kfd->gtt_sa_lock); 1001 return 0; 1002 1003 kfd_gtt_no_free_chunk: 1004 pr_debug("Allocation failed with mem_obj = %p\n", mem_obj); 1005 mutex_unlock(&kfd->gtt_sa_lock); 1006 kfree(mem_obj); 1007 return -ENOMEM; 1008 } 1009 1010 int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj) 1011 { 1012 unsigned int bit; 1013 1014 /* Act like kfree when trying to free a NULL object */ 1015 if (!mem_obj) 1016 return 0; 1017 1018 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1019 mem_obj, mem_obj->range_start, mem_obj->range_end); 1020 1021 mutex_lock(&kfd->gtt_sa_lock); 1022 1023 /* Mark the chunks as free */ 1024 for (bit = mem_obj->range_start; 1025 bit <= mem_obj->range_end; 1026 bit++) 1027 clear_bit(bit, kfd->gtt_sa_bitmap); 1028 1029 mutex_unlock(&kfd->gtt_sa_lock); 1030 1031 kfree(mem_obj); 1032 return 0; 1033 } 1034 1035 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1036 { 1037 if (kfd) 1038 atomic_inc(&kfd->sram_ecc_flag); 1039 } 1040 1041 void kfd_inc_compute_active(struct kfd_dev *kfd) 1042 { 1043 if (atomic_inc_return(&kfd->compute_profile) == 1) 1044 amdgpu_amdkfd_set_compute_idle(kfd->kgd, false); 1045 } 1046 1047 void kfd_dec_compute_active(struct kfd_dev *kfd) 1048 { 1049 int count = atomic_dec_return(&kfd->compute_profile); 1050 1051 if (count == 0) 1052 amdgpu_amdkfd_set_compute_idle(kfd->kgd, true); 1053 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1054 } 1055 1056 #if defined(CONFIG_DEBUG_FS) 1057 1058 /* This function will send a package to HIQ to hang the HWS 1059 * which will trigger a GPU reset and bring the HWS back to normal state 1060 */ 1061 int kfd_debugfs_hang_hws(struct kfd_dev *dev) 1062 { 1063 int r = 0; 1064 1065 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1066 pr_err("HWS is not enabled"); 1067 return -EINVAL; 1068 } 1069 1070 r = pm_debugfs_hang_hws(&dev->dqm->packets); 1071 if (!r) 1072 r = dqm_debugfs_execute_queues(dev->dqm); 1073 1074 return r; 1075 } 1076 1077 #endif 1078