1 /*
2  * Copyright 2014 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22 
23 #include <linux/bsearch.h>
24 #include <linux/pci.h>
25 #include <linux/slab.h>
26 #include "kfd_priv.h"
27 #include "kfd_device_queue_manager.h"
28 #include "kfd_pm4_headers_vi.h"
29 #include "kfd_pm4_headers_aldebaran.h"
30 #include "cwsr_trap_handler.h"
31 #include "kfd_iommu.h"
32 #include "amdgpu_amdkfd.h"
33 #include "kfd_smi_events.h"
34 #include "kfd_migrate.h"
35 #include "amdgpu.h"
36 
37 #define MQD_SIZE_ALIGNED 768
38 
39 /*
40  * kfd_locked is used to lock the kfd driver during suspend or reset
41  * once locked, kfd driver will stop any further GPU execution.
42  * create process (open) will return -EAGAIN.
43  */
44 static atomic_t kfd_locked = ATOMIC_INIT(0);
45 
46 #ifdef CONFIG_DRM_AMDGPU_CIK
47 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd;
48 #endif
49 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd;
50 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd;
51 extern const struct kfd2kgd_calls arcturus_kfd2kgd;
52 extern const struct kfd2kgd_calls aldebaran_kfd2kgd;
53 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd;
54 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd;
55 
56 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
57 				unsigned int chunk_size);
58 static void kfd_gtt_sa_fini(struct kfd_dev *kfd);
59 
60 static int kfd_resume(struct kfd_dev *kfd);
61 
62 static void kfd_device_info_init(struct kfd_dev *kfd,
63 				 bool vf, uint32_t gfx_target_version)
64 {
65 	uint32_t gc_version = KFD_GC_VERSION(kfd);
66 	uint32_t sdma_version = kfd->adev->ip_versions[SDMA0_HWIP][0];
67 	uint32_t asic_type = kfd->adev->asic_type;
68 
69 	kfd->device_info.max_pasid_bits = 16;
70 	kfd->device_info.max_no_of_hqd = 24;
71 	kfd->device_info.num_of_watch_points = 4;
72 	kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED;
73 	kfd->device_info.gfx_target_version = gfx_target_version;
74 
75 	if (KFD_IS_SOC15(kfd)) {
76 		kfd->device_info.doorbell_size = 8;
77 		kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t);
78 		kfd->device_info.event_interrupt_class = &event_interrupt_class_v9;
79 		kfd->device_info.supports_cwsr = true;
80 
81 		if ((sdma_version >= IP_VERSION(4, 0, 0)  &&
82 		     sdma_version <= IP_VERSION(4, 2, 0)) ||
83 		     sdma_version == IP_VERSION(5, 2, 1)  ||
84 		     sdma_version == IP_VERSION(5, 2, 3))
85 			kfd->device_info.num_sdma_queues_per_engine = 2;
86 		else
87 			kfd->device_info.num_sdma_queues_per_engine = 8;
88 
89 		/* Raven */
90 		if (gc_version == IP_VERSION(9, 1, 0) ||
91 		    gc_version == IP_VERSION(9, 2, 2))
92 			kfd->device_info.needs_iommu_device = true;
93 
94 		if (gc_version < IP_VERSION(11, 0, 0)) {
95 			/* Navi2x+, Navi1x+ */
96 			if (gc_version >= IP_VERSION(10, 3, 0))
97 				kfd->device_info.no_atomic_fw_version = 92;
98 			else if (gc_version >= IP_VERSION(10, 1, 1))
99 				kfd->device_info.no_atomic_fw_version = 145;
100 
101 			/* Navi1x+ */
102 			if (gc_version >= IP_VERSION(10, 1, 1))
103 				kfd->device_info.needs_pci_atomics = true;
104 		}
105 	} else {
106 		kfd->device_info.doorbell_size = 4;
107 		kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t);
108 		kfd->device_info.event_interrupt_class = &event_interrupt_class_cik;
109 		kfd->device_info.num_sdma_queues_per_engine = 2;
110 
111 		if (asic_type != CHIP_KAVERI &&
112 		    asic_type != CHIP_HAWAII &&
113 		    asic_type != CHIP_TONGA)
114 			kfd->device_info.supports_cwsr = true;
115 
116 		if (asic_type == CHIP_KAVERI ||
117 		    asic_type == CHIP_CARRIZO)
118 			kfd->device_info.needs_iommu_device = true;
119 
120 		if (asic_type != CHIP_HAWAII && !vf)
121 			kfd->device_info.needs_pci_atomics = true;
122 	}
123 }
124 
125 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf)
126 {
127 	struct kfd_dev *kfd = NULL;
128 	const struct kfd2kgd_calls *f2g = NULL;
129 	struct pci_dev *pdev = adev->pdev;
130 	uint32_t gfx_target_version = 0;
131 
132 	switch (adev->asic_type) {
133 #ifdef KFD_SUPPORT_IOMMU_V2
134 #ifdef CONFIG_DRM_AMDGPU_CIK
135 	case CHIP_KAVERI:
136 		gfx_target_version = 70000;
137 		if (!vf)
138 			f2g = &gfx_v7_kfd2kgd;
139 		break;
140 #endif
141 	case CHIP_CARRIZO:
142 		gfx_target_version = 80001;
143 		if (!vf)
144 			f2g = &gfx_v8_kfd2kgd;
145 		break;
146 #endif
147 #ifdef CONFIG_DRM_AMDGPU_CIK
148 	case CHIP_HAWAII:
149 		gfx_target_version = 70001;
150 		if (!vf)
151 			f2g = &gfx_v7_kfd2kgd;
152 		break;
153 #endif
154 	case CHIP_TONGA:
155 		gfx_target_version = 80002;
156 		if (!vf)
157 			f2g = &gfx_v8_kfd2kgd;
158 		break;
159 	case CHIP_FIJI:
160 		gfx_target_version = 80003;
161 		f2g = &gfx_v8_kfd2kgd;
162 		break;
163 	case CHIP_POLARIS10:
164 		gfx_target_version = 80003;
165 		f2g = &gfx_v8_kfd2kgd;
166 		break;
167 	case CHIP_POLARIS11:
168 		gfx_target_version = 80003;
169 		if (!vf)
170 			f2g = &gfx_v8_kfd2kgd;
171 		break;
172 	case CHIP_POLARIS12:
173 		gfx_target_version = 80003;
174 		if (!vf)
175 			f2g = &gfx_v8_kfd2kgd;
176 		break;
177 	case CHIP_VEGAM:
178 		gfx_target_version = 80003;
179 		if (!vf)
180 			f2g = &gfx_v8_kfd2kgd;
181 		break;
182 	default:
183 		switch (adev->ip_versions[GC_HWIP][0]) {
184 		/* Vega 10 */
185 		case IP_VERSION(9, 0, 1):
186 			gfx_target_version = 90000;
187 			f2g = &gfx_v9_kfd2kgd;
188 			break;
189 #ifdef KFD_SUPPORT_IOMMU_V2
190 		/* Raven */
191 		case IP_VERSION(9, 1, 0):
192 		case IP_VERSION(9, 2, 2):
193 			gfx_target_version = 90002;
194 			if (!vf)
195 				f2g = &gfx_v9_kfd2kgd;
196 			break;
197 #endif
198 		/* Vega12 */
199 		case IP_VERSION(9, 2, 1):
200 			gfx_target_version = 90004;
201 			if (!vf)
202 				f2g = &gfx_v9_kfd2kgd;
203 			break;
204 		/* Renoir */
205 		case IP_VERSION(9, 3, 0):
206 			gfx_target_version = 90012;
207 			if (!vf)
208 				f2g = &gfx_v9_kfd2kgd;
209 			break;
210 		/* Vega20 */
211 		case IP_VERSION(9, 4, 0):
212 			gfx_target_version = 90006;
213 			if (!vf)
214 				f2g = &gfx_v9_kfd2kgd;
215 			break;
216 		/* Arcturus */
217 		case IP_VERSION(9, 4, 1):
218 			gfx_target_version = 90008;
219 			f2g = &arcturus_kfd2kgd;
220 			break;
221 		/* Aldebaran */
222 		case IP_VERSION(9, 4, 2):
223 			gfx_target_version = 90010;
224 			f2g = &aldebaran_kfd2kgd;
225 			break;
226 		/* Navi10 */
227 		case IP_VERSION(10, 1, 10):
228 			gfx_target_version = 100100;
229 			if (!vf)
230 				f2g = &gfx_v10_kfd2kgd;
231 			break;
232 		/* Navi12 */
233 		case IP_VERSION(10, 1, 2):
234 			gfx_target_version = 100101;
235 			f2g = &gfx_v10_kfd2kgd;
236 			break;
237 		/* Navi14 */
238 		case IP_VERSION(10, 1, 1):
239 			gfx_target_version = 100102;
240 			if (!vf)
241 				f2g = &gfx_v10_kfd2kgd;
242 			break;
243 		/* Cyan Skillfish */
244 		case IP_VERSION(10, 1, 3):
245 			gfx_target_version = 100103;
246 			if (!vf)
247 				f2g = &gfx_v10_kfd2kgd;
248 			break;
249 		/* Sienna Cichlid */
250 		case IP_VERSION(10, 3, 0):
251 			gfx_target_version = 100300;
252 			f2g = &gfx_v10_3_kfd2kgd;
253 			break;
254 		/* Navy Flounder */
255 		case IP_VERSION(10, 3, 2):
256 			gfx_target_version = 100301;
257 			f2g = &gfx_v10_3_kfd2kgd;
258 			break;
259 		/* Van Gogh */
260 		case IP_VERSION(10, 3, 1):
261 			gfx_target_version = 100303;
262 			if (!vf)
263 				f2g = &gfx_v10_3_kfd2kgd;
264 			break;
265 		/* Dimgrey Cavefish */
266 		case IP_VERSION(10, 3, 4):
267 			gfx_target_version = 100302;
268 			f2g = &gfx_v10_3_kfd2kgd;
269 			break;
270 		/* Beige Goby */
271 		case IP_VERSION(10, 3, 5):
272 			gfx_target_version = 100304;
273 			f2g = &gfx_v10_3_kfd2kgd;
274 			break;
275 		/* Yellow Carp */
276 		case IP_VERSION(10, 3, 3):
277 			gfx_target_version = 100305;
278 			if (!vf)
279 				f2g = &gfx_v10_3_kfd2kgd;
280 			break;
281 		default:
282 			break;
283 		}
284 		break;
285 	}
286 
287 	if (!f2g) {
288 		if (adev->ip_versions[GC_HWIP][0])
289 			dev_err(kfd_device, "GC IP %06x %s not supported in kfd\n",
290 				adev->ip_versions[GC_HWIP][0], vf ? "VF" : "");
291 		else
292 			dev_err(kfd_device, "%s %s not supported in kfd\n",
293 				amdgpu_asic_name[adev->asic_type], vf ? "VF" : "");
294 		return NULL;
295 	}
296 
297 	kfd = kzalloc(sizeof(*kfd), GFP_KERNEL);
298 	if (!kfd)
299 		return NULL;
300 
301 	kfd->adev = adev;
302 	kfd_device_info_init(kfd, vf, gfx_target_version);
303 	kfd->pdev = pdev;
304 	kfd->init_complete = false;
305 	kfd->kfd2kgd = f2g;
306 	atomic_set(&kfd->compute_profile, 0);
307 
308 	mutex_init(&kfd->doorbell_mutex);
309 	memset(&kfd->doorbell_available_index, 0,
310 		sizeof(kfd->doorbell_available_index));
311 
312 	atomic_set(&kfd->sram_ecc_flag, 0);
313 
314 	ida_init(&kfd->doorbell_ida);
315 
316 	return kfd;
317 }
318 
319 static void kfd_cwsr_init(struct kfd_dev *kfd)
320 {
321 	if (cwsr_enable && kfd->device_info.supports_cwsr) {
322 		if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) {
323 			BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE);
324 			kfd->cwsr_isa = cwsr_trap_gfx8_hex;
325 			kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex);
326 		} else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) {
327 			BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE);
328 			kfd->cwsr_isa = cwsr_trap_arcturus_hex;
329 			kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex);
330 		} else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) {
331 			BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) > PAGE_SIZE);
332 			kfd->cwsr_isa = cwsr_trap_aldebaran_hex;
333 			kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex);
334 		} else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) {
335 			BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE);
336 			kfd->cwsr_isa = cwsr_trap_gfx9_hex;
337 			kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex);
338 		} else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) {
339 			BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE);
340 			kfd->cwsr_isa = cwsr_trap_nv1x_hex;
341 			kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex);
342 		} else {
343 			BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE);
344 			kfd->cwsr_isa = cwsr_trap_gfx10_hex;
345 			kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex);
346 		}
347 
348 		kfd->cwsr_enabled = true;
349 	}
350 }
351 
352 static int kfd_gws_init(struct kfd_dev *kfd)
353 {
354 	int ret = 0;
355 
356 	if (kfd->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS)
357 		return 0;
358 
359 	if (hws_gws_support || (KFD_IS_SOC15(kfd) &&
360 		((KFD_GC_VERSION(kfd) == IP_VERSION(9, 0, 1)
361 			&& kfd->mec2_fw_version >= 0x81b3) ||
362 		(KFD_GC_VERSION(kfd) <= IP_VERSION(9, 4, 0)
363 			&& kfd->mec2_fw_version >= 0x1b3)  ||
364 		(KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)
365 			&& kfd->mec2_fw_version >= 0x30)   ||
366 		(KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)
367 			&& kfd->mec2_fw_version >= 0x28))))
368 		ret = amdgpu_amdkfd_alloc_gws(kfd->adev,
369 				kfd->adev->gds.gws_size, &kfd->gws);
370 
371 	return ret;
372 }
373 
374 static void kfd_smi_init(struct kfd_dev *dev) {
375 	INIT_LIST_HEAD(&dev->smi_clients);
376 	spin_lock_init(&dev->smi_lock);
377 }
378 
379 bool kgd2kfd_device_init(struct kfd_dev *kfd,
380 			 struct drm_device *ddev,
381 			 const struct kgd2kfd_shared_resources *gpu_resources)
382 {
383 	unsigned int size, map_process_packet_size;
384 
385 	kfd->ddev = ddev;
386 	kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev,
387 			KGD_ENGINE_MEC1);
388 	kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev,
389 			KGD_ENGINE_MEC2);
390 	kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev,
391 			KGD_ENGINE_SDMA1);
392 	kfd->shared_resources = *gpu_resources;
393 
394 	kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1;
395 	kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1;
396 	kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd
397 			- kfd->vm_info.first_vmid_kfd + 1;
398 
399 	/* Allow BIF to recode atomics to PCIe 3.0 AtomicOps.
400 	 * 32 and 64-bit requests are possible and must be
401 	 * supported.
402 	 */
403 	kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev);
404 	if (!kfd->pci_atomic_requested &&
405 	    kfd->device_info.needs_pci_atomics &&
406 	    (!kfd->device_info.no_atomic_fw_version ||
407 	     kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) {
408 		dev_info(kfd_device,
409 			 "skipped device %x:%x, PCI rejects atomics %d<%d\n",
410 			 kfd->pdev->vendor, kfd->pdev->device,
411 			 kfd->mec_fw_version,
412 			 kfd->device_info.no_atomic_fw_version);
413 		return false;
414 	}
415 
416 	/* Verify module parameters regarding mapped process number*/
417 	if ((hws_max_conc_proc < 0)
418 			|| (hws_max_conc_proc > kfd->vm_info.vmid_num_kfd)) {
419 		dev_err(kfd_device,
420 			"hws_max_conc_proc %d must be between 0 and %d, use %d instead\n",
421 			hws_max_conc_proc, kfd->vm_info.vmid_num_kfd,
422 			kfd->vm_info.vmid_num_kfd);
423 		kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd;
424 	} else
425 		kfd->max_proc_per_quantum = hws_max_conc_proc;
426 
427 	/* calculate max size of mqds needed for queues */
428 	size = max_num_of_queues_per_device *
429 			kfd->device_info.mqd_size_aligned;
430 
431 	/*
432 	 * calculate max size of runlist packet.
433 	 * There can be only 2 packets at once
434 	 */
435 	map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ?
436 				sizeof(struct pm4_mes_map_process_aldebaran) :
437 				sizeof(struct pm4_mes_map_process);
438 	size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size +
439 		max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues)
440 		+ sizeof(struct pm4_mes_runlist)) * 2;
441 
442 	/* Add size of HIQ & DIQ */
443 	size += KFD_KERNEL_QUEUE_SIZE * 2;
444 
445 	/* add another 512KB for all other allocations on gart (HPD, fences) */
446 	size += 512 * 1024;
447 
448 	if (amdgpu_amdkfd_alloc_gtt_mem(
449 			kfd->adev, size, &kfd->gtt_mem,
450 			&kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr,
451 			false)) {
452 		dev_err(kfd_device, "Could not allocate %d bytes\n", size);
453 		goto alloc_gtt_mem_failure;
454 	}
455 
456 	dev_info(kfd_device, "Allocated %d bytes on gart\n", size);
457 
458 	/* Initialize GTT sa with 512 byte chunk size */
459 	if (kfd_gtt_sa_init(kfd, size, 512) != 0) {
460 		dev_err(kfd_device, "Error initializing gtt sub-allocator\n");
461 		goto kfd_gtt_sa_init_error;
462 	}
463 
464 	if (kfd_doorbell_init(kfd)) {
465 		dev_err(kfd_device,
466 			"Error initializing doorbell aperture\n");
467 		goto kfd_doorbell_error;
468 	}
469 
470 	kfd->hive_id = kfd->adev->gmc.xgmi.hive_id;
471 
472 	kfd->noretry = kfd->adev->gmc.noretry;
473 
474 	if (kfd_interrupt_init(kfd)) {
475 		dev_err(kfd_device, "Error initializing interrupts\n");
476 		goto kfd_interrupt_error;
477 	}
478 
479 	kfd->dqm = device_queue_manager_init(kfd);
480 	if (!kfd->dqm) {
481 		dev_err(kfd_device, "Error initializing queue manager\n");
482 		goto device_queue_manager_error;
483 	}
484 
485 	/* If supported on this device, allocate global GWS that is shared
486 	 * by all KFD processes
487 	 */
488 	if (kfd_gws_init(kfd)) {
489 		dev_err(kfd_device, "Could not allocate %d gws\n",
490 			kfd->adev->gds.gws_size);
491 		goto gws_error;
492 	}
493 
494 	/* If CRAT is broken, won't set iommu enabled */
495 	kfd_double_confirm_iommu_support(kfd);
496 
497 	if (kfd_iommu_device_init(kfd)) {
498 		kfd->use_iommu_v2 = false;
499 		dev_err(kfd_device, "Error initializing iommuv2\n");
500 		goto device_iommu_error;
501 	}
502 
503 	kfd_cwsr_init(kfd);
504 
505 	svm_migrate_init(kfd->adev);
506 
507 	if(kgd2kfd_resume_iommu(kfd))
508 		goto device_iommu_error;
509 
510 	if (kfd_resume(kfd))
511 		goto kfd_resume_error;
512 
513 	kfd->dbgmgr = NULL;
514 
515 	if (kfd_topology_add_device(kfd)) {
516 		dev_err(kfd_device, "Error adding device to topology\n");
517 		goto kfd_topology_add_device_error;
518 	}
519 
520 	kfd_smi_init(kfd);
521 
522 	kfd->init_complete = true;
523 	dev_info(kfd_device, "added device %x:%x\n", kfd->pdev->vendor,
524 		 kfd->pdev->device);
525 
526 	pr_debug("Starting kfd with the following scheduling policy %d\n",
527 		kfd->dqm->sched_policy);
528 
529 	goto out;
530 
531 kfd_topology_add_device_error:
532 kfd_resume_error:
533 device_iommu_error:
534 gws_error:
535 	device_queue_manager_uninit(kfd->dqm);
536 device_queue_manager_error:
537 	kfd_interrupt_exit(kfd);
538 kfd_interrupt_error:
539 	kfd_doorbell_fini(kfd);
540 kfd_doorbell_error:
541 	kfd_gtt_sa_fini(kfd);
542 kfd_gtt_sa_init_error:
543 	amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem);
544 alloc_gtt_mem_failure:
545 	if (kfd->gws)
546 		amdgpu_amdkfd_free_gws(kfd->adev, kfd->gws);
547 	dev_err(kfd_device,
548 		"device %x:%x NOT added due to errors\n",
549 		kfd->pdev->vendor, kfd->pdev->device);
550 out:
551 	return kfd->init_complete;
552 }
553 
554 void kgd2kfd_device_exit(struct kfd_dev *kfd)
555 {
556 	if (kfd->init_complete) {
557 		device_queue_manager_uninit(kfd->dqm);
558 		kfd_interrupt_exit(kfd);
559 		kfd_topology_remove_device(kfd);
560 		kfd_doorbell_fini(kfd);
561 		ida_destroy(&kfd->doorbell_ida);
562 		kfd_gtt_sa_fini(kfd);
563 		amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem);
564 		if (kfd->gws)
565 			amdgpu_amdkfd_free_gws(kfd->adev, kfd->gws);
566 	}
567 
568 	kfree(kfd);
569 }
570 
571 int kgd2kfd_pre_reset(struct kfd_dev *kfd)
572 {
573 	if (!kfd->init_complete)
574 		return 0;
575 
576 	kfd_smi_event_update_gpu_reset(kfd, false);
577 
578 	kfd->dqm->ops.pre_reset(kfd->dqm);
579 
580 	kgd2kfd_suspend(kfd, false);
581 
582 	kfd_signal_reset_event(kfd);
583 	return 0;
584 }
585 
586 /*
587  * Fix me. KFD won't be able to resume existing process for now.
588  * We will keep all existing process in a evicted state and
589  * wait the process to be terminated.
590  */
591 
592 int kgd2kfd_post_reset(struct kfd_dev *kfd)
593 {
594 	int ret;
595 
596 	if (!kfd->init_complete)
597 		return 0;
598 
599 	ret = kfd_resume(kfd);
600 	if (ret)
601 		return ret;
602 	atomic_dec(&kfd_locked);
603 
604 	atomic_set(&kfd->sram_ecc_flag, 0);
605 
606 	kfd_smi_event_update_gpu_reset(kfd, true);
607 
608 	return 0;
609 }
610 
611 bool kfd_is_locked(void)
612 {
613 	return  (atomic_read(&kfd_locked) > 0);
614 }
615 
616 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)
617 {
618 	if (!kfd->init_complete)
619 		return;
620 
621 	/* for runtime suspend, skip locking kfd */
622 	if (!run_pm) {
623 		/* For first KFD device suspend all the KFD processes */
624 		if (atomic_inc_return(&kfd_locked) == 1)
625 			kfd_suspend_all_processes();
626 	}
627 
628 	kfd->dqm->ops.stop(kfd->dqm);
629 	kfd_iommu_suspend(kfd);
630 }
631 
632 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
633 {
634 	int ret, count;
635 
636 	if (!kfd->init_complete)
637 		return 0;
638 
639 	ret = kfd_resume(kfd);
640 	if (ret)
641 		return ret;
642 
643 	/* for runtime resume, skip unlocking kfd */
644 	if (!run_pm) {
645 		count = atomic_dec_return(&kfd_locked);
646 		WARN_ONCE(count < 0, "KFD suspend / resume ref. error");
647 		if (count == 0)
648 			ret = kfd_resume_all_processes();
649 	}
650 
651 	return ret;
652 }
653 
654 int kgd2kfd_resume_iommu(struct kfd_dev *kfd)
655 {
656 	int err = 0;
657 
658 	err = kfd_iommu_resume(kfd);
659 	if (err)
660 		dev_err(kfd_device,
661 			"Failed to resume IOMMU for device %x:%x\n",
662 			kfd->pdev->vendor, kfd->pdev->device);
663 	return err;
664 }
665 
666 static int kfd_resume(struct kfd_dev *kfd)
667 {
668 	int err = 0;
669 
670 	err = kfd->dqm->ops.start(kfd->dqm);
671 	if (err)
672 		dev_err(kfd_device,
673 			"Error starting queue manager for device %x:%x\n",
674 			kfd->pdev->vendor, kfd->pdev->device);
675 
676 	return err;
677 }
678 
679 static inline void kfd_queue_work(struct workqueue_struct *wq,
680 				  struct work_struct *work)
681 {
682 	int cpu, new_cpu;
683 
684 	cpu = new_cpu = smp_processor_id();
685 	do {
686 		new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids;
687 		if (cpu_to_node(new_cpu) == numa_node_id())
688 			break;
689 	} while (cpu != new_cpu);
690 
691 	queue_work_on(new_cpu, wq, work);
692 }
693 
694 /* This is called directly from KGD at ISR. */
695 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
696 {
697 	uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE];
698 	bool is_patched = false;
699 	unsigned long flags;
700 
701 	if (!kfd->init_complete)
702 		return;
703 
704 	if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) {
705 		dev_err_once(kfd_device, "Ring entry too small\n");
706 		return;
707 	}
708 
709 	spin_lock_irqsave(&kfd->interrupt_lock, flags);
710 
711 	if (kfd->interrupts_active
712 	    && interrupt_is_wanted(kfd, ih_ring_entry,
713 				   patched_ihre, &is_patched)
714 	    && enqueue_ih_ring_entry(kfd,
715 				     is_patched ? patched_ihre : ih_ring_entry))
716 		kfd_queue_work(kfd->ih_wq, &kfd->interrupt_work);
717 
718 	spin_unlock_irqrestore(&kfd->interrupt_lock, flags);
719 }
720 
721 int kgd2kfd_quiesce_mm(struct mm_struct *mm)
722 {
723 	struct kfd_process *p;
724 	int r;
725 
726 	/* Because we are called from arbitrary context (workqueue) as opposed
727 	 * to process context, kfd_process could attempt to exit while we are
728 	 * running so the lookup function increments the process ref count.
729 	 */
730 	p = kfd_lookup_process_by_mm(mm);
731 	if (!p)
732 		return -ESRCH;
733 
734 	WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid);
735 	r = kfd_process_evict_queues(p);
736 
737 	kfd_unref_process(p);
738 	return r;
739 }
740 
741 int kgd2kfd_resume_mm(struct mm_struct *mm)
742 {
743 	struct kfd_process *p;
744 	int r;
745 
746 	/* Because we are called from arbitrary context (workqueue) as opposed
747 	 * to process context, kfd_process could attempt to exit while we are
748 	 * running so the lookup function increments the process ref count.
749 	 */
750 	p = kfd_lookup_process_by_mm(mm);
751 	if (!p)
752 		return -ESRCH;
753 
754 	r = kfd_process_restore_queues(p);
755 
756 	kfd_unref_process(p);
757 	return r;
758 }
759 
760 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will
761  *   prepare for safe eviction of KFD BOs that belong to the specified
762  *   process.
763  *
764  * @mm: mm_struct that identifies the specified KFD process
765  * @fence: eviction fence attached to KFD process BOs
766  *
767  */
768 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
769 					       struct dma_fence *fence)
770 {
771 	struct kfd_process *p;
772 	unsigned long active_time;
773 	unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS);
774 
775 	if (!fence)
776 		return -EINVAL;
777 
778 	if (dma_fence_is_signaled(fence))
779 		return 0;
780 
781 	p = kfd_lookup_process_by_mm(mm);
782 	if (!p)
783 		return -ENODEV;
784 
785 	if (fence->seqno == p->last_eviction_seqno)
786 		goto out;
787 
788 	p->last_eviction_seqno = fence->seqno;
789 
790 	/* Avoid KFD process starvation. Wait for at least
791 	 * PROCESS_ACTIVE_TIME_MS before evicting the process again
792 	 */
793 	active_time = get_jiffies_64() - p->last_restore_timestamp;
794 	if (delay_jiffies > active_time)
795 		delay_jiffies -= active_time;
796 	else
797 		delay_jiffies = 0;
798 
799 	/* During process initialization eviction_work.dwork is initialized
800 	 * to kfd_evict_bo_worker
801 	 */
802 	WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies",
803 	     p->lead_thread->pid, delay_jiffies);
804 	schedule_delayed_work(&p->eviction_work, delay_jiffies);
805 out:
806 	kfd_unref_process(p);
807 	return 0;
808 }
809 
810 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
811 				unsigned int chunk_size)
812 {
813 	unsigned int num_of_longs;
814 
815 	if (WARN_ON(buf_size < chunk_size))
816 		return -EINVAL;
817 	if (WARN_ON(buf_size == 0))
818 		return -EINVAL;
819 	if (WARN_ON(chunk_size == 0))
820 		return -EINVAL;
821 
822 	kfd->gtt_sa_chunk_size = chunk_size;
823 	kfd->gtt_sa_num_of_chunks = buf_size / chunk_size;
824 
825 	num_of_longs = (kfd->gtt_sa_num_of_chunks + BITS_PER_LONG - 1) /
826 		BITS_PER_LONG;
827 
828 	kfd->gtt_sa_bitmap = kcalloc(num_of_longs, sizeof(long), GFP_KERNEL);
829 
830 	if (!kfd->gtt_sa_bitmap)
831 		return -ENOMEM;
832 
833 	pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n",
834 			kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap);
835 
836 	mutex_init(&kfd->gtt_sa_lock);
837 
838 	return 0;
839 
840 }
841 
842 static void kfd_gtt_sa_fini(struct kfd_dev *kfd)
843 {
844 	mutex_destroy(&kfd->gtt_sa_lock);
845 	kfree(kfd->gtt_sa_bitmap);
846 }
847 
848 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr,
849 						unsigned int bit_num,
850 						unsigned int chunk_size)
851 {
852 	return start_addr + bit_num * chunk_size;
853 }
854 
855 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr,
856 						unsigned int bit_num,
857 						unsigned int chunk_size)
858 {
859 	return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size);
860 }
861 
862 int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size,
863 			struct kfd_mem_obj **mem_obj)
864 {
865 	unsigned int found, start_search, cur_size;
866 
867 	if (size == 0)
868 		return -EINVAL;
869 
870 	if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size)
871 		return -ENOMEM;
872 
873 	*mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
874 	if (!(*mem_obj))
875 		return -ENOMEM;
876 
877 	pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size);
878 
879 	start_search = 0;
880 
881 	mutex_lock(&kfd->gtt_sa_lock);
882 
883 kfd_gtt_restart_search:
884 	/* Find the first chunk that is free */
885 	found = find_next_zero_bit(kfd->gtt_sa_bitmap,
886 					kfd->gtt_sa_num_of_chunks,
887 					start_search);
888 
889 	pr_debug("Found = %d\n", found);
890 
891 	/* If there wasn't any free chunk, bail out */
892 	if (found == kfd->gtt_sa_num_of_chunks)
893 		goto kfd_gtt_no_free_chunk;
894 
895 	/* Update fields of mem_obj */
896 	(*mem_obj)->range_start = found;
897 	(*mem_obj)->range_end = found;
898 	(*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr(
899 					kfd->gtt_start_gpu_addr,
900 					found,
901 					kfd->gtt_sa_chunk_size);
902 	(*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr(
903 					kfd->gtt_start_cpu_ptr,
904 					found,
905 					kfd->gtt_sa_chunk_size);
906 
907 	pr_debug("gpu_addr = %p, cpu_addr = %p\n",
908 			(uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr);
909 
910 	/* If we need only one chunk, mark it as allocated and get out */
911 	if (size <= kfd->gtt_sa_chunk_size) {
912 		pr_debug("Single bit\n");
913 		set_bit(found, kfd->gtt_sa_bitmap);
914 		goto kfd_gtt_out;
915 	}
916 
917 	/* Otherwise, try to see if we have enough contiguous chunks */
918 	cur_size = size - kfd->gtt_sa_chunk_size;
919 	do {
920 		(*mem_obj)->range_end =
921 			find_next_zero_bit(kfd->gtt_sa_bitmap,
922 					kfd->gtt_sa_num_of_chunks, ++found);
923 		/*
924 		 * If next free chunk is not contiguous than we need to
925 		 * restart our search from the last free chunk we found (which
926 		 * wasn't contiguous to the previous ones
927 		 */
928 		if ((*mem_obj)->range_end != found) {
929 			start_search = found;
930 			goto kfd_gtt_restart_search;
931 		}
932 
933 		/*
934 		 * If we reached end of buffer, bail out with error
935 		 */
936 		if (found == kfd->gtt_sa_num_of_chunks)
937 			goto kfd_gtt_no_free_chunk;
938 
939 		/* Check if we don't need another chunk */
940 		if (cur_size <= kfd->gtt_sa_chunk_size)
941 			cur_size = 0;
942 		else
943 			cur_size -= kfd->gtt_sa_chunk_size;
944 
945 	} while (cur_size > 0);
946 
947 	pr_debug("range_start = %d, range_end = %d\n",
948 		(*mem_obj)->range_start, (*mem_obj)->range_end);
949 
950 	/* Mark the chunks as allocated */
951 	for (found = (*mem_obj)->range_start;
952 		found <= (*mem_obj)->range_end;
953 		found++)
954 		set_bit(found, kfd->gtt_sa_bitmap);
955 
956 kfd_gtt_out:
957 	mutex_unlock(&kfd->gtt_sa_lock);
958 	return 0;
959 
960 kfd_gtt_no_free_chunk:
961 	pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj);
962 	mutex_unlock(&kfd->gtt_sa_lock);
963 	kfree(*mem_obj);
964 	return -ENOMEM;
965 }
966 
967 int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj)
968 {
969 	unsigned int bit;
970 
971 	/* Act like kfree when trying to free a NULL object */
972 	if (!mem_obj)
973 		return 0;
974 
975 	pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n",
976 			mem_obj, mem_obj->range_start, mem_obj->range_end);
977 
978 	mutex_lock(&kfd->gtt_sa_lock);
979 
980 	/* Mark the chunks as free */
981 	for (bit = mem_obj->range_start;
982 		bit <= mem_obj->range_end;
983 		bit++)
984 		clear_bit(bit, kfd->gtt_sa_bitmap);
985 
986 	mutex_unlock(&kfd->gtt_sa_lock);
987 
988 	kfree(mem_obj);
989 	return 0;
990 }
991 
992 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
993 {
994 	if (kfd)
995 		atomic_inc(&kfd->sram_ecc_flag);
996 }
997 
998 void kfd_inc_compute_active(struct kfd_dev *kfd)
999 {
1000 	if (atomic_inc_return(&kfd->compute_profile) == 1)
1001 		amdgpu_amdkfd_set_compute_idle(kfd->adev, false);
1002 }
1003 
1004 void kfd_dec_compute_active(struct kfd_dev *kfd)
1005 {
1006 	int count = atomic_dec_return(&kfd->compute_profile);
1007 
1008 	if (count == 0)
1009 		amdgpu_amdkfd_set_compute_idle(kfd->adev, true);
1010 	WARN_ONCE(count < 0, "Compute profile ref. count error");
1011 }
1012 
1013 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask)
1014 {
1015 	if (kfd && kfd->init_complete)
1016 		kfd_smi_event_update_thermal_throttling(kfd, throttle_bitmask);
1017 }
1018 
1019 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and
1020  * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA.
1021  * When the device has more than two engines, we reserve two for PCIe to enable
1022  * full-duplex and the rest are used as XGMI.
1023  */
1024 unsigned int kfd_get_num_sdma_engines(struct kfd_dev *kdev)
1025 {
1026 	/* If XGMI is not supported, all SDMA engines are PCIe */
1027 	if (!kdev->adev->gmc.xgmi.supported)
1028 		return kdev->adev->sdma.num_instances;
1029 
1030 	return min(kdev->adev->sdma.num_instances, 2);
1031 }
1032 
1033 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_dev *kdev)
1034 {
1035 	/* After reserved for PCIe, the rest of engines are XGMI */
1036 	return kdev->adev->sdma.num_instances - kfd_get_num_sdma_engines(kdev);
1037 }
1038 
1039 #if defined(CONFIG_DEBUG_FS)
1040 
1041 /* This function will send a package to HIQ to hang the HWS
1042  * which will trigger a GPU reset and bring the HWS back to normal state
1043  */
1044 int kfd_debugfs_hang_hws(struct kfd_dev *dev)
1045 {
1046 	if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) {
1047 		pr_err("HWS is not enabled");
1048 		return -EINVAL;
1049 	}
1050 
1051 	return dqm_debugfs_hang_hws(dev->dqm);
1052 }
1053 
1054 #endif
1055