1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/bsearch.h> 24 #include <linux/pci.h> 25 #include <linux/slab.h> 26 #include "kfd_priv.h" 27 #include "kfd_device_queue_manager.h" 28 #include "kfd_pm4_headers_vi.h" 29 #include "kfd_pm4_headers_aldebaran.h" 30 #include "cwsr_trap_handler.h" 31 #include "kfd_iommu.h" 32 #include "amdgpu_amdkfd.h" 33 #include "kfd_smi_events.h" 34 #include "kfd_migrate.h" 35 #include "amdgpu.h" 36 37 #define MQD_SIZE_ALIGNED 768 38 39 /* 40 * kfd_locked is used to lock the kfd driver during suspend or reset 41 * once locked, kfd driver will stop any further GPU execution. 42 * create process (open) will return -EAGAIN. 43 */ 44 static atomic_t kfd_locked = ATOMIC_INIT(0); 45 46 #ifdef CONFIG_DRM_AMDGPU_CIK 47 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 48 #endif 49 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 50 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 51 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 52 extern const struct kfd2kgd_calls aldebaran_kfd2kgd; 53 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 54 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 55 56 #ifdef KFD_SUPPORT_IOMMU_V2 57 static const struct kfd_device_info kaveri_device_info = { 58 .asic_family = CHIP_KAVERI, 59 .asic_name = "kaveri", 60 .gfx_target_version = 70000, 61 .max_pasid_bits = 16, 62 /* max num of queues for KV.TODO should be a dynamic value */ 63 .max_no_of_hqd = 24, 64 .doorbell_size = 4, 65 .ih_ring_entry_size = 4 * sizeof(uint32_t), 66 .event_interrupt_class = &event_interrupt_class_cik, 67 .num_of_watch_points = 4, 68 .mqd_size_aligned = MQD_SIZE_ALIGNED, 69 .supports_cwsr = false, 70 .needs_iommu_device = true, 71 .needs_pci_atomics = false, 72 .num_sdma_engines = 2, 73 .num_xgmi_sdma_engines = 0, 74 .num_sdma_queues_per_engine = 2, 75 }; 76 77 static const struct kfd_device_info carrizo_device_info = { 78 .asic_family = CHIP_CARRIZO, 79 .asic_name = "carrizo", 80 .gfx_target_version = 80001, 81 .max_pasid_bits = 16, 82 /* max num of queues for CZ.TODO should be a dynamic value */ 83 .max_no_of_hqd = 24, 84 .doorbell_size = 4, 85 .ih_ring_entry_size = 4 * sizeof(uint32_t), 86 .event_interrupt_class = &event_interrupt_class_cik, 87 .num_of_watch_points = 4, 88 .mqd_size_aligned = MQD_SIZE_ALIGNED, 89 .supports_cwsr = true, 90 .needs_iommu_device = true, 91 .needs_pci_atomics = false, 92 .num_sdma_engines = 2, 93 .num_xgmi_sdma_engines = 0, 94 .num_sdma_queues_per_engine = 2, 95 }; 96 #endif 97 98 static const struct kfd_device_info raven_device_info = { 99 .asic_family = CHIP_RAVEN, 100 .asic_name = "raven", 101 .gfx_target_version = 90002, 102 .max_pasid_bits = 16, 103 .max_no_of_hqd = 24, 104 .doorbell_size = 8, 105 .ih_ring_entry_size = 8 * sizeof(uint32_t), 106 .event_interrupt_class = &event_interrupt_class_v9, 107 .num_of_watch_points = 4, 108 .mqd_size_aligned = MQD_SIZE_ALIGNED, 109 .supports_cwsr = true, 110 .needs_iommu_device = true, 111 .needs_pci_atomics = true, 112 .num_sdma_engines = 1, 113 .num_xgmi_sdma_engines = 0, 114 .num_sdma_queues_per_engine = 2, 115 }; 116 117 static const struct kfd_device_info hawaii_device_info = { 118 .asic_family = CHIP_HAWAII, 119 .asic_name = "hawaii", 120 .gfx_target_version = 70001, 121 .max_pasid_bits = 16, 122 /* max num of queues for KV.TODO should be a dynamic value */ 123 .max_no_of_hqd = 24, 124 .doorbell_size = 4, 125 .ih_ring_entry_size = 4 * sizeof(uint32_t), 126 .event_interrupt_class = &event_interrupt_class_cik, 127 .num_of_watch_points = 4, 128 .mqd_size_aligned = MQD_SIZE_ALIGNED, 129 .supports_cwsr = false, 130 .needs_iommu_device = false, 131 .needs_pci_atomics = false, 132 .num_sdma_engines = 2, 133 .num_xgmi_sdma_engines = 0, 134 .num_sdma_queues_per_engine = 2, 135 }; 136 137 static const struct kfd_device_info tonga_device_info = { 138 .asic_family = CHIP_TONGA, 139 .asic_name = "tonga", 140 .gfx_target_version = 80002, 141 .max_pasid_bits = 16, 142 .max_no_of_hqd = 24, 143 .doorbell_size = 4, 144 .ih_ring_entry_size = 4 * sizeof(uint32_t), 145 .event_interrupt_class = &event_interrupt_class_cik, 146 .num_of_watch_points = 4, 147 .mqd_size_aligned = MQD_SIZE_ALIGNED, 148 .supports_cwsr = false, 149 .needs_iommu_device = false, 150 .needs_pci_atomics = true, 151 .num_sdma_engines = 2, 152 .num_xgmi_sdma_engines = 0, 153 .num_sdma_queues_per_engine = 2, 154 }; 155 156 static const struct kfd_device_info fiji_device_info = { 157 .asic_family = CHIP_FIJI, 158 .asic_name = "fiji", 159 .gfx_target_version = 80003, 160 .max_pasid_bits = 16, 161 .max_no_of_hqd = 24, 162 .doorbell_size = 4, 163 .ih_ring_entry_size = 4 * sizeof(uint32_t), 164 .event_interrupt_class = &event_interrupt_class_cik, 165 .num_of_watch_points = 4, 166 .mqd_size_aligned = MQD_SIZE_ALIGNED, 167 .supports_cwsr = true, 168 .needs_iommu_device = false, 169 .needs_pci_atomics = true, 170 .num_sdma_engines = 2, 171 .num_xgmi_sdma_engines = 0, 172 .num_sdma_queues_per_engine = 2, 173 }; 174 175 static const struct kfd_device_info fiji_vf_device_info = { 176 .asic_family = CHIP_FIJI, 177 .asic_name = "fiji", 178 .gfx_target_version = 80003, 179 .max_pasid_bits = 16, 180 .max_no_of_hqd = 24, 181 .doorbell_size = 4, 182 .ih_ring_entry_size = 4 * sizeof(uint32_t), 183 .event_interrupt_class = &event_interrupt_class_cik, 184 .num_of_watch_points = 4, 185 .mqd_size_aligned = MQD_SIZE_ALIGNED, 186 .supports_cwsr = true, 187 .needs_iommu_device = false, 188 .needs_pci_atomics = false, 189 .num_sdma_engines = 2, 190 .num_xgmi_sdma_engines = 0, 191 .num_sdma_queues_per_engine = 2, 192 }; 193 194 195 static const struct kfd_device_info polaris10_device_info = { 196 .asic_family = CHIP_POLARIS10, 197 .asic_name = "polaris10", 198 .gfx_target_version = 80003, 199 .max_pasid_bits = 16, 200 .max_no_of_hqd = 24, 201 .doorbell_size = 4, 202 .ih_ring_entry_size = 4 * sizeof(uint32_t), 203 .event_interrupt_class = &event_interrupt_class_cik, 204 .num_of_watch_points = 4, 205 .mqd_size_aligned = MQD_SIZE_ALIGNED, 206 .supports_cwsr = true, 207 .needs_iommu_device = false, 208 .needs_pci_atomics = true, 209 .num_sdma_engines = 2, 210 .num_xgmi_sdma_engines = 0, 211 .num_sdma_queues_per_engine = 2, 212 }; 213 214 static const struct kfd_device_info polaris10_vf_device_info = { 215 .asic_family = CHIP_POLARIS10, 216 .asic_name = "polaris10", 217 .gfx_target_version = 80003, 218 .max_pasid_bits = 16, 219 .max_no_of_hqd = 24, 220 .doorbell_size = 4, 221 .ih_ring_entry_size = 4 * sizeof(uint32_t), 222 .event_interrupt_class = &event_interrupt_class_cik, 223 .num_of_watch_points = 4, 224 .mqd_size_aligned = MQD_SIZE_ALIGNED, 225 .supports_cwsr = true, 226 .needs_iommu_device = false, 227 .needs_pci_atomics = false, 228 .num_sdma_engines = 2, 229 .num_xgmi_sdma_engines = 0, 230 .num_sdma_queues_per_engine = 2, 231 }; 232 233 static const struct kfd_device_info polaris11_device_info = { 234 .asic_family = CHIP_POLARIS11, 235 .asic_name = "polaris11", 236 .gfx_target_version = 80003, 237 .max_pasid_bits = 16, 238 .max_no_of_hqd = 24, 239 .doorbell_size = 4, 240 .ih_ring_entry_size = 4 * sizeof(uint32_t), 241 .event_interrupt_class = &event_interrupt_class_cik, 242 .num_of_watch_points = 4, 243 .mqd_size_aligned = MQD_SIZE_ALIGNED, 244 .supports_cwsr = true, 245 .needs_iommu_device = false, 246 .needs_pci_atomics = true, 247 .num_sdma_engines = 2, 248 .num_xgmi_sdma_engines = 0, 249 .num_sdma_queues_per_engine = 2, 250 }; 251 252 static const struct kfd_device_info polaris12_device_info = { 253 .asic_family = CHIP_POLARIS12, 254 .asic_name = "polaris12", 255 .gfx_target_version = 80003, 256 .max_pasid_bits = 16, 257 .max_no_of_hqd = 24, 258 .doorbell_size = 4, 259 .ih_ring_entry_size = 4 * sizeof(uint32_t), 260 .event_interrupt_class = &event_interrupt_class_cik, 261 .num_of_watch_points = 4, 262 .mqd_size_aligned = MQD_SIZE_ALIGNED, 263 .supports_cwsr = true, 264 .needs_iommu_device = false, 265 .needs_pci_atomics = true, 266 .num_sdma_engines = 2, 267 .num_xgmi_sdma_engines = 0, 268 .num_sdma_queues_per_engine = 2, 269 }; 270 271 static const struct kfd_device_info vegam_device_info = { 272 .asic_family = CHIP_VEGAM, 273 .asic_name = "vegam", 274 .gfx_target_version = 80003, 275 .max_pasid_bits = 16, 276 .max_no_of_hqd = 24, 277 .doorbell_size = 4, 278 .ih_ring_entry_size = 4 * sizeof(uint32_t), 279 .event_interrupt_class = &event_interrupt_class_cik, 280 .num_of_watch_points = 4, 281 .mqd_size_aligned = MQD_SIZE_ALIGNED, 282 .supports_cwsr = true, 283 .needs_iommu_device = false, 284 .needs_pci_atomics = true, 285 .num_sdma_engines = 2, 286 .num_xgmi_sdma_engines = 0, 287 .num_sdma_queues_per_engine = 2, 288 }; 289 290 static const struct kfd_device_info vega10_device_info = { 291 .asic_family = CHIP_VEGA10, 292 .asic_name = "vega10", 293 .gfx_target_version = 90000, 294 .max_pasid_bits = 16, 295 .max_no_of_hqd = 24, 296 .doorbell_size = 8, 297 .ih_ring_entry_size = 8 * sizeof(uint32_t), 298 .event_interrupt_class = &event_interrupt_class_v9, 299 .num_of_watch_points = 4, 300 .mqd_size_aligned = MQD_SIZE_ALIGNED, 301 .supports_cwsr = true, 302 .needs_iommu_device = false, 303 .needs_pci_atomics = false, 304 .num_sdma_engines = 2, 305 .num_xgmi_sdma_engines = 0, 306 .num_sdma_queues_per_engine = 2, 307 }; 308 309 static const struct kfd_device_info vega10_vf_device_info = { 310 .asic_family = CHIP_VEGA10, 311 .asic_name = "vega10", 312 .gfx_target_version = 90000, 313 .max_pasid_bits = 16, 314 .max_no_of_hqd = 24, 315 .doorbell_size = 8, 316 .ih_ring_entry_size = 8 * sizeof(uint32_t), 317 .event_interrupt_class = &event_interrupt_class_v9, 318 .num_of_watch_points = 4, 319 .mqd_size_aligned = MQD_SIZE_ALIGNED, 320 .supports_cwsr = true, 321 .needs_iommu_device = false, 322 .needs_pci_atomics = false, 323 .num_sdma_engines = 2, 324 .num_xgmi_sdma_engines = 0, 325 .num_sdma_queues_per_engine = 2, 326 }; 327 328 static const struct kfd_device_info vega12_device_info = { 329 .asic_family = CHIP_VEGA12, 330 .asic_name = "vega12", 331 .gfx_target_version = 90004, 332 .max_pasid_bits = 16, 333 .max_no_of_hqd = 24, 334 .doorbell_size = 8, 335 .ih_ring_entry_size = 8 * sizeof(uint32_t), 336 .event_interrupt_class = &event_interrupt_class_v9, 337 .num_of_watch_points = 4, 338 .mqd_size_aligned = MQD_SIZE_ALIGNED, 339 .supports_cwsr = true, 340 .needs_iommu_device = false, 341 .needs_pci_atomics = false, 342 .num_sdma_engines = 2, 343 .num_xgmi_sdma_engines = 0, 344 .num_sdma_queues_per_engine = 2, 345 }; 346 347 static const struct kfd_device_info vega20_device_info = { 348 .asic_family = CHIP_VEGA20, 349 .asic_name = "vega20", 350 .gfx_target_version = 90006, 351 .max_pasid_bits = 16, 352 .max_no_of_hqd = 24, 353 .doorbell_size = 8, 354 .ih_ring_entry_size = 8 * sizeof(uint32_t), 355 .event_interrupt_class = &event_interrupt_class_v9, 356 .num_of_watch_points = 4, 357 .mqd_size_aligned = MQD_SIZE_ALIGNED, 358 .supports_cwsr = true, 359 .needs_iommu_device = false, 360 .needs_pci_atomics = false, 361 .num_sdma_engines = 2, 362 .num_xgmi_sdma_engines = 0, 363 .num_sdma_queues_per_engine = 8, 364 }; 365 366 static const struct kfd_device_info arcturus_device_info = { 367 .asic_family = CHIP_ARCTURUS, 368 .asic_name = "arcturus", 369 .gfx_target_version = 90008, 370 .max_pasid_bits = 16, 371 .max_no_of_hqd = 24, 372 .doorbell_size = 8, 373 .ih_ring_entry_size = 8 * sizeof(uint32_t), 374 .event_interrupt_class = &event_interrupt_class_v9, 375 .num_of_watch_points = 4, 376 .mqd_size_aligned = MQD_SIZE_ALIGNED, 377 .supports_cwsr = true, 378 .needs_iommu_device = false, 379 .needs_pci_atomics = false, 380 .num_sdma_engines = 2, 381 .num_xgmi_sdma_engines = 6, 382 .num_sdma_queues_per_engine = 8, 383 }; 384 385 static const struct kfd_device_info aldebaran_device_info = { 386 .asic_family = CHIP_ALDEBARAN, 387 .asic_name = "aldebaran", 388 .gfx_target_version = 90010, 389 .max_pasid_bits = 16, 390 .max_no_of_hqd = 24, 391 .doorbell_size = 8, 392 .ih_ring_entry_size = 8 * sizeof(uint32_t), 393 .event_interrupt_class = &event_interrupt_class_v9, 394 .num_of_watch_points = 4, 395 .mqd_size_aligned = MQD_SIZE_ALIGNED, 396 .supports_cwsr = true, 397 .needs_iommu_device = false, 398 .needs_pci_atomics = false, 399 .num_sdma_engines = 2, 400 .num_xgmi_sdma_engines = 3, 401 .num_sdma_queues_per_engine = 8, 402 }; 403 404 static const struct kfd_device_info renoir_device_info = { 405 .asic_family = CHIP_RENOIR, 406 .asic_name = "renoir", 407 .gfx_target_version = 90002, 408 .max_pasid_bits = 16, 409 .max_no_of_hqd = 24, 410 .doorbell_size = 8, 411 .ih_ring_entry_size = 8 * sizeof(uint32_t), 412 .event_interrupt_class = &event_interrupt_class_v9, 413 .num_of_watch_points = 4, 414 .mqd_size_aligned = MQD_SIZE_ALIGNED, 415 .supports_cwsr = true, 416 .needs_iommu_device = false, 417 .needs_pci_atomics = false, 418 .num_sdma_engines = 1, 419 .num_xgmi_sdma_engines = 0, 420 .num_sdma_queues_per_engine = 2, 421 }; 422 423 static const struct kfd_device_info navi10_device_info = { 424 .asic_family = CHIP_NAVI10, 425 .asic_name = "navi10", 426 .gfx_target_version = 100100, 427 .max_pasid_bits = 16, 428 .max_no_of_hqd = 24, 429 .doorbell_size = 8, 430 .ih_ring_entry_size = 8 * sizeof(uint32_t), 431 .event_interrupt_class = &event_interrupt_class_v9, 432 .num_of_watch_points = 4, 433 .mqd_size_aligned = MQD_SIZE_ALIGNED, 434 .needs_iommu_device = false, 435 .supports_cwsr = true, 436 .needs_pci_atomics = true, 437 .no_atomic_fw_version = 145, 438 .num_sdma_engines = 2, 439 .num_xgmi_sdma_engines = 0, 440 .num_sdma_queues_per_engine = 8, 441 }; 442 443 static const struct kfd_device_info navi12_device_info = { 444 .asic_family = CHIP_NAVI12, 445 .asic_name = "navi12", 446 .gfx_target_version = 100101, 447 .max_pasid_bits = 16, 448 .max_no_of_hqd = 24, 449 .doorbell_size = 8, 450 .ih_ring_entry_size = 8 * sizeof(uint32_t), 451 .event_interrupt_class = &event_interrupt_class_v9, 452 .num_of_watch_points = 4, 453 .mqd_size_aligned = MQD_SIZE_ALIGNED, 454 .needs_iommu_device = false, 455 .supports_cwsr = true, 456 .needs_pci_atomics = true, 457 .no_atomic_fw_version = 145, 458 .num_sdma_engines = 2, 459 .num_xgmi_sdma_engines = 0, 460 .num_sdma_queues_per_engine = 8, 461 }; 462 463 static const struct kfd_device_info navi14_device_info = { 464 .asic_family = CHIP_NAVI14, 465 .asic_name = "navi14", 466 .gfx_target_version = 100102, 467 .max_pasid_bits = 16, 468 .max_no_of_hqd = 24, 469 .doorbell_size = 8, 470 .ih_ring_entry_size = 8 * sizeof(uint32_t), 471 .event_interrupt_class = &event_interrupt_class_v9, 472 .num_of_watch_points = 4, 473 .mqd_size_aligned = MQD_SIZE_ALIGNED, 474 .needs_iommu_device = false, 475 .supports_cwsr = true, 476 .needs_pci_atomics = true, 477 .no_atomic_fw_version = 145, 478 .num_sdma_engines = 2, 479 .num_xgmi_sdma_engines = 0, 480 .num_sdma_queues_per_engine = 8, 481 }; 482 483 static const struct kfd_device_info sienna_cichlid_device_info = { 484 .asic_family = CHIP_SIENNA_CICHLID, 485 .asic_name = "sienna_cichlid", 486 .gfx_target_version = 100300, 487 .max_pasid_bits = 16, 488 .max_no_of_hqd = 24, 489 .doorbell_size = 8, 490 .ih_ring_entry_size = 8 * sizeof(uint32_t), 491 .event_interrupt_class = &event_interrupt_class_v9, 492 .num_of_watch_points = 4, 493 .mqd_size_aligned = MQD_SIZE_ALIGNED, 494 .needs_iommu_device = false, 495 .supports_cwsr = true, 496 .needs_pci_atomics = true, 497 .no_atomic_fw_version = 92, 498 .num_sdma_engines = 4, 499 .num_xgmi_sdma_engines = 0, 500 .num_sdma_queues_per_engine = 8, 501 }; 502 503 static const struct kfd_device_info navy_flounder_device_info = { 504 .asic_family = CHIP_NAVY_FLOUNDER, 505 .asic_name = "navy_flounder", 506 .gfx_target_version = 100301, 507 .max_pasid_bits = 16, 508 .max_no_of_hqd = 24, 509 .doorbell_size = 8, 510 .ih_ring_entry_size = 8 * sizeof(uint32_t), 511 .event_interrupt_class = &event_interrupt_class_v9, 512 .num_of_watch_points = 4, 513 .mqd_size_aligned = MQD_SIZE_ALIGNED, 514 .needs_iommu_device = false, 515 .supports_cwsr = true, 516 .needs_pci_atomics = true, 517 .no_atomic_fw_version = 92, 518 .num_sdma_engines = 2, 519 .num_xgmi_sdma_engines = 0, 520 .num_sdma_queues_per_engine = 8, 521 }; 522 523 static const struct kfd_device_info vangogh_device_info = { 524 .asic_family = CHIP_VANGOGH, 525 .asic_name = "vangogh", 526 .gfx_target_version = 100303, 527 .max_pasid_bits = 16, 528 .max_no_of_hqd = 24, 529 .doorbell_size = 8, 530 .ih_ring_entry_size = 8 * sizeof(uint32_t), 531 .event_interrupt_class = &event_interrupt_class_v9, 532 .num_of_watch_points = 4, 533 .mqd_size_aligned = MQD_SIZE_ALIGNED, 534 .needs_iommu_device = false, 535 .supports_cwsr = true, 536 .needs_pci_atomics = true, 537 .no_atomic_fw_version = 92, 538 .num_sdma_engines = 1, 539 .num_xgmi_sdma_engines = 0, 540 .num_sdma_queues_per_engine = 2, 541 }; 542 543 static const struct kfd_device_info dimgrey_cavefish_device_info = { 544 .asic_family = CHIP_DIMGREY_CAVEFISH, 545 .asic_name = "dimgrey_cavefish", 546 .gfx_target_version = 100302, 547 .max_pasid_bits = 16, 548 .max_no_of_hqd = 24, 549 .doorbell_size = 8, 550 .ih_ring_entry_size = 8 * sizeof(uint32_t), 551 .event_interrupt_class = &event_interrupt_class_v9, 552 .num_of_watch_points = 4, 553 .mqd_size_aligned = MQD_SIZE_ALIGNED, 554 .needs_iommu_device = false, 555 .supports_cwsr = true, 556 .needs_pci_atomics = true, 557 .no_atomic_fw_version = 92, 558 .num_sdma_engines = 2, 559 .num_xgmi_sdma_engines = 0, 560 .num_sdma_queues_per_engine = 8, 561 }; 562 563 static const struct kfd_device_info beige_goby_device_info = { 564 .asic_family = CHIP_BEIGE_GOBY, 565 .asic_name = "beige_goby", 566 .gfx_target_version = 100304, 567 .max_pasid_bits = 16, 568 .max_no_of_hqd = 24, 569 .doorbell_size = 8, 570 .ih_ring_entry_size = 8 * sizeof(uint32_t), 571 .event_interrupt_class = &event_interrupt_class_v9, 572 .num_of_watch_points = 4, 573 .mqd_size_aligned = MQD_SIZE_ALIGNED, 574 .needs_iommu_device = false, 575 .supports_cwsr = true, 576 .needs_pci_atomics = true, 577 .no_atomic_fw_version = 92, 578 .num_sdma_engines = 1, 579 .num_xgmi_sdma_engines = 0, 580 .num_sdma_queues_per_engine = 8, 581 }; 582 583 static const struct kfd_device_info yellow_carp_device_info = { 584 .asic_family = CHIP_YELLOW_CARP, 585 .asic_name = "yellow_carp", 586 .gfx_target_version = 100305, 587 .max_pasid_bits = 16, 588 .max_no_of_hqd = 24, 589 .doorbell_size = 8, 590 .ih_ring_entry_size = 8 * sizeof(uint32_t), 591 .event_interrupt_class = &event_interrupt_class_v9, 592 .num_of_watch_points = 4, 593 .mqd_size_aligned = MQD_SIZE_ALIGNED, 594 .needs_iommu_device = false, 595 .supports_cwsr = true, 596 .needs_pci_atomics = true, 597 .no_atomic_fw_version = 92, 598 .num_sdma_engines = 1, 599 .num_xgmi_sdma_engines = 0, 600 .num_sdma_queues_per_engine = 2, 601 }; 602 603 static const struct kfd_device_info cyan_skillfish_device_info = { 604 .asic_family = CHIP_CYAN_SKILLFISH, 605 .asic_name = "cyan_skillfish", 606 .gfx_target_version = 100103, 607 .max_pasid_bits = 16, 608 .max_no_of_hqd = 24, 609 .doorbell_size = 8, 610 .ih_ring_entry_size = 8 * sizeof(uint32_t), 611 .event_interrupt_class = &event_interrupt_class_v9, 612 .num_of_watch_points = 4, 613 .mqd_size_aligned = MQD_SIZE_ALIGNED, 614 .needs_iommu_device = false, 615 .supports_cwsr = true, 616 .needs_pci_atomics = true, 617 .num_sdma_engines = 2, 618 .num_xgmi_sdma_engines = 0, 619 .num_sdma_queues_per_engine = 8, 620 }; 621 622 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 623 unsigned int chunk_size); 624 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 625 626 static int kfd_resume(struct kfd_dev *kfd); 627 628 struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, bool vf) 629 { 630 struct kfd_dev *kfd; 631 const struct kfd_device_info *device_info; 632 const struct kfd2kgd_calls *f2g; 633 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 634 struct pci_dev *pdev = adev->pdev; 635 636 switch (adev->asic_type) { 637 #ifdef KFD_SUPPORT_IOMMU_V2 638 #ifdef CONFIG_DRM_AMDGPU_CIK 639 case CHIP_KAVERI: 640 if (vf) 641 device_info = NULL; 642 else 643 device_info = &kaveri_device_info; 644 f2g = &gfx_v7_kfd2kgd; 645 break; 646 #endif 647 case CHIP_CARRIZO: 648 if (vf) 649 device_info = NULL; 650 else 651 device_info = &carrizo_device_info; 652 f2g = &gfx_v8_kfd2kgd; 653 break; 654 #endif 655 #ifdef CONFIG_DRM_AMDGPU_CIK 656 case CHIP_HAWAII: 657 if (vf) 658 device_info = NULL; 659 else 660 device_info = &hawaii_device_info; 661 f2g = &gfx_v7_kfd2kgd; 662 break; 663 #endif 664 case CHIP_TONGA: 665 if (vf) 666 device_info = NULL; 667 else 668 device_info = &tonga_device_info; 669 f2g = &gfx_v8_kfd2kgd; 670 break; 671 case CHIP_FIJI: 672 if (vf) 673 device_info = &fiji_vf_device_info; 674 else 675 device_info = &fiji_device_info; 676 f2g = &gfx_v8_kfd2kgd; 677 break; 678 case CHIP_POLARIS10: 679 if (vf) 680 device_info = &polaris10_vf_device_info; 681 else 682 device_info = &polaris10_device_info; 683 f2g = &gfx_v8_kfd2kgd; 684 break; 685 case CHIP_POLARIS11: 686 if (vf) 687 device_info = NULL; 688 else 689 device_info = &polaris11_device_info; 690 f2g = &gfx_v8_kfd2kgd; 691 break; 692 case CHIP_POLARIS12: 693 if (vf) 694 device_info = NULL; 695 else 696 device_info = &polaris12_device_info; 697 f2g = &gfx_v8_kfd2kgd; 698 break; 699 case CHIP_VEGAM: 700 if (vf) 701 device_info = NULL; 702 else 703 device_info = &vegam_device_info; 704 f2g = &gfx_v8_kfd2kgd; 705 break; 706 default: 707 switch (adev->ip_versions[GC_HWIP][0]) { 708 case IP_VERSION(9, 0, 1): 709 if (vf) 710 device_info = &vega10_vf_device_info; 711 else 712 device_info = &vega10_device_info; 713 f2g = &gfx_v9_kfd2kgd; 714 break; 715 #ifdef KFD_SUPPORT_IOMMU_V2 716 case IP_VERSION(9, 1, 0): 717 case IP_VERSION(9, 2, 2): 718 if (vf) 719 device_info = NULL; 720 else 721 device_info = &raven_device_info; 722 f2g = &gfx_v9_kfd2kgd; 723 break; 724 #endif 725 case IP_VERSION(9, 2, 1): 726 if (vf) 727 device_info = NULL; 728 else 729 device_info = &vega12_device_info; 730 f2g = &gfx_v9_kfd2kgd; 731 break; 732 case IP_VERSION(9, 3, 0): 733 if (vf) 734 device_info = NULL; 735 else 736 device_info = &renoir_device_info; 737 f2g = &gfx_v9_kfd2kgd; 738 break; 739 case IP_VERSION(9, 4, 0): 740 if (vf) 741 device_info = NULL; 742 else 743 device_info = &vega20_device_info; 744 f2g = &gfx_v9_kfd2kgd; 745 break; 746 case IP_VERSION(9, 4, 1): 747 device_info = &arcturus_device_info; 748 f2g = &arcturus_kfd2kgd; 749 break; 750 case IP_VERSION(9, 4, 2): 751 device_info = &aldebaran_device_info; 752 f2g = &aldebaran_kfd2kgd; 753 break; 754 case IP_VERSION(10, 1, 10): 755 if (vf) 756 device_info = NULL; 757 else 758 device_info = &navi10_device_info; 759 f2g = &gfx_v10_kfd2kgd; 760 break; 761 case IP_VERSION(10, 1, 2): 762 device_info = &navi12_device_info; 763 f2g = &gfx_v10_kfd2kgd; 764 break; 765 case IP_VERSION(10, 1, 1): 766 if (vf) 767 device_info = NULL; 768 else 769 device_info = &navi14_device_info; 770 f2g = &gfx_v10_kfd2kgd; 771 break; 772 case IP_VERSION(10, 1, 3): 773 if (vf) 774 device_info = NULL; 775 else 776 device_info = &cyan_skillfish_device_info; 777 f2g = &gfx_v10_kfd2kgd; 778 break; 779 case IP_VERSION(10, 3, 0): 780 device_info = &sienna_cichlid_device_info; 781 f2g = &gfx_v10_3_kfd2kgd; 782 break; 783 case IP_VERSION(10, 3, 2): 784 device_info = &navy_flounder_device_info; 785 f2g = &gfx_v10_3_kfd2kgd; 786 break; 787 case IP_VERSION(10, 3, 1): 788 if (vf) 789 device_info = NULL; 790 else 791 device_info = &vangogh_device_info; 792 f2g = &gfx_v10_3_kfd2kgd; 793 break; 794 case IP_VERSION(10, 3, 4): 795 device_info = &dimgrey_cavefish_device_info; 796 f2g = &gfx_v10_3_kfd2kgd; 797 break; 798 case IP_VERSION(10, 3, 5): 799 device_info = &beige_goby_device_info; 800 f2g = &gfx_v10_3_kfd2kgd; 801 break; 802 case IP_VERSION(10, 3, 3): 803 if (vf) 804 device_info = NULL; 805 else 806 device_info = &yellow_carp_device_info; 807 f2g = &gfx_v10_3_kfd2kgd; 808 break; 809 default: 810 return NULL; 811 } 812 break; 813 } 814 815 if (!device_info || !f2g) { 816 dev_err(kfd_device, "%s %s not supported in kfd\n", 817 amdgpu_asic_name[adev->asic_type], vf ? "VF" : ""); 818 return NULL; 819 } 820 821 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 822 if (!kfd) 823 return NULL; 824 825 kfd->kgd = kgd; 826 kfd->device_info = device_info; 827 kfd->pdev = pdev; 828 kfd->init_complete = false; 829 kfd->kfd2kgd = f2g; 830 atomic_set(&kfd->compute_profile, 0); 831 832 mutex_init(&kfd->doorbell_mutex); 833 memset(&kfd->doorbell_available_index, 0, 834 sizeof(kfd->doorbell_available_index)); 835 836 atomic_set(&kfd->sram_ecc_flag, 0); 837 838 ida_init(&kfd->doorbell_ida); 839 840 return kfd; 841 } 842 843 static void kfd_cwsr_init(struct kfd_dev *kfd) 844 { 845 if (cwsr_enable && kfd->device_info->supports_cwsr) { 846 if (kfd->device_info->asic_family < CHIP_VEGA10) { 847 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE); 848 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 849 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 850 } else if (kfd->device_info->asic_family == CHIP_ARCTURUS) { 851 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE); 852 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 853 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 854 } else if (kfd->device_info->asic_family == CHIP_ALDEBARAN) { 855 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) > PAGE_SIZE); 856 kfd->cwsr_isa = cwsr_trap_aldebaran_hex; 857 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); 858 } else if (kfd->device_info->asic_family < CHIP_NAVI10) { 859 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE); 860 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 861 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 862 } else if (kfd->device_info->asic_family < CHIP_SIENNA_CICHLID) { 863 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE); 864 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 865 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 866 } else { 867 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE); 868 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 869 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 870 } 871 872 kfd->cwsr_enabled = true; 873 } 874 } 875 876 static int kfd_gws_init(struct kfd_dev *kfd) 877 { 878 int ret = 0; 879 880 if (kfd->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 881 return 0; 882 883 if (hws_gws_support 884 || (kfd->device_info->asic_family == CHIP_VEGA10 885 && kfd->mec2_fw_version >= 0x81b3) 886 || (kfd->device_info->asic_family >= CHIP_VEGA12 887 && kfd->device_info->asic_family <= CHIP_RAVEN 888 && kfd->mec2_fw_version >= 0x1b3) 889 || (kfd->device_info->asic_family == CHIP_ARCTURUS 890 && kfd->mec2_fw_version >= 0x30) 891 || (kfd->device_info->asic_family == CHIP_ALDEBARAN 892 && kfd->mec2_fw_version >= 0x28)) 893 ret = amdgpu_amdkfd_alloc_gws(kfd->kgd, 894 amdgpu_amdkfd_get_num_gws(kfd->kgd), &kfd->gws); 895 896 return ret; 897 } 898 899 static void kfd_smi_init(struct kfd_dev *dev) { 900 INIT_LIST_HEAD(&dev->smi_clients); 901 spin_lock_init(&dev->smi_lock); 902 } 903 904 bool kgd2kfd_device_init(struct kfd_dev *kfd, 905 struct drm_device *ddev, 906 const struct kgd2kfd_shared_resources *gpu_resources) 907 { 908 unsigned int size, map_process_packet_size; 909 910 kfd->ddev = ddev; 911 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd, 912 KGD_ENGINE_MEC1); 913 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd, 914 KGD_ENGINE_MEC2); 915 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd, 916 KGD_ENGINE_SDMA1); 917 kfd->shared_resources = *gpu_resources; 918 919 kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 920 kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 921 kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd 922 - kfd->vm_info.first_vmid_kfd + 1; 923 924 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 925 * 32 and 64-bit requests are possible and must be 926 * supported. 927 */ 928 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->kgd); 929 if (!kfd->pci_atomic_requested && 930 kfd->device_info->needs_pci_atomics && 931 (!kfd->device_info->no_atomic_fw_version || 932 kfd->mec_fw_version < kfd->device_info->no_atomic_fw_version)) { 933 dev_info(kfd_device, 934 "skipped device %x:%x, PCI rejects atomics %d<%d\n", 935 kfd->pdev->vendor, kfd->pdev->device, 936 kfd->mec_fw_version, 937 kfd->device_info->no_atomic_fw_version); 938 return false; 939 } 940 941 /* Verify module parameters regarding mapped process number*/ 942 if ((hws_max_conc_proc < 0) 943 || (hws_max_conc_proc > kfd->vm_info.vmid_num_kfd)) { 944 dev_err(kfd_device, 945 "hws_max_conc_proc %d must be between 0 and %d, use %d instead\n", 946 hws_max_conc_proc, kfd->vm_info.vmid_num_kfd, 947 kfd->vm_info.vmid_num_kfd); 948 kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd; 949 } else 950 kfd->max_proc_per_quantum = hws_max_conc_proc; 951 952 /* calculate max size of mqds needed for queues */ 953 size = max_num_of_queues_per_device * 954 kfd->device_info->mqd_size_aligned; 955 956 /* 957 * calculate max size of runlist packet. 958 * There can be only 2 packets at once 959 */ 960 map_process_packet_size = 961 kfd->device_info->asic_family == CHIP_ALDEBARAN ? 962 sizeof(struct pm4_mes_map_process_aldebaran) : 963 sizeof(struct pm4_mes_map_process); 964 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + 965 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 966 + sizeof(struct pm4_mes_runlist)) * 2; 967 968 /* Add size of HIQ & DIQ */ 969 size += KFD_KERNEL_QUEUE_SIZE * 2; 970 971 /* add another 512KB for all other allocations on gart (HPD, fences) */ 972 size += 512 * 1024; 973 974 if (amdgpu_amdkfd_alloc_gtt_mem( 975 kfd->kgd, size, &kfd->gtt_mem, 976 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 977 false)) { 978 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 979 goto alloc_gtt_mem_failure; 980 } 981 982 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 983 984 /* Initialize GTT sa with 512 byte chunk size */ 985 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 986 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 987 goto kfd_gtt_sa_init_error; 988 } 989 990 if (kfd_doorbell_init(kfd)) { 991 dev_err(kfd_device, 992 "Error initializing doorbell aperture\n"); 993 goto kfd_doorbell_error; 994 } 995 996 kfd->hive_id = amdgpu_amdkfd_get_hive_id(kfd->kgd); 997 998 kfd->noretry = amdgpu_amdkfd_get_noretry(kfd->kgd); 999 1000 if (kfd_interrupt_init(kfd)) { 1001 dev_err(kfd_device, "Error initializing interrupts\n"); 1002 goto kfd_interrupt_error; 1003 } 1004 1005 kfd->dqm = device_queue_manager_init(kfd); 1006 if (!kfd->dqm) { 1007 dev_err(kfd_device, "Error initializing queue manager\n"); 1008 goto device_queue_manager_error; 1009 } 1010 1011 /* If supported on this device, allocate global GWS that is shared 1012 * by all KFD processes 1013 */ 1014 if (kfd_gws_init(kfd)) { 1015 dev_err(kfd_device, "Could not allocate %d gws\n", 1016 amdgpu_amdkfd_get_num_gws(kfd->kgd)); 1017 goto gws_error; 1018 } 1019 1020 /* If CRAT is broken, won't set iommu enabled */ 1021 kfd_double_confirm_iommu_support(kfd); 1022 1023 if (kfd_iommu_device_init(kfd)) { 1024 dev_err(kfd_device, "Error initializing iommuv2\n"); 1025 goto device_iommu_error; 1026 } 1027 1028 kfd_cwsr_init(kfd); 1029 1030 svm_migrate_init((struct amdgpu_device *)kfd->kgd); 1031 1032 if (kfd_resume(kfd)) 1033 goto kfd_resume_error; 1034 1035 kfd->dbgmgr = NULL; 1036 1037 if (kfd_topology_add_device(kfd)) { 1038 dev_err(kfd_device, "Error adding device to topology\n"); 1039 goto kfd_topology_add_device_error; 1040 } 1041 1042 kfd_smi_init(kfd); 1043 1044 kfd->init_complete = true; 1045 dev_info(kfd_device, "added device %x:%x\n", kfd->pdev->vendor, 1046 kfd->pdev->device); 1047 1048 pr_debug("Starting kfd with the following scheduling policy %d\n", 1049 kfd->dqm->sched_policy); 1050 1051 goto out; 1052 1053 kfd_topology_add_device_error: 1054 kfd_resume_error: 1055 device_iommu_error: 1056 gws_error: 1057 device_queue_manager_uninit(kfd->dqm); 1058 device_queue_manager_error: 1059 kfd_interrupt_exit(kfd); 1060 kfd_interrupt_error: 1061 kfd_doorbell_fini(kfd); 1062 kfd_doorbell_error: 1063 kfd_gtt_sa_fini(kfd); 1064 kfd_gtt_sa_init_error: 1065 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem); 1066 alloc_gtt_mem_failure: 1067 if (kfd->gws) 1068 amdgpu_amdkfd_free_gws(kfd->kgd, kfd->gws); 1069 dev_err(kfd_device, 1070 "device %x:%x NOT added due to errors\n", 1071 kfd->pdev->vendor, kfd->pdev->device); 1072 out: 1073 return kfd->init_complete; 1074 } 1075 1076 void kgd2kfd_device_exit(struct kfd_dev *kfd) 1077 { 1078 if (kfd->init_complete) { 1079 device_queue_manager_uninit(kfd->dqm); 1080 kfd_interrupt_exit(kfd); 1081 kfd_topology_remove_device(kfd); 1082 kfd_doorbell_fini(kfd); 1083 ida_destroy(&kfd->doorbell_ida); 1084 kfd_gtt_sa_fini(kfd); 1085 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem); 1086 if (kfd->gws) 1087 amdgpu_amdkfd_free_gws(kfd->kgd, kfd->gws); 1088 } 1089 1090 kfree(kfd); 1091 } 1092 1093 int kgd2kfd_pre_reset(struct kfd_dev *kfd) 1094 { 1095 if (!kfd->init_complete) 1096 return 0; 1097 1098 kfd_smi_event_update_gpu_reset(kfd, false); 1099 1100 kfd->dqm->ops.pre_reset(kfd->dqm); 1101 1102 kgd2kfd_suspend(kfd, false); 1103 1104 kfd_signal_reset_event(kfd); 1105 return 0; 1106 } 1107 1108 /* 1109 * Fix me. KFD won't be able to resume existing process for now. 1110 * We will keep all existing process in a evicted state and 1111 * wait the process to be terminated. 1112 */ 1113 1114 int kgd2kfd_post_reset(struct kfd_dev *kfd) 1115 { 1116 int ret; 1117 1118 if (!kfd->init_complete) 1119 return 0; 1120 1121 ret = kfd_resume(kfd); 1122 if (ret) 1123 return ret; 1124 atomic_dec(&kfd_locked); 1125 1126 atomic_set(&kfd->sram_ecc_flag, 0); 1127 1128 kfd_smi_event_update_gpu_reset(kfd, true); 1129 1130 return 0; 1131 } 1132 1133 bool kfd_is_locked(void) 1134 { 1135 return (atomic_read(&kfd_locked) > 0); 1136 } 1137 1138 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 1139 { 1140 if (!kfd->init_complete) 1141 return; 1142 1143 /* for runtime suspend, skip locking kfd */ 1144 if (!run_pm) { 1145 /* For first KFD device suspend all the KFD processes */ 1146 if (atomic_inc_return(&kfd_locked) == 1) 1147 kfd_suspend_all_processes(); 1148 } 1149 1150 kfd->dqm->ops.stop(kfd->dqm); 1151 kfd_iommu_suspend(kfd); 1152 } 1153 1154 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 1155 { 1156 int ret, count; 1157 1158 if (!kfd->init_complete) 1159 return 0; 1160 1161 ret = kfd_resume(kfd); 1162 if (ret) 1163 return ret; 1164 1165 /* for runtime resume, skip unlocking kfd */ 1166 if (!run_pm) { 1167 count = atomic_dec_return(&kfd_locked); 1168 WARN_ONCE(count < 0, "KFD suspend / resume ref. error"); 1169 if (count == 0) 1170 ret = kfd_resume_all_processes(); 1171 } 1172 1173 return ret; 1174 } 1175 1176 int kgd2kfd_resume_iommu(struct kfd_dev *kfd) 1177 { 1178 int err = 0; 1179 1180 err = kfd_iommu_resume(kfd); 1181 if (err) 1182 dev_err(kfd_device, 1183 "Failed to resume IOMMU for device %x:%x\n", 1184 kfd->pdev->vendor, kfd->pdev->device); 1185 return err; 1186 } 1187 1188 static int kfd_resume(struct kfd_dev *kfd) 1189 { 1190 int err = 0; 1191 1192 err = kfd->dqm->ops.start(kfd->dqm); 1193 if (err) 1194 dev_err(kfd_device, 1195 "Error starting queue manager for device %x:%x\n", 1196 kfd->pdev->vendor, kfd->pdev->device); 1197 1198 return err; 1199 } 1200 1201 static inline void kfd_queue_work(struct workqueue_struct *wq, 1202 struct work_struct *work) 1203 { 1204 int cpu, new_cpu; 1205 1206 cpu = new_cpu = smp_processor_id(); 1207 do { 1208 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids; 1209 if (cpu_to_node(new_cpu) == numa_node_id()) 1210 break; 1211 } while (cpu != new_cpu); 1212 1213 queue_work_on(new_cpu, wq, work); 1214 } 1215 1216 /* This is called directly from KGD at ISR. */ 1217 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 1218 { 1219 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE]; 1220 bool is_patched = false; 1221 unsigned long flags; 1222 1223 if (!kfd->init_complete) 1224 return; 1225 1226 if (kfd->device_info->ih_ring_entry_size > sizeof(patched_ihre)) { 1227 dev_err_once(kfd_device, "Ring entry too small\n"); 1228 return; 1229 } 1230 1231 spin_lock_irqsave(&kfd->interrupt_lock, flags); 1232 1233 if (kfd->interrupts_active 1234 && interrupt_is_wanted(kfd, ih_ring_entry, 1235 patched_ihre, &is_patched) 1236 && enqueue_ih_ring_entry(kfd, 1237 is_patched ? patched_ihre : ih_ring_entry)) 1238 kfd_queue_work(kfd->ih_wq, &kfd->interrupt_work); 1239 1240 spin_unlock_irqrestore(&kfd->interrupt_lock, flags); 1241 } 1242 1243 int kgd2kfd_quiesce_mm(struct mm_struct *mm) 1244 { 1245 struct kfd_process *p; 1246 int r; 1247 1248 /* Because we are called from arbitrary context (workqueue) as opposed 1249 * to process context, kfd_process could attempt to exit while we are 1250 * running so the lookup function increments the process ref count. 1251 */ 1252 p = kfd_lookup_process_by_mm(mm); 1253 if (!p) 1254 return -ESRCH; 1255 1256 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 1257 r = kfd_process_evict_queues(p); 1258 1259 kfd_unref_process(p); 1260 return r; 1261 } 1262 1263 int kgd2kfd_resume_mm(struct mm_struct *mm) 1264 { 1265 struct kfd_process *p; 1266 int r; 1267 1268 /* Because we are called from arbitrary context (workqueue) as opposed 1269 * to process context, kfd_process could attempt to exit while we are 1270 * running so the lookup function increments the process ref count. 1271 */ 1272 p = kfd_lookup_process_by_mm(mm); 1273 if (!p) 1274 return -ESRCH; 1275 1276 r = kfd_process_restore_queues(p); 1277 1278 kfd_unref_process(p); 1279 return r; 1280 } 1281 1282 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 1283 * prepare for safe eviction of KFD BOs that belong to the specified 1284 * process. 1285 * 1286 * @mm: mm_struct that identifies the specified KFD process 1287 * @fence: eviction fence attached to KFD process BOs 1288 * 1289 */ 1290 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 1291 struct dma_fence *fence) 1292 { 1293 struct kfd_process *p; 1294 unsigned long active_time; 1295 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 1296 1297 if (!fence) 1298 return -EINVAL; 1299 1300 if (dma_fence_is_signaled(fence)) 1301 return 0; 1302 1303 p = kfd_lookup_process_by_mm(mm); 1304 if (!p) 1305 return -ENODEV; 1306 1307 if (fence->seqno == p->last_eviction_seqno) 1308 goto out; 1309 1310 p->last_eviction_seqno = fence->seqno; 1311 1312 /* Avoid KFD process starvation. Wait for at least 1313 * PROCESS_ACTIVE_TIME_MS before evicting the process again 1314 */ 1315 active_time = get_jiffies_64() - p->last_restore_timestamp; 1316 if (delay_jiffies > active_time) 1317 delay_jiffies -= active_time; 1318 else 1319 delay_jiffies = 0; 1320 1321 /* During process initialization eviction_work.dwork is initialized 1322 * to kfd_evict_bo_worker 1323 */ 1324 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 1325 p->lead_thread->pid, delay_jiffies); 1326 schedule_delayed_work(&p->eviction_work, delay_jiffies); 1327 out: 1328 kfd_unref_process(p); 1329 return 0; 1330 } 1331 1332 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 1333 unsigned int chunk_size) 1334 { 1335 unsigned int num_of_longs; 1336 1337 if (WARN_ON(buf_size < chunk_size)) 1338 return -EINVAL; 1339 if (WARN_ON(buf_size == 0)) 1340 return -EINVAL; 1341 if (WARN_ON(chunk_size == 0)) 1342 return -EINVAL; 1343 1344 kfd->gtt_sa_chunk_size = chunk_size; 1345 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 1346 1347 num_of_longs = (kfd->gtt_sa_num_of_chunks + BITS_PER_LONG - 1) / 1348 BITS_PER_LONG; 1349 1350 kfd->gtt_sa_bitmap = kcalloc(num_of_longs, sizeof(long), GFP_KERNEL); 1351 1352 if (!kfd->gtt_sa_bitmap) 1353 return -ENOMEM; 1354 1355 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 1356 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 1357 1358 mutex_init(&kfd->gtt_sa_lock); 1359 1360 return 0; 1361 1362 } 1363 1364 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 1365 { 1366 mutex_destroy(&kfd->gtt_sa_lock); 1367 kfree(kfd->gtt_sa_bitmap); 1368 } 1369 1370 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 1371 unsigned int bit_num, 1372 unsigned int chunk_size) 1373 { 1374 return start_addr + bit_num * chunk_size; 1375 } 1376 1377 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 1378 unsigned int bit_num, 1379 unsigned int chunk_size) 1380 { 1381 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 1382 } 1383 1384 int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size, 1385 struct kfd_mem_obj **mem_obj) 1386 { 1387 unsigned int found, start_search, cur_size; 1388 1389 if (size == 0) 1390 return -EINVAL; 1391 1392 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 1393 return -ENOMEM; 1394 1395 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 1396 if (!(*mem_obj)) 1397 return -ENOMEM; 1398 1399 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 1400 1401 start_search = 0; 1402 1403 mutex_lock(&kfd->gtt_sa_lock); 1404 1405 kfd_gtt_restart_search: 1406 /* Find the first chunk that is free */ 1407 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1408 kfd->gtt_sa_num_of_chunks, 1409 start_search); 1410 1411 pr_debug("Found = %d\n", found); 1412 1413 /* If there wasn't any free chunk, bail out */ 1414 if (found == kfd->gtt_sa_num_of_chunks) 1415 goto kfd_gtt_no_free_chunk; 1416 1417 /* Update fields of mem_obj */ 1418 (*mem_obj)->range_start = found; 1419 (*mem_obj)->range_end = found; 1420 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1421 kfd->gtt_start_gpu_addr, 1422 found, 1423 kfd->gtt_sa_chunk_size); 1424 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1425 kfd->gtt_start_cpu_ptr, 1426 found, 1427 kfd->gtt_sa_chunk_size); 1428 1429 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1430 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1431 1432 /* If we need only one chunk, mark it as allocated and get out */ 1433 if (size <= kfd->gtt_sa_chunk_size) { 1434 pr_debug("Single bit\n"); 1435 set_bit(found, kfd->gtt_sa_bitmap); 1436 goto kfd_gtt_out; 1437 } 1438 1439 /* Otherwise, try to see if we have enough contiguous chunks */ 1440 cur_size = size - kfd->gtt_sa_chunk_size; 1441 do { 1442 (*mem_obj)->range_end = 1443 find_next_zero_bit(kfd->gtt_sa_bitmap, 1444 kfd->gtt_sa_num_of_chunks, ++found); 1445 /* 1446 * If next free chunk is not contiguous than we need to 1447 * restart our search from the last free chunk we found (which 1448 * wasn't contiguous to the previous ones 1449 */ 1450 if ((*mem_obj)->range_end != found) { 1451 start_search = found; 1452 goto kfd_gtt_restart_search; 1453 } 1454 1455 /* 1456 * If we reached end of buffer, bail out with error 1457 */ 1458 if (found == kfd->gtt_sa_num_of_chunks) 1459 goto kfd_gtt_no_free_chunk; 1460 1461 /* Check if we don't need another chunk */ 1462 if (cur_size <= kfd->gtt_sa_chunk_size) 1463 cur_size = 0; 1464 else 1465 cur_size -= kfd->gtt_sa_chunk_size; 1466 1467 } while (cur_size > 0); 1468 1469 pr_debug("range_start = %d, range_end = %d\n", 1470 (*mem_obj)->range_start, (*mem_obj)->range_end); 1471 1472 /* Mark the chunks as allocated */ 1473 for (found = (*mem_obj)->range_start; 1474 found <= (*mem_obj)->range_end; 1475 found++) 1476 set_bit(found, kfd->gtt_sa_bitmap); 1477 1478 kfd_gtt_out: 1479 mutex_unlock(&kfd->gtt_sa_lock); 1480 return 0; 1481 1482 kfd_gtt_no_free_chunk: 1483 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1484 mutex_unlock(&kfd->gtt_sa_lock); 1485 kfree(*mem_obj); 1486 return -ENOMEM; 1487 } 1488 1489 int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj) 1490 { 1491 unsigned int bit; 1492 1493 /* Act like kfree when trying to free a NULL object */ 1494 if (!mem_obj) 1495 return 0; 1496 1497 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1498 mem_obj, mem_obj->range_start, mem_obj->range_end); 1499 1500 mutex_lock(&kfd->gtt_sa_lock); 1501 1502 /* Mark the chunks as free */ 1503 for (bit = mem_obj->range_start; 1504 bit <= mem_obj->range_end; 1505 bit++) 1506 clear_bit(bit, kfd->gtt_sa_bitmap); 1507 1508 mutex_unlock(&kfd->gtt_sa_lock); 1509 1510 kfree(mem_obj); 1511 return 0; 1512 } 1513 1514 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1515 { 1516 if (kfd) 1517 atomic_inc(&kfd->sram_ecc_flag); 1518 } 1519 1520 void kfd_inc_compute_active(struct kfd_dev *kfd) 1521 { 1522 if (atomic_inc_return(&kfd->compute_profile) == 1) 1523 amdgpu_amdkfd_set_compute_idle(kfd->kgd, false); 1524 } 1525 1526 void kfd_dec_compute_active(struct kfd_dev *kfd) 1527 { 1528 int count = atomic_dec_return(&kfd->compute_profile); 1529 1530 if (count == 0) 1531 amdgpu_amdkfd_set_compute_idle(kfd->kgd, true); 1532 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1533 } 1534 1535 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 1536 { 1537 if (kfd && kfd->init_complete) 1538 kfd_smi_event_update_thermal_throttling(kfd, throttle_bitmask); 1539 } 1540 1541 #if defined(CONFIG_DEBUG_FS) 1542 1543 /* This function will send a package to HIQ to hang the HWS 1544 * which will trigger a GPU reset and bring the HWS back to normal state 1545 */ 1546 int kfd_debugfs_hang_hws(struct kfd_dev *dev) 1547 { 1548 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1549 pr_err("HWS is not enabled"); 1550 return -EINVAL; 1551 } 1552 1553 return dqm_debugfs_hang_hws(dev->dqm); 1554 } 1555 1556 #endif 1557