1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/bsearch.h> 24 #include <linux/pci.h> 25 #include <linux/slab.h> 26 #include "kfd_priv.h" 27 #include "kfd_device_queue_manager.h" 28 #include "kfd_pm4_headers_vi.h" 29 #include "cwsr_trap_handler.h" 30 #include "kfd_iommu.h" 31 #include "amdgpu_amdkfd.h" 32 33 #define MQD_SIZE_ALIGNED 768 34 35 /* 36 * kfd_locked is used to lock the kfd driver during suspend or reset 37 * once locked, kfd driver will stop any further GPU execution. 38 * create process (open) will return -EAGAIN. 39 */ 40 static atomic_t kfd_locked = ATOMIC_INIT(0); 41 42 #ifdef KFD_SUPPORT_IOMMU_V2 43 static const struct kfd_device_info kaveri_device_info = { 44 .asic_family = CHIP_KAVERI, 45 .max_pasid_bits = 16, 46 /* max num of queues for KV.TODO should be a dynamic value */ 47 .max_no_of_hqd = 24, 48 .doorbell_size = 4, 49 .ih_ring_entry_size = 4 * sizeof(uint32_t), 50 .event_interrupt_class = &event_interrupt_class_cik, 51 .num_of_watch_points = 4, 52 .mqd_size_aligned = MQD_SIZE_ALIGNED, 53 .supports_cwsr = false, 54 .needs_iommu_device = true, 55 .needs_pci_atomics = false, 56 .num_sdma_engines = 2, 57 .num_sdma_queues_per_engine = 2, 58 }; 59 60 static const struct kfd_device_info carrizo_device_info = { 61 .asic_family = CHIP_CARRIZO, 62 .max_pasid_bits = 16, 63 /* max num of queues for CZ.TODO should be a dynamic value */ 64 .max_no_of_hqd = 24, 65 .doorbell_size = 4, 66 .ih_ring_entry_size = 4 * sizeof(uint32_t), 67 .event_interrupt_class = &event_interrupt_class_cik, 68 .num_of_watch_points = 4, 69 .mqd_size_aligned = MQD_SIZE_ALIGNED, 70 .supports_cwsr = true, 71 .needs_iommu_device = true, 72 .needs_pci_atomics = false, 73 .num_sdma_engines = 2, 74 .num_sdma_queues_per_engine = 2, 75 }; 76 77 static const struct kfd_device_info raven_device_info = { 78 .asic_family = CHIP_RAVEN, 79 .max_pasid_bits = 16, 80 .max_no_of_hqd = 24, 81 .doorbell_size = 8, 82 .ih_ring_entry_size = 8 * sizeof(uint32_t), 83 .event_interrupt_class = &event_interrupt_class_v9, 84 .num_of_watch_points = 4, 85 .mqd_size_aligned = MQD_SIZE_ALIGNED, 86 .supports_cwsr = true, 87 .needs_iommu_device = true, 88 .needs_pci_atomics = true, 89 .num_sdma_engines = 1, 90 .num_sdma_queues_per_engine = 2, 91 }; 92 #endif 93 94 static const struct kfd_device_info hawaii_device_info = { 95 .asic_family = CHIP_HAWAII, 96 .max_pasid_bits = 16, 97 /* max num of queues for KV.TODO should be a dynamic value */ 98 .max_no_of_hqd = 24, 99 .doorbell_size = 4, 100 .ih_ring_entry_size = 4 * sizeof(uint32_t), 101 .event_interrupt_class = &event_interrupt_class_cik, 102 .num_of_watch_points = 4, 103 .mqd_size_aligned = MQD_SIZE_ALIGNED, 104 .supports_cwsr = false, 105 .needs_iommu_device = false, 106 .needs_pci_atomics = false, 107 .num_sdma_engines = 2, 108 .num_sdma_queues_per_engine = 2, 109 }; 110 111 static const struct kfd_device_info tonga_device_info = { 112 .asic_family = CHIP_TONGA, 113 .max_pasid_bits = 16, 114 .max_no_of_hqd = 24, 115 .doorbell_size = 4, 116 .ih_ring_entry_size = 4 * sizeof(uint32_t), 117 .event_interrupt_class = &event_interrupt_class_cik, 118 .num_of_watch_points = 4, 119 .mqd_size_aligned = MQD_SIZE_ALIGNED, 120 .supports_cwsr = false, 121 .needs_iommu_device = false, 122 .needs_pci_atomics = true, 123 .num_sdma_engines = 2, 124 .num_sdma_queues_per_engine = 2, 125 }; 126 127 static const struct kfd_device_info fiji_device_info = { 128 .asic_family = CHIP_FIJI, 129 .max_pasid_bits = 16, 130 .max_no_of_hqd = 24, 131 .doorbell_size = 4, 132 .ih_ring_entry_size = 4 * sizeof(uint32_t), 133 .event_interrupt_class = &event_interrupt_class_cik, 134 .num_of_watch_points = 4, 135 .mqd_size_aligned = MQD_SIZE_ALIGNED, 136 .supports_cwsr = true, 137 .needs_iommu_device = false, 138 .needs_pci_atomics = true, 139 .num_sdma_engines = 2, 140 .num_sdma_queues_per_engine = 2, 141 }; 142 143 static const struct kfd_device_info fiji_vf_device_info = { 144 .asic_family = CHIP_FIJI, 145 .max_pasid_bits = 16, 146 .max_no_of_hqd = 24, 147 .doorbell_size = 4, 148 .ih_ring_entry_size = 4 * sizeof(uint32_t), 149 .event_interrupt_class = &event_interrupt_class_cik, 150 .num_of_watch_points = 4, 151 .mqd_size_aligned = MQD_SIZE_ALIGNED, 152 .supports_cwsr = true, 153 .needs_iommu_device = false, 154 .needs_pci_atomics = false, 155 .num_sdma_engines = 2, 156 .num_sdma_queues_per_engine = 2, 157 }; 158 159 160 static const struct kfd_device_info polaris10_device_info = { 161 .asic_family = CHIP_POLARIS10, 162 .max_pasid_bits = 16, 163 .max_no_of_hqd = 24, 164 .doorbell_size = 4, 165 .ih_ring_entry_size = 4 * sizeof(uint32_t), 166 .event_interrupt_class = &event_interrupt_class_cik, 167 .num_of_watch_points = 4, 168 .mqd_size_aligned = MQD_SIZE_ALIGNED, 169 .supports_cwsr = true, 170 .needs_iommu_device = false, 171 .needs_pci_atomics = true, 172 .num_sdma_engines = 2, 173 .num_sdma_queues_per_engine = 2, 174 }; 175 176 static const struct kfd_device_info polaris10_vf_device_info = { 177 .asic_family = CHIP_POLARIS10, 178 .max_pasid_bits = 16, 179 .max_no_of_hqd = 24, 180 .doorbell_size = 4, 181 .ih_ring_entry_size = 4 * sizeof(uint32_t), 182 .event_interrupt_class = &event_interrupt_class_cik, 183 .num_of_watch_points = 4, 184 .mqd_size_aligned = MQD_SIZE_ALIGNED, 185 .supports_cwsr = true, 186 .needs_iommu_device = false, 187 .needs_pci_atomics = false, 188 .num_sdma_engines = 2, 189 .num_sdma_queues_per_engine = 2, 190 }; 191 192 static const struct kfd_device_info polaris11_device_info = { 193 .asic_family = CHIP_POLARIS11, 194 .max_pasid_bits = 16, 195 .max_no_of_hqd = 24, 196 .doorbell_size = 4, 197 .ih_ring_entry_size = 4 * sizeof(uint32_t), 198 .event_interrupt_class = &event_interrupt_class_cik, 199 .num_of_watch_points = 4, 200 .mqd_size_aligned = MQD_SIZE_ALIGNED, 201 .supports_cwsr = true, 202 .needs_iommu_device = false, 203 .needs_pci_atomics = true, 204 .num_sdma_engines = 2, 205 .num_sdma_queues_per_engine = 2, 206 }; 207 208 static const struct kfd_device_info polaris12_device_info = { 209 .asic_family = CHIP_POLARIS12, 210 .max_pasid_bits = 16, 211 .max_no_of_hqd = 24, 212 .doorbell_size = 4, 213 .ih_ring_entry_size = 4 * sizeof(uint32_t), 214 .event_interrupt_class = &event_interrupt_class_cik, 215 .num_of_watch_points = 4, 216 .mqd_size_aligned = MQD_SIZE_ALIGNED, 217 .supports_cwsr = true, 218 .needs_iommu_device = false, 219 .needs_pci_atomics = true, 220 .num_sdma_engines = 2, 221 .num_sdma_queues_per_engine = 2, 222 }; 223 224 static const struct kfd_device_info vega10_device_info = { 225 .asic_family = CHIP_VEGA10, 226 .max_pasid_bits = 16, 227 .max_no_of_hqd = 24, 228 .doorbell_size = 8, 229 .ih_ring_entry_size = 8 * sizeof(uint32_t), 230 .event_interrupt_class = &event_interrupt_class_v9, 231 .num_of_watch_points = 4, 232 .mqd_size_aligned = MQD_SIZE_ALIGNED, 233 .supports_cwsr = true, 234 .needs_iommu_device = false, 235 .needs_pci_atomics = false, 236 .num_sdma_engines = 2, 237 .num_sdma_queues_per_engine = 2, 238 }; 239 240 static const struct kfd_device_info vega10_vf_device_info = { 241 .asic_family = CHIP_VEGA10, 242 .max_pasid_bits = 16, 243 .max_no_of_hqd = 24, 244 .doorbell_size = 8, 245 .ih_ring_entry_size = 8 * sizeof(uint32_t), 246 .event_interrupt_class = &event_interrupt_class_v9, 247 .num_of_watch_points = 4, 248 .mqd_size_aligned = MQD_SIZE_ALIGNED, 249 .supports_cwsr = true, 250 .needs_iommu_device = false, 251 .needs_pci_atomics = false, 252 .num_sdma_engines = 2, 253 .num_sdma_queues_per_engine = 2, 254 }; 255 256 static const struct kfd_device_info vega12_device_info = { 257 .asic_family = CHIP_VEGA12, 258 .max_pasid_bits = 16, 259 .max_no_of_hqd = 24, 260 .doorbell_size = 8, 261 .ih_ring_entry_size = 8 * sizeof(uint32_t), 262 .event_interrupt_class = &event_interrupt_class_v9, 263 .num_of_watch_points = 4, 264 .mqd_size_aligned = MQD_SIZE_ALIGNED, 265 .supports_cwsr = true, 266 .needs_iommu_device = false, 267 .needs_pci_atomics = false, 268 .num_sdma_engines = 2, 269 .num_sdma_queues_per_engine = 2, 270 }; 271 272 static const struct kfd_device_info vega20_device_info = { 273 .asic_family = CHIP_VEGA20, 274 .max_pasid_bits = 16, 275 .max_no_of_hqd = 24, 276 .doorbell_size = 8, 277 .ih_ring_entry_size = 8 * sizeof(uint32_t), 278 .event_interrupt_class = &event_interrupt_class_v9, 279 .num_of_watch_points = 4, 280 .mqd_size_aligned = MQD_SIZE_ALIGNED, 281 .supports_cwsr = true, 282 .needs_iommu_device = false, 283 .needs_pci_atomics = false, 284 .num_sdma_engines = 2, 285 .num_sdma_queues_per_engine = 8, 286 }; 287 288 struct kfd_deviceid { 289 unsigned short did; 290 const struct kfd_device_info *device_info; 291 }; 292 293 static const struct kfd_deviceid supported_devices[] = { 294 #ifdef KFD_SUPPORT_IOMMU_V2 295 { 0x1304, &kaveri_device_info }, /* Kaveri */ 296 { 0x1305, &kaveri_device_info }, /* Kaveri */ 297 { 0x1306, &kaveri_device_info }, /* Kaveri */ 298 { 0x1307, &kaveri_device_info }, /* Kaveri */ 299 { 0x1309, &kaveri_device_info }, /* Kaveri */ 300 { 0x130A, &kaveri_device_info }, /* Kaveri */ 301 { 0x130B, &kaveri_device_info }, /* Kaveri */ 302 { 0x130C, &kaveri_device_info }, /* Kaveri */ 303 { 0x130D, &kaveri_device_info }, /* Kaveri */ 304 { 0x130E, &kaveri_device_info }, /* Kaveri */ 305 { 0x130F, &kaveri_device_info }, /* Kaveri */ 306 { 0x1310, &kaveri_device_info }, /* Kaveri */ 307 { 0x1311, &kaveri_device_info }, /* Kaveri */ 308 { 0x1312, &kaveri_device_info }, /* Kaveri */ 309 { 0x1313, &kaveri_device_info }, /* Kaveri */ 310 { 0x1315, &kaveri_device_info }, /* Kaveri */ 311 { 0x1316, &kaveri_device_info }, /* Kaveri */ 312 { 0x1317, &kaveri_device_info }, /* Kaveri */ 313 { 0x1318, &kaveri_device_info }, /* Kaveri */ 314 { 0x131B, &kaveri_device_info }, /* Kaveri */ 315 { 0x131C, &kaveri_device_info }, /* Kaveri */ 316 { 0x131D, &kaveri_device_info }, /* Kaveri */ 317 { 0x9870, &carrizo_device_info }, /* Carrizo */ 318 { 0x9874, &carrizo_device_info }, /* Carrizo */ 319 { 0x9875, &carrizo_device_info }, /* Carrizo */ 320 { 0x9876, &carrizo_device_info }, /* Carrizo */ 321 { 0x9877, &carrizo_device_info }, /* Carrizo */ 322 { 0x15DD, &raven_device_info }, /* Raven */ 323 #endif 324 { 0x67A0, &hawaii_device_info }, /* Hawaii */ 325 { 0x67A1, &hawaii_device_info }, /* Hawaii */ 326 { 0x67A2, &hawaii_device_info }, /* Hawaii */ 327 { 0x67A8, &hawaii_device_info }, /* Hawaii */ 328 { 0x67A9, &hawaii_device_info }, /* Hawaii */ 329 { 0x67AA, &hawaii_device_info }, /* Hawaii */ 330 { 0x67B0, &hawaii_device_info }, /* Hawaii */ 331 { 0x67B1, &hawaii_device_info }, /* Hawaii */ 332 { 0x67B8, &hawaii_device_info }, /* Hawaii */ 333 { 0x67B9, &hawaii_device_info }, /* Hawaii */ 334 { 0x67BA, &hawaii_device_info }, /* Hawaii */ 335 { 0x67BE, &hawaii_device_info }, /* Hawaii */ 336 { 0x6920, &tonga_device_info }, /* Tonga */ 337 { 0x6921, &tonga_device_info }, /* Tonga */ 338 { 0x6928, &tonga_device_info }, /* Tonga */ 339 { 0x6929, &tonga_device_info }, /* Tonga */ 340 { 0x692B, &tonga_device_info }, /* Tonga */ 341 { 0x6938, &tonga_device_info }, /* Tonga */ 342 { 0x6939, &tonga_device_info }, /* Tonga */ 343 { 0x7300, &fiji_device_info }, /* Fiji */ 344 { 0x730F, &fiji_vf_device_info }, /* Fiji vf*/ 345 { 0x67C0, &polaris10_device_info }, /* Polaris10 */ 346 { 0x67C1, &polaris10_device_info }, /* Polaris10 */ 347 { 0x67C2, &polaris10_device_info }, /* Polaris10 */ 348 { 0x67C4, &polaris10_device_info }, /* Polaris10 */ 349 { 0x67C7, &polaris10_device_info }, /* Polaris10 */ 350 { 0x67C8, &polaris10_device_info }, /* Polaris10 */ 351 { 0x67C9, &polaris10_device_info }, /* Polaris10 */ 352 { 0x67CA, &polaris10_device_info }, /* Polaris10 */ 353 { 0x67CC, &polaris10_device_info }, /* Polaris10 */ 354 { 0x67CF, &polaris10_device_info }, /* Polaris10 */ 355 { 0x67D0, &polaris10_vf_device_info }, /* Polaris10 vf*/ 356 { 0x67DF, &polaris10_device_info }, /* Polaris10 */ 357 { 0x67E0, &polaris11_device_info }, /* Polaris11 */ 358 { 0x67E1, &polaris11_device_info }, /* Polaris11 */ 359 { 0x67E3, &polaris11_device_info }, /* Polaris11 */ 360 { 0x67E7, &polaris11_device_info }, /* Polaris11 */ 361 { 0x67E8, &polaris11_device_info }, /* Polaris11 */ 362 { 0x67E9, &polaris11_device_info }, /* Polaris11 */ 363 { 0x67EB, &polaris11_device_info }, /* Polaris11 */ 364 { 0x67EF, &polaris11_device_info }, /* Polaris11 */ 365 { 0x67FF, &polaris11_device_info }, /* Polaris11 */ 366 { 0x6980, &polaris12_device_info }, /* Polaris12 */ 367 { 0x6981, &polaris12_device_info }, /* Polaris12 */ 368 { 0x6985, &polaris12_device_info }, /* Polaris12 */ 369 { 0x6986, &polaris12_device_info }, /* Polaris12 */ 370 { 0x6987, &polaris12_device_info }, /* Polaris12 */ 371 { 0x6995, &polaris12_device_info }, /* Polaris12 */ 372 { 0x6997, &polaris12_device_info }, /* Polaris12 */ 373 { 0x699F, &polaris12_device_info }, /* Polaris12 */ 374 { 0x6860, &vega10_device_info }, /* Vega10 */ 375 { 0x6861, &vega10_device_info }, /* Vega10 */ 376 { 0x6862, &vega10_device_info }, /* Vega10 */ 377 { 0x6863, &vega10_device_info }, /* Vega10 */ 378 { 0x6864, &vega10_device_info }, /* Vega10 */ 379 { 0x6867, &vega10_device_info }, /* Vega10 */ 380 { 0x6868, &vega10_device_info }, /* Vega10 */ 381 { 0x6869, &vega10_device_info }, /* Vega10 */ 382 { 0x686A, &vega10_device_info }, /* Vega10 */ 383 { 0x686B, &vega10_device_info }, /* Vega10 */ 384 { 0x686C, &vega10_vf_device_info }, /* Vega10 vf*/ 385 { 0x686D, &vega10_device_info }, /* Vega10 */ 386 { 0x686E, &vega10_device_info }, /* Vega10 */ 387 { 0x686F, &vega10_device_info }, /* Vega10 */ 388 { 0x687F, &vega10_device_info }, /* Vega10 */ 389 { 0x69A0, &vega12_device_info }, /* Vega12 */ 390 { 0x69A1, &vega12_device_info }, /* Vega12 */ 391 { 0x69A2, &vega12_device_info }, /* Vega12 */ 392 { 0x69A3, &vega12_device_info }, /* Vega12 */ 393 { 0x69AF, &vega12_device_info }, /* Vega12 */ 394 { 0x66a0, &vega20_device_info }, /* Vega20 */ 395 { 0x66a1, &vega20_device_info }, /* Vega20 */ 396 { 0x66a2, &vega20_device_info }, /* Vega20 */ 397 { 0x66a3, &vega20_device_info }, /* Vega20 */ 398 { 0x66a4, &vega20_device_info }, /* Vega20 */ 399 { 0x66a7, &vega20_device_info }, /* Vega20 */ 400 { 0x66af, &vega20_device_info } /* Vega20 */ 401 }; 402 403 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 404 unsigned int chunk_size); 405 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 406 407 static int kfd_resume(struct kfd_dev *kfd); 408 409 static const struct kfd_device_info *lookup_device_info(unsigned short did) 410 { 411 size_t i; 412 413 for (i = 0; i < ARRAY_SIZE(supported_devices); i++) { 414 if (supported_devices[i].did == did) { 415 WARN_ON(!supported_devices[i].device_info); 416 return supported_devices[i].device_info; 417 } 418 } 419 420 dev_warn(kfd_device, "DID %04x is missing in supported_devices\n", 421 did); 422 423 return NULL; 424 } 425 426 struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, 427 struct pci_dev *pdev, const struct kfd2kgd_calls *f2g) 428 { 429 struct kfd_dev *kfd; 430 int ret; 431 const struct kfd_device_info *device_info = 432 lookup_device_info(pdev->device); 433 434 if (!device_info) { 435 dev_err(kfd_device, "kgd2kfd_probe failed\n"); 436 return NULL; 437 } 438 439 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 440 if (!kfd) 441 return NULL; 442 443 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 444 * 32 and 64-bit requests are possible and must be 445 * supported. 446 */ 447 ret = pci_enable_atomic_ops_to_root(pdev, 448 PCI_EXP_DEVCAP2_ATOMIC_COMP32 | 449 PCI_EXP_DEVCAP2_ATOMIC_COMP64); 450 if (device_info->needs_pci_atomics && ret < 0) { 451 dev_info(kfd_device, 452 "skipped device %x:%x, PCI rejects atomics\n", 453 pdev->vendor, pdev->device); 454 kfree(kfd); 455 return NULL; 456 } else if (!ret) 457 kfd->pci_atomic_requested = true; 458 459 kfd->kgd = kgd; 460 kfd->device_info = device_info; 461 kfd->pdev = pdev; 462 kfd->init_complete = false; 463 kfd->kfd2kgd = f2g; 464 465 mutex_init(&kfd->doorbell_mutex); 466 memset(&kfd->doorbell_available_index, 0, 467 sizeof(kfd->doorbell_available_index)); 468 469 atomic_set(&kfd->sram_ecc_flag, 0); 470 471 return kfd; 472 } 473 474 static void kfd_cwsr_init(struct kfd_dev *kfd) 475 { 476 if (cwsr_enable && kfd->device_info->supports_cwsr) { 477 if (kfd->device_info->asic_family < CHIP_VEGA10) { 478 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE); 479 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 480 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 481 } else { 482 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE); 483 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 484 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 485 } 486 487 kfd->cwsr_enabled = true; 488 } 489 } 490 491 bool kgd2kfd_device_init(struct kfd_dev *kfd, 492 const struct kgd2kfd_shared_resources *gpu_resources) 493 { 494 unsigned int size; 495 496 kfd->mec_fw_version = kfd->kfd2kgd->get_fw_version(kfd->kgd, 497 KGD_ENGINE_MEC1); 498 kfd->sdma_fw_version = kfd->kfd2kgd->get_fw_version(kfd->kgd, 499 KGD_ENGINE_SDMA1); 500 kfd->shared_resources = *gpu_resources; 501 502 kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 503 kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 504 kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd 505 - kfd->vm_info.first_vmid_kfd + 1; 506 507 /* Verify module parameters regarding mapped process number*/ 508 if ((hws_max_conc_proc < 0) 509 || (hws_max_conc_proc > kfd->vm_info.vmid_num_kfd)) { 510 dev_err(kfd_device, 511 "hws_max_conc_proc %d must be between 0 and %d, use %d instead\n", 512 hws_max_conc_proc, kfd->vm_info.vmid_num_kfd, 513 kfd->vm_info.vmid_num_kfd); 514 kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd; 515 } else 516 kfd->max_proc_per_quantum = hws_max_conc_proc; 517 518 /* calculate max size of mqds needed for queues */ 519 size = max_num_of_queues_per_device * 520 kfd->device_info->mqd_size_aligned; 521 522 /* 523 * calculate max size of runlist packet. 524 * There can be only 2 packets at once 525 */ 526 size += (KFD_MAX_NUM_OF_PROCESSES * sizeof(struct pm4_mes_map_process) + 527 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 528 + sizeof(struct pm4_mes_runlist)) * 2; 529 530 /* Add size of HIQ & DIQ */ 531 size += KFD_KERNEL_QUEUE_SIZE * 2; 532 533 /* add another 512KB for all other allocations on gart (HPD, fences) */ 534 size += 512 * 1024; 535 536 if (amdgpu_amdkfd_alloc_gtt_mem( 537 kfd->kgd, size, &kfd->gtt_mem, 538 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 539 false)) { 540 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 541 goto out; 542 } 543 544 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 545 546 /* Initialize GTT sa with 512 byte chunk size */ 547 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 548 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 549 goto kfd_gtt_sa_init_error; 550 } 551 552 if (kfd_doorbell_init(kfd)) { 553 dev_err(kfd_device, 554 "Error initializing doorbell aperture\n"); 555 goto kfd_doorbell_error; 556 } 557 558 if (kfd->kfd2kgd->get_hive_id) 559 kfd->hive_id = kfd->kfd2kgd->get_hive_id(kfd->kgd); 560 561 if (kfd_topology_add_device(kfd)) { 562 dev_err(kfd_device, "Error adding device to topology\n"); 563 goto kfd_topology_add_device_error; 564 } 565 566 if (kfd_interrupt_init(kfd)) { 567 dev_err(kfd_device, "Error initializing interrupts\n"); 568 goto kfd_interrupt_error; 569 } 570 571 kfd->dqm = device_queue_manager_init(kfd); 572 if (!kfd->dqm) { 573 dev_err(kfd_device, "Error initializing queue manager\n"); 574 goto device_queue_manager_error; 575 } 576 577 if (kfd_iommu_device_init(kfd)) { 578 dev_err(kfd_device, "Error initializing iommuv2\n"); 579 goto device_iommu_error; 580 } 581 582 kfd_cwsr_init(kfd); 583 584 if (kfd_resume(kfd)) 585 goto kfd_resume_error; 586 587 kfd->dbgmgr = NULL; 588 589 kfd->init_complete = true; 590 dev_info(kfd_device, "added device %x:%x\n", kfd->pdev->vendor, 591 kfd->pdev->device); 592 593 pr_debug("Starting kfd with the following scheduling policy %d\n", 594 kfd->dqm->sched_policy); 595 596 goto out; 597 598 kfd_resume_error: 599 device_iommu_error: 600 device_queue_manager_uninit(kfd->dqm); 601 device_queue_manager_error: 602 kfd_interrupt_exit(kfd); 603 kfd_interrupt_error: 604 kfd_topology_remove_device(kfd); 605 kfd_topology_add_device_error: 606 kfd_doorbell_fini(kfd); 607 kfd_doorbell_error: 608 kfd_gtt_sa_fini(kfd); 609 kfd_gtt_sa_init_error: 610 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem); 611 dev_err(kfd_device, 612 "device %x:%x NOT added due to errors\n", 613 kfd->pdev->vendor, kfd->pdev->device); 614 out: 615 return kfd->init_complete; 616 } 617 618 void kgd2kfd_device_exit(struct kfd_dev *kfd) 619 { 620 if (kfd->init_complete) { 621 kgd2kfd_suspend(kfd); 622 device_queue_manager_uninit(kfd->dqm); 623 kfd_interrupt_exit(kfd); 624 kfd_topology_remove_device(kfd); 625 kfd_doorbell_fini(kfd); 626 kfd_gtt_sa_fini(kfd); 627 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem); 628 } 629 630 kfree(kfd); 631 } 632 633 int kgd2kfd_pre_reset(struct kfd_dev *kfd) 634 { 635 if (!kfd->init_complete) 636 return 0; 637 kgd2kfd_suspend(kfd); 638 639 /* hold dqm->lock to prevent further execution*/ 640 dqm_lock(kfd->dqm); 641 642 kfd_signal_reset_event(kfd); 643 return 0; 644 } 645 646 /* 647 * Fix me. KFD won't be able to resume existing process for now. 648 * We will keep all existing process in a evicted state and 649 * wait the process to be terminated. 650 */ 651 652 int kgd2kfd_post_reset(struct kfd_dev *kfd) 653 { 654 int ret, count; 655 656 if (!kfd->init_complete) 657 return 0; 658 659 dqm_unlock(kfd->dqm); 660 661 ret = kfd_resume(kfd); 662 if (ret) 663 return ret; 664 count = atomic_dec_return(&kfd_locked); 665 WARN_ONCE(count != 0, "KFD reset ref. error"); 666 667 atomic_set(&kfd->sram_ecc_flag, 0); 668 669 return 0; 670 } 671 672 bool kfd_is_locked(void) 673 { 674 return (atomic_read(&kfd_locked) > 0); 675 } 676 677 void kgd2kfd_suspend(struct kfd_dev *kfd) 678 { 679 if (!kfd->init_complete) 680 return; 681 682 /* For first KFD device suspend all the KFD processes */ 683 if (atomic_inc_return(&kfd_locked) == 1) 684 kfd_suspend_all_processes(); 685 686 kfd->dqm->ops.stop(kfd->dqm); 687 688 kfd_iommu_suspend(kfd); 689 } 690 691 int kgd2kfd_resume(struct kfd_dev *kfd) 692 { 693 int ret, count; 694 695 if (!kfd->init_complete) 696 return 0; 697 698 ret = kfd_resume(kfd); 699 if (ret) 700 return ret; 701 702 count = atomic_dec_return(&kfd_locked); 703 WARN_ONCE(count < 0, "KFD suspend / resume ref. error"); 704 if (count == 0) 705 ret = kfd_resume_all_processes(); 706 707 return ret; 708 } 709 710 static int kfd_resume(struct kfd_dev *kfd) 711 { 712 int err = 0; 713 714 err = kfd_iommu_resume(kfd); 715 if (err) { 716 dev_err(kfd_device, 717 "Failed to resume IOMMU for device %x:%x\n", 718 kfd->pdev->vendor, kfd->pdev->device); 719 return err; 720 } 721 722 err = kfd->dqm->ops.start(kfd->dqm); 723 if (err) { 724 dev_err(kfd_device, 725 "Error starting queue manager for device %x:%x\n", 726 kfd->pdev->vendor, kfd->pdev->device); 727 goto dqm_start_error; 728 } 729 730 return err; 731 732 dqm_start_error: 733 kfd_iommu_suspend(kfd); 734 return err; 735 } 736 737 /* This is called directly from KGD at ISR. */ 738 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 739 { 740 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE]; 741 bool is_patched = false; 742 unsigned long flags; 743 744 if (!kfd->init_complete) 745 return; 746 747 if (kfd->device_info->ih_ring_entry_size > sizeof(patched_ihre)) { 748 dev_err_once(kfd_device, "Ring entry too small\n"); 749 return; 750 } 751 752 spin_lock_irqsave(&kfd->interrupt_lock, flags); 753 754 if (kfd->interrupts_active 755 && interrupt_is_wanted(kfd, ih_ring_entry, 756 patched_ihre, &is_patched) 757 && enqueue_ih_ring_entry(kfd, 758 is_patched ? patched_ihre : ih_ring_entry)) 759 queue_work(kfd->ih_wq, &kfd->interrupt_work); 760 761 spin_unlock_irqrestore(&kfd->interrupt_lock, flags); 762 } 763 764 int kgd2kfd_quiesce_mm(struct mm_struct *mm) 765 { 766 struct kfd_process *p; 767 int r; 768 769 /* Because we are called from arbitrary context (workqueue) as opposed 770 * to process context, kfd_process could attempt to exit while we are 771 * running so the lookup function increments the process ref count. 772 */ 773 p = kfd_lookup_process_by_mm(mm); 774 if (!p) 775 return -ESRCH; 776 777 r = kfd_process_evict_queues(p); 778 779 kfd_unref_process(p); 780 return r; 781 } 782 783 int kgd2kfd_resume_mm(struct mm_struct *mm) 784 { 785 struct kfd_process *p; 786 int r; 787 788 /* Because we are called from arbitrary context (workqueue) as opposed 789 * to process context, kfd_process could attempt to exit while we are 790 * running so the lookup function increments the process ref count. 791 */ 792 p = kfd_lookup_process_by_mm(mm); 793 if (!p) 794 return -ESRCH; 795 796 r = kfd_process_restore_queues(p); 797 798 kfd_unref_process(p); 799 return r; 800 } 801 802 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 803 * prepare for safe eviction of KFD BOs that belong to the specified 804 * process. 805 * 806 * @mm: mm_struct that identifies the specified KFD process 807 * @fence: eviction fence attached to KFD process BOs 808 * 809 */ 810 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 811 struct dma_fence *fence) 812 { 813 struct kfd_process *p; 814 unsigned long active_time; 815 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 816 817 if (!fence) 818 return -EINVAL; 819 820 if (dma_fence_is_signaled(fence)) 821 return 0; 822 823 p = kfd_lookup_process_by_mm(mm); 824 if (!p) 825 return -ENODEV; 826 827 if (fence->seqno == p->last_eviction_seqno) 828 goto out; 829 830 p->last_eviction_seqno = fence->seqno; 831 832 /* Avoid KFD process starvation. Wait for at least 833 * PROCESS_ACTIVE_TIME_MS before evicting the process again 834 */ 835 active_time = get_jiffies_64() - p->last_restore_timestamp; 836 if (delay_jiffies > active_time) 837 delay_jiffies -= active_time; 838 else 839 delay_jiffies = 0; 840 841 /* During process initialization eviction_work.dwork is initialized 842 * to kfd_evict_bo_worker 843 */ 844 schedule_delayed_work(&p->eviction_work, delay_jiffies); 845 out: 846 kfd_unref_process(p); 847 return 0; 848 } 849 850 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 851 unsigned int chunk_size) 852 { 853 unsigned int num_of_longs; 854 855 if (WARN_ON(buf_size < chunk_size)) 856 return -EINVAL; 857 if (WARN_ON(buf_size == 0)) 858 return -EINVAL; 859 if (WARN_ON(chunk_size == 0)) 860 return -EINVAL; 861 862 kfd->gtt_sa_chunk_size = chunk_size; 863 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 864 865 num_of_longs = (kfd->gtt_sa_num_of_chunks + BITS_PER_LONG - 1) / 866 BITS_PER_LONG; 867 868 kfd->gtt_sa_bitmap = kcalloc(num_of_longs, sizeof(long), GFP_KERNEL); 869 870 if (!kfd->gtt_sa_bitmap) 871 return -ENOMEM; 872 873 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 874 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 875 876 mutex_init(&kfd->gtt_sa_lock); 877 878 return 0; 879 880 } 881 882 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 883 { 884 mutex_destroy(&kfd->gtt_sa_lock); 885 kfree(kfd->gtt_sa_bitmap); 886 } 887 888 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 889 unsigned int bit_num, 890 unsigned int chunk_size) 891 { 892 return start_addr + bit_num * chunk_size; 893 } 894 895 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 896 unsigned int bit_num, 897 unsigned int chunk_size) 898 { 899 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 900 } 901 902 int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size, 903 struct kfd_mem_obj **mem_obj) 904 { 905 unsigned int found, start_search, cur_size; 906 907 if (size == 0) 908 return -EINVAL; 909 910 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 911 return -ENOMEM; 912 913 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 914 if (!(*mem_obj)) 915 return -ENOMEM; 916 917 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 918 919 start_search = 0; 920 921 mutex_lock(&kfd->gtt_sa_lock); 922 923 kfd_gtt_restart_search: 924 /* Find the first chunk that is free */ 925 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 926 kfd->gtt_sa_num_of_chunks, 927 start_search); 928 929 pr_debug("Found = %d\n", found); 930 931 /* If there wasn't any free chunk, bail out */ 932 if (found == kfd->gtt_sa_num_of_chunks) 933 goto kfd_gtt_no_free_chunk; 934 935 /* Update fields of mem_obj */ 936 (*mem_obj)->range_start = found; 937 (*mem_obj)->range_end = found; 938 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 939 kfd->gtt_start_gpu_addr, 940 found, 941 kfd->gtt_sa_chunk_size); 942 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 943 kfd->gtt_start_cpu_ptr, 944 found, 945 kfd->gtt_sa_chunk_size); 946 947 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 948 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 949 950 /* If we need only one chunk, mark it as allocated and get out */ 951 if (size <= kfd->gtt_sa_chunk_size) { 952 pr_debug("Single bit\n"); 953 set_bit(found, kfd->gtt_sa_bitmap); 954 goto kfd_gtt_out; 955 } 956 957 /* Otherwise, try to see if we have enough contiguous chunks */ 958 cur_size = size - kfd->gtt_sa_chunk_size; 959 do { 960 (*mem_obj)->range_end = 961 find_next_zero_bit(kfd->gtt_sa_bitmap, 962 kfd->gtt_sa_num_of_chunks, ++found); 963 /* 964 * If next free chunk is not contiguous than we need to 965 * restart our search from the last free chunk we found (which 966 * wasn't contiguous to the previous ones 967 */ 968 if ((*mem_obj)->range_end != found) { 969 start_search = found; 970 goto kfd_gtt_restart_search; 971 } 972 973 /* 974 * If we reached end of buffer, bail out with error 975 */ 976 if (found == kfd->gtt_sa_num_of_chunks) 977 goto kfd_gtt_no_free_chunk; 978 979 /* Check if we don't need another chunk */ 980 if (cur_size <= kfd->gtt_sa_chunk_size) 981 cur_size = 0; 982 else 983 cur_size -= kfd->gtt_sa_chunk_size; 984 985 } while (cur_size > 0); 986 987 pr_debug("range_start = %d, range_end = %d\n", 988 (*mem_obj)->range_start, (*mem_obj)->range_end); 989 990 /* Mark the chunks as allocated */ 991 for (found = (*mem_obj)->range_start; 992 found <= (*mem_obj)->range_end; 993 found++) 994 set_bit(found, kfd->gtt_sa_bitmap); 995 996 kfd_gtt_out: 997 mutex_unlock(&kfd->gtt_sa_lock); 998 return 0; 999 1000 kfd_gtt_no_free_chunk: 1001 pr_debug("Allocation failed with mem_obj = %p\n", mem_obj); 1002 mutex_unlock(&kfd->gtt_sa_lock); 1003 kfree(mem_obj); 1004 return -ENOMEM; 1005 } 1006 1007 int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj) 1008 { 1009 unsigned int bit; 1010 1011 /* Act like kfree when trying to free a NULL object */ 1012 if (!mem_obj) 1013 return 0; 1014 1015 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1016 mem_obj, mem_obj->range_start, mem_obj->range_end); 1017 1018 mutex_lock(&kfd->gtt_sa_lock); 1019 1020 /* Mark the chunks as free */ 1021 for (bit = mem_obj->range_start; 1022 bit <= mem_obj->range_end; 1023 bit++) 1024 clear_bit(bit, kfd->gtt_sa_bitmap); 1025 1026 mutex_unlock(&kfd->gtt_sa_lock); 1027 1028 kfree(mem_obj); 1029 return 0; 1030 } 1031 1032 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1033 { 1034 if (kfd) 1035 atomic_inc(&kfd->sram_ecc_flag); 1036 } 1037 1038 #if defined(CONFIG_DEBUG_FS) 1039 1040 /* This function will send a package to HIQ to hang the HWS 1041 * which will trigger a GPU reset and bring the HWS back to normal state 1042 */ 1043 int kfd_debugfs_hang_hws(struct kfd_dev *dev) 1044 { 1045 int r = 0; 1046 1047 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1048 pr_err("HWS is not enabled"); 1049 return -EINVAL; 1050 } 1051 1052 r = pm_debugfs_hang_hws(&dev->dqm->packets); 1053 if (!r) 1054 r = dqm_debugfs_execute_queues(dev->dqm); 1055 1056 return r; 1057 } 1058 1059 #endif 1060