1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/bsearch.h> 24 #include <linux/pci.h> 25 #include <linux/slab.h> 26 #include "kfd_priv.h" 27 #include "kfd_device_queue_manager.h" 28 #include "kfd_pm4_headers_vi.h" 29 #include "cwsr_trap_handler.h" 30 #include "kfd_iommu.h" 31 #include "amdgpu_amdkfd.h" 32 33 #define MQD_SIZE_ALIGNED 768 34 35 /* 36 * kfd_locked is used to lock the kfd driver during suspend or reset 37 * once locked, kfd driver will stop any further GPU execution. 38 * create process (open) will return -EAGAIN. 39 */ 40 static atomic_t kfd_locked = ATOMIC_INIT(0); 41 42 #ifdef KFD_SUPPORT_IOMMU_V2 43 static const struct kfd_device_info kaveri_device_info = { 44 .asic_family = CHIP_KAVERI, 45 .max_pasid_bits = 16, 46 /* max num of queues for KV.TODO should be a dynamic value */ 47 .max_no_of_hqd = 24, 48 .doorbell_size = 4, 49 .ih_ring_entry_size = 4 * sizeof(uint32_t), 50 .event_interrupt_class = &event_interrupt_class_cik, 51 .num_of_watch_points = 4, 52 .mqd_size_aligned = MQD_SIZE_ALIGNED, 53 .supports_cwsr = false, 54 .needs_iommu_device = true, 55 .needs_pci_atomics = false, 56 .num_sdma_engines = 2, 57 .num_xgmi_sdma_engines = 0, 58 .num_sdma_queues_per_engine = 2, 59 }; 60 61 static const struct kfd_device_info carrizo_device_info = { 62 .asic_family = CHIP_CARRIZO, 63 .max_pasid_bits = 16, 64 /* max num of queues for CZ.TODO should be a dynamic value */ 65 .max_no_of_hqd = 24, 66 .doorbell_size = 4, 67 .ih_ring_entry_size = 4 * sizeof(uint32_t), 68 .event_interrupt_class = &event_interrupt_class_cik, 69 .num_of_watch_points = 4, 70 .mqd_size_aligned = MQD_SIZE_ALIGNED, 71 .supports_cwsr = true, 72 .needs_iommu_device = true, 73 .needs_pci_atomics = false, 74 .num_sdma_engines = 2, 75 .num_xgmi_sdma_engines = 0, 76 .num_sdma_queues_per_engine = 2, 77 }; 78 79 static const struct kfd_device_info raven_device_info = { 80 .asic_family = CHIP_RAVEN, 81 .max_pasid_bits = 16, 82 .max_no_of_hqd = 24, 83 .doorbell_size = 8, 84 .ih_ring_entry_size = 8 * sizeof(uint32_t), 85 .event_interrupt_class = &event_interrupt_class_v9, 86 .num_of_watch_points = 4, 87 .mqd_size_aligned = MQD_SIZE_ALIGNED, 88 .supports_cwsr = true, 89 .needs_iommu_device = true, 90 .needs_pci_atomics = true, 91 .num_sdma_engines = 1, 92 .num_xgmi_sdma_engines = 0, 93 .num_sdma_queues_per_engine = 2, 94 }; 95 #endif 96 97 static const struct kfd_device_info hawaii_device_info = { 98 .asic_family = CHIP_HAWAII, 99 .max_pasid_bits = 16, 100 /* max num of queues for KV.TODO should be a dynamic value */ 101 .max_no_of_hqd = 24, 102 .doorbell_size = 4, 103 .ih_ring_entry_size = 4 * sizeof(uint32_t), 104 .event_interrupt_class = &event_interrupt_class_cik, 105 .num_of_watch_points = 4, 106 .mqd_size_aligned = MQD_SIZE_ALIGNED, 107 .supports_cwsr = false, 108 .needs_iommu_device = false, 109 .needs_pci_atomics = false, 110 .num_sdma_engines = 2, 111 .num_xgmi_sdma_engines = 0, 112 .num_sdma_queues_per_engine = 2, 113 }; 114 115 static const struct kfd_device_info tonga_device_info = { 116 .asic_family = CHIP_TONGA, 117 .max_pasid_bits = 16, 118 .max_no_of_hqd = 24, 119 .doorbell_size = 4, 120 .ih_ring_entry_size = 4 * sizeof(uint32_t), 121 .event_interrupt_class = &event_interrupt_class_cik, 122 .num_of_watch_points = 4, 123 .mqd_size_aligned = MQD_SIZE_ALIGNED, 124 .supports_cwsr = false, 125 .needs_iommu_device = false, 126 .needs_pci_atomics = true, 127 .num_sdma_engines = 2, 128 .num_xgmi_sdma_engines = 0, 129 .num_sdma_queues_per_engine = 2, 130 }; 131 132 static const struct kfd_device_info fiji_device_info = { 133 .asic_family = CHIP_FIJI, 134 .max_pasid_bits = 16, 135 .max_no_of_hqd = 24, 136 .doorbell_size = 4, 137 .ih_ring_entry_size = 4 * sizeof(uint32_t), 138 .event_interrupt_class = &event_interrupt_class_cik, 139 .num_of_watch_points = 4, 140 .mqd_size_aligned = MQD_SIZE_ALIGNED, 141 .supports_cwsr = true, 142 .needs_iommu_device = false, 143 .needs_pci_atomics = true, 144 .num_sdma_engines = 2, 145 .num_xgmi_sdma_engines = 0, 146 .num_sdma_queues_per_engine = 2, 147 }; 148 149 static const struct kfd_device_info fiji_vf_device_info = { 150 .asic_family = CHIP_FIJI, 151 .max_pasid_bits = 16, 152 .max_no_of_hqd = 24, 153 .doorbell_size = 4, 154 .ih_ring_entry_size = 4 * sizeof(uint32_t), 155 .event_interrupt_class = &event_interrupt_class_cik, 156 .num_of_watch_points = 4, 157 .mqd_size_aligned = MQD_SIZE_ALIGNED, 158 .supports_cwsr = true, 159 .needs_iommu_device = false, 160 .needs_pci_atomics = false, 161 .num_sdma_engines = 2, 162 .num_xgmi_sdma_engines = 0, 163 .num_sdma_queues_per_engine = 2, 164 }; 165 166 167 static const struct kfd_device_info polaris10_device_info = { 168 .asic_family = CHIP_POLARIS10, 169 .max_pasid_bits = 16, 170 .max_no_of_hqd = 24, 171 .doorbell_size = 4, 172 .ih_ring_entry_size = 4 * sizeof(uint32_t), 173 .event_interrupt_class = &event_interrupt_class_cik, 174 .num_of_watch_points = 4, 175 .mqd_size_aligned = MQD_SIZE_ALIGNED, 176 .supports_cwsr = true, 177 .needs_iommu_device = false, 178 .needs_pci_atomics = true, 179 .num_sdma_engines = 2, 180 .num_xgmi_sdma_engines = 0, 181 .num_sdma_queues_per_engine = 2, 182 }; 183 184 static const struct kfd_device_info polaris10_vf_device_info = { 185 .asic_family = CHIP_POLARIS10, 186 .max_pasid_bits = 16, 187 .max_no_of_hqd = 24, 188 .doorbell_size = 4, 189 .ih_ring_entry_size = 4 * sizeof(uint32_t), 190 .event_interrupt_class = &event_interrupt_class_cik, 191 .num_of_watch_points = 4, 192 .mqd_size_aligned = MQD_SIZE_ALIGNED, 193 .supports_cwsr = true, 194 .needs_iommu_device = false, 195 .needs_pci_atomics = false, 196 .num_sdma_engines = 2, 197 .num_xgmi_sdma_engines = 0, 198 .num_sdma_queues_per_engine = 2, 199 }; 200 201 static const struct kfd_device_info polaris11_device_info = { 202 .asic_family = CHIP_POLARIS11, 203 .max_pasid_bits = 16, 204 .max_no_of_hqd = 24, 205 .doorbell_size = 4, 206 .ih_ring_entry_size = 4 * sizeof(uint32_t), 207 .event_interrupt_class = &event_interrupt_class_cik, 208 .num_of_watch_points = 4, 209 .mqd_size_aligned = MQD_SIZE_ALIGNED, 210 .supports_cwsr = true, 211 .needs_iommu_device = false, 212 .needs_pci_atomics = true, 213 .num_sdma_engines = 2, 214 .num_xgmi_sdma_engines = 0, 215 .num_sdma_queues_per_engine = 2, 216 }; 217 218 static const struct kfd_device_info polaris12_device_info = { 219 .asic_family = CHIP_POLARIS12, 220 .max_pasid_bits = 16, 221 .max_no_of_hqd = 24, 222 .doorbell_size = 4, 223 .ih_ring_entry_size = 4 * sizeof(uint32_t), 224 .event_interrupt_class = &event_interrupt_class_cik, 225 .num_of_watch_points = 4, 226 .mqd_size_aligned = MQD_SIZE_ALIGNED, 227 .supports_cwsr = true, 228 .needs_iommu_device = false, 229 .needs_pci_atomics = true, 230 .num_sdma_engines = 2, 231 .num_xgmi_sdma_engines = 0, 232 .num_sdma_queues_per_engine = 2, 233 }; 234 235 static const struct kfd_device_info vegam_device_info = { 236 .asic_family = CHIP_VEGAM, 237 .max_pasid_bits = 16, 238 .max_no_of_hqd = 24, 239 .doorbell_size = 4, 240 .ih_ring_entry_size = 4 * sizeof(uint32_t), 241 .event_interrupt_class = &event_interrupt_class_cik, 242 .num_of_watch_points = 4, 243 .mqd_size_aligned = MQD_SIZE_ALIGNED, 244 .supports_cwsr = true, 245 .needs_iommu_device = false, 246 .needs_pci_atomics = true, 247 .num_sdma_engines = 2, 248 .num_xgmi_sdma_engines = 0, 249 .num_sdma_queues_per_engine = 2, 250 }; 251 252 static const struct kfd_device_info vega10_device_info = { 253 .asic_family = CHIP_VEGA10, 254 .max_pasid_bits = 16, 255 .max_no_of_hqd = 24, 256 .doorbell_size = 8, 257 .ih_ring_entry_size = 8 * sizeof(uint32_t), 258 .event_interrupt_class = &event_interrupt_class_v9, 259 .num_of_watch_points = 4, 260 .mqd_size_aligned = MQD_SIZE_ALIGNED, 261 .supports_cwsr = true, 262 .needs_iommu_device = false, 263 .needs_pci_atomics = false, 264 .num_sdma_engines = 2, 265 .num_xgmi_sdma_engines = 0, 266 .num_sdma_queues_per_engine = 2, 267 }; 268 269 static const struct kfd_device_info vega10_vf_device_info = { 270 .asic_family = CHIP_VEGA10, 271 .max_pasid_bits = 16, 272 .max_no_of_hqd = 24, 273 .doorbell_size = 8, 274 .ih_ring_entry_size = 8 * sizeof(uint32_t), 275 .event_interrupt_class = &event_interrupt_class_v9, 276 .num_of_watch_points = 4, 277 .mqd_size_aligned = MQD_SIZE_ALIGNED, 278 .supports_cwsr = true, 279 .needs_iommu_device = false, 280 .needs_pci_atomics = false, 281 .num_sdma_engines = 2, 282 .num_xgmi_sdma_engines = 0, 283 .num_sdma_queues_per_engine = 2, 284 }; 285 286 static const struct kfd_device_info vega12_device_info = { 287 .asic_family = CHIP_VEGA12, 288 .max_pasid_bits = 16, 289 .max_no_of_hqd = 24, 290 .doorbell_size = 8, 291 .ih_ring_entry_size = 8 * sizeof(uint32_t), 292 .event_interrupt_class = &event_interrupt_class_v9, 293 .num_of_watch_points = 4, 294 .mqd_size_aligned = MQD_SIZE_ALIGNED, 295 .supports_cwsr = true, 296 .needs_iommu_device = false, 297 .needs_pci_atomics = false, 298 .num_sdma_engines = 2, 299 .num_xgmi_sdma_engines = 0, 300 .num_sdma_queues_per_engine = 2, 301 }; 302 303 static const struct kfd_device_info vega20_device_info = { 304 .asic_family = CHIP_VEGA20, 305 .max_pasid_bits = 16, 306 .max_no_of_hqd = 24, 307 .doorbell_size = 8, 308 .ih_ring_entry_size = 8 * sizeof(uint32_t), 309 .event_interrupt_class = &event_interrupt_class_v9, 310 .num_of_watch_points = 4, 311 .mqd_size_aligned = MQD_SIZE_ALIGNED, 312 .supports_cwsr = true, 313 .needs_iommu_device = false, 314 .needs_pci_atomics = false, 315 .num_sdma_engines = 2, 316 .num_xgmi_sdma_engines = 0, 317 .num_sdma_queues_per_engine = 8, 318 }; 319 320 struct kfd_deviceid { 321 unsigned short did; 322 const struct kfd_device_info *device_info; 323 }; 324 325 static const struct kfd_deviceid supported_devices[] = { 326 #ifdef KFD_SUPPORT_IOMMU_V2 327 { 0x1304, &kaveri_device_info }, /* Kaveri */ 328 { 0x1305, &kaveri_device_info }, /* Kaveri */ 329 { 0x1306, &kaveri_device_info }, /* Kaveri */ 330 { 0x1307, &kaveri_device_info }, /* Kaveri */ 331 { 0x1309, &kaveri_device_info }, /* Kaveri */ 332 { 0x130A, &kaveri_device_info }, /* Kaveri */ 333 { 0x130B, &kaveri_device_info }, /* Kaveri */ 334 { 0x130C, &kaveri_device_info }, /* Kaveri */ 335 { 0x130D, &kaveri_device_info }, /* Kaveri */ 336 { 0x130E, &kaveri_device_info }, /* Kaveri */ 337 { 0x130F, &kaveri_device_info }, /* Kaveri */ 338 { 0x1310, &kaveri_device_info }, /* Kaveri */ 339 { 0x1311, &kaveri_device_info }, /* Kaveri */ 340 { 0x1312, &kaveri_device_info }, /* Kaveri */ 341 { 0x1313, &kaveri_device_info }, /* Kaveri */ 342 { 0x1315, &kaveri_device_info }, /* Kaveri */ 343 { 0x1316, &kaveri_device_info }, /* Kaveri */ 344 { 0x1317, &kaveri_device_info }, /* Kaveri */ 345 { 0x1318, &kaveri_device_info }, /* Kaveri */ 346 { 0x131B, &kaveri_device_info }, /* Kaveri */ 347 { 0x131C, &kaveri_device_info }, /* Kaveri */ 348 { 0x131D, &kaveri_device_info }, /* Kaveri */ 349 { 0x9870, &carrizo_device_info }, /* Carrizo */ 350 { 0x9874, &carrizo_device_info }, /* Carrizo */ 351 { 0x9875, &carrizo_device_info }, /* Carrizo */ 352 { 0x9876, &carrizo_device_info }, /* Carrizo */ 353 { 0x9877, &carrizo_device_info }, /* Carrizo */ 354 { 0x15DD, &raven_device_info }, /* Raven */ 355 { 0x15D8, &raven_device_info }, /* Raven */ 356 #endif 357 { 0x67A0, &hawaii_device_info }, /* Hawaii */ 358 { 0x67A1, &hawaii_device_info }, /* Hawaii */ 359 { 0x67A2, &hawaii_device_info }, /* Hawaii */ 360 { 0x67A8, &hawaii_device_info }, /* Hawaii */ 361 { 0x67A9, &hawaii_device_info }, /* Hawaii */ 362 { 0x67AA, &hawaii_device_info }, /* Hawaii */ 363 { 0x67B0, &hawaii_device_info }, /* Hawaii */ 364 { 0x67B1, &hawaii_device_info }, /* Hawaii */ 365 { 0x67B8, &hawaii_device_info }, /* Hawaii */ 366 { 0x67B9, &hawaii_device_info }, /* Hawaii */ 367 { 0x67BA, &hawaii_device_info }, /* Hawaii */ 368 { 0x67BE, &hawaii_device_info }, /* Hawaii */ 369 { 0x6920, &tonga_device_info }, /* Tonga */ 370 { 0x6921, &tonga_device_info }, /* Tonga */ 371 { 0x6928, &tonga_device_info }, /* Tonga */ 372 { 0x6929, &tonga_device_info }, /* Tonga */ 373 { 0x692B, &tonga_device_info }, /* Tonga */ 374 { 0x6938, &tonga_device_info }, /* Tonga */ 375 { 0x6939, &tonga_device_info }, /* Tonga */ 376 { 0x7300, &fiji_device_info }, /* Fiji */ 377 { 0x730F, &fiji_vf_device_info }, /* Fiji vf*/ 378 { 0x67C0, &polaris10_device_info }, /* Polaris10 */ 379 { 0x67C1, &polaris10_device_info }, /* Polaris10 */ 380 { 0x67C2, &polaris10_device_info }, /* Polaris10 */ 381 { 0x67C4, &polaris10_device_info }, /* Polaris10 */ 382 { 0x67C7, &polaris10_device_info }, /* Polaris10 */ 383 { 0x67C8, &polaris10_device_info }, /* Polaris10 */ 384 { 0x67C9, &polaris10_device_info }, /* Polaris10 */ 385 { 0x67CA, &polaris10_device_info }, /* Polaris10 */ 386 { 0x67CC, &polaris10_device_info }, /* Polaris10 */ 387 { 0x67CF, &polaris10_device_info }, /* Polaris10 */ 388 { 0x67D0, &polaris10_vf_device_info }, /* Polaris10 vf*/ 389 { 0x67DF, &polaris10_device_info }, /* Polaris10 */ 390 { 0x6FDF, &polaris10_device_info }, /* Polaris10 */ 391 { 0x67E0, &polaris11_device_info }, /* Polaris11 */ 392 { 0x67E1, &polaris11_device_info }, /* Polaris11 */ 393 { 0x67E3, &polaris11_device_info }, /* Polaris11 */ 394 { 0x67E7, &polaris11_device_info }, /* Polaris11 */ 395 { 0x67E8, &polaris11_device_info }, /* Polaris11 */ 396 { 0x67E9, &polaris11_device_info }, /* Polaris11 */ 397 { 0x67EB, &polaris11_device_info }, /* Polaris11 */ 398 { 0x67EF, &polaris11_device_info }, /* Polaris11 */ 399 { 0x67FF, &polaris11_device_info }, /* Polaris11 */ 400 { 0x6980, &polaris12_device_info }, /* Polaris12 */ 401 { 0x6981, &polaris12_device_info }, /* Polaris12 */ 402 { 0x6985, &polaris12_device_info }, /* Polaris12 */ 403 { 0x6986, &polaris12_device_info }, /* Polaris12 */ 404 { 0x6987, &polaris12_device_info }, /* Polaris12 */ 405 { 0x6995, &polaris12_device_info }, /* Polaris12 */ 406 { 0x6997, &polaris12_device_info }, /* Polaris12 */ 407 { 0x699F, &polaris12_device_info }, /* Polaris12 */ 408 { 0x694C, &vegam_device_info }, /* VegaM */ 409 { 0x694E, &vegam_device_info }, /* VegaM */ 410 { 0x694F, &vegam_device_info }, /* VegaM */ 411 { 0x6860, &vega10_device_info }, /* Vega10 */ 412 { 0x6861, &vega10_device_info }, /* Vega10 */ 413 { 0x6862, &vega10_device_info }, /* Vega10 */ 414 { 0x6863, &vega10_device_info }, /* Vega10 */ 415 { 0x6864, &vega10_device_info }, /* Vega10 */ 416 { 0x6867, &vega10_device_info }, /* Vega10 */ 417 { 0x6868, &vega10_device_info }, /* Vega10 */ 418 { 0x6869, &vega10_device_info }, /* Vega10 */ 419 { 0x686A, &vega10_device_info }, /* Vega10 */ 420 { 0x686B, &vega10_device_info }, /* Vega10 */ 421 { 0x686C, &vega10_vf_device_info }, /* Vega10 vf*/ 422 { 0x686D, &vega10_device_info }, /* Vega10 */ 423 { 0x686E, &vega10_device_info }, /* Vega10 */ 424 { 0x686F, &vega10_device_info }, /* Vega10 */ 425 { 0x687F, &vega10_device_info }, /* Vega10 */ 426 { 0x69A0, &vega12_device_info }, /* Vega12 */ 427 { 0x69A1, &vega12_device_info }, /* Vega12 */ 428 { 0x69A2, &vega12_device_info }, /* Vega12 */ 429 { 0x69A3, &vega12_device_info }, /* Vega12 */ 430 { 0x69AF, &vega12_device_info }, /* Vega12 */ 431 { 0x66a0, &vega20_device_info }, /* Vega20 */ 432 { 0x66a1, &vega20_device_info }, /* Vega20 */ 433 { 0x66a2, &vega20_device_info }, /* Vega20 */ 434 { 0x66a3, &vega20_device_info }, /* Vega20 */ 435 { 0x66a4, &vega20_device_info }, /* Vega20 */ 436 { 0x66a7, &vega20_device_info }, /* Vega20 */ 437 { 0x66af, &vega20_device_info } /* Vega20 */ 438 }; 439 440 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 441 unsigned int chunk_size); 442 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 443 444 static int kfd_resume(struct kfd_dev *kfd); 445 446 static const struct kfd_device_info *lookup_device_info(unsigned short did) 447 { 448 size_t i; 449 450 for (i = 0; i < ARRAY_SIZE(supported_devices); i++) { 451 if (supported_devices[i].did == did) { 452 WARN_ON(!supported_devices[i].device_info); 453 return supported_devices[i].device_info; 454 } 455 } 456 457 dev_warn(kfd_device, "DID %04x is missing in supported_devices\n", 458 did); 459 460 return NULL; 461 } 462 463 struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, 464 struct pci_dev *pdev, const struct kfd2kgd_calls *f2g) 465 { 466 struct kfd_dev *kfd; 467 int ret; 468 const struct kfd_device_info *device_info = 469 lookup_device_info(pdev->device); 470 471 if (!device_info) { 472 dev_err(kfd_device, "kgd2kfd_probe failed\n"); 473 return NULL; 474 } 475 476 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 477 if (!kfd) 478 return NULL; 479 480 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 481 * 32 and 64-bit requests are possible and must be 482 * supported. 483 */ 484 ret = pci_enable_atomic_ops_to_root(pdev, 485 PCI_EXP_DEVCAP2_ATOMIC_COMP32 | 486 PCI_EXP_DEVCAP2_ATOMIC_COMP64); 487 if (device_info->needs_pci_atomics && ret < 0) { 488 dev_info(kfd_device, 489 "skipped device %x:%x, PCI rejects atomics\n", 490 pdev->vendor, pdev->device); 491 kfree(kfd); 492 return NULL; 493 } else if (!ret) 494 kfd->pci_atomic_requested = true; 495 496 kfd->kgd = kgd; 497 kfd->device_info = device_info; 498 kfd->pdev = pdev; 499 kfd->init_complete = false; 500 kfd->kfd2kgd = f2g; 501 atomic_set(&kfd->compute_profile, 0); 502 503 mutex_init(&kfd->doorbell_mutex); 504 memset(&kfd->doorbell_available_index, 0, 505 sizeof(kfd->doorbell_available_index)); 506 507 atomic_set(&kfd->sram_ecc_flag, 0); 508 509 return kfd; 510 } 511 512 static void kfd_cwsr_init(struct kfd_dev *kfd) 513 { 514 if (cwsr_enable && kfd->device_info->supports_cwsr) { 515 if (kfd->device_info->asic_family < CHIP_VEGA10) { 516 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE); 517 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 518 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 519 } else { 520 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE); 521 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 522 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 523 } 524 525 kfd->cwsr_enabled = true; 526 } 527 } 528 529 bool kgd2kfd_device_init(struct kfd_dev *kfd, 530 const struct kgd2kfd_shared_resources *gpu_resources) 531 { 532 unsigned int size; 533 534 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd, 535 KGD_ENGINE_MEC1); 536 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd, 537 KGD_ENGINE_SDMA1); 538 kfd->shared_resources = *gpu_resources; 539 540 kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 541 kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 542 kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd 543 - kfd->vm_info.first_vmid_kfd + 1; 544 545 /* Verify module parameters regarding mapped process number*/ 546 if ((hws_max_conc_proc < 0) 547 || (hws_max_conc_proc > kfd->vm_info.vmid_num_kfd)) { 548 dev_err(kfd_device, 549 "hws_max_conc_proc %d must be between 0 and %d, use %d instead\n", 550 hws_max_conc_proc, kfd->vm_info.vmid_num_kfd, 551 kfd->vm_info.vmid_num_kfd); 552 kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd; 553 } else 554 kfd->max_proc_per_quantum = hws_max_conc_proc; 555 556 /* Allocate global GWS that is shared by all KFD processes */ 557 if (hws_gws_support && amdgpu_amdkfd_alloc_gws(kfd->kgd, 558 amdgpu_amdkfd_get_num_gws(kfd->kgd), &kfd->gws)) { 559 dev_err(kfd_device, "Could not allocate %d gws\n", 560 amdgpu_amdkfd_get_num_gws(kfd->kgd)); 561 goto out; 562 } 563 /* calculate max size of mqds needed for queues */ 564 size = max_num_of_queues_per_device * 565 kfd->device_info->mqd_size_aligned; 566 567 /* 568 * calculate max size of runlist packet. 569 * There can be only 2 packets at once 570 */ 571 size += (KFD_MAX_NUM_OF_PROCESSES * sizeof(struct pm4_mes_map_process) + 572 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 573 + sizeof(struct pm4_mes_runlist)) * 2; 574 575 /* Add size of HIQ & DIQ */ 576 size += KFD_KERNEL_QUEUE_SIZE * 2; 577 578 /* add another 512KB for all other allocations on gart (HPD, fences) */ 579 size += 512 * 1024; 580 581 if (amdgpu_amdkfd_alloc_gtt_mem( 582 kfd->kgd, size, &kfd->gtt_mem, 583 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 584 false)) { 585 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 586 goto alloc_gtt_mem_failure; 587 } 588 589 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 590 591 /* Initialize GTT sa with 512 byte chunk size */ 592 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 593 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 594 goto kfd_gtt_sa_init_error; 595 } 596 597 if (kfd_doorbell_init(kfd)) { 598 dev_err(kfd_device, 599 "Error initializing doorbell aperture\n"); 600 goto kfd_doorbell_error; 601 } 602 603 if (kfd->kfd2kgd->get_hive_id) 604 kfd->hive_id = kfd->kfd2kgd->get_hive_id(kfd->kgd); 605 606 if (kfd_interrupt_init(kfd)) { 607 dev_err(kfd_device, "Error initializing interrupts\n"); 608 goto kfd_interrupt_error; 609 } 610 611 kfd->dqm = device_queue_manager_init(kfd); 612 if (!kfd->dqm) { 613 dev_err(kfd_device, "Error initializing queue manager\n"); 614 goto device_queue_manager_error; 615 } 616 617 if (kfd_iommu_device_init(kfd)) { 618 dev_err(kfd_device, "Error initializing iommuv2\n"); 619 goto device_iommu_error; 620 } 621 622 kfd_cwsr_init(kfd); 623 624 if (kfd_resume(kfd)) 625 goto kfd_resume_error; 626 627 kfd->dbgmgr = NULL; 628 629 if (kfd_topology_add_device(kfd)) { 630 dev_err(kfd_device, "Error adding device to topology\n"); 631 goto kfd_topology_add_device_error; 632 } 633 634 kfd->init_complete = true; 635 dev_info(kfd_device, "added device %x:%x\n", kfd->pdev->vendor, 636 kfd->pdev->device); 637 638 pr_debug("Starting kfd with the following scheduling policy %d\n", 639 kfd->dqm->sched_policy); 640 641 goto out; 642 643 kfd_topology_add_device_error: 644 kfd_resume_error: 645 device_iommu_error: 646 device_queue_manager_uninit(kfd->dqm); 647 device_queue_manager_error: 648 kfd_interrupt_exit(kfd); 649 kfd_interrupt_error: 650 kfd_doorbell_fini(kfd); 651 kfd_doorbell_error: 652 kfd_gtt_sa_fini(kfd); 653 kfd_gtt_sa_init_error: 654 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem); 655 alloc_gtt_mem_failure: 656 if (hws_gws_support) 657 amdgpu_amdkfd_free_gws(kfd->kgd, kfd->gws); 658 dev_err(kfd_device, 659 "device %x:%x NOT added due to errors\n", 660 kfd->pdev->vendor, kfd->pdev->device); 661 out: 662 return kfd->init_complete; 663 } 664 665 void kgd2kfd_device_exit(struct kfd_dev *kfd) 666 { 667 if (kfd->init_complete) { 668 kgd2kfd_suspend(kfd); 669 device_queue_manager_uninit(kfd->dqm); 670 kfd_interrupt_exit(kfd); 671 kfd_topology_remove_device(kfd); 672 kfd_doorbell_fini(kfd); 673 kfd_gtt_sa_fini(kfd); 674 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem); 675 if (hws_gws_support) 676 amdgpu_amdkfd_free_gws(kfd->kgd, kfd->gws); 677 } 678 679 kfree(kfd); 680 } 681 682 int kgd2kfd_pre_reset(struct kfd_dev *kfd) 683 { 684 if (!kfd->init_complete) 685 return 0; 686 kgd2kfd_suspend(kfd); 687 688 /* hold dqm->lock to prevent further execution*/ 689 dqm_lock(kfd->dqm); 690 691 kfd_signal_reset_event(kfd); 692 return 0; 693 } 694 695 /* 696 * Fix me. KFD won't be able to resume existing process for now. 697 * We will keep all existing process in a evicted state and 698 * wait the process to be terminated. 699 */ 700 701 int kgd2kfd_post_reset(struct kfd_dev *kfd) 702 { 703 int ret, count; 704 705 if (!kfd->init_complete) 706 return 0; 707 708 dqm_unlock(kfd->dqm); 709 710 ret = kfd_resume(kfd); 711 if (ret) 712 return ret; 713 count = atomic_dec_return(&kfd_locked); 714 WARN_ONCE(count != 0, "KFD reset ref. error"); 715 716 atomic_set(&kfd->sram_ecc_flag, 0); 717 718 return 0; 719 } 720 721 bool kfd_is_locked(void) 722 { 723 return (atomic_read(&kfd_locked) > 0); 724 } 725 726 void kgd2kfd_suspend(struct kfd_dev *kfd) 727 { 728 if (!kfd->init_complete) 729 return; 730 731 /* For first KFD device suspend all the KFD processes */ 732 if (atomic_inc_return(&kfd_locked) == 1) 733 kfd_suspend_all_processes(); 734 735 kfd->dqm->ops.stop(kfd->dqm); 736 737 kfd_iommu_suspend(kfd); 738 } 739 740 int kgd2kfd_resume(struct kfd_dev *kfd) 741 { 742 int ret, count; 743 744 if (!kfd->init_complete) 745 return 0; 746 747 ret = kfd_resume(kfd); 748 if (ret) 749 return ret; 750 751 count = atomic_dec_return(&kfd_locked); 752 WARN_ONCE(count < 0, "KFD suspend / resume ref. error"); 753 if (count == 0) 754 ret = kfd_resume_all_processes(); 755 756 return ret; 757 } 758 759 static int kfd_resume(struct kfd_dev *kfd) 760 { 761 int err = 0; 762 763 err = kfd_iommu_resume(kfd); 764 if (err) { 765 dev_err(kfd_device, 766 "Failed to resume IOMMU for device %x:%x\n", 767 kfd->pdev->vendor, kfd->pdev->device); 768 return err; 769 } 770 771 err = kfd->dqm->ops.start(kfd->dqm); 772 if (err) { 773 dev_err(kfd_device, 774 "Error starting queue manager for device %x:%x\n", 775 kfd->pdev->vendor, kfd->pdev->device); 776 goto dqm_start_error; 777 } 778 779 return err; 780 781 dqm_start_error: 782 kfd_iommu_suspend(kfd); 783 return err; 784 } 785 786 /* This is called directly from KGD at ISR. */ 787 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 788 { 789 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE]; 790 bool is_patched = false; 791 unsigned long flags; 792 793 if (!kfd->init_complete) 794 return; 795 796 if (kfd->device_info->ih_ring_entry_size > sizeof(patched_ihre)) { 797 dev_err_once(kfd_device, "Ring entry too small\n"); 798 return; 799 } 800 801 spin_lock_irqsave(&kfd->interrupt_lock, flags); 802 803 if (kfd->interrupts_active 804 && interrupt_is_wanted(kfd, ih_ring_entry, 805 patched_ihre, &is_patched) 806 && enqueue_ih_ring_entry(kfd, 807 is_patched ? patched_ihre : ih_ring_entry)) 808 queue_work(kfd->ih_wq, &kfd->interrupt_work); 809 810 spin_unlock_irqrestore(&kfd->interrupt_lock, flags); 811 } 812 813 int kgd2kfd_quiesce_mm(struct mm_struct *mm) 814 { 815 struct kfd_process *p; 816 int r; 817 818 /* Because we are called from arbitrary context (workqueue) as opposed 819 * to process context, kfd_process could attempt to exit while we are 820 * running so the lookup function increments the process ref count. 821 */ 822 p = kfd_lookup_process_by_mm(mm); 823 if (!p) 824 return -ESRCH; 825 826 r = kfd_process_evict_queues(p); 827 828 kfd_unref_process(p); 829 return r; 830 } 831 832 int kgd2kfd_resume_mm(struct mm_struct *mm) 833 { 834 struct kfd_process *p; 835 int r; 836 837 /* Because we are called from arbitrary context (workqueue) as opposed 838 * to process context, kfd_process could attempt to exit while we are 839 * running so the lookup function increments the process ref count. 840 */ 841 p = kfd_lookup_process_by_mm(mm); 842 if (!p) 843 return -ESRCH; 844 845 r = kfd_process_restore_queues(p); 846 847 kfd_unref_process(p); 848 return r; 849 } 850 851 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 852 * prepare for safe eviction of KFD BOs that belong to the specified 853 * process. 854 * 855 * @mm: mm_struct that identifies the specified KFD process 856 * @fence: eviction fence attached to KFD process BOs 857 * 858 */ 859 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 860 struct dma_fence *fence) 861 { 862 struct kfd_process *p; 863 unsigned long active_time; 864 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 865 866 if (!fence) 867 return -EINVAL; 868 869 if (dma_fence_is_signaled(fence)) 870 return 0; 871 872 p = kfd_lookup_process_by_mm(mm); 873 if (!p) 874 return -ENODEV; 875 876 if (fence->seqno == p->last_eviction_seqno) 877 goto out; 878 879 p->last_eviction_seqno = fence->seqno; 880 881 /* Avoid KFD process starvation. Wait for at least 882 * PROCESS_ACTIVE_TIME_MS before evicting the process again 883 */ 884 active_time = get_jiffies_64() - p->last_restore_timestamp; 885 if (delay_jiffies > active_time) 886 delay_jiffies -= active_time; 887 else 888 delay_jiffies = 0; 889 890 /* During process initialization eviction_work.dwork is initialized 891 * to kfd_evict_bo_worker 892 */ 893 schedule_delayed_work(&p->eviction_work, delay_jiffies); 894 out: 895 kfd_unref_process(p); 896 return 0; 897 } 898 899 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 900 unsigned int chunk_size) 901 { 902 unsigned int num_of_longs; 903 904 if (WARN_ON(buf_size < chunk_size)) 905 return -EINVAL; 906 if (WARN_ON(buf_size == 0)) 907 return -EINVAL; 908 if (WARN_ON(chunk_size == 0)) 909 return -EINVAL; 910 911 kfd->gtt_sa_chunk_size = chunk_size; 912 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 913 914 num_of_longs = (kfd->gtt_sa_num_of_chunks + BITS_PER_LONG - 1) / 915 BITS_PER_LONG; 916 917 kfd->gtt_sa_bitmap = kcalloc(num_of_longs, sizeof(long), GFP_KERNEL); 918 919 if (!kfd->gtt_sa_bitmap) 920 return -ENOMEM; 921 922 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 923 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 924 925 mutex_init(&kfd->gtt_sa_lock); 926 927 return 0; 928 929 } 930 931 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 932 { 933 mutex_destroy(&kfd->gtt_sa_lock); 934 kfree(kfd->gtt_sa_bitmap); 935 } 936 937 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 938 unsigned int bit_num, 939 unsigned int chunk_size) 940 { 941 return start_addr + bit_num * chunk_size; 942 } 943 944 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 945 unsigned int bit_num, 946 unsigned int chunk_size) 947 { 948 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 949 } 950 951 int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size, 952 struct kfd_mem_obj **mem_obj) 953 { 954 unsigned int found, start_search, cur_size; 955 956 if (size == 0) 957 return -EINVAL; 958 959 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 960 return -ENOMEM; 961 962 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 963 if (!(*mem_obj)) 964 return -ENOMEM; 965 966 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 967 968 start_search = 0; 969 970 mutex_lock(&kfd->gtt_sa_lock); 971 972 kfd_gtt_restart_search: 973 /* Find the first chunk that is free */ 974 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 975 kfd->gtt_sa_num_of_chunks, 976 start_search); 977 978 pr_debug("Found = %d\n", found); 979 980 /* If there wasn't any free chunk, bail out */ 981 if (found == kfd->gtt_sa_num_of_chunks) 982 goto kfd_gtt_no_free_chunk; 983 984 /* Update fields of mem_obj */ 985 (*mem_obj)->range_start = found; 986 (*mem_obj)->range_end = found; 987 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 988 kfd->gtt_start_gpu_addr, 989 found, 990 kfd->gtt_sa_chunk_size); 991 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 992 kfd->gtt_start_cpu_ptr, 993 found, 994 kfd->gtt_sa_chunk_size); 995 996 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 997 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 998 999 /* If we need only one chunk, mark it as allocated and get out */ 1000 if (size <= kfd->gtt_sa_chunk_size) { 1001 pr_debug("Single bit\n"); 1002 set_bit(found, kfd->gtt_sa_bitmap); 1003 goto kfd_gtt_out; 1004 } 1005 1006 /* Otherwise, try to see if we have enough contiguous chunks */ 1007 cur_size = size - kfd->gtt_sa_chunk_size; 1008 do { 1009 (*mem_obj)->range_end = 1010 find_next_zero_bit(kfd->gtt_sa_bitmap, 1011 kfd->gtt_sa_num_of_chunks, ++found); 1012 /* 1013 * If next free chunk is not contiguous than we need to 1014 * restart our search from the last free chunk we found (which 1015 * wasn't contiguous to the previous ones 1016 */ 1017 if ((*mem_obj)->range_end != found) { 1018 start_search = found; 1019 goto kfd_gtt_restart_search; 1020 } 1021 1022 /* 1023 * If we reached end of buffer, bail out with error 1024 */ 1025 if (found == kfd->gtt_sa_num_of_chunks) 1026 goto kfd_gtt_no_free_chunk; 1027 1028 /* Check if we don't need another chunk */ 1029 if (cur_size <= kfd->gtt_sa_chunk_size) 1030 cur_size = 0; 1031 else 1032 cur_size -= kfd->gtt_sa_chunk_size; 1033 1034 } while (cur_size > 0); 1035 1036 pr_debug("range_start = %d, range_end = %d\n", 1037 (*mem_obj)->range_start, (*mem_obj)->range_end); 1038 1039 /* Mark the chunks as allocated */ 1040 for (found = (*mem_obj)->range_start; 1041 found <= (*mem_obj)->range_end; 1042 found++) 1043 set_bit(found, kfd->gtt_sa_bitmap); 1044 1045 kfd_gtt_out: 1046 mutex_unlock(&kfd->gtt_sa_lock); 1047 return 0; 1048 1049 kfd_gtt_no_free_chunk: 1050 pr_debug("Allocation failed with mem_obj = %p\n", mem_obj); 1051 mutex_unlock(&kfd->gtt_sa_lock); 1052 kfree(mem_obj); 1053 return -ENOMEM; 1054 } 1055 1056 int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj) 1057 { 1058 unsigned int bit; 1059 1060 /* Act like kfree when trying to free a NULL object */ 1061 if (!mem_obj) 1062 return 0; 1063 1064 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1065 mem_obj, mem_obj->range_start, mem_obj->range_end); 1066 1067 mutex_lock(&kfd->gtt_sa_lock); 1068 1069 /* Mark the chunks as free */ 1070 for (bit = mem_obj->range_start; 1071 bit <= mem_obj->range_end; 1072 bit++) 1073 clear_bit(bit, kfd->gtt_sa_bitmap); 1074 1075 mutex_unlock(&kfd->gtt_sa_lock); 1076 1077 kfree(mem_obj); 1078 return 0; 1079 } 1080 1081 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1082 { 1083 if (kfd) 1084 atomic_inc(&kfd->sram_ecc_flag); 1085 } 1086 1087 void kfd_inc_compute_active(struct kfd_dev *kfd) 1088 { 1089 if (atomic_inc_return(&kfd->compute_profile) == 1) 1090 amdgpu_amdkfd_set_compute_idle(kfd->kgd, false); 1091 } 1092 1093 void kfd_dec_compute_active(struct kfd_dev *kfd) 1094 { 1095 int count = atomic_dec_return(&kfd->compute_profile); 1096 1097 if (count == 0) 1098 amdgpu_amdkfd_set_compute_idle(kfd->kgd, true); 1099 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1100 } 1101 1102 #if defined(CONFIG_DEBUG_FS) 1103 1104 /* This function will send a package to HIQ to hang the HWS 1105 * which will trigger a GPU reset and bring the HWS back to normal state 1106 */ 1107 int kfd_debugfs_hang_hws(struct kfd_dev *dev) 1108 { 1109 int r = 0; 1110 1111 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1112 pr_err("HWS is not enabled"); 1113 return -EINVAL; 1114 } 1115 1116 r = pm_debugfs_hang_hws(&dev->dqm->packets); 1117 if (!r) 1118 r = dqm_debugfs_execute_queues(dev->dqm); 1119 1120 return r; 1121 } 1122 1123 #endif 1124