1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/bsearch.h> 24 #include <linux/pci.h> 25 #include <linux/slab.h> 26 #include "kfd_priv.h" 27 #include "kfd_device_queue_manager.h" 28 #include "kfd_pm4_headers_vi.h" 29 #include "cwsr_trap_handler.h" 30 #include "kfd_iommu.h" 31 #include "amdgpu_amdkfd.h" 32 #include "kfd_smi_events.h" 33 34 #define MQD_SIZE_ALIGNED 768 35 36 /* 37 * kfd_locked is used to lock the kfd driver during suspend or reset 38 * once locked, kfd driver will stop any further GPU execution. 39 * create process (open) will return -EAGAIN. 40 */ 41 static atomic_t kfd_locked = ATOMIC_INIT(0); 42 43 #ifdef CONFIG_DRM_AMDGPU_CIK 44 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 45 #endif 46 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 47 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 48 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 49 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 50 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 51 52 static const struct kfd2kgd_calls *kfd2kgd_funcs[] = { 53 #ifdef KFD_SUPPORT_IOMMU_V2 54 #ifdef CONFIG_DRM_AMDGPU_CIK 55 [CHIP_KAVERI] = &gfx_v7_kfd2kgd, 56 #endif 57 [CHIP_CARRIZO] = &gfx_v8_kfd2kgd, 58 [CHIP_RAVEN] = &gfx_v9_kfd2kgd, 59 #endif 60 #ifdef CONFIG_DRM_AMDGPU_CIK 61 [CHIP_HAWAII] = &gfx_v7_kfd2kgd, 62 #endif 63 [CHIP_TONGA] = &gfx_v8_kfd2kgd, 64 [CHIP_FIJI] = &gfx_v8_kfd2kgd, 65 [CHIP_POLARIS10] = &gfx_v8_kfd2kgd, 66 [CHIP_POLARIS11] = &gfx_v8_kfd2kgd, 67 [CHIP_POLARIS12] = &gfx_v8_kfd2kgd, 68 [CHIP_VEGAM] = &gfx_v8_kfd2kgd, 69 [CHIP_VEGA10] = &gfx_v9_kfd2kgd, 70 [CHIP_VEGA12] = &gfx_v9_kfd2kgd, 71 [CHIP_VEGA20] = &gfx_v9_kfd2kgd, 72 [CHIP_RENOIR] = &gfx_v9_kfd2kgd, 73 [CHIP_ARCTURUS] = &arcturus_kfd2kgd, 74 [CHIP_NAVI10] = &gfx_v10_kfd2kgd, 75 [CHIP_NAVI12] = &gfx_v10_kfd2kgd, 76 [CHIP_NAVI14] = &gfx_v10_kfd2kgd, 77 [CHIP_SIENNA_CICHLID] = &gfx_v10_3_kfd2kgd, 78 [CHIP_NAVY_FLOUNDER] = &gfx_v10_3_kfd2kgd, 79 [CHIP_VANGOGH] = &gfx_v10_3_kfd2kgd, 80 }; 81 82 #ifdef KFD_SUPPORT_IOMMU_V2 83 static const struct kfd_device_info kaveri_device_info = { 84 .asic_family = CHIP_KAVERI, 85 .asic_name = "kaveri", 86 .max_pasid_bits = 16, 87 /* max num of queues for KV.TODO should be a dynamic value */ 88 .max_no_of_hqd = 24, 89 .doorbell_size = 4, 90 .ih_ring_entry_size = 4 * sizeof(uint32_t), 91 .event_interrupt_class = &event_interrupt_class_cik, 92 .num_of_watch_points = 4, 93 .mqd_size_aligned = MQD_SIZE_ALIGNED, 94 .supports_cwsr = false, 95 .needs_iommu_device = true, 96 .needs_pci_atomics = false, 97 .num_sdma_engines = 2, 98 .num_xgmi_sdma_engines = 0, 99 .num_sdma_queues_per_engine = 2, 100 }; 101 102 static const struct kfd_device_info carrizo_device_info = { 103 .asic_family = CHIP_CARRIZO, 104 .asic_name = "carrizo", 105 .max_pasid_bits = 16, 106 /* max num of queues for CZ.TODO should be a dynamic value */ 107 .max_no_of_hqd = 24, 108 .doorbell_size = 4, 109 .ih_ring_entry_size = 4 * sizeof(uint32_t), 110 .event_interrupt_class = &event_interrupt_class_cik, 111 .num_of_watch_points = 4, 112 .mqd_size_aligned = MQD_SIZE_ALIGNED, 113 .supports_cwsr = true, 114 .needs_iommu_device = true, 115 .needs_pci_atomics = false, 116 .num_sdma_engines = 2, 117 .num_xgmi_sdma_engines = 0, 118 .num_sdma_queues_per_engine = 2, 119 }; 120 #endif 121 122 static const struct kfd_device_info raven_device_info = { 123 .asic_family = CHIP_RAVEN, 124 .asic_name = "raven", 125 .max_pasid_bits = 16, 126 .max_no_of_hqd = 24, 127 .doorbell_size = 8, 128 .ih_ring_entry_size = 8 * sizeof(uint32_t), 129 .event_interrupt_class = &event_interrupt_class_v9, 130 .num_of_watch_points = 4, 131 .mqd_size_aligned = MQD_SIZE_ALIGNED, 132 .supports_cwsr = true, 133 .needs_iommu_device = true, 134 .needs_pci_atomics = true, 135 .num_sdma_engines = 1, 136 .num_xgmi_sdma_engines = 0, 137 .num_sdma_queues_per_engine = 2, 138 }; 139 140 static const struct kfd_device_info hawaii_device_info = { 141 .asic_family = CHIP_HAWAII, 142 .asic_name = "hawaii", 143 .max_pasid_bits = 16, 144 /* max num of queues for KV.TODO should be a dynamic value */ 145 .max_no_of_hqd = 24, 146 .doorbell_size = 4, 147 .ih_ring_entry_size = 4 * sizeof(uint32_t), 148 .event_interrupt_class = &event_interrupt_class_cik, 149 .num_of_watch_points = 4, 150 .mqd_size_aligned = MQD_SIZE_ALIGNED, 151 .supports_cwsr = false, 152 .needs_iommu_device = false, 153 .needs_pci_atomics = false, 154 .num_sdma_engines = 2, 155 .num_xgmi_sdma_engines = 0, 156 .num_sdma_queues_per_engine = 2, 157 }; 158 159 static const struct kfd_device_info tonga_device_info = { 160 .asic_family = CHIP_TONGA, 161 .asic_name = "tonga", 162 .max_pasid_bits = 16, 163 .max_no_of_hqd = 24, 164 .doorbell_size = 4, 165 .ih_ring_entry_size = 4 * sizeof(uint32_t), 166 .event_interrupt_class = &event_interrupt_class_cik, 167 .num_of_watch_points = 4, 168 .mqd_size_aligned = MQD_SIZE_ALIGNED, 169 .supports_cwsr = false, 170 .needs_iommu_device = false, 171 .needs_pci_atomics = true, 172 .num_sdma_engines = 2, 173 .num_xgmi_sdma_engines = 0, 174 .num_sdma_queues_per_engine = 2, 175 }; 176 177 static const struct kfd_device_info fiji_device_info = { 178 .asic_family = CHIP_FIJI, 179 .asic_name = "fiji", 180 .max_pasid_bits = 16, 181 .max_no_of_hqd = 24, 182 .doorbell_size = 4, 183 .ih_ring_entry_size = 4 * sizeof(uint32_t), 184 .event_interrupt_class = &event_interrupt_class_cik, 185 .num_of_watch_points = 4, 186 .mqd_size_aligned = MQD_SIZE_ALIGNED, 187 .supports_cwsr = true, 188 .needs_iommu_device = false, 189 .needs_pci_atomics = true, 190 .num_sdma_engines = 2, 191 .num_xgmi_sdma_engines = 0, 192 .num_sdma_queues_per_engine = 2, 193 }; 194 195 static const struct kfd_device_info fiji_vf_device_info = { 196 .asic_family = CHIP_FIJI, 197 .asic_name = "fiji", 198 .max_pasid_bits = 16, 199 .max_no_of_hqd = 24, 200 .doorbell_size = 4, 201 .ih_ring_entry_size = 4 * sizeof(uint32_t), 202 .event_interrupt_class = &event_interrupt_class_cik, 203 .num_of_watch_points = 4, 204 .mqd_size_aligned = MQD_SIZE_ALIGNED, 205 .supports_cwsr = true, 206 .needs_iommu_device = false, 207 .needs_pci_atomics = false, 208 .num_sdma_engines = 2, 209 .num_xgmi_sdma_engines = 0, 210 .num_sdma_queues_per_engine = 2, 211 }; 212 213 214 static const struct kfd_device_info polaris10_device_info = { 215 .asic_family = CHIP_POLARIS10, 216 .asic_name = "polaris10", 217 .max_pasid_bits = 16, 218 .max_no_of_hqd = 24, 219 .doorbell_size = 4, 220 .ih_ring_entry_size = 4 * sizeof(uint32_t), 221 .event_interrupt_class = &event_interrupt_class_cik, 222 .num_of_watch_points = 4, 223 .mqd_size_aligned = MQD_SIZE_ALIGNED, 224 .supports_cwsr = true, 225 .needs_iommu_device = false, 226 .needs_pci_atomics = true, 227 .num_sdma_engines = 2, 228 .num_xgmi_sdma_engines = 0, 229 .num_sdma_queues_per_engine = 2, 230 }; 231 232 static const struct kfd_device_info polaris10_vf_device_info = { 233 .asic_family = CHIP_POLARIS10, 234 .asic_name = "polaris10", 235 .max_pasid_bits = 16, 236 .max_no_of_hqd = 24, 237 .doorbell_size = 4, 238 .ih_ring_entry_size = 4 * sizeof(uint32_t), 239 .event_interrupt_class = &event_interrupt_class_cik, 240 .num_of_watch_points = 4, 241 .mqd_size_aligned = MQD_SIZE_ALIGNED, 242 .supports_cwsr = true, 243 .needs_iommu_device = false, 244 .needs_pci_atomics = false, 245 .num_sdma_engines = 2, 246 .num_xgmi_sdma_engines = 0, 247 .num_sdma_queues_per_engine = 2, 248 }; 249 250 static const struct kfd_device_info polaris11_device_info = { 251 .asic_family = CHIP_POLARIS11, 252 .asic_name = "polaris11", 253 .max_pasid_bits = 16, 254 .max_no_of_hqd = 24, 255 .doorbell_size = 4, 256 .ih_ring_entry_size = 4 * sizeof(uint32_t), 257 .event_interrupt_class = &event_interrupt_class_cik, 258 .num_of_watch_points = 4, 259 .mqd_size_aligned = MQD_SIZE_ALIGNED, 260 .supports_cwsr = true, 261 .needs_iommu_device = false, 262 .needs_pci_atomics = true, 263 .num_sdma_engines = 2, 264 .num_xgmi_sdma_engines = 0, 265 .num_sdma_queues_per_engine = 2, 266 }; 267 268 static const struct kfd_device_info polaris12_device_info = { 269 .asic_family = CHIP_POLARIS12, 270 .asic_name = "polaris12", 271 .max_pasid_bits = 16, 272 .max_no_of_hqd = 24, 273 .doorbell_size = 4, 274 .ih_ring_entry_size = 4 * sizeof(uint32_t), 275 .event_interrupt_class = &event_interrupt_class_cik, 276 .num_of_watch_points = 4, 277 .mqd_size_aligned = MQD_SIZE_ALIGNED, 278 .supports_cwsr = true, 279 .needs_iommu_device = false, 280 .needs_pci_atomics = true, 281 .num_sdma_engines = 2, 282 .num_xgmi_sdma_engines = 0, 283 .num_sdma_queues_per_engine = 2, 284 }; 285 286 static const struct kfd_device_info vegam_device_info = { 287 .asic_family = CHIP_VEGAM, 288 .asic_name = "vegam", 289 .max_pasid_bits = 16, 290 .max_no_of_hqd = 24, 291 .doorbell_size = 4, 292 .ih_ring_entry_size = 4 * sizeof(uint32_t), 293 .event_interrupt_class = &event_interrupt_class_cik, 294 .num_of_watch_points = 4, 295 .mqd_size_aligned = MQD_SIZE_ALIGNED, 296 .supports_cwsr = true, 297 .needs_iommu_device = false, 298 .needs_pci_atomics = true, 299 .num_sdma_engines = 2, 300 .num_xgmi_sdma_engines = 0, 301 .num_sdma_queues_per_engine = 2, 302 }; 303 304 static const struct kfd_device_info vega10_device_info = { 305 .asic_family = CHIP_VEGA10, 306 .asic_name = "vega10", 307 .max_pasid_bits = 16, 308 .max_no_of_hqd = 24, 309 .doorbell_size = 8, 310 .ih_ring_entry_size = 8 * sizeof(uint32_t), 311 .event_interrupt_class = &event_interrupt_class_v9, 312 .num_of_watch_points = 4, 313 .mqd_size_aligned = MQD_SIZE_ALIGNED, 314 .supports_cwsr = true, 315 .needs_iommu_device = false, 316 .needs_pci_atomics = false, 317 .num_sdma_engines = 2, 318 .num_xgmi_sdma_engines = 0, 319 .num_sdma_queues_per_engine = 2, 320 }; 321 322 static const struct kfd_device_info vega10_vf_device_info = { 323 .asic_family = CHIP_VEGA10, 324 .asic_name = "vega10", 325 .max_pasid_bits = 16, 326 .max_no_of_hqd = 24, 327 .doorbell_size = 8, 328 .ih_ring_entry_size = 8 * sizeof(uint32_t), 329 .event_interrupt_class = &event_interrupt_class_v9, 330 .num_of_watch_points = 4, 331 .mqd_size_aligned = MQD_SIZE_ALIGNED, 332 .supports_cwsr = true, 333 .needs_iommu_device = false, 334 .needs_pci_atomics = false, 335 .num_sdma_engines = 2, 336 .num_xgmi_sdma_engines = 0, 337 .num_sdma_queues_per_engine = 2, 338 }; 339 340 static const struct kfd_device_info vega12_device_info = { 341 .asic_family = CHIP_VEGA12, 342 .asic_name = "vega12", 343 .max_pasid_bits = 16, 344 .max_no_of_hqd = 24, 345 .doorbell_size = 8, 346 .ih_ring_entry_size = 8 * sizeof(uint32_t), 347 .event_interrupt_class = &event_interrupt_class_v9, 348 .num_of_watch_points = 4, 349 .mqd_size_aligned = MQD_SIZE_ALIGNED, 350 .supports_cwsr = true, 351 .needs_iommu_device = false, 352 .needs_pci_atomics = false, 353 .num_sdma_engines = 2, 354 .num_xgmi_sdma_engines = 0, 355 .num_sdma_queues_per_engine = 2, 356 }; 357 358 static const struct kfd_device_info vega20_device_info = { 359 .asic_family = CHIP_VEGA20, 360 .asic_name = "vega20", 361 .max_pasid_bits = 16, 362 .max_no_of_hqd = 24, 363 .doorbell_size = 8, 364 .ih_ring_entry_size = 8 * sizeof(uint32_t), 365 .event_interrupt_class = &event_interrupt_class_v9, 366 .num_of_watch_points = 4, 367 .mqd_size_aligned = MQD_SIZE_ALIGNED, 368 .supports_cwsr = true, 369 .needs_iommu_device = false, 370 .needs_pci_atomics = false, 371 .num_sdma_engines = 2, 372 .num_xgmi_sdma_engines = 0, 373 .num_sdma_queues_per_engine = 8, 374 }; 375 376 static const struct kfd_device_info arcturus_device_info = { 377 .asic_family = CHIP_ARCTURUS, 378 .asic_name = "arcturus", 379 .max_pasid_bits = 16, 380 .max_no_of_hqd = 24, 381 .doorbell_size = 8, 382 .ih_ring_entry_size = 8 * sizeof(uint32_t), 383 .event_interrupt_class = &event_interrupt_class_v9, 384 .num_of_watch_points = 4, 385 .mqd_size_aligned = MQD_SIZE_ALIGNED, 386 .supports_cwsr = true, 387 .needs_iommu_device = false, 388 .needs_pci_atomics = false, 389 .num_sdma_engines = 2, 390 .num_xgmi_sdma_engines = 6, 391 .num_sdma_queues_per_engine = 8, 392 }; 393 394 static const struct kfd_device_info renoir_device_info = { 395 .asic_family = CHIP_RENOIR, 396 .asic_name = "renoir", 397 .max_pasid_bits = 16, 398 .max_no_of_hqd = 24, 399 .doorbell_size = 8, 400 .ih_ring_entry_size = 8 * sizeof(uint32_t), 401 .event_interrupt_class = &event_interrupt_class_v9, 402 .num_of_watch_points = 4, 403 .mqd_size_aligned = MQD_SIZE_ALIGNED, 404 .supports_cwsr = true, 405 .needs_iommu_device = false, 406 .needs_pci_atomics = false, 407 .num_sdma_engines = 1, 408 .num_xgmi_sdma_engines = 0, 409 .num_sdma_queues_per_engine = 2, 410 }; 411 412 static const struct kfd_device_info navi10_device_info = { 413 .asic_family = CHIP_NAVI10, 414 .asic_name = "navi10", 415 .max_pasid_bits = 16, 416 .max_no_of_hqd = 24, 417 .doorbell_size = 8, 418 .ih_ring_entry_size = 8 * sizeof(uint32_t), 419 .event_interrupt_class = &event_interrupt_class_v9, 420 .num_of_watch_points = 4, 421 .mqd_size_aligned = MQD_SIZE_ALIGNED, 422 .needs_iommu_device = false, 423 .supports_cwsr = true, 424 .needs_pci_atomics = false, 425 .num_sdma_engines = 2, 426 .num_xgmi_sdma_engines = 0, 427 .num_sdma_queues_per_engine = 8, 428 }; 429 430 static const struct kfd_device_info navi12_device_info = { 431 .asic_family = CHIP_NAVI12, 432 .asic_name = "navi12", 433 .max_pasid_bits = 16, 434 .max_no_of_hqd = 24, 435 .doorbell_size = 8, 436 .ih_ring_entry_size = 8 * sizeof(uint32_t), 437 .event_interrupt_class = &event_interrupt_class_v9, 438 .num_of_watch_points = 4, 439 .mqd_size_aligned = MQD_SIZE_ALIGNED, 440 .needs_iommu_device = false, 441 .supports_cwsr = true, 442 .needs_pci_atomics = false, 443 .num_sdma_engines = 2, 444 .num_xgmi_sdma_engines = 0, 445 .num_sdma_queues_per_engine = 8, 446 }; 447 448 static const struct kfd_device_info navi14_device_info = { 449 .asic_family = CHIP_NAVI14, 450 .asic_name = "navi14", 451 .max_pasid_bits = 16, 452 .max_no_of_hqd = 24, 453 .doorbell_size = 8, 454 .ih_ring_entry_size = 8 * sizeof(uint32_t), 455 .event_interrupt_class = &event_interrupt_class_v9, 456 .num_of_watch_points = 4, 457 .mqd_size_aligned = MQD_SIZE_ALIGNED, 458 .needs_iommu_device = false, 459 .supports_cwsr = true, 460 .needs_pci_atomics = false, 461 .num_sdma_engines = 2, 462 .num_xgmi_sdma_engines = 0, 463 .num_sdma_queues_per_engine = 8, 464 }; 465 466 static const struct kfd_device_info sienna_cichlid_device_info = { 467 .asic_family = CHIP_SIENNA_CICHLID, 468 .asic_name = "sienna_cichlid", 469 .max_pasid_bits = 16, 470 .max_no_of_hqd = 24, 471 .doorbell_size = 8, 472 .ih_ring_entry_size = 8 * sizeof(uint32_t), 473 .event_interrupt_class = &event_interrupt_class_v9, 474 .num_of_watch_points = 4, 475 .mqd_size_aligned = MQD_SIZE_ALIGNED, 476 .needs_iommu_device = false, 477 .supports_cwsr = true, 478 .needs_pci_atomics = false, 479 .num_sdma_engines = 4, 480 .num_xgmi_sdma_engines = 0, 481 .num_sdma_queues_per_engine = 8, 482 }; 483 484 static const struct kfd_device_info navy_flounder_device_info = { 485 .asic_family = CHIP_NAVY_FLOUNDER, 486 .asic_name = "navy_flounder", 487 .max_pasid_bits = 16, 488 .max_no_of_hqd = 24, 489 .doorbell_size = 8, 490 .ih_ring_entry_size = 8 * sizeof(uint32_t), 491 .event_interrupt_class = &event_interrupt_class_v9, 492 .num_of_watch_points = 4, 493 .mqd_size_aligned = MQD_SIZE_ALIGNED, 494 .needs_iommu_device = false, 495 .supports_cwsr = true, 496 .needs_pci_atomics = false, 497 .num_sdma_engines = 2, 498 .num_xgmi_sdma_engines = 0, 499 .num_sdma_queues_per_engine = 8, 500 }; 501 502 static const struct kfd_device_info vangogh_device_info = { 503 .asic_family = CHIP_VANGOGH, 504 .asic_name = "vangogh", 505 .max_pasid_bits = 16, 506 .max_no_of_hqd = 24, 507 .doorbell_size = 8, 508 .ih_ring_entry_size = 8 * sizeof(uint32_t), 509 .event_interrupt_class = &event_interrupt_class_v9, 510 .num_of_watch_points = 4, 511 .mqd_size_aligned = MQD_SIZE_ALIGNED, 512 .needs_iommu_device = false, 513 .supports_cwsr = true, 514 .needs_pci_atomics = false, 515 .num_sdma_engines = 1, 516 .num_xgmi_sdma_engines = 0, 517 .num_sdma_queues_per_engine = 2, 518 }; 519 520 /* For each entry, [0] is regular and [1] is virtualisation device. */ 521 static const struct kfd_device_info *kfd_supported_devices[][2] = { 522 #ifdef KFD_SUPPORT_IOMMU_V2 523 [CHIP_KAVERI] = {&kaveri_device_info, NULL}, 524 [CHIP_CARRIZO] = {&carrizo_device_info, NULL}, 525 #endif 526 [CHIP_RAVEN] = {&raven_device_info, NULL}, 527 [CHIP_HAWAII] = {&hawaii_device_info, NULL}, 528 [CHIP_TONGA] = {&tonga_device_info, NULL}, 529 [CHIP_FIJI] = {&fiji_device_info, &fiji_vf_device_info}, 530 [CHIP_POLARIS10] = {&polaris10_device_info, &polaris10_vf_device_info}, 531 [CHIP_POLARIS11] = {&polaris11_device_info, NULL}, 532 [CHIP_POLARIS12] = {&polaris12_device_info, NULL}, 533 [CHIP_VEGAM] = {&vegam_device_info, NULL}, 534 [CHIP_VEGA10] = {&vega10_device_info, &vega10_vf_device_info}, 535 [CHIP_VEGA12] = {&vega12_device_info, NULL}, 536 [CHIP_VEGA20] = {&vega20_device_info, NULL}, 537 [CHIP_RENOIR] = {&renoir_device_info, NULL}, 538 [CHIP_ARCTURUS] = {&arcturus_device_info, &arcturus_device_info}, 539 [CHIP_NAVI10] = {&navi10_device_info, NULL}, 540 [CHIP_NAVI12] = {&navi12_device_info, &navi12_device_info}, 541 [CHIP_NAVI14] = {&navi14_device_info, NULL}, 542 [CHIP_SIENNA_CICHLID] = {&sienna_cichlid_device_info, &sienna_cichlid_device_info}, 543 [CHIP_NAVY_FLOUNDER] = {&navy_flounder_device_info, &navy_flounder_device_info}, 544 [CHIP_VANGOGH] = {&vangogh_device_info, NULL}, 545 }; 546 547 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 548 unsigned int chunk_size); 549 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 550 551 static int kfd_resume(struct kfd_dev *kfd); 552 553 struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, 554 struct pci_dev *pdev, unsigned int asic_type, bool vf) 555 { 556 struct kfd_dev *kfd; 557 const struct kfd_device_info *device_info; 558 const struct kfd2kgd_calls *f2g; 559 560 if (asic_type >= sizeof(kfd_supported_devices) / (sizeof(void *) * 2) 561 || asic_type >= sizeof(kfd2kgd_funcs) / sizeof(void *)) { 562 dev_err(kfd_device, "asic_type %d out of range\n", asic_type); 563 return NULL; /* asic_type out of range */ 564 } 565 566 device_info = kfd_supported_devices[asic_type][vf]; 567 f2g = kfd2kgd_funcs[asic_type]; 568 569 if (!device_info || !f2g) { 570 dev_err(kfd_device, "%s %s not supported in kfd\n", 571 amdgpu_asic_name[asic_type], vf ? "VF" : ""); 572 return NULL; 573 } 574 575 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 576 if (!kfd) 577 return NULL; 578 579 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 580 * 32 and 64-bit requests are possible and must be 581 * supported. 582 */ 583 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kgd); 584 if (device_info->needs_pci_atomics && 585 !kfd->pci_atomic_requested) { 586 dev_info(kfd_device, 587 "skipped device %x:%x, PCI rejects atomics\n", 588 pdev->vendor, pdev->device); 589 kfree(kfd); 590 return NULL; 591 } 592 593 kfd->kgd = kgd; 594 kfd->device_info = device_info; 595 kfd->pdev = pdev; 596 kfd->init_complete = false; 597 kfd->kfd2kgd = f2g; 598 atomic_set(&kfd->compute_profile, 0); 599 600 mutex_init(&kfd->doorbell_mutex); 601 memset(&kfd->doorbell_available_index, 0, 602 sizeof(kfd->doorbell_available_index)); 603 604 atomic_set(&kfd->sram_ecc_flag, 0); 605 606 ida_init(&kfd->doorbell_ida); 607 608 return kfd; 609 } 610 611 static void kfd_cwsr_init(struct kfd_dev *kfd) 612 { 613 if (cwsr_enable && kfd->device_info->supports_cwsr) { 614 if (kfd->device_info->asic_family < CHIP_VEGA10) { 615 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE); 616 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 617 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 618 } else if (kfd->device_info->asic_family == CHIP_ARCTURUS) { 619 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE); 620 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 621 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 622 } else if (kfd->device_info->asic_family < CHIP_NAVI10) { 623 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE); 624 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 625 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 626 } else if (kfd->device_info->asic_family < CHIP_SIENNA_CICHLID) { 627 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE); 628 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 629 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 630 } else { 631 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE); 632 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 633 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 634 } 635 636 kfd->cwsr_enabled = true; 637 } 638 } 639 640 static int kfd_gws_init(struct kfd_dev *kfd) 641 { 642 int ret = 0; 643 644 if (kfd->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 645 return 0; 646 647 if (hws_gws_support 648 || (kfd->device_info->asic_family == CHIP_VEGA10 649 && kfd->mec2_fw_version >= 0x81b3) 650 || (kfd->device_info->asic_family >= CHIP_VEGA12 651 && kfd->device_info->asic_family <= CHIP_RAVEN 652 && kfd->mec2_fw_version >= 0x1b3) 653 || (kfd->device_info->asic_family == CHIP_ARCTURUS 654 && kfd->mec2_fw_version >= 0x30)) 655 ret = amdgpu_amdkfd_alloc_gws(kfd->kgd, 656 amdgpu_amdkfd_get_num_gws(kfd->kgd), &kfd->gws); 657 658 return ret; 659 } 660 661 static void kfd_smi_init(struct kfd_dev *dev) { 662 INIT_LIST_HEAD(&dev->smi_clients); 663 spin_lock_init(&dev->smi_lock); 664 } 665 666 bool kgd2kfd_device_init(struct kfd_dev *kfd, 667 struct drm_device *ddev, 668 const struct kgd2kfd_shared_resources *gpu_resources) 669 { 670 unsigned int size; 671 672 kfd->ddev = ddev; 673 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd, 674 KGD_ENGINE_MEC1); 675 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd, 676 KGD_ENGINE_MEC2); 677 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd, 678 KGD_ENGINE_SDMA1); 679 kfd->shared_resources = *gpu_resources; 680 681 kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 682 kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 683 kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd 684 - kfd->vm_info.first_vmid_kfd + 1; 685 686 /* Verify module parameters regarding mapped process number*/ 687 if ((hws_max_conc_proc < 0) 688 || (hws_max_conc_proc > kfd->vm_info.vmid_num_kfd)) { 689 dev_err(kfd_device, 690 "hws_max_conc_proc %d must be between 0 and %d, use %d instead\n", 691 hws_max_conc_proc, kfd->vm_info.vmid_num_kfd, 692 kfd->vm_info.vmid_num_kfd); 693 kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd; 694 } else 695 kfd->max_proc_per_quantum = hws_max_conc_proc; 696 697 /* calculate max size of mqds needed for queues */ 698 size = max_num_of_queues_per_device * 699 kfd->device_info->mqd_size_aligned; 700 701 /* 702 * calculate max size of runlist packet. 703 * There can be only 2 packets at once 704 */ 705 size += (KFD_MAX_NUM_OF_PROCESSES * sizeof(struct pm4_mes_map_process) + 706 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 707 + sizeof(struct pm4_mes_runlist)) * 2; 708 709 /* Add size of HIQ & DIQ */ 710 size += KFD_KERNEL_QUEUE_SIZE * 2; 711 712 /* add another 512KB for all other allocations on gart (HPD, fences) */ 713 size += 512 * 1024; 714 715 if (amdgpu_amdkfd_alloc_gtt_mem( 716 kfd->kgd, size, &kfd->gtt_mem, 717 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 718 false)) { 719 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 720 goto alloc_gtt_mem_failure; 721 } 722 723 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 724 725 /* Initialize GTT sa with 512 byte chunk size */ 726 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 727 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 728 goto kfd_gtt_sa_init_error; 729 } 730 731 if (kfd_doorbell_init(kfd)) { 732 dev_err(kfd_device, 733 "Error initializing doorbell aperture\n"); 734 goto kfd_doorbell_error; 735 } 736 737 kfd->hive_id = amdgpu_amdkfd_get_hive_id(kfd->kgd); 738 739 kfd->unique_id = amdgpu_amdkfd_get_unique_id(kfd->kgd); 740 741 kfd->noretry = amdgpu_amdkfd_get_noretry(kfd->kgd); 742 743 if (kfd_interrupt_init(kfd)) { 744 dev_err(kfd_device, "Error initializing interrupts\n"); 745 goto kfd_interrupt_error; 746 } 747 748 kfd->dqm = device_queue_manager_init(kfd); 749 if (!kfd->dqm) { 750 dev_err(kfd_device, "Error initializing queue manager\n"); 751 goto device_queue_manager_error; 752 } 753 754 /* If supported on this device, allocate global GWS that is shared 755 * by all KFD processes 756 */ 757 if (kfd_gws_init(kfd)) { 758 dev_err(kfd_device, "Could not allocate %d gws\n", 759 amdgpu_amdkfd_get_num_gws(kfd->kgd)); 760 goto gws_error; 761 } 762 763 /* If CRAT is broken, won't set iommu enabled */ 764 kfd_double_confirm_iommu_support(kfd); 765 766 if (kfd_iommu_device_init(kfd)) { 767 dev_err(kfd_device, "Error initializing iommuv2\n"); 768 goto device_iommu_error; 769 } 770 771 kfd_cwsr_init(kfd); 772 773 if (kfd_resume(kfd)) 774 goto kfd_resume_error; 775 776 kfd->dbgmgr = NULL; 777 778 if (kfd_topology_add_device(kfd)) { 779 dev_err(kfd_device, "Error adding device to topology\n"); 780 goto kfd_topology_add_device_error; 781 } 782 783 kfd_smi_init(kfd); 784 785 kfd->init_complete = true; 786 dev_info(kfd_device, "added device %x:%x\n", kfd->pdev->vendor, 787 kfd->pdev->device); 788 789 pr_debug("Starting kfd with the following scheduling policy %d\n", 790 kfd->dqm->sched_policy); 791 792 goto out; 793 794 kfd_topology_add_device_error: 795 kfd_resume_error: 796 device_iommu_error: 797 gws_error: 798 device_queue_manager_uninit(kfd->dqm); 799 device_queue_manager_error: 800 kfd_interrupt_exit(kfd); 801 kfd_interrupt_error: 802 kfd_doorbell_fini(kfd); 803 kfd_doorbell_error: 804 kfd_gtt_sa_fini(kfd); 805 kfd_gtt_sa_init_error: 806 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem); 807 alloc_gtt_mem_failure: 808 if (kfd->gws) 809 amdgpu_amdkfd_free_gws(kfd->kgd, kfd->gws); 810 dev_err(kfd_device, 811 "device %x:%x NOT added due to errors\n", 812 kfd->pdev->vendor, kfd->pdev->device); 813 out: 814 return kfd->init_complete; 815 } 816 817 void kgd2kfd_device_exit(struct kfd_dev *kfd) 818 { 819 if (kfd->init_complete) { 820 kgd2kfd_suspend(kfd, false); 821 device_queue_manager_uninit(kfd->dqm); 822 kfd_interrupt_exit(kfd); 823 kfd_topology_remove_device(kfd); 824 kfd_doorbell_fini(kfd); 825 ida_destroy(&kfd->doorbell_ida); 826 kfd_gtt_sa_fini(kfd); 827 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem); 828 if (kfd->gws) 829 amdgpu_amdkfd_free_gws(kfd->kgd, kfd->gws); 830 } 831 832 kfree(kfd); 833 } 834 835 int kgd2kfd_pre_reset(struct kfd_dev *kfd) 836 { 837 if (!kfd->init_complete) 838 return 0; 839 840 kfd_smi_event_update_gpu_reset(kfd, false); 841 842 kfd->dqm->ops.pre_reset(kfd->dqm); 843 844 kgd2kfd_suspend(kfd, false); 845 846 kfd_signal_reset_event(kfd); 847 return 0; 848 } 849 850 /* 851 * Fix me. KFD won't be able to resume existing process for now. 852 * We will keep all existing process in a evicted state and 853 * wait the process to be terminated. 854 */ 855 856 int kgd2kfd_post_reset(struct kfd_dev *kfd) 857 { 858 int ret; 859 860 if (!kfd->init_complete) 861 return 0; 862 863 ret = kfd_resume(kfd); 864 if (ret) 865 return ret; 866 atomic_dec(&kfd_locked); 867 868 atomic_set(&kfd->sram_ecc_flag, 0); 869 870 kfd_smi_event_update_gpu_reset(kfd, true); 871 872 return 0; 873 } 874 875 bool kfd_is_locked(void) 876 { 877 return (atomic_read(&kfd_locked) > 0); 878 } 879 880 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 881 { 882 if (!kfd->init_complete) 883 return; 884 885 /* for runtime suspend, skip locking kfd */ 886 if (!run_pm) { 887 /* For first KFD device suspend all the KFD processes */ 888 if (atomic_inc_return(&kfd_locked) == 1) 889 kfd_suspend_all_processes(); 890 } 891 892 kfd->dqm->ops.stop(kfd->dqm); 893 kfd_iommu_suspend(kfd); 894 } 895 896 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 897 { 898 int ret, count; 899 900 if (!kfd->init_complete) 901 return 0; 902 903 ret = kfd_resume(kfd); 904 if (ret) 905 return ret; 906 907 /* for runtime resume, skip unlocking kfd */ 908 if (!run_pm) { 909 count = atomic_dec_return(&kfd_locked); 910 WARN_ONCE(count < 0, "KFD suspend / resume ref. error"); 911 if (count == 0) 912 ret = kfd_resume_all_processes(); 913 } 914 915 return ret; 916 } 917 918 static int kfd_resume(struct kfd_dev *kfd) 919 { 920 int err = 0; 921 922 err = kfd_iommu_resume(kfd); 923 if (err) { 924 dev_err(kfd_device, 925 "Failed to resume IOMMU for device %x:%x\n", 926 kfd->pdev->vendor, kfd->pdev->device); 927 return err; 928 } 929 930 err = kfd->dqm->ops.start(kfd->dqm); 931 if (err) { 932 dev_err(kfd_device, 933 "Error starting queue manager for device %x:%x\n", 934 kfd->pdev->vendor, kfd->pdev->device); 935 goto dqm_start_error; 936 } 937 938 return err; 939 940 dqm_start_error: 941 kfd_iommu_suspend(kfd); 942 return err; 943 } 944 945 static inline void kfd_queue_work(struct workqueue_struct *wq, 946 struct work_struct *work) 947 { 948 int cpu, new_cpu; 949 950 cpu = new_cpu = smp_processor_id(); 951 do { 952 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids; 953 if (cpu_to_node(new_cpu) == numa_node_id()) 954 break; 955 } while (cpu != new_cpu); 956 957 queue_work_on(new_cpu, wq, work); 958 } 959 960 /* This is called directly from KGD at ISR. */ 961 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 962 { 963 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE]; 964 bool is_patched = false; 965 unsigned long flags; 966 967 if (!kfd->init_complete) 968 return; 969 970 if (kfd->device_info->ih_ring_entry_size > sizeof(patched_ihre)) { 971 dev_err_once(kfd_device, "Ring entry too small\n"); 972 return; 973 } 974 975 spin_lock_irqsave(&kfd->interrupt_lock, flags); 976 977 if (kfd->interrupts_active 978 && interrupt_is_wanted(kfd, ih_ring_entry, 979 patched_ihre, &is_patched) 980 && enqueue_ih_ring_entry(kfd, 981 is_patched ? patched_ihre : ih_ring_entry)) 982 kfd_queue_work(kfd->ih_wq, &kfd->interrupt_work); 983 984 spin_unlock_irqrestore(&kfd->interrupt_lock, flags); 985 } 986 987 int kgd2kfd_quiesce_mm(struct mm_struct *mm) 988 { 989 struct kfd_process *p; 990 int r; 991 992 /* Because we are called from arbitrary context (workqueue) as opposed 993 * to process context, kfd_process could attempt to exit while we are 994 * running so the lookup function increments the process ref count. 995 */ 996 p = kfd_lookup_process_by_mm(mm); 997 if (!p) 998 return -ESRCH; 999 1000 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 1001 r = kfd_process_evict_queues(p); 1002 1003 kfd_unref_process(p); 1004 return r; 1005 } 1006 1007 int kgd2kfd_resume_mm(struct mm_struct *mm) 1008 { 1009 struct kfd_process *p; 1010 int r; 1011 1012 /* Because we are called from arbitrary context (workqueue) as opposed 1013 * to process context, kfd_process could attempt to exit while we are 1014 * running so the lookup function increments the process ref count. 1015 */ 1016 p = kfd_lookup_process_by_mm(mm); 1017 if (!p) 1018 return -ESRCH; 1019 1020 r = kfd_process_restore_queues(p); 1021 1022 kfd_unref_process(p); 1023 return r; 1024 } 1025 1026 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 1027 * prepare for safe eviction of KFD BOs that belong to the specified 1028 * process. 1029 * 1030 * @mm: mm_struct that identifies the specified KFD process 1031 * @fence: eviction fence attached to KFD process BOs 1032 * 1033 */ 1034 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 1035 struct dma_fence *fence) 1036 { 1037 struct kfd_process *p; 1038 unsigned long active_time; 1039 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 1040 1041 if (!fence) 1042 return -EINVAL; 1043 1044 if (dma_fence_is_signaled(fence)) 1045 return 0; 1046 1047 p = kfd_lookup_process_by_mm(mm); 1048 if (!p) 1049 return -ENODEV; 1050 1051 if (fence->seqno == p->last_eviction_seqno) 1052 goto out; 1053 1054 p->last_eviction_seqno = fence->seqno; 1055 1056 /* Avoid KFD process starvation. Wait for at least 1057 * PROCESS_ACTIVE_TIME_MS before evicting the process again 1058 */ 1059 active_time = get_jiffies_64() - p->last_restore_timestamp; 1060 if (delay_jiffies > active_time) 1061 delay_jiffies -= active_time; 1062 else 1063 delay_jiffies = 0; 1064 1065 /* During process initialization eviction_work.dwork is initialized 1066 * to kfd_evict_bo_worker 1067 */ 1068 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 1069 p->lead_thread->pid, delay_jiffies); 1070 schedule_delayed_work(&p->eviction_work, delay_jiffies); 1071 out: 1072 kfd_unref_process(p); 1073 return 0; 1074 } 1075 1076 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 1077 unsigned int chunk_size) 1078 { 1079 unsigned int num_of_longs; 1080 1081 if (WARN_ON(buf_size < chunk_size)) 1082 return -EINVAL; 1083 if (WARN_ON(buf_size == 0)) 1084 return -EINVAL; 1085 if (WARN_ON(chunk_size == 0)) 1086 return -EINVAL; 1087 1088 kfd->gtt_sa_chunk_size = chunk_size; 1089 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 1090 1091 num_of_longs = (kfd->gtt_sa_num_of_chunks + BITS_PER_LONG - 1) / 1092 BITS_PER_LONG; 1093 1094 kfd->gtt_sa_bitmap = kcalloc(num_of_longs, sizeof(long), GFP_KERNEL); 1095 1096 if (!kfd->gtt_sa_bitmap) 1097 return -ENOMEM; 1098 1099 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 1100 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 1101 1102 mutex_init(&kfd->gtt_sa_lock); 1103 1104 return 0; 1105 1106 } 1107 1108 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 1109 { 1110 mutex_destroy(&kfd->gtt_sa_lock); 1111 kfree(kfd->gtt_sa_bitmap); 1112 } 1113 1114 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 1115 unsigned int bit_num, 1116 unsigned int chunk_size) 1117 { 1118 return start_addr + bit_num * chunk_size; 1119 } 1120 1121 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 1122 unsigned int bit_num, 1123 unsigned int chunk_size) 1124 { 1125 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 1126 } 1127 1128 int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size, 1129 struct kfd_mem_obj **mem_obj) 1130 { 1131 unsigned int found, start_search, cur_size; 1132 1133 if (size == 0) 1134 return -EINVAL; 1135 1136 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 1137 return -ENOMEM; 1138 1139 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 1140 if (!(*mem_obj)) 1141 return -ENOMEM; 1142 1143 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 1144 1145 start_search = 0; 1146 1147 mutex_lock(&kfd->gtt_sa_lock); 1148 1149 kfd_gtt_restart_search: 1150 /* Find the first chunk that is free */ 1151 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1152 kfd->gtt_sa_num_of_chunks, 1153 start_search); 1154 1155 pr_debug("Found = %d\n", found); 1156 1157 /* If there wasn't any free chunk, bail out */ 1158 if (found == kfd->gtt_sa_num_of_chunks) 1159 goto kfd_gtt_no_free_chunk; 1160 1161 /* Update fields of mem_obj */ 1162 (*mem_obj)->range_start = found; 1163 (*mem_obj)->range_end = found; 1164 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1165 kfd->gtt_start_gpu_addr, 1166 found, 1167 kfd->gtt_sa_chunk_size); 1168 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1169 kfd->gtt_start_cpu_ptr, 1170 found, 1171 kfd->gtt_sa_chunk_size); 1172 1173 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1174 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1175 1176 /* If we need only one chunk, mark it as allocated and get out */ 1177 if (size <= kfd->gtt_sa_chunk_size) { 1178 pr_debug("Single bit\n"); 1179 set_bit(found, kfd->gtt_sa_bitmap); 1180 goto kfd_gtt_out; 1181 } 1182 1183 /* Otherwise, try to see if we have enough contiguous chunks */ 1184 cur_size = size - kfd->gtt_sa_chunk_size; 1185 do { 1186 (*mem_obj)->range_end = 1187 find_next_zero_bit(kfd->gtt_sa_bitmap, 1188 kfd->gtt_sa_num_of_chunks, ++found); 1189 /* 1190 * If next free chunk is not contiguous than we need to 1191 * restart our search from the last free chunk we found (which 1192 * wasn't contiguous to the previous ones 1193 */ 1194 if ((*mem_obj)->range_end != found) { 1195 start_search = found; 1196 goto kfd_gtt_restart_search; 1197 } 1198 1199 /* 1200 * If we reached end of buffer, bail out with error 1201 */ 1202 if (found == kfd->gtt_sa_num_of_chunks) 1203 goto kfd_gtt_no_free_chunk; 1204 1205 /* Check if we don't need another chunk */ 1206 if (cur_size <= kfd->gtt_sa_chunk_size) 1207 cur_size = 0; 1208 else 1209 cur_size -= kfd->gtt_sa_chunk_size; 1210 1211 } while (cur_size > 0); 1212 1213 pr_debug("range_start = %d, range_end = %d\n", 1214 (*mem_obj)->range_start, (*mem_obj)->range_end); 1215 1216 /* Mark the chunks as allocated */ 1217 for (found = (*mem_obj)->range_start; 1218 found <= (*mem_obj)->range_end; 1219 found++) 1220 set_bit(found, kfd->gtt_sa_bitmap); 1221 1222 kfd_gtt_out: 1223 mutex_unlock(&kfd->gtt_sa_lock); 1224 return 0; 1225 1226 kfd_gtt_no_free_chunk: 1227 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1228 mutex_unlock(&kfd->gtt_sa_lock); 1229 kfree(*mem_obj); 1230 return -ENOMEM; 1231 } 1232 1233 int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj) 1234 { 1235 unsigned int bit; 1236 1237 /* Act like kfree when trying to free a NULL object */ 1238 if (!mem_obj) 1239 return 0; 1240 1241 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1242 mem_obj, mem_obj->range_start, mem_obj->range_end); 1243 1244 mutex_lock(&kfd->gtt_sa_lock); 1245 1246 /* Mark the chunks as free */ 1247 for (bit = mem_obj->range_start; 1248 bit <= mem_obj->range_end; 1249 bit++) 1250 clear_bit(bit, kfd->gtt_sa_bitmap); 1251 1252 mutex_unlock(&kfd->gtt_sa_lock); 1253 1254 kfree(mem_obj); 1255 return 0; 1256 } 1257 1258 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1259 { 1260 if (kfd) 1261 atomic_inc(&kfd->sram_ecc_flag); 1262 } 1263 1264 void kfd_inc_compute_active(struct kfd_dev *kfd) 1265 { 1266 if (atomic_inc_return(&kfd->compute_profile) == 1) 1267 amdgpu_amdkfd_set_compute_idle(kfd->kgd, false); 1268 } 1269 1270 void kfd_dec_compute_active(struct kfd_dev *kfd) 1271 { 1272 int count = atomic_dec_return(&kfd->compute_profile); 1273 1274 if (count == 0) 1275 amdgpu_amdkfd_set_compute_idle(kfd->kgd, true); 1276 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1277 } 1278 1279 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint32_t throttle_bitmask) 1280 { 1281 if (kfd) 1282 kfd_smi_event_update_thermal_throttling(kfd, throttle_bitmask); 1283 } 1284 1285 #if defined(CONFIG_DEBUG_FS) 1286 1287 /* This function will send a package to HIQ to hang the HWS 1288 * which will trigger a GPU reset and bring the HWS back to normal state 1289 */ 1290 int kfd_debugfs_hang_hws(struct kfd_dev *dev) 1291 { 1292 int r = 0; 1293 1294 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1295 pr_err("HWS is not enabled"); 1296 return -EINVAL; 1297 } 1298 1299 r = pm_debugfs_hang_hws(&dev->dqm->packets); 1300 if (!r) 1301 r = dqm_debugfs_execute_queues(dev->dqm); 1302 1303 return r; 1304 } 1305 1306 #endif 1307