1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/bsearch.h> 25 #include <linux/pci.h> 26 #include <linux/slab.h> 27 #include "kfd_priv.h" 28 #include "kfd_device_queue_manager.h" 29 #include "kfd_pm4_headers_vi.h" 30 #include "kfd_pm4_headers_aldebaran.h" 31 #include "cwsr_trap_handler.h" 32 #include "kfd_iommu.h" 33 #include "amdgpu_amdkfd.h" 34 #include "kfd_smi_events.h" 35 #include "kfd_svm.h" 36 #include "kfd_migrate.h" 37 #include "amdgpu.h" 38 #include "amdgpu_xcp.h" 39 40 #define MQD_SIZE_ALIGNED 768 41 42 /* 43 * kfd_locked is used to lock the kfd driver during suspend or reset 44 * once locked, kfd driver will stop any further GPU execution. 45 * create process (open) will return -EAGAIN. 46 */ 47 static int kfd_locked; 48 49 #ifdef CONFIG_DRM_AMDGPU_CIK 50 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 51 #endif 52 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 53 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 54 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 55 extern const struct kfd2kgd_calls aldebaran_kfd2kgd; 56 extern const struct kfd2kgd_calls gc_9_4_3_kfd2kgd; 57 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 58 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 59 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd; 60 61 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 62 unsigned int chunk_size); 63 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 64 65 static int kfd_resume_iommu(struct kfd_dev *kfd); 66 static int kfd_resume(struct kfd_node *kfd); 67 68 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) 69 { 70 uint32_t sdma_version = kfd->adev->ip_versions[SDMA0_HWIP][0]; 71 72 switch (sdma_version) { 73 case IP_VERSION(4, 0, 0):/* VEGA10 */ 74 case IP_VERSION(4, 0, 1):/* VEGA12 */ 75 case IP_VERSION(4, 1, 0):/* RAVEN */ 76 case IP_VERSION(4, 1, 1):/* RAVEN */ 77 case IP_VERSION(4, 1, 2):/* RENOIR */ 78 case IP_VERSION(5, 2, 1):/* VANGOGH */ 79 case IP_VERSION(5, 2, 3):/* YELLOW_CARP */ 80 case IP_VERSION(5, 2, 6):/* GC 10.3.6 */ 81 case IP_VERSION(5, 2, 7):/* GC 10.3.7 */ 82 kfd->device_info.num_sdma_queues_per_engine = 2; 83 break; 84 case IP_VERSION(4, 2, 0):/* VEGA20 */ 85 case IP_VERSION(4, 2, 2):/* ARCTURUS */ 86 case IP_VERSION(4, 4, 0):/* ALDEBARAN */ 87 case IP_VERSION(4, 4, 2): 88 case IP_VERSION(5, 0, 0):/* NAVI10 */ 89 case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */ 90 case IP_VERSION(5, 0, 2):/* NAVI14 */ 91 case IP_VERSION(5, 0, 5):/* NAVI12 */ 92 case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */ 93 case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */ 94 case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */ 95 case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */ 96 case IP_VERSION(6, 0, 0): 97 case IP_VERSION(6, 0, 1): 98 case IP_VERSION(6, 0, 2): 99 case IP_VERSION(6, 0, 3): 100 kfd->device_info.num_sdma_queues_per_engine = 8; 101 break; 102 default: 103 dev_warn(kfd_device, 104 "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n", 105 sdma_version); 106 kfd->device_info.num_sdma_queues_per_engine = 8; 107 } 108 109 switch (sdma_version) { 110 case IP_VERSION(6, 0, 0): 111 case IP_VERSION(6, 0, 2): 112 case IP_VERSION(6, 0, 3): 113 /* Reserve 1 for paging and 1 for gfx */ 114 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 115 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */ 116 kfd->device_info.reserved_sdma_queues_bitmap = 0xFULL; 117 break; 118 case IP_VERSION(6, 0, 1): 119 /* Reserve 1 for paging and 1 for gfx */ 120 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 121 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-0 queue-1; ... */ 122 kfd->device_info.reserved_sdma_queues_bitmap = 0x3ULL; 123 break; 124 default: 125 break; 126 } 127 } 128 129 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) 130 { 131 uint32_t gc_version = KFD_GC_VERSION(kfd); 132 133 switch (gc_version) { 134 case IP_VERSION(9, 0, 1): /* VEGA10 */ 135 case IP_VERSION(9, 1, 0): /* RAVEN */ 136 case IP_VERSION(9, 2, 1): /* VEGA12 */ 137 case IP_VERSION(9, 2, 2): /* RAVEN */ 138 case IP_VERSION(9, 3, 0): /* RENOIR */ 139 case IP_VERSION(9, 4, 0): /* VEGA20 */ 140 case IP_VERSION(9, 4, 1): /* ARCTURUS */ 141 case IP_VERSION(9, 4, 2): /* ALDEBARAN */ 142 case IP_VERSION(10, 3, 1): /* VANGOGH */ 143 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */ 144 case IP_VERSION(10, 3, 6): /* GC 10.3.6 */ 145 case IP_VERSION(10, 3, 7): /* GC 10.3.7 */ 146 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */ 147 case IP_VERSION(10, 1, 4): 148 case IP_VERSION(10, 1, 10): /* NAVI10 */ 149 case IP_VERSION(10, 1, 2): /* NAVI12 */ 150 case IP_VERSION(10, 1, 1): /* NAVI14 */ 151 case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */ 152 case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */ 153 case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */ 154 case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */ 155 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 156 break; 157 case IP_VERSION(11, 0, 0): 158 case IP_VERSION(11, 0, 1): 159 case IP_VERSION(11, 0, 2): 160 case IP_VERSION(11, 0, 3): 161 case IP_VERSION(11, 0, 4): 162 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 163 break; 164 default: 165 dev_warn(kfd_device, "v9 event interrupt handler is set due to " 166 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version); 167 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 168 } 169 } 170 171 static void kfd_device_info_init(struct kfd_dev *kfd, 172 bool vf, uint32_t gfx_target_version) 173 { 174 uint32_t gc_version = KFD_GC_VERSION(kfd); 175 uint32_t asic_type = kfd->adev->asic_type; 176 177 kfd->device_info.max_pasid_bits = 16; 178 kfd->device_info.max_no_of_hqd = 24; 179 kfd->device_info.num_of_watch_points = 4; 180 kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED; 181 kfd->device_info.gfx_target_version = gfx_target_version; 182 183 if (KFD_IS_SOC15(kfd)) { 184 kfd->device_info.doorbell_size = 8; 185 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t); 186 kfd->device_info.supports_cwsr = true; 187 188 kfd_device_info_set_sdma_info(kfd); 189 190 kfd_device_info_set_event_interrupt_class(kfd); 191 192 /* Raven */ 193 if (gc_version == IP_VERSION(9, 1, 0) || 194 gc_version == IP_VERSION(9, 2, 2)) 195 kfd->device_info.needs_iommu_device = true; 196 197 if (gc_version < IP_VERSION(11, 0, 0)) { 198 /* Navi2x+, Navi1x+ */ 199 if (gc_version == IP_VERSION(10, 3, 6)) 200 kfd->device_info.no_atomic_fw_version = 14; 201 else if (gc_version == IP_VERSION(10, 3, 7)) 202 kfd->device_info.no_atomic_fw_version = 3; 203 else if (gc_version >= IP_VERSION(10, 3, 0)) 204 kfd->device_info.no_atomic_fw_version = 92; 205 else if (gc_version >= IP_VERSION(10, 1, 1)) 206 kfd->device_info.no_atomic_fw_version = 145; 207 208 /* Navi1x+ */ 209 if (gc_version >= IP_VERSION(10, 1, 1)) 210 kfd->device_info.needs_pci_atomics = true; 211 } else if (gc_version < IP_VERSION(12, 0, 0)) { 212 /* 213 * PCIe atomics support acknowledgment in GFX11 RS64 CPFW requires 214 * MEC version >= 509. Prior RS64 CPFW versions (and all F32) require 215 * PCIe atomics support. 216 */ 217 kfd->device_info.needs_pci_atomics = true; 218 kfd->device_info.no_atomic_fw_version = kfd->adev->gfx.rs64_enable ? 509 : 0; 219 } 220 } else { 221 kfd->device_info.doorbell_size = 4; 222 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t); 223 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik; 224 kfd->device_info.num_sdma_queues_per_engine = 2; 225 226 if (asic_type != CHIP_KAVERI && 227 asic_type != CHIP_HAWAII && 228 asic_type != CHIP_TONGA) 229 kfd->device_info.supports_cwsr = true; 230 231 if (asic_type == CHIP_KAVERI || 232 asic_type == CHIP_CARRIZO) 233 kfd->device_info.needs_iommu_device = true; 234 235 if (asic_type != CHIP_HAWAII && !vf) 236 kfd->device_info.needs_pci_atomics = true; 237 } 238 } 239 240 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 241 { 242 struct kfd_dev *kfd = NULL; 243 const struct kfd2kgd_calls *f2g = NULL; 244 uint32_t gfx_target_version = 0; 245 246 switch (adev->asic_type) { 247 #ifdef KFD_SUPPORT_IOMMU_V2 248 #ifdef CONFIG_DRM_AMDGPU_CIK 249 case CHIP_KAVERI: 250 gfx_target_version = 70000; 251 if (!vf) 252 f2g = &gfx_v7_kfd2kgd; 253 break; 254 #endif 255 case CHIP_CARRIZO: 256 gfx_target_version = 80001; 257 if (!vf) 258 f2g = &gfx_v8_kfd2kgd; 259 break; 260 #endif 261 #ifdef CONFIG_DRM_AMDGPU_CIK 262 case CHIP_HAWAII: 263 gfx_target_version = 70001; 264 if (!amdgpu_exp_hw_support) 265 pr_info( 266 "KFD support on Hawaii is experimental. See modparam exp_hw_support\n" 267 ); 268 else if (!vf) 269 f2g = &gfx_v7_kfd2kgd; 270 break; 271 #endif 272 case CHIP_TONGA: 273 gfx_target_version = 80002; 274 if (!vf) 275 f2g = &gfx_v8_kfd2kgd; 276 break; 277 case CHIP_FIJI: 278 case CHIP_POLARIS10: 279 gfx_target_version = 80003; 280 f2g = &gfx_v8_kfd2kgd; 281 break; 282 case CHIP_POLARIS11: 283 case CHIP_POLARIS12: 284 case CHIP_VEGAM: 285 gfx_target_version = 80003; 286 if (!vf) 287 f2g = &gfx_v8_kfd2kgd; 288 break; 289 default: 290 switch (adev->ip_versions[GC_HWIP][0]) { 291 /* Vega 10 */ 292 case IP_VERSION(9, 0, 1): 293 gfx_target_version = 90000; 294 f2g = &gfx_v9_kfd2kgd; 295 break; 296 #ifdef KFD_SUPPORT_IOMMU_V2 297 /* Raven */ 298 case IP_VERSION(9, 1, 0): 299 case IP_VERSION(9, 2, 2): 300 gfx_target_version = 90002; 301 if (!vf) 302 f2g = &gfx_v9_kfd2kgd; 303 break; 304 #endif 305 /* Vega12 */ 306 case IP_VERSION(9, 2, 1): 307 gfx_target_version = 90004; 308 if (!vf) 309 f2g = &gfx_v9_kfd2kgd; 310 break; 311 /* Renoir */ 312 case IP_VERSION(9, 3, 0): 313 gfx_target_version = 90012; 314 if (!vf) 315 f2g = &gfx_v9_kfd2kgd; 316 break; 317 /* Vega20 */ 318 case IP_VERSION(9, 4, 0): 319 gfx_target_version = 90006; 320 if (!vf) 321 f2g = &gfx_v9_kfd2kgd; 322 break; 323 /* Arcturus */ 324 case IP_VERSION(9, 4, 1): 325 gfx_target_version = 90008; 326 f2g = &arcturus_kfd2kgd; 327 break; 328 /* Aldebaran */ 329 case IP_VERSION(9, 4, 2): 330 gfx_target_version = 90010; 331 f2g = &aldebaran_kfd2kgd; 332 break; 333 case IP_VERSION(9, 4, 3): 334 gfx_target_version = 90400; 335 f2g = &gc_9_4_3_kfd2kgd; 336 break; 337 /* Navi10 */ 338 case IP_VERSION(10, 1, 10): 339 gfx_target_version = 100100; 340 if (!vf) 341 f2g = &gfx_v10_kfd2kgd; 342 break; 343 /* Navi12 */ 344 case IP_VERSION(10, 1, 2): 345 gfx_target_version = 100101; 346 f2g = &gfx_v10_kfd2kgd; 347 break; 348 /* Navi14 */ 349 case IP_VERSION(10, 1, 1): 350 gfx_target_version = 100102; 351 if (!vf) 352 f2g = &gfx_v10_kfd2kgd; 353 break; 354 /* Cyan Skillfish */ 355 case IP_VERSION(10, 1, 3): 356 case IP_VERSION(10, 1, 4): 357 gfx_target_version = 100103; 358 if (!vf) 359 f2g = &gfx_v10_kfd2kgd; 360 break; 361 /* Sienna Cichlid */ 362 case IP_VERSION(10, 3, 0): 363 gfx_target_version = 100300; 364 f2g = &gfx_v10_3_kfd2kgd; 365 break; 366 /* Navy Flounder */ 367 case IP_VERSION(10, 3, 2): 368 gfx_target_version = 100301; 369 f2g = &gfx_v10_3_kfd2kgd; 370 break; 371 /* Van Gogh */ 372 case IP_VERSION(10, 3, 1): 373 gfx_target_version = 100303; 374 if (!vf) 375 f2g = &gfx_v10_3_kfd2kgd; 376 break; 377 /* Dimgrey Cavefish */ 378 case IP_VERSION(10, 3, 4): 379 gfx_target_version = 100302; 380 f2g = &gfx_v10_3_kfd2kgd; 381 break; 382 /* Beige Goby */ 383 case IP_VERSION(10, 3, 5): 384 gfx_target_version = 100304; 385 f2g = &gfx_v10_3_kfd2kgd; 386 break; 387 /* Yellow Carp */ 388 case IP_VERSION(10, 3, 3): 389 gfx_target_version = 100305; 390 if (!vf) 391 f2g = &gfx_v10_3_kfd2kgd; 392 break; 393 case IP_VERSION(10, 3, 6): 394 case IP_VERSION(10, 3, 7): 395 gfx_target_version = 100306; 396 if (!vf) 397 f2g = &gfx_v10_3_kfd2kgd; 398 break; 399 case IP_VERSION(11, 0, 0): 400 gfx_target_version = 110000; 401 f2g = &gfx_v11_kfd2kgd; 402 break; 403 case IP_VERSION(11, 0, 1): 404 case IP_VERSION(11, 0, 4): 405 gfx_target_version = 110003; 406 f2g = &gfx_v11_kfd2kgd; 407 break; 408 case IP_VERSION(11, 0, 2): 409 gfx_target_version = 110002; 410 f2g = &gfx_v11_kfd2kgd; 411 break; 412 case IP_VERSION(11, 0, 3): 413 /* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */ 414 gfx_target_version = 110001; 415 f2g = &gfx_v11_kfd2kgd; 416 break; 417 default: 418 break; 419 } 420 break; 421 } 422 423 if (!f2g) { 424 if (adev->ip_versions[GC_HWIP][0]) 425 dev_err(kfd_device, "GC IP %06x %s not supported in kfd\n", 426 adev->ip_versions[GC_HWIP][0], vf ? "VF" : ""); 427 else 428 dev_err(kfd_device, "%s %s not supported in kfd\n", 429 amdgpu_asic_name[adev->asic_type], vf ? "VF" : ""); 430 return NULL; 431 } 432 433 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 434 if (!kfd) 435 return NULL; 436 437 kfd->adev = adev; 438 kfd_device_info_init(kfd, vf, gfx_target_version); 439 kfd->init_complete = false; 440 kfd->kfd2kgd = f2g; 441 atomic_set(&kfd->compute_profile, 0); 442 443 mutex_init(&kfd->doorbell_mutex); 444 memset(&kfd->doorbell_available_index, 0, 445 sizeof(kfd->doorbell_available_index)); 446 447 ida_init(&kfd->doorbell_ida); 448 449 return kfd; 450 } 451 452 static void kfd_cwsr_init(struct kfd_dev *kfd) 453 { 454 if (cwsr_enable && kfd->device_info.supports_cwsr) { 455 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) { 456 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE); 457 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 458 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 459 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) { 460 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE); 461 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 462 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 463 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) { 464 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) > PAGE_SIZE); 465 kfd->cwsr_isa = cwsr_trap_aldebaran_hex; 466 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); 467 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3)) { 468 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_4_3_hex) > PAGE_SIZE); 469 kfd->cwsr_isa = cwsr_trap_gfx9_4_3_hex; 470 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_4_3_hex); 471 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) { 472 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE); 473 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 474 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 475 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) { 476 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE); 477 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 478 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 479 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) { 480 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE); 481 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 482 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 483 } else { 484 BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE); 485 kfd->cwsr_isa = cwsr_trap_gfx11_hex; 486 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex); 487 } 488 489 kfd->cwsr_enabled = true; 490 } 491 } 492 493 static int kfd_gws_init(struct kfd_node *node) 494 { 495 int ret = 0; 496 struct kfd_dev *kfd = node->kfd; 497 498 if (node->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 499 return 0; 500 501 if (hws_gws_support || (KFD_IS_SOC15(node) && 502 ((KFD_GC_VERSION(node) == IP_VERSION(9, 0, 1) 503 && kfd->mec2_fw_version >= 0x81b3) || 504 (KFD_GC_VERSION(node) <= IP_VERSION(9, 4, 0) 505 && kfd->mec2_fw_version >= 0x1b3) || 506 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 1) 507 && kfd->mec2_fw_version >= 0x30) || 508 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 2) 509 && kfd->mec2_fw_version >= 0x28) || 510 (KFD_GC_VERSION(node) >= IP_VERSION(10, 3, 0) 511 && KFD_GC_VERSION(node) < IP_VERSION(11, 0, 0) 512 && kfd->mec2_fw_version >= 0x6b)))) 513 ret = amdgpu_amdkfd_alloc_gws(node->adev, 514 node->adev->gds.gws_size, &node->gws); 515 516 return ret; 517 } 518 519 static void kfd_smi_init(struct kfd_node *dev) 520 { 521 INIT_LIST_HEAD(&dev->smi_clients); 522 spin_lock_init(&dev->smi_lock); 523 } 524 525 static int kfd_init_node(struct kfd_node *node) 526 { 527 int err = -1; 528 529 if (kfd_interrupt_init(node)) { 530 dev_err(kfd_device, "Error initializing interrupts\n"); 531 goto kfd_interrupt_error; 532 } 533 534 node->dqm = device_queue_manager_init(node); 535 if (!node->dqm) { 536 dev_err(kfd_device, "Error initializing queue manager\n"); 537 goto device_queue_manager_error; 538 } 539 540 if (kfd_gws_init(node)) { 541 dev_err(kfd_device, "Could not allocate %d gws\n", 542 node->adev->gds.gws_size); 543 goto gws_error; 544 } 545 546 if (kfd_resume(node)) 547 goto kfd_resume_error; 548 549 if (kfd_topology_add_device(node)) { 550 dev_err(kfd_device, "Error adding device to topology\n"); 551 goto kfd_topology_add_device_error; 552 } 553 554 kfd_smi_init(node); 555 556 return 0; 557 558 kfd_topology_add_device_error: 559 kfd_resume_error: 560 gws_error: 561 device_queue_manager_uninit(node->dqm); 562 device_queue_manager_error: 563 kfd_interrupt_exit(node); 564 kfd_interrupt_error: 565 if (node->gws) 566 amdgpu_amdkfd_free_gws(node->adev, node->gws); 567 568 /* Cleanup the node memory here */ 569 kfree(node); 570 return err; 571 } 572 573 static void kfd_cleanup_nodes(struct kfd_dev *kfd, unsigned int num_nodes) 574 { 575 struct kfd_node *knode; 576 unsigned int i; 577 578 for (i = 0; i < num_nodes; i++) { 579 knode = kfd->nodes[i]; 580 device_queue_manager_uninit(knode->dqm); 581 kfd_interrupt_exit(knode); 582 kfd_topology_remove_device(knode); 583 if (knode->gws) 584 amdgpu_amdkfd_free_gws(knode->adev, knode->gws); 585 kfree(knode); 586 kfd->nodes[i] = NULL; 587 } 588 } 589 590 bool kgd2kfd_device_init(struct kfd_dev *kfd, 591 const struct kgd2kfd_shared_resources *gpu_resources) 592 { 593 unsigned int size, map_process_packet_size, i; 594 struct kfd_node *node; 595 uint32_t first_vmid_kfd, last_vmid_kfd, vmid_num_kfd; 596 unsigned int max_proc_per_quantum; 597 int partition_mode; 598 int xcp_idx; 599 600 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 601 KGD_ENGINE_MEC1); 602 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 603 KGD_ENGINE_MEC2); 604 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 605 KGD_ENGINE_SDMA1); 606 kfd->shared_resources = *gpu_resources; 607 608 kfd->num_nodes = amdgpu_xcp_get_num_xcp(kfd->adev->xcp_mgr); 609 610 if (kfd->num_nodes == 0) { 611 dev_err(kfd_device, 612 "KFD num nodes cannot be 0, num_xcc_in_node: %d\n", 613 kfd->adev->gfx.num_xcc_per_xcp); 614 goto out; 615 } 616 617 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 618 * 32 and 64-bit requests are possible and must be 619 * supported. 620 */ 621 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev); 622 if (!kfd->pci_atomic_requested && 623 kfd->device_info.needs_pci_atomics && 624 (!kfd->device_info.no_atomic_fw_version || 625 kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) { 626 dev_info(kfd_device, 627 "skipped device %x:%x, PCI rejects atomics %d<%d\n", 628 kfd->adev->pdev->vendor, kfd->adev->pdev->device, 629 kfd->mec_fw_version, 630 kfd->device_info.no_atomic_fw_version); 631 return false; 632 } 633 634 first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 635 last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 636 vmid_num_kfd = last_vmid_kfd - first_vmid_kfd + 1; 637 638 /* For GFX9.4.3, we need special handling for VMIDs depending on 639 * partition mode. 640 * In CPX mode, the VMID range needs to be shared between XCDs. 641 * Additionally, there are 13 VMIDs (3-15) available for KFD. To 642 * divide them equally, we change starting VMID to 4 and not use 643 * VMID 3. 644 * If the VMID range changes for GFX9.4.3, then this code MUST be 645 * revisited. 646 */ 647 if (kfd->adev->xcp_mgr) { 648 partition_mode = amdgpu_xcp_query_partition_mode(kfd->adev->xcp_mgr, 649 AMDGPU_XCP_FL_LOCKED); 650 if (partition_mode == AMDGPU_CPX_PARTITION_MODE && 651 kfd->num_nodes != 1) { 652 vmid_num_kfd /= 2; 653 first_vmid_kfd = last_vmid_kfd + 1 - vmid_num_kfd*2; 654 } 655 } 656 657 /* Verify module parameters regarding mapped process number*/ 658 if (hws_max_conc_proc >= 0) 659 max_proc_per_quantum = min((u32)hws_max_conc_proc, vmid_num_kfd); 660 else 661 max_proc_per_quantum = vmid_num_kfd; 662 663 /* calculate max size of mqds needed for queues */ 664 size = max_num_of_queues_per_device * 665 kfd->device_info.mqd_size_aligned; 666 667 /* 668 * calculate max size of runlist packet. 669 * There can be only 2 packets at once 670 */ 671 map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ? 672 sizeof(struct pm4_mes_map_process_aldebaran) : 673 sizeof(struct pm4_mes_map_process); 674 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + 675 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 676 + sizeof(struct pm4_mes_runlist)) * 2; 677 678 /* Add size of HIQ & DIQ */ 679 size += KFD_KERNEL_QUEUE_SIZE * 2; 680 681 /* add another 512KB for all other allocations on gart (HPD, fences) */ 682 size += 512 * 1024; 683 684 if (amdgpu_amdkfd_alloc_gtt_mem( 685 kfd->adev, size, &kfd->gtt_mem, 686 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 687 false)) { 688 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 689 goto alloc_gtt_mem_failure; 690 } 691 692 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 693 694 /* Initialize GTT sa with 512 byte chunk size */ 695 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 696 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 697 goto kfd_gtt_sa_init_error; 698 } 699 700 if (kfd_doorbell_init(kfd)) { 701 dev_err(kfd_device, 702 "Error initializing doorbell aperture\n"); 703 goto kfd_doorbell_error; 704 } 705 706 if (amdgpu_use_xgmi_p2p) 707 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id; 708 709 /* 710 * For GFX9.4.3, the KFD abstracts all partitions within a socket as 711 * xGMI connected in the topology so assign a unique hive id per 712 * device based on the pci device location if device is in PCIe mode. 713 */ 714 if (!kfd->hive_id && (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3)) && kfd->num_nodes > 1) 715 kfd->hive_id = pci_dev_id(kfd->adev->pdev); 716 717 kfd->noretry = kfd->adev->gmc.noretry; 718 719 /* If CRAT is broken, won't set iommu enabled */ 720 kfd_double_confirm_iommu_support(kfd); 721 722 if (kfd_iommu_device_init(kfd)) { 723 kfd->use_iommu_v2 = false; 724 dev_err(kfd_device, "Error initializing iommuv2\n"); 725 goto device_iommu_error; 726 } 727 728 kfd_cwsr_init(kfd); 729 730 dev_info(kfd_device, "Total number of KFD nodes to be created: %d\n", 731 kfd->num_nodes); 732 733 /* Allocate the KFD nodes */ 734 for (i = 0, xcp_idx = 0; i < kfd->num_nodes; i++) { 735 node = kzalloc(sizeof(struct kfd_node), GFP_KERNEL); 736 if (!node) 737 goto node_alloc_error; 738 739 node->node_id = i; 740 node->adev = kfd->adev; 741 node->kfd = kfd; 742 node->kfd2kgd = kfd->kfd2kgd; 743 node->vm_info.vmid_num_kfd = vmid_num_kfd; 744 node->xcp = amdgpu_get_next_xcp(kfd->adev->xcp_mgr, &xcp_idx); 745 /* TODO : Check if error handling is needed */ 746 if (node->xcp) { 747 amdgpu_xcp_get_inst_details(node->xcp, AMDGPU_XCP_GFX, 748 &node->xcc_mask); 749 ++xcp_idx; 750 } else { 751 node->xcc_mask = 752 (1U << NUM_XCC(kfd->adev->gfx.xcc_mask)) - 1; 753 } 754 755 if (node->xcp) { 756 dev_info(kfd_device, "KFD node %d partition %d size %lldM\n", 757 node->node_id, node->xcp->mem_id, 758 KFD_XCP_MEMORY_SIZE(node->adev, node->node_id) >> 20); 759 } 760 761 if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) && 762 partition_mode == AMDGPU_CPX_PARTITION_MODE && 763 kfd->num_nodes != 1) { 764 /* For GFX9.4.3 and CPX mode, first XCD gets VMID range 765 * 4-9 and second XCD gets VMID range 10-15. 766 */ 767 768 node->vm_info.first_vmid_kfd = (i%2 == 0) ? 769 first_vmid_kfd : 770 first_vmid_kfd+vmid_num_kfd; 771 node->vm_info.last_vmid_kfd = (i%2 == 0) ? 772 last_vmid_kfd-vmid_num_kfd : 773 last_vmid_kfd; 774 node->compute_vmid_bitmap = 775 ((0x1 << (node->vm_info.last_vmid_kfd + 1)) - 1) - 776 ((0x1 << (node->vm_info.first_vmid_kfd)) - 1); 777 } else { 778 node->vm_info.first_vmid_kfd = first_vmid_kfd; 779 node->vm_info.last_vmid_kfd = last_vmid_kfd; 780 node->compute_vmid_bitmap = 781 gpu_resources->compute_vmid_bitmap; 782 } 783 node->max_proc_per_quantum = max_proc_per_quantum; 784 atomic_set(&node->sram_ecc_flag, 0); 785 786 amdgpu_amdkfd_get_local_mem_info(kfd->adev, 787 &node->local_mem_info, node->xcp); 788 789 /* Initialize the KFD node */ 790 if (kfd_init_node(node)) { 791 dev_err(kfd_device, "Error initializing KFD node\n"); 792 goto node_init_error; 793 } 794 kfd->nodes[i] = node; 795 } 796 797 svm_range_set_max_pages(kfd->adev); 798 799 if (kfd_resume_iommu(kfd)) 800 goto kfd_resume_iommu_error; 801 802 kfd->init_complete = true; 803 dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, 804 kfd->adev->pdev->device); 805 806 pr_debug("Starting kfd with the following scheduling policy %d\n", 807 node->dqm->sched_policy); 808 809 goto out; 810 811 kfd_resume_iommu_error: 812 node_init_error: 813 node_alloc_error: 814 kfd_cleanup_nodes(kfd, i); 815 device_iommu_error: 816 kfd_doorbell_fini(kfd); 817 kfd_doorbell_error: 818 kfd_gtt_sa_fini(kfd); 819 kfd_gtt_sa_init_error: 820 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 821 alloc_gtt_mem_failure: 822 dev_err(kfd_device, 823 "device %x:%x NOT added due to errors\n", 824 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 825 out: 826 return kfd->init_complete; 827 } 828 829 void kgd2kfd_device_exit(struct kfd_dev *kfd) 830 { 831 if (kfd->init_complete) { 832 /* Cleanup KFD nodes */ 833 kfd_cleanup_nodes(kfd, kfd->num_nodes); 834 /* Cleanup common/shared resources */ 835 kfd_doorbell_fini(kfd); 836 ida_destroy(&kfd->doorbell_ida); 837 kfd_gtt_sa_fini(kfd); 838 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 839 } 840 841 kfree(kfd); 842 } 843 844 int kgd2kfd_pre_reset(struct kfd_dev *kfd) 845 { 846 struct kfd_node *node; 847 int i; 848 849 if (!kfd->init_complete) 850 return 0; 851 852 for (i = 0; i < kfd->num_nodes; i++) { 853 node = kfd->nodes[i]; 854 kfd_smi_event_update_gpu_reset(node, false); 855 node->dqm->ops.pre_reset(node->dqm); 856 } 857 858 kgd2kfd_suspend(kfd, false); 859 860 for (i = 0; i < kfd->num_nodes; i++) 861 kfd_signal_reset_event(kfd->nodes[i]); 862 863 return 0; 864 } 865 866 /* 867 * Fix me. KFD won't be able to resume existing process for now. 868 * We will keep all existing process in a evicted state and 869 * wait the process to be terminated. 870 */ 871 872 int kgd2kfd_post_reset(struct kfd_dev *kfd) 873 { 874 int ret; 875 struct kfd_node *node; 876 int i; 877 878 if (!kfd->init_complete) 879 return 0; 880 881 for (i = 0; i < kfd->num_nodes; i++) { 882 ret = kfd_resume(kfd->nodes[i]); 883 if (ret) 884 return ret; 885 } 886 887 mutex_lock(&kfd_processes_mutex); 888 --kfd_locked; 889 mutex_unlock(&kfd_processes_mutex); 890 891 for (i = 0; i < kfd->num_nodes; i++) { 892 node = kfd->nodes[i]; 893 atomic_set(&node->sram_ecc_flag, 0); 894 kfd_smi_event_update_gpu_reset(node, true); 895 } 896 897 return 0; 898 } 899 900 bool kfd_is_locked(void) 901 { 902 lockdep_assert_held(&kfd_processes_mutex); 903 return (kfd_locked > 0); 904 } 905 906 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 907 { 908 struct kfd_node *node; 909 int i; 910 int count; 911 912 if (!kfd->init_complete) 913 return; 914 915 /* for runtime suspend, skip locking kfd */ 916 if (!run_pm) { 917 mutex_lock(&kfd_processes_mutex); 918 count = ++kfd_locked; 919 mutex_unlock(&kfd_processes_mutex); 920 921 /* For first KFD device suspend all the KFD processes */ 922 if (count == 1) 923 kfd_suspend_all_processes(); 924 } 925 926 for (i = 0; i < kfd->num_nodes; i++) { 927 node = kfd->nodes[i]; 928 node->dqm->ops.stop(node->dqm); 929 } 930 kfd_iommu_suspend(kfd); 931 } 932 933 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 934 { 935 int ret, count, i; 936 937 if (!kfd->init_complete) 938 return 0; 939 940 for (i = 0; i < kfd->num_nodes; i++) { 941 ret = kfd_resume(kfd->nodes[i]); 942 if (ret) 943 return ret; 944 } 945 946 /* for runtime resume, skip unlocking kfd */ 947 if (!run_pm) { 948 mutex_lock(&kfd_processes_mutex); 949 count = --kfd_locked; 950 mutex_unlock(&kfd_processes_mutex); 951 952 WARN_ONCE(count < 0, "KFD suspend / resume ref. error"); 953 if (count == 0) 954 ret = kfd_resume_all_processes(); 955 } 956 957 return ret; 958 } 959 960 int kgd2kfd_resume_iommu(struct kfd_dev *kfd) 961 { 962 if (!kfd->init_complete) 963 return 0; 964 965 return kfd_resume_iommu(kfd); 966 } 967 968 static int kfd_resume_iommu(struct kfd_dev *kfd) 969 { 970 int err = 0; 971 972 err = kfd_iommu_resume(kfd); 973 if (err) 974 dev_err(kfd_device, 975 "Failed to resume IOMMU for device %x:%x\n", 976 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 977 return err; 978 } 979 980 static int kfd_resume(struct kfd_node *node) 981 { 982 int err = 0; 983 984 err = node->dqm->ops.start(node->dqm); 985 if (err) 986 dev_err(kfd_device, 987 "Error starting queue manager for device %x:%x\n", 988 node->adev->pdev->vendor, node->adev->pdev->device); 989 990 return err; 991 } 992 993 static inline void kfd_queue_work(struct workqueue_struct *wq, 994 struct work_struct *work) 995 { 996 int cpu, new_cpu; 997 998 cpu = new_cpu = smp_processor_id(); 999 do { 1000 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids; 1001 if (cpu_to_node(new_cpu) == numa_node_id()) 1002 break; 1003 } while (cpu != new_cpu); 1004 1005 queue_work_on(new_cpu, wq, work); 1006 } 1007 1008 /* This is called directly from KGD at ISR. */ 1009 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 1010 { 1011 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE], i; 1012 bool is_patched = false; 1013 unsigned long flags; 1014 struct kfd_node *node; 1015 1016 if (!kfd->init_complete) 1017 return; 1018 1019 if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) { 1020 dev_err_once(kfd_device, "Ring entry too small\n"); 1021 return; 1022 } 1023 1024 for (i = 0; i < kfd->num_nodes; i++) { 1025 node = kfd->nodes[i]; 1026 spin_lock_irqsave(&node->interrupt_lock, flags); 1027 1028 if (node->interrupts_active 1029 && interrupt_is_wanted(node, ih_ring_entry, 1030 patched_ihre, &is_patched) 1031 && enqueue_ih_ring_entry(node, 1032 is_patched ? patched_ihre : ih_ring_entry)) { 1033 kfd_queue_work(node->ih_wq, &node->interrupt_work); 1034 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1035 return; 1036 } 1037 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1038 } 1039 1040 } 1041 1042 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger) 1043 { 1044 struct kfd_process *p; 1045 int r; 1046 1047 /* Because we are called from arbitrary context (workqueue) as opposed 1048 * to process context, kfd_process could attempt to exit while we are 1049 * running so the lookup function increments the process ref count. 1050 */ 1051 p = kfd_lookup_process_by_mm(mm); 1052 if (!p) 1053 return -ESRCH; 1054 1055 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 1056 r = kfd_process_evict_queues(p, trigger); 1057 1058 kfd_unref_process(p); 1059 return r; 1060 } 1061 1062 int kgd2kfd_resume_mm(struct mm_struct *mm) 1063 { 1064 struct kfd_process *p; 1065 int r; 1066 1067 /* Because we are called from arbitrary context (workqueue) as opposed 1068 * to process context, kfd_process could attempt to exit while we are 1069 * running so the lookup function increments the process ref count. 1070 */ 1071 p = kfd_lookup_process_by_mm(mm); 1072 if (!p) 1073 return -ESRCH; 1074 1075 r = kfd_process_restore_queues(p); 1076 1077 kfd_unref_process(p); 1078 return r; 1079 } 1080 1081 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 1082 * prepare for safe eviction of KFD BOs that belong to the specified 1083 * process. 1084 * 1085 * @mm: mm_struct that identifies the specified KFD process 1086 * @fence: eviction fence attached to KFD process BOs 1087 * 1088 */ 1089 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 1090 struct dma_fence *fence) 1091 { 1092 struct kfd_process *p; 1093 unsigned long active_time; 1094 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 1095 1096 if (!fence) 1097 return -EINVAL; 1098 1099 if (dma_fence_is_signaled(fence)) 1100 return 0; 1101 1102 p = kfd_lookup_process_by_mm(mm); 1103 if (!p) 1104 return -ENODEV; 1105 1106 if (fence->seqno == p->last_eviction_seqno) 1107 goto out; 1108 1109 p->last_eviction_seqno = fence->seqno; 1110 1111 /* Avoid KFD process starvation. Wait for at least 1112 * PROCESS_ACTIVE_TIME_MS before evicting the process again 1113 */ 1114 active_time = get_jiffies_64() - p->last_restore_timestamp; 1115 if (delay_jiffies > active_time) 1116 delay_jiffies -= active_time; 1117 else 1118 delay_jiffies = 0; 1119 1120 /* During process initialization eviction_work.dwork is initialized 1121 * to kfd_evict_bo_worker 1122 */ 1123 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 1124 p->lead_thread->pid, delay_jiffies); 1125 schedule_delayed_work(&p->eviction_work, delay_jiffies); 1126 out: 1127 kfd_unref_process(p); 1128 return 0; 1129 } 1130 1131 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 1132 unsigned int chunk_size) 1133 { 1134 if (WARN_ON(buf_size < chunk_size)) 1135 return -EINVAL; 1136 if (WARN_ON(buf_size == 0)) 1137 return -EINVAL; 1138 if (WARN_ON(chunk_size == 0)) 1139 return -EINVAL; 1140 1141 kfd->gtt_sa_chunk_size = chunk_size; 1142 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 1143 1144 kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks, 1145 GFP_KERNEL); 1146 if (!kfd->gtt_sa_bitmap) 1147 return -ENOMEM; 1148 1149 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 1150 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 1151 1152 mutex_init(&kfd->gtt_sa_lock); 1153 1154 return 0; 1155 } 1156 1157 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 1158 { 1159 mutex_destroy(&kfd->gtt_sa_lock); 1160 bitmap_free(kfd->gtt_sa_bitmap); 1161 } 1162 1163 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 1164 unsigned int bit_num, 1165 unsigned int chunk_size) 1166 { 1167 return start_addr + bit_num * chunk_size; 1168 } 1169 1170 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 1171 unsigned int bit_num, 1172 unsigned int chunk_size) 1173 { 1174 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 1175 } 1176 1177 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size, 1178 struct kfd_mem_obj **mem_obj) 1179 { 1180 unsigned int found, start_search, cur_size; 1181 struct kfd_dev *kfd = node->kfd; 1182 1183 if (size == 0) 1184 return -EINVAL; 1185 1186 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 1187 return -ENOMEM; 1188 1189 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 1190 if (!(*mem_obj)) 1191 return -ENOMEM; 1192 1193 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 1194 1195 start_search = 0; 1196 1197 mutex_lock(&kfd->gtt_sa_lock); 1198 1199 kfd_gtt_restart_search: 1200 /* Find the first chunk that is free */ 1201 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1202 kfd->gtt_sa_num_of_chunks, 1203 start_search); 1204 1205 pr_debug("Found = %d\n", found); 1206 1207 /* If there wasn't any free chunk, bail out */ 1208 if (found == kfd->gtt_sa_num_of_chunks) 1209 goto kfd_gtt_no_free_chunk; 1210 1211 /* Update fields of mem_obj */ 1212 (*mem_obj)->range_start = found; 1213 (*mem_obj)->range_end = found; 1214 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1215 kfd->gtt_start_gpu_addr, 1216 found, 1217 kfd->gtt_sa_chunk_size); 1218 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1219 kfd->gtt_start_cpu_ptr, 1220 found, 1221 kfd->gtt_sa_chunk_size); 1222 1223 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1224 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1225 1226 /* If we need only one chunk, mark it as allocated and get out */ 1227 if (size <= kfd->gtt_sa_chunk_size) { 1228 pr_debug("Single bit\n"); 1229 __set_bit(found, kfd->gtt_sa_bitmap); 1230 goto kfd_gtt_out; 1231 } 1232 1233 /* Otherwise, try to see if we have enough contiguous chunks */ 1234 cur_size = size - kfd->gtt_sa_chunk_size; 1235 do { 1236 (*mem_obj)->range_end = 1237 find_next_zero_bit(kfd->gtt_sa_bitmap, 1238 kfd->gtt_sa_num_of_chunks, ++found); 1239 /* 1240 * If next free chunk is not contiguous than we need to 1241 * restart our search from the last free chunk we found (which 1242 * wasn't contiguous to the previous ones 1243 */ 1244 if ((*mem_obj)->range_end != found) { 1245 start_search = found; 1246 goto kfd_gtt_restart_search; 1247 } 1248 1249 /* 1250 * If we reached end of buffer, bail out with error 1251 */ 1252 if (found == kfd->gtt_sa_num_of_chunks) 1253 goto kfd_gtt_no_free_chunk; 1254 1255 /* Check if we don't need another chunk */ 1256 if (cur_size <= kfd->gtt_sa_chunk_size) 1257 cur_size = 0; 1258 else 1259 cur_size -= kfd->gtt_sa_chunk_size; 1260 1261 } while (cur_size > 0); 1262 1263 pr_debug("range_start = %d, range_end = %d\n", 1264 (*mem_obj)->range_start, (*mem_obj)->range_end); 1265 1266 /* Mark the chunks as allocated */ 1267 bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start, 1268 (*mem_obj)->range_end - (*mem_obj)->range_start + 1); 1269 1270 kfd_gtt_out: 1271 mutex_unlock(&kfd->gtt_sa_lock); 1272 return 0; 1273 1274 kfd_gtt_no_free_chunk: 1275 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1276 mutex_unlock(&kfd->gtt_sa_lock); 1277 kfree(*mem_obj); 1278 return -ENOMEM; 1279 } 1280 1281 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj) 1282 { 1283 struct kfd_dev *kfd = node->kfd; 1284 1285 /* Act like kfree when trying to free a NULL object */ 1286 if (!mem_obj) 1287 return 0; 1288 1289 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1290 mem_obj, mem_obj->range_start, mem_obj->range_end); 1291 1292 mutex_lock(&kfd->gtt_sa_lock); 1293 1294 /* Mark the chunks as free */ 1295 bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start, 1296 mem_obj->range_end - mem_obj->range_start + 1); 1297 1298 mutex_unlock(&kfd->gtt_sa_lock); 1299 1300 kfree(mem_obj); 1301 return 0; 1302 } 1303 1304 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1305 { 1306 /* 1307 * TODO: Currently update SRAM ECC flag for first node. 1308 * This needs to be updated later when we can 1309 * identify SRAM ECC error on other nodes also. 1310 */ 1311 if (kfd) 1312 atomic_inc(&kfd->nodes[0]->sram_ecc_flag); 1313 } 1314 1315 void kfd_inc_compute_active(struct kfd_node *node) 1316 { 1317 if (atomic_inc_return(&node->kfd->compute_profile) == 1) 1318 amdgpu_amdkfd_set_compute_idle(node->adev, false); 1319 } 1320 1321 void kfd_dec_compute_active(struct kfd_node *node) 1322 { 1323 int count = atomic_dec_return(&node->kfd->compute_profile); 1324 1325 if (count == 0) 1326 amdgpu_amdkfd_set_compute_idle(node->adev, true); 1327 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1328 } 1329 1330 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 1331 { 1332 /* 1333 * TODO: For now, raise the throttling event only on first node. 1334 * This will need to change after we are able to determine 1335 * which node raised the throttling event. 1336 */ 1337 if (kfd && kfd->init_complete) 1338 kfd_smi_event_update_thermal_throttling(kfd->nodes[0], 1339 throttle_bitmask); 1340 } 1341 1342 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and 1343 * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA. 1344 * When the device has more than two engines, we reserve two for PCIe to enable 1345 * full-duplex and the rest are used as XGMI. 1346 */ 1347 unsigned int kfd_get_num_sdma_engines(struct kfd_node *node) 1348 { 1349 /* If XGMI is not supported, all SDMA engines are PCIe */ 1350 if (!node->adev->gmc.xgmi.supported) 1351 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes; 1352 1353 return min(node->adev->sdma.num_instances/(int)node->kfd->num_nodes, 2); 1354 } 1355 1356 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *node) 1357 { 1358 /* After reserved for PCIe, the rest of engines are XGMI */ 1359 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes - 1360 kfd_get_num_sdma_engines(node); 1361 } 1362 1363 int kgd2kfd_check_and_lock_kfd(void) 1364 { 1365 mutex_lock(&kfd_processes_mutex); 1366 if (!hash_empty(kfd_processes_table) || kfd_is_locked()) { 1367 mutex_unlock(&kfd_processes_mutex); 1368 return -EBUSY; 1369 } 1370 1371 ++kfd_locked; 1372 mutex_unlock(&kfd_processes_mutex); 1373 1374 return 0; 1375 } 1376 1377 void kgd2kfd_unlock_kfd(void) 1378 { 1379 mutex_lock(&kfd_processes_mutex); 1380 --kfd_locked; 1381 mutex_unlock(&kfd_processes_mutex); 1382 } 1383 1384 #if defined(CONFIG_DEBUG_FS) 1385 1386 /* This function will send a package to HIQ to hang the HWS 1387 * which will trigger a GPU reset and bring the HWS back to normal state 1388 */ 1389 int kfd_debugfs_hang_hws(struct kfd_node *dev) 1390 { 1391 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1392 pr_err("HWS is not enabled"); 1393 return -EINVAL; 1394 } 1395 1396 return dqm_debugfs_hang_hws(dev->dqm); 1397 } 1398 1399 #endif 1400