1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/bsearch.h> 25 #include <linux/pci.h> 26 #include <linux/slab.h> 27 #include "kfd_priv.h" 28 #include "kfd_device_queue_manager.h" 29 #include "kfd_pm4_headers_vi.h" 30 #include "kfd_pm4_headers_aldebaran.h" 31 #include "cwsr_trap_handler.h" 32 #include "kfd_iommu.h" 33 #include "amdgpu_amdkfd.h" 34 #include "kfd_smi_events.h" 35 #include "kfd_migrate.h" 36 #include "amdgpu.h" 37 38 #define MQD_SIZE_ALIGNED 768 39 40 /* 41 * kfd_locked is used to lock the kfd driver during suspend or reset 42 * once locked, kfd driver will stop any further GPU execution. 43 * create process (open) will return -EAGAIN. 44 */ 45 static atomic_t kfd_locked = ATOMIC_INIT(0); 46 47 #ifdef CONFIG_DRM_AMDGPU_CIK 48 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 49 #endif 50 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 51 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 52 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 53 extern const struct kfd2kgd_calls aldebaran_kfd2kgd; 54 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 55 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 56 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd; 57 58 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 59 unsigned int chunk_size); 60 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 61 62 static int kfd_resume_iommu(struct kfd_dev *kfd); 63 static int kfd_resume(struct kfd_dev *kfd); 64 65 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) 66 { 67 uint32_t sdma_version = kfd->adev->ip_versions[SDMA0_HWIP][0]; 68 69 switch (sdma_version) { 70 case IP_VERSION(4, 0, 0):/* VEGA10 */ 71 case IP_VERSION(4, 0, 1):/* VEGA12 */ 72 case IP_VERSION(4, 1, 0):/* RAVEN */ 73 case IP_VERSION(4, 1, 1):/* RAVEN */ 74 case IP_VERSION(4, 1, 2):/* RENOIR */ 75 case IP_VERSION(5, 2, 1):/* VANGOGH */ 76 case IP_VERSION(5, 2, 3):/* YELLOW_CARP */ 77 case IP_VERSION(5, 2, 6):/* GC 10.3.6 */ 78 case IP_VERSION(5, 2, 7):/* GC 10.3.7 */ 79 kfd->device_info.num_sdma_queues_per_engine = 2; 80 break; 81 case IP_VERSION(4, 2, 0):/* VEGA20 */ 82 case IP_VERSION(4, 2, 2):/* ARCTURUS */ 83 case IP_VERSION(4, 4, 0):/* ALDEBARAN */ 84 case IP_VERSION(5, 0, 0):/* NAVI10 */ 85 case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */ 86 case IP_VERSION(5, 0, 2):/* NAVI14 */ 87 case IP_VERSION(5, 0, 5):/* NAVI12 */ 88 case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */ 89 case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */ 90 case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */ 91 case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */ 92 case IP_VERSION(6, 0, 0): 93 case IP_VERSION(6, 0, 1): 94 case IP_VERSION(6, 0, 2): 95 case IP_VERSION(6, 0, 3): 96 kfd->device_info.num_sdma_queues_per_engine = 8; 97 break; 98 default: 99 dev_warn(kfd_device, 100 "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n", 101 sdma_version); 102 kfd->device_info.num_sdma_queues_per_engine = 8; 103 } 104 105 switch (sdma_version) { 106 case IP_VERSION(6, 0, 0): 107 case IP_VERSION(6, 0, 2): 108 case IP_VERSION(6, 0, 3): 109 /* Reserve 1 for paging and 1 for gfx */ 110 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 111 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */ 112 kfd->device_info.reserved_sdma_queues_bitmap = 0xFULL; 113 break; 114 case IP_VERSION(6, 0, 1): 115 /* Reserve 1 for paging and 1 for gfx */ 116 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 117 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-0 queue-1; ... */ 118 kfd->device_info.reserved_sdma_queues_bitmap = 0x3ULL; 119 break; 120 default: 121 break; 122 } 123 } 124 125 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) 126 { 127 uint32_t gc_version = KFD_GC_VERSION(kfd); 128 129 switch (gc_version) { 130 case IP_VERSION(9, 0, 1): /* VEGA10 */ 131 case IP_VERSION(9, 1, 0): /* RAVEN */ 132 case IP_VERSION(9, 2, 1): /* VEGA12 */ 133 case IP_VERSION(9, 2, 2): /* RAVEN */ 134 case IP_VERSION(9, 3, 0): /* RENOIR */ 135 case IP_VERSION(9, 4, 0): /* VEGA20 */ 136 case IP_VERSION(9, 4, 1): /* ARCTURUS */ 137 case IP_VERSION(9, 4, 2): /* ALDEBARAN */ 138 case IP_VERSION(10, 3, 1): /* VANGOGH */ 139 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */ 140 case IP_VERSION(10, 3, 6): /* GC 10.3.6 */ 141 case IP_VERSION(10, 3, 7): /* GC 10.3.7 */ 142 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */ 143 case IP_VERSION(10, 1, 4): 144 case IP_VERSION(10, 1, 10): /* NAVI10 */ 145 case IP_VERSION(10, 1, 2): /* NAVI12 */ 146 case IP_VERSION(10, 1, 1): /* NAVI14 */ 147 case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */ 148 case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */ 149 case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */ 150 case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */ 151 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 152 break; 153 case IP_VERSION(11, 0, 0): 154 case IP_VERSION(11, 0, 1): 155 case IP_VERSION(11, 0, 2): 156 case IP_VERSION(11, 0, 3): 157 case IP_VERSION(11, 0, 4): 158 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 159 break; 160 default: 161 dev_warn(kfd_device, "v9 event interrupt handler is set due to " 162 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version); 163 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 164 } 165 } 166 167 static void kfd_device_info_init(struct kfd_dev *kfd, 168 bool vf, uint32_t gfx_target_version) 169 { 170 uint32_t gc_version = KFD_GC_VERSION(kfd); 171 uint32_t asic_type = kfd->adev->asic_type; 172 173 kfd->device_info.max_pasid_bits = 16; 174 kfd->device_info.max_no_of_hqd = 24; 175 kfd->device_info.num_of_watch_points = 4; 176 kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED; 177 kfd->device_info.gfx_target_version = gfx_target_version; 178 179 if (KFD_IS_SOC15(kfd)) { 180 kfd->device_info.doorbell_size = 8; 181 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t); 182 kfd->device_info.supports_cwsr = true; 183 184 kfd_device_info_set_sdma_info(kfd); 185 186 kfd_device_info_set_event_interrupt_class(kfd); 187 188 /* Raven */ 189 if (gc_version == IP_VERSION(9, 1, 0) || 190 gc_version == IP_VERSION(9, 2, 2)) 191 kfd->device_info.needs_iommu_device = true; 192 193 if (gc_version < IP_VERSION(11, 0, 0)) { 194 /* Navi2x+, Navi1x+ */ 195 if (gc_version == IP_VERSION(10, 3, 6)) 196 kfd->device_info.no_atomic_fw_version = 14; 197 else if (gc_version == IP_VERSION(10, 3, 7)) 198 kfd->device_info.no_atomic_fw_version = 3; 199 else if (gc_version >= IP_VERSION(10, 3, 0)) 200 kfd->device_info.no_atomic_fw_version = 92; 201 else if (gc_version >= IP_VERSION(10, 1, 1)) 202 kfd->device_info.no_atomic_fw_version = 145; 203 204 /* Navi1x+ */ 205 if (gc_version >= IP_VERSION(10, 1, 1)) 206 kfd->device_info.needs_pci_atomics = true; 207 } 208 } else { 209 kfd->device_info.doorbell_size = 4; 210 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t); 211 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik; 212 kfd->device_info.num_sdma_queues_per_engine = 2; 213 214 if (asic_type != CHIP_KAVERI && 215 asic_type != CHIP_HAWAII && 216 asic_type != CHIP_TONGA) 217 kfd->device_info.supports_cwsr = true; 218 219 if (asic_type == CHIP_KAVERI || 220 asic_type == CHIP_CARRIZO) 221 kfd->device_info.needs_iommu_device = true; 222 223 if (asic_type != CHIP_HAWAII && !vf) 224 kfd->device_info.needs_pci_atomics = true; 225 } 226 } 227 228 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 229 { 230 struct kfd_dev *kfd = NULL; 231 const struct kfd2kgd_calls *f2g = NULL; 232 uint32_t gfx_target_version = 0; 233 234 switch (adev->asic_type) { 235 #ifdef KFD_SUPPORT_IOMMU_V2 236 #ifdef CONFIG_DRM_AMDGPU_CIK 237 case CHIP_KAVERI: 238 gfx_target_version = 70000; 239 if (!vf) 240 f2g = &gfx_v7_kfd2kgd; 241 break; 242 #endif 243 case CHIP_CARRIZO: 244 gfx_target_version = 80001; 245 if (!vf) 246 f2g = &gfx_v8_kfd2kgd; 247 break; 248 #endif 249 #ifdef CONFIG_DRM_AMDGPU_CIK 250 case CHIP_HAWAII: 251 gfx_target_version = 70001; 252 if (!amdgpu_exp_hw_support) 253 pr_info( 254 "KFD support on Hawaii is experimental. See modparam exp_hw_support\n" 255 ); 256 else if (!vf) 257 f2g = &gfx_v7_kfd2kgd; 258 break; 259 #endif 260 case CHIP_TONGA: 261 gfx_target_version = 80002; 262 if (!vf) 263 f2g = &gfx_v8_kfd2kgd; 264 break; 265 case CHIP_FIJI: 266 case CHIP_POLARIS10: 267 gfx_target_version = 80003; 268 f2g = &gfx_v8_kfd2kgd; 269 break; 270 case CHIP_POLARIS11: 271 case CHIP_POLARIS12: 272 case CHIP_VEGAM: 273 gfx_target_version = 80003; 274 if (!vf) 275 f2g = &gfx_v8_kfd2kgd; 276 break; 277 default: 278 switch (adev->ip_versions[GC_HWIP][0]) { 279 /* Vega 10 */ 280 case IP_VERSION(9, 0, 1): 281 gfx_target_version = 90000; 282 f2g = &gfx_v9_kfd2kgd; 283 break; 284 #ifdef KFD_SUPPORT_IOMMU_V2 285 /* Raven */ 286 case IP_VERSION(9, 1, 0): 287 case IP_VERSION(9, 2, 2): 288 gfx_target_version = 90002; 289 if (!vf) 290 f2g = &gfx_v9_kfd2kgd; 291 break; 292 #endif 293 /* Vega12 */ 294 case IP_VERSION(9, 2, 1): 295 gfx_target_version = 90004; 296 if (!vf) 297 f2g = &gfx_v9_kfd2kgd; 298 break; 299 /* Renoir */ 300 case IP_VERSION(9, 3, 0): 301 gfx_target_version = 90012; 302 if (!vf) 303 f2g = &gfx_v9_kfd2kgd; 304 break; 305 /* Vega20 */ 306 case IP_VERSION(9, 4, 0): 307 gfx_target_version = 90006; 308 if (!vf) 309 f2g = &gfx_v9_kfd2kgd; 310 break; 311 /* Arcturus */ 312 case IP_VERSION(9, 4, 1): 313 gfx_target_version = 90008; 314 f2g = &arcturus_kfd2kgd; 315 break; 316 /* Aldebaran */ 317 case IP_VERSION(9, 4, 2): 318 case IP_VERSION(9, 4, 3): 319 gfx_target_version = 90010; 320 f2g = &aldebaran_kfd2kgd; 321 break; 322 /* Navi10 */ 323 case IP_VERSION(10, 1, 10): 324 gfx_target_version = 100100; 325 if (!vf) 326 f2g = &gfx_v10_kfd2kgd; 327 break; 328 /* Navi12 */ 329 case IP_VERSION(10, 1, 2): 330 gfx_target_version = 100101; 331 f2g = &gfx_v10_kfd2kgd; 332 break; 333 /* Navi14 */ 334 case IP_VERSION(10, 1, 1): 335 gfx_target_version = 100102; 336 if (!vf) 337 f2g = &gfx_v10_kfd2kgd; 338 break; 339 /* Cyan Skillfish */ 340 case IP_VERSION(10, 1, 3): 341 case IP_VERSION(10, 1, 4): 342 gfx_target_version = 100103; 343 if (!vf) 344 f2g = &gfx_v10_kfd2kgd; 345 break; 346 /* Sienna Cichlid */ 347 case IP_VERSION(10, 3, 0): 348 gfx_target_version = 100300; 349 f2g = &gfx_v10_3_kfd2kgd; 350 break; 351 /* Navy Flounder */ 352 case IP_VERSION(10, 3, 2): 353 gfx_target_version = 100301; 354 f2g = &gfx_v10_3_kfd2kgd; 355 break; 356 /* Van Gogh */ 357 case IP_VERSION(10, 3, 1): 358 gfx_target_version = 100303; 359 if (!vf) 360 f2g = &gfx_v10_3_kfd2kgd; 361 break; 362 /* Dimgrey Cavefish */ 363 case IP_VERSION(10, 3, 4): 364 gfx_target_version = 100302; 365 f2g = &gfx_v10_3_kfd2kgd; 366 break; 367 /* Beige Goby */ 368 case IP_VERSION(10, 3, 5): 369 gfx_target_version = 100304; 370 f2g = &gfx_v10_3_kfd2kgd; 371 break; 372 /* Yellow Carp */ 373 case IP_VERSION(10, 3, 3): 374 gfx_target_version = 100305; 375 if (!vf) 376 f2g = &gfx_v10_3_kfd2kgd; 377 break; 378 case IP_VERSION(10, 3, 6): 379 case IP_VERSION(10, 3, 7): 380 gfx_target_version = 100306; 381 if (!vf) 382 f2g = &gfx_v10_3_kfd2kgd; 383 break; 384 case IP_VERSION(11, 0, 0): 385 gfx_target_version = 110000; 386 f2g = &gfx_v11_kfd2kgd; 387 break; 388 case IP_VERSION(11, 0, 1): 389 case IP_VERSION(11, 0, 4): 390 gfx_target_version = 110003; 391 f2g = &gfx_v11_kfd2kgd; 392 break; 393 case IP_VERSION(11, 0, 2): 394 gfx_target_version = 110002; 395 f2g = &gfx_v11_kfd2kgd; 396 break; 397 case IP_VERSION(11, 0, 3): 398 /* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */ 399 gfx_target_version = 110001; 400 f2g = &gfx_v11_kfd2kgd; 401 break; 402 default: 403 break; 404 } 405 break; 406 } 407 408 if (!f2g) { 409 if (adev->ip_versions[GC_HWIP][0]) 410 dev_err(kfd_device, "GC IP %06x %s not supported in kfd\n", 411 adev->ip_versions[GC_HWIP][0], vf ? "VF" : ""); 412 else 413 dev_err(kfd_device, "%s %s not supported in kfd\n", 414 amdgpu_asic_name[adev->asic_type], vf ? "VF" : ""); 415 return NULL; 416 } 417 418 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 419 if (!kfd) 420 return NULL; 421 422 kfd->adev = adev; 423 kfd_device_info_init(kfd, vf, gfx_target_version); 424 kfd->init_complete = false; 425 kfd->kfd2kgd = f2g; 426 atomic_set(&kfd->compute_profile, 0); 427 428 mutex_init(&kfd->doorbell_mutex); 429 memset(&kfd->doorbell_available_index, 0, 430 sizeof(kfd->doorbell_available_index)); 431 432 atomic_set(&kfd->sram_ecc_flag, 0); 433 434 ida_init(&kfd->doorbell_ida); 435 436 return kfd; 437 } 438 439 static void kfd_cwsr_init(struct kfd_dev *kfd) 440 { 441 if (cwsr_enable && kfd->device_info.supports_cwsr) { 442 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) { 443 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE); 444 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 445 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 446 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) { 447 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE); 448 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 449 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 450 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) { 451 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) > PAGE_SIZE); 452 kfd->cwsr_isa = cwsr_trap_aldebaran_hex; 453 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); 454 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3)) { 455 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_4_3_hex) > PAGE_SIZE); 456 kfd->cwsr_isa = cwsr_trap_gfx9_4_3_hex; 457 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_4_3_hex); 458 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) { 459 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE); 460 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 461 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 462 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) { 463 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE); 464 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 465 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 466 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) { 467 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE); 468 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 469 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 470 } else { 471 BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE); 472 kfd->cwsr_isa = cwsr_trap_gfx11_hex; 473 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex); 474 } 475 476 kfd->cwsr_enabled = true; 477 } 478 } 479 480 static int kfd_gws_init(struct kfd_dev *kfd) 481 { 482 int ret = 0; 483 484 if (kfd->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 485 return 0; 486 487 if (hws_gws_support || (KFD_IS_SOC15(kfd) && 488 ((KFD_GC_VERSION(kfd) == IP_VERSION(9, 0, 1) 489 && kfd->mec2_fw_version >= 0x81b3) || 490 (KFD_GC_VERSION(kfd) <= IP_VERSION(9, 4, 0) 491 && kfd->mec2_fw_version >= 0x1b3) || 492 (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1) 493 && kfd->mec2_fw_version >= 0x30) || 494 (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) 495 && kfd->mec2_fw_version >= 0x28) || 496 (KFD_GC_VERSION(kfd) >= IP_VERSION(10, 3, 0) 497 && KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0) 498 && kfd->mec2_fw_version >= 0x6b)))) 499 ret = amdgpu_amdkfd_alloc_gws(kfd->adev, 500 kfd->adev->gds.gws_size, &kfd->gws); 501 502 return ret; 503 } 504 505 static void kfd_smi_init(struct kfd_dev *dev) 506 { 507 INIT_LIST_HEAD(&dev->smi_clients); 508 spin_lock_init(&dev->smi_lock); 509 } 510 511 bool kgd2kfd_device_init(struct kfd_dev *kfd, 512 const struct kgd2kfd_shared_resources *gpu_resources) 513 { 514 unsigned int size, map_process_packet_size; 515 516 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 517 KGD_ENGINE_MEC1); 518 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 519 KGD_ENGINE_MEC2); 520 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 521 KGD_ENGINE_SDMA1); 522 kfd->shared_resources = *gpu_resources; 523 524 kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 525 kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 526 kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd 527 - kfd->vm_info.first_vmid_kfd + 1; 528 529 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 530 * 32 and 64-bit requests are possible and must be 531 * supported. 532 */ 533 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev); 534 if (!kfd->pci_atomic_requested && 535 kfd->device_info.needs_pci_atomics && 536 (!kfd->device_info.no_atomic_fw_version || 537 kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) { 538 dev_info(kfd_device, 539 "skipped device %x:%x, PCI rejects atomics %d<%d\n", 540 kfd->adev->pdev->vendor, kfd->adev->pdev->device, 541 kfd->mec_fw_version, 542 kfd->device_info.no_atomic_fw_version); 543 return false; 544 } 545 546 /* Verify module parameters regarding mapped process number*/ 547 if (hws_max_conc_proc >= 0) 548 kfd->max_proc_per_quantum = min((u32)hws_max_conc_proc, kfd->vm_info.vmid_num_kfd); 549 else 550 kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd; 551 552 /* calculate max size of mqds needed for queues */ 553 size = max_num_of_queues_per_device * 554 kfd->device_info.mqd_size_aligned; 555 556 /* 557 * calculate max size of runlist packet. 558 * There can be only 2 packets at once 559 */ 560 map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ? 561 sizeof(struct pm4_mes_map_process_aldebaran) : 562 sizeof(struct pm4_mes_map_process); 563 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + 564 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 565 + sizeof(struct pm4_mes_runlist)) * 2; 566 567 /* Add size of HIQ & DIQ */ 568 size += KFD_KERNEL_QUEUE_SIZE * 2; 569 570 /* add another 512KB for all other allocations on gart (HPD, fences) */ 571 size += 512 * 1024; 572 573 if (amdgpu_amdkfd_alloc_gtt_mem( 574 kfd->adev, size, &kfd->gtt_mem, 575 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 576 false)) { 577 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 578 goto alloc_gtt_mem_failure; 579 } 580 581 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 582 583 /* Initialize GTT sa with 512 byte chunk size */ 584 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 585 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 586 goto kfd_gtt_sa_init_error; 587 } 588 589 if (kfd_doorbell_init(kfd)) { 590 dev_err(kfd_device, 591 "Error initializing doorbell aperture\n"); 592 goto kfd_doorbell_error; 593 } 594 595 if (amdgpu_use_xgmi_p2p) 596 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id; 597 598 kfd->noretry = kfd->adev->gmc.noretry; 599 600 if (kfd_interrupt_init(kfd)) { 601 dev_err(kfd_device, "Error initializing interrupts\n"); 602 goto kfd_interrupt_error; 603 } 604 605 kfd->dqm = device_queue_manager_init(kfd); 606 if (!kfd->dqm) { 607 dev_err(kfd_device, "Error initializing queue manager\n"); 608 goto device_queue_manager_error; 609 } 610 611 /* If supported on this device, allocate global GWS that is shared 612 * by all KFD processes 613 */ 614 if (kfd_gws_init(kfd)) { 615 dev_err(kfd_device, "Could not allocate %d gws\n", 616 kfd->adev->gds.gws_size); 617 goto gws_error; 618 } 619 620 /* If CRAT is broken, won't set iommu enabled */ 621 kfd_double_confirm_iommu_support(kfd); 622 623 if (kfd_iommu_device_init(kfd)) { 624 kfd->use_iommu_v2 = false; 625 dev_err(kfd_device, "Error initializing iommuv2\n"); 626 goto device_iommu_error; 627 } 628 629 kfd_cwsr_init(kfd); 630 631 svm_migrate_init(kfd->adev); 632 633 if (kfd_resume_iommu(kfd)) 634 goto device_iommu_error; 635 636 if (kfd_resume(kfd)) 637 goto kfd_resume_error; 638 639 amdgpu_amdkfd_get_local_mem_info(kfd->adev, &kfd->local_mem_info); 640 641 if (kfd_topology_add_device(kfd)) { 642 dev_err(kfd_device, "Error adding device to topology\n"); 643 goto kfd_topology_add_device_error; 644 } 645 646 kfd_smi_init(kfd); 647 648 kfd->init_complete = true; 649 dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, 650 kfd->adev->pdev->device); 651 652 pr_debug("Starting kfd with the following scheduling policy %d\n", 653 kfd->dqm->sched_policy); 654 655 goto out; 656 657 kfd_topology_add_device_error: 658 kfd_resume_error: 659 device_iommu_error: 660 gws_error: 661 device_queue_manager_uninit(kfd->dqm); 662 device_queue_manager_error: 663 kfd_interrupt_exit(kfd); 664 kfd_interrupt_error: 665 kfd_doorbell_fini(kfd); 666 kfd_doorbell_error: 667 kfd_gtt_sa_fini(kfd); 668 kfd_gtt_sa_init_error: 669 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 670 alloc_gtt_mem_failure: 671 if (kfd->gws) 672 amdgpu_amdkfd_free_gws(kfd->adev, kfd->gws); 673 dev_err(kfd_device, 674 "device %x:%x NOT added due to errors\n", 675 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 676 out: 677 return kfd->init_complete; 678 } 679 680 void kgd2kfd_device_exit(struct kfd_dev *kfd) 681 { 682 if (kfd->init_complete) { 683 device_queue_manager_uninit(kfd->dqm); 684 kfd_interrupt_exit(kfd); 685 kfd_topology_remove_device(kfd); 686 kfd_doorbell_fini(kfd); 687 ida_destroy(&kfd->doorbell_ida); 688 kfd_gtt_sa_fini(kfd); 689 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 690 if (kfd->gws) 691 amdgpu_amdkfd_free_gws(kfd->adev, kfd->gws); 692 } 693 694 kfree(kfd); 695 } 696 697 int kgd2kfd_pre_reset(struct kfd_dev *kfd) 698 { 699 if (!kfd->init_complete) 700 return 0; 701 702 kfd_smi_event_update_gpu_reset(kfd, false); 703 704 kfd->dqm->ops.pre_reset(kfd->dqm); 705 706 kgd2kfd_suspend(kfd, false); 707 708 kfd_signal_reset_event(kfd); 709 return 0; 710 } 711 712 /* 713 * Fix me. KFD won't be able to resume existing process for now. 714 * We will keep all existing process in a evicted state and 715 * wait the process to be terminated. 716 */ 717 718 int kgd2kfd_post_reset(struct kfd_dev *kfd) 719 { 720 int ret; 721 722 if (!kfd->init_complete) 723 return 0; 724 725 ret = kfd_resume(kfd); 726 if (ret) 727 return ret; 728 atomic_dec(&kfd_locked); 729 730 atomic_set(&kfd->sram_ecc_flag, 0); 731 732 kfd_smi_event_update_gpu_reset(kfd, true); 733 734 return 0; 735 } 736 737 bool kfd_is_locked(void) 738 { 739 return (atomic_read(&kfd_locked) > 0); 740 } 741 742 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 743 { 744 if (!kfd->init_complete) 745 return; 746 747 /* for runtime suspend, skip locking kfd */ 748 if (!run_pm) { 749 /* For first KFD device suspend all the KFD processes */ 750 if (atomic_inc_return(&kfd_locked) == 1) 751 kfd_suspend_all_processes(); 752 } 753 754 kfd->dqm->ops.stop(kfd->dqm); 755 kfd_iommu_suspend(kfd); 756 } 757 758 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 759 { 760 int ret, count; 761 762 if (!kfd->init_complete) 763 return 0; 764 765 ret = kfd_resume(kfd); 766 if (ret) 767 return ret; 768 769 /* for runtime resume, skip unlocking kfd */ 770 if (!run_pm) { 771 count = atomic_dec_return(&kfd_locked); 772 WARN_ONCE(count < 0, "KFD suspend / resume ref. error"); 773 if (count == 0) 774 ret = kfd_resume_all_processes(); 775 } 776 777 return ret; 778 } 779 780 int kgd2kfd_resume_iommu(struct kfd_dev *kfd) 781 { 782 if (!kfd->init_complete) 783 return 0; 784 785 return kfd_resume_iommu(kfd); 786 } 787 788 static int kfd_resume_iommu(struct kfd_dev *kfd) 789 { 790 int err = 0; 791 792 err = kfd_iommu_resume(kfd); 793 if (err) 794 dev_err(kfd_device, 795 "Failed to resume IOMMU for device %x:%x\n", 796 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 797 return err; 798 } 799 800 static int kfd_resume(struct kfd_dev *kfd) 801 { 802 int err = 0; 803 804 err = kfd->dqm->ops.start(kfd->dqm); 805 if (err) 806 dev_err(kfd_device, 807 "Error starting queue manager for device %x:%x\n", 808 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 809 810 return err; 811 } 812 813 static inline void kfd_queue_work(struct workqueue_struct *wq, 814 struct work_struct *work) 815 { 816 int cpu, new_cpu; 817 818 cpu = new_cpu = smp_processor_id(); 819 do { 820 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids; 821 if (cpu_to_node(new_cpu) == numa_node_id()) 822 break; 823 } while (cpu != new_cpu); 824 825 queue_work_on(new_cpu, wq, work); 826 } 827 828 /* This is called directly from KGD at ISR. */ 829 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 830 { 831 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE]; 832 bool is_patched = false; 833 unsigned long flags; 834 835 if (!kfd->init_complete) 836 return; 837 838 if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) { 839 dev_err_once(kfd_device, "Ring entry too small\n"); 840 return; 841 } 842 843 spin_lock_irqsave(&kfd->interrupt_lock, flags); 844 845 if (kfd->interrupts_active 846 && interrupt_is_wanted(kfd, ih_ring_entry, 847 patched_ihre, &is_patched) 848 && enqueue_ih_ring_entry(kfd, 849 is_patched ? patched_ihre : ih_ring_entry)) 850 kfd_queue_work(kfd->ih_wq, &kfd->interrupt_work); 851 852 spin_unlock_irqrestore(&kfd->interrupt_lock, flags); 853 } 854 855 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger) 856 { 857 struct kfd_process *p; 858 int r; 859 860 /* Because we are called from arbitrary context (workqueue) as opposed 861 * to process context, kfd_process could attempt to exit while we are 862 * running so the lookup function increments the process ref count. 863 */ 864 p = kfd_lookup_process_by_mm(mm); 865 if (!p) 866 return -ESRCH; 867 868 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 869 r = kfd_process_evict_queues(p, trigger); 870 871 kfd_unref_process(p); 872 return r; 873 } 874 875 int kgd2kfd_resume_mm(struct mm_struct *mm) 876 { 877 struct kfd_process *p; 878 int r; 879 880 /* Because we are called from arbitrary context (workqueue) as opposed 881 * to process context, kfd_process could attempt to exit while we are 882 * running so the lookup function increments the process ref count. 883 */ 884 p = kfd_lookup_process_by_mm(mm); 885 if (!p) 886 return -ESRCH; 887 888 r = kfd_process_restore_queues(p); 889 890 kfd_unref_process(p); 891 return r; 892 } 893 894 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 895 * prepare for safe eviction of KFD BOs that belong to the specified 896 * process. 897 * 898 * @mm: mm_struct that identifies the specified KFD process 899 * @fence: eviction fence attached to KFD process BOs 900 * 901 */ 902 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 903 struct dma_fence *fence) 904 { 905 struct kfd_process *p; 906 unsigned long active_time; 907 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 908 909 if (!fence) 910 return -EINVAL; 911 912 if (dma_fence_is_signaled(fence)) 913 return 0; 914 915 p = kfd_lookup_process_by_mm(mm); 916 if (!p) 917 return -ENODEV; 918 919 if (fence->seqno == p->last_eviction_seqno) 920 goto out; 921 922 p->last_eviction_seqno = fence->seqno; 923 924 /* Avoid KFD process starvation. Wait for at least 925 * PROCESS_ACTIVE_TIME_MS before evicting the process again 926 */ 927 active_time = get_jiffies_64() - p->last_restore_timestamp; 928 if (delay_jiffies > active_time) 929 delay_jiffies -= active_time; 930 else 931 delay_jiffies = 0; 932 933 /* During process initialization eviction_work.dwork is initialized 934 * to kfd_evict_bo_worker 935 */ 936 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 937 p->lead_thread->pid, delay_jiffies); 938 schedule_delayed_work(&p->eviction_work, delay_jiffies); 939 out: 940 kfd_unref_process(p); 941 return 0; 942 } 943 944 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 945 unsigned int chunk_size) 946 { 947 if (WARN_ON(buf_size < chunk_size)) 948 return -EINVAL; 949 if (WARN_ON(buf_size == 0)) 950 return -EINVAL; 951 if (WARN_ON(chunk_size == 0)) 952 return -EINVAL; 953 954 kfd->gtt_sa_chunk_size = chunk_size; 955 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 956 957 kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks, 958 GFP_KERNEL); 959 if (!kfd->gtt_sa_bitmap) 960 return -ENOMEM; 961 962 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 963 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 964 965 mutex_init(&kfd->gtt_sa_lock); 966 967 return 0; 968 } 969 970 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 971 { 972 mutex_destroy(&kfd->gtt_sa_lock); 973 bitmap_free(kfd->gtt_sa_bitmap); 974 } 975 976 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 977 unsigned int bit_num, 978 unsigned int chunk_size) 979 { 980 return start_addr + bit_num * chunk_size; 981 } 982 983 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 984 unsigned int bit_num, 985 unsigned int chunk_size) 986 { 987 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 988 } 989 990 int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size, 991 struct kfd_mem_obj **mem_obj) 992 { 993 unsigned int found, start_search, cur_size; 994 995 if (size == 0) 996 return -EINVAL; 997 998 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 999 return -ENOMEM; 1000 1001 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 1002 if (!(*mem_obj)) 1003 return -ENOMEM; 1004 1005 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 1006 1007 start_search = 0; 1008 1009 mutex_lock(&kfd->gtt_sa_lock); 1010 1011 kfd_gtt_restart_search: 1012 /* Find the first chunk that is free */ 1013 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1014 kfd->gtt_sa_num_of_chunks, 1015 start_search); 1016 1017 pr_debug("Found = %d\n", found); 1018 1019 /* If there wasn't any free chunk, bail out */ 1020 if (found == kfd->gtt_sa_num_of_chunks) 1021 goto kfd_gtt_no_free_chunk; 1022 1023 /* Update fields of mem_obj */ 1024 (*mem_obj)->range_start = found; 1025 (*mem_obj)->range_end = found; 1026 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1027 kfd->gtt_start_gpu_addr, 1028 found, 1029 kfd->gtt_sa_chunk_size); 1030 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1031 kfd->gtt_start_cpu_ptr, 1032 found, 1033 kfd->gtt_sa_chunk_size); 1034 1035 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1036 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1037 1038 /* If we need only one chunk, mark it as allocated and get out */ 1039 if (size <= kfd->gtt_sa_chunk_size) { 1040 pr_debug("Single bit\n"); 1041 __set_bit(found, kfd->gtt_sa_bitmap); 1042 goto kfd_gtt_out; 1043 } 1044 1045 /* Otherwise, try to see if we have enough contiguous chunks */ 1046 cur_size = size - kfd->gtt_sa_chunk_size; 1047 do { 1048 (*mem_obj)->range_end = 1049 find_next_zero_bit(kfd->gtt_sa_bitmap, 1050 kfd->gtt_sa_num_of_chunks, ++found); 1051 /* 1052 * If next free chunk is not contiguous than we need to 1053 * restart our search from the last free chunk we found (which 1054 * wasn't contiguous to the previous ones 1055 */ 1056 if ((*mem_obj)->range_end != found) { 1057 start_search = found; 1058 goto kfd_gtt_restart_search; 1059 } 1060 1061 /* 1062 * If we reached end of buffer, bail out with error 1063 */ 1064 if (found == kfd->gtt_sa_num_of_chunks) 1065 goto kfd_gtt_no_free_chunk; 1066 1067 /* Check if we don't need another chunk */ 1068 if (cur_size <= kfd->gtt_sa_chunk_size) 1069 cur_size = 0; 1070 else 1071 cur_size -= kfd->gtt_sa_chunk_size; 1072 1073 } while (cur_size > 0); 1074 1075 pr_debug("range_start = %d, range_end = %d\n", 1076 (*mem_obj)->range_start, (*mem_obj)->range_end); 1077 1078 /* Mark the chunks as allocated */ 1079 bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start, 1080 (*mem_obj)->range_end - (*mem_obj)->range_start + 1); 1081 1082 kfd_gtt_out: 1083 mutex_unlock(&kfd->gtt_sa_lock); 1084 return 0; 1085 1086 kfd_gtt_no_free_chunk: 1087 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1088 mutex_unlock(&kfd->gtt_sa_lock); 1089 kfree(*mem_obj); 1090 return -ENOMEM; 1091 } 1092 1093 int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj) 1094 { 1095 /* Act like kfree when trying to free a NULL object */ 1096 if (!mem_obj) 1097 return 0; 1098 1099 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1100 mem_obj, mem_obj->range_start, mem_obj->range_end); 1101 1102 mutex_lock(&kfd->gtt_sa_lock); 1103 1104 /* Mark the chunks as free */ 1105 bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start, 1106 mem_obj->range_end - mem_obj->range_start + 1); 1107 1108 mutex_unlock(&kfd->gtt_sa_lock); 1109 1110 kfree(mem_obj); 1111 return 0; 1112 } 1113 1114 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1115 { 1116 if (kfd) 1117 atomic_inc(&kfd->sram_ecc_flag); 1118 } 1119 1120 void kfd_inc_compute_active(struct kfd_dev *kfd) 1121 { 1122 if (atomic_inc_return(&kfd->compute_profile) == 1) 1123 amdgpu_amdkfd_set_compute_idle(kfd->adev, false); 1124 } 1125 1126 void kfd_dec_compute_active(struct kfd_dev *kfd) 1127 { 1128 int count = atomic_dec_return(&kfd->compute_profile); 1129 1130 if (count == 0) 1131 amdgpu_amdkfd_set_compute_idle(kfd->adev, true); 1132 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1133 } 1134 1135 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 1136 { 1137 if (kfd && kfd->init_complete) 1138 kfd_smi_event_update_thermal_throttling(kfd, throttle_bitmask); 1139 } 1140 1141 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and 1142 * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA. 1143 * When the device has more than two engines, we reserve two for PCIe to enable 1144 * full-duplex and the rest are used as XGMI. 1145 */ 1146 unsigned int kfd_get_num_sdma_engines(struct kfd_dev *kdev) 1147 { 1148 /* If XGMI is not supported, all SDMA engines are PCIe */ 1149 if (!kdev->adev->gmc.xgmi.supported) 1150 return kdev->adev->sdma.num_instances; 1151 1152 return min(kdev->adev->sdma.num_instances, 2); 1153 } 1154 1155 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_dev *kdev) 1156 { 1157 /* After reserved for PCIe, the rest of engines are XGMI */ 1158 return kdev->adev->sdma.num_instances - kfd_get_num_sdma_engines(kdev); 1159 } 1160 1161 #if defined(CONFIG_DEBUG_FS) 1162 1163 /* This function will send a package to HIQ to hang the HWS 1164 * which will trigger a GPU reset and bring the HWS back to normal state 1165 */ 1166 int kfd_debugfs_hang_hws(struct kfd_dev *dev) 1167 { 1168 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1169 pr_err("HWS is not enabled"); 1170 return -EINVAL; 1171 } 1172 1173 return dqm_debugfs_hang_hws(dev->dqm); 1174 } 1175 1176 #endif 1177