1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/bsearch.h> 25 #include <linux/pci.h> 26 #include <linux/slab.h> 27 #include "kfd_priv.h" 28 #include "kfd_device_queue_manager.h" 29 #include "kfd_pm4_headers_vi.h" 30 #include "kfd_pm4_headers_aldebaran.h" 31 #include "cwsr_trap_handler.h" 32 #include "kfd_iommu.h" 33 #include "amdgpu_amdkfd.h" 34 #include "kfd_smi_events.h" 35 #include "kfd_migrate.h" 36 #include "amdgpu.h" 37 38 #define MQD_SIZE_ALIGNED 768 39 40 /* 41 * kfd_locked is used to lock the kfd driver during suspend or reset 42 * once locked, kfd driver will stop any further GPU execution. 43 * create process (open) will return -EAGAIN. 44 */ 45 static atomic_t kfd_locked = ATOMIC_INIT(0); 46 47 #ifdef CONFIG_DRM_AMDGPU_CIK 48 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 49 #endif 50 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 51 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 52 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 53 extern const struct kfd2kgd_calls aldebaran_kfd2kgd; 54 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 55 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 56 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd; 57 58 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 59 unsigned int chunk_size); 60 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 61 62 static int kfd_resume(struct kfd_dev *kfd); 63 64 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) 65 { 66 uint32_t sdma_version = kfd->adev->ip_versions[SDMA0_HWIP][0]; 67 68 switch (sdma_version) { 69 case IP_VERSION(4, 0, 0):/* VEGA10 */ 70 case IP_VERSION(4, 0, 1):/* VEGA12 */ 71 case IP_VERSION(4, 1, 0):/* RAVEN */ 72 case IP_VERSION(4, 1, 1):/* RAVEN */ 73 case IP_VERSION(4, 1, 2):/* RENOIR */ 74 case IP_VERSION(5, 2, 1):/* VANGOGH */ 75 case IP_VERSION(5, 2, 3):/* YELLOW_CARP */ 76 case IP_VERSION(5, 2, 6):/* GC 10.3.6 */ 77 case IP_VERSION(5, 2, 7):/* GC 10.3.7 */ 78 kfd->device_info.num_sdma_queues_per_engine = 2; 79 break; 80 case IP_VERSION(4, 2, 0):/* VEGA20 */ 81 case IP_VERSION(4, 2, 2):/* ARCTURUS */ 82 case IP_VERSION(4, 4, 0):/* ALDEBARAN */ 83 case IP_VERSION(5, 0, 0):/* NAVI10 */ 84 case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */ 85 case IP_VERSION(5, 0, 2):/* NAVI14 */ 86 case IP_VERSION(5, 0, 5):/* NAVI12 */ 87 case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */ 88 case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */ 89 case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */ 90 case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */ 91 case IP_VERSION(6, 0, 0): 92 case IP_VERSION(6, 0, 1): 93 case IP_VERSION(6, 0, 2): 94 kfd->device_info.num_sdma_queues_per_engine = 8; 95 break; 96 default: 97 dev_warn(kfd_device, 98 "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n", 99 sdma_version); 100 kfd->device_info.num_sdma_queues_per_engine = 8; 101 } 102 103 switch (sdma_version) { 104 case IP_VERSION(6, 0, 0): 105 case IP_VERSION(6, 0, 2): 106 /* Reserve 1 for paging and 1 for gfx */ 107 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 108 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */ 109 kfd->device_info.reserved_sdma_queues_bitmap = 0xFULL; 110 break; 111 case IP_VERSION(6, 0, 1): 112 /* Reserve 1 for paging and 1 for gfx */ 113 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 114 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-0 queue-1; ... */ 115 kfd->device_info.reserved_sdma_queues_bitmap = 0x3ULL; 116 break; 117 default: 118 break; 119 } 120 } 121 122 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) 123 { 124 uint32_t gc_version = KFD_GC_VERSION(kfd); 125 126 switch (gc_version) { 127 case IP_VERSION(9, 0, 1): /* VEGA10 */ 128 case IP_VERSION(9, 1, 0): /* RAVEN */ 129 case IP_VERSION(9, 2, 1): /* VEGA12 */ 130 case IP_VERSION(9, 2, 2): /* RAVEN */ 131 case IP_VERSION(9, 3, 0): /* RENOIR */ 132 case IP_VERSION(9, 4, 0): /* VEGA20 */ 133 case IP_VERSION(9, 4, 1): /* ARCTURUS */ 134 case IP_VERSION(9, 4, 2): /* ALDEBARAN */ 135 case IP_VERSION(10, 3, 1): /* VANGOGH */ 136 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */ 137 case IP_VERSION(10, 3, 6): /* GC 10.3.6 */ 138 case IP_VERSION(10, 3, 7): /* GC 10.3.7 */ 139 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */ 140 case IP_VERSION(10, 1, 4): 141 case IP_VERSION(10, 1, 10): /* NAVI10 */ 142 case IP_VERSION(10, 1, 2): /* NAVI12 */ 143 case IP_VERSION(10, 1, 1): /* NAVI14 */ 144 case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */ 145 case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */ 146 case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */ 147 case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */ 148 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 149 break; 150 case IP_VERSION(11, 0, 0): 151 case IP_VERSION(11, 0, 1): 152 case IP_VERSION(11, 0, 2): 153 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 154 break; 155 default: 156 dev_warn(kfd_device, "v9 event interrupt handler is set due to " 157 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version); 158 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 159 } 160 } 161 162 static void kfd_device_info_init(struct kfd_dev *kfd, 163 bool vf, uint32_t gfx_target_version) 164 { 165 uint32_t gc_version = KFD_GC_VERSION(kfd); 166 uint32_t asic_type = kfd->adev->asic_type; 167 168 kfd->device_info.max_pasid_bits = 16; 169 kfd->device_info.max_no_of_hqd = 24; 170 kfd->device_info.num_of_watch_points = 4; 171 kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED; 172 kfd->device_info.gfx_target_version = gfx_target_version; 173 174 if (KFD_IS_SOC15(kfd)) { 175 kfd->device_info.doorbell_size = 8; 176 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t); 177 kfd->device_info.supports_cwsr = true; 178 179 kfd_device_info_set_sdma_info(kfd); 180 181 kfd_device_info_set_event_interrupt_class(kfd); 182 183 /* Raven */ 184 if (gc_version == IP_VERSION(9, 1, 0) || 185 gc_version == IP_VERSION(9, 2, 2)) 186 kfd->device_info.needs_iommu_device = true; 187 188 if (gc_version < IP_VERSION(11, 0, 0)) { 189 /* Navi2x+, Navi1x+ */ 190 if (gc_version == IP_VERSION(10, 3, 6)) 191 kfd->device_info.no_atomic_fw_version = 14; 192 else if (gc_version == IP_VERSION(10, 3, 7)) 193 kfd->device_info.no_atomic_fw_version = 3; 194 else if (gc_version >= IP_VERSION(10, 3, 0)) 195 kfd->device_info.no_atomic_fw_version = 92; 196 else if (gc_version >= IP_VERSION(10, 1, 1)) 197 kfd->device_info.no_atomic_fw_version = 145; 198 199 /* Navi1x+ */ 200 if (gc_version >= IP_VERSION(10, 1, 1)) 201 kfd->device_info.needs_pci_atomics = true; 202 } 203 } else { 204 kfd->device_info.doorbell_size = 4; 205 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t); 206 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik; 207 kfd->device_info.num_sdma_queues_per_engine = 2; 208 209 if (asic_type != CHIP_KAVERI && 210 asic_type != CHIP_HAWAII && 211 asic_type != CHIP_TONGA) 212 kfd->device_info.supports_cwsr = true; 213 214 if (asic_type == CHIP_KAVERI || 215 asic_type == CHIP_CARRIZO) 216 kfd->device_info.needs_iommu_device = true; 217 218 if (asic_type != CHIP_HAWAII && !vf) 219 kfd->device_info.needs_pci_atomics = true; 220 } 221 } 222 223 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 224 { 225 struct kfd_dev *kfd = NULL; 226 const struct kfd2kgd_calls *f2g = NULL; 227 struct pci_dev *pdev = adev->pdev; 228 uint32_t gfx_target_version = 0; 229 230 switch (adev->asic_type) { 231 #ifdef KFD_SUPPORT_IOMMU_V2 232 #ifdef CONFIG_DRM_AMDGPU_CIK 233 case CHIP_KAVERI: 234 gfx_target_version = 70000; 235 if (!vf) 236 f2g = &gfx_v7_kfd2kgd; 237 break; 238 #endif 239 case CHIP_CARRIZO: 240 gfx_target_version = 80001; 241 if (!vf) 242 f2g = &gfx_v8_kfd2kgd; 243 break; 244 #endif 245 #ifdef CONFIG_DRM_AMDGPU_CIK 246 case CHIP_HAWAII: 247 gfx_target_version = 70001; 248 if (!amdgpu_exp_hw_support) 249 pr_info( 250 "KFD support on Hawaii is experimental. See modparam exp_hw_support\n" 251 ); 252 else if (!vf) 253 f2g = &gfx_v7_kfd2kgd; 254 break; 255 #endif 256 case CHIP_TONGA: 257 gfx_target_version = 80002; 258 if (!vf) 259 f2g = &gfx_v8_kfd2kgd; 260 break; 261 case CHIP_FIJI: 262 gfx_target_version = 80003; 263 f2g = &gfx_v8_kfd2kgd; 264 break; 265 case CHIP_POLARIS10: 266 gfx_target_version = 80003; 267 f2g = &gfx_v8_kfd2kgd; 268 break; 269 case CHIP_POLARIS11: 270 gfx_target_version = 80003; 271 if (!vf) 272 f2g = &gfx_v8_kfd2kgd; 273 break; 274 case CHIP_POLARIS12: 275 gfx_target_version = 80003; 276 if (!vf) 277 f2g = &gfx_v8_kfd2kgd; 278 break; 279 case CHIP_VEGAM: 280 gfx_target_version = 80003; 281 if (!vf) 282 f2g = &gfx_v8_kfd2kgd; 283 break; 284 default: 285 switch (adev->ip_versions[GC_HWIP][0]) { 286 /* Vega 10 */ 287 case IP_VERSION(9, 0, 1): 288 gfx_target_version = 90000; 289 f2g = &gfx_v9_kfd2kgd; 290 break; 291 #ifdef KFD_SUPPORT_IOMMU_V2 292 /* Raven */ 293 case IP_VERSION(9, 1, 0): 294 case IP_VERSION(9, 2, 2): 295 gfx_target_version = 90002; 296 if (!vf) 297 f2g = &gfx_v9_kfd2kgd; 298 break; 299 #endif 300 /* Vega12 */ 301 case IP_VERSION(9, 2, 1): 302 gfx_target_version = 90004; 303 if (!vf) 304 f2g = &gfx_v9_kfd2kgd; 305 break; 306 /* Renoir */ 307 case IP_VERSION(9, 3, 0): 308 gfx_target_version = 90012; 309 if (!vf) 310 f2g = &gfx_v9_kfd2kgd; 311 break; 312 /* Vega20 */ 313 case IP_VERSION(9, 4, 0): 314 gfx_target_version = 90006; 315 if (!vf) 316 f2g = &gfx_v9_kfd2kgd; 317 break; 318 /* Arcturus */ 319 case IP_VERSION(9, 4, 1): 320 gfx_target_version = 90008; 321 f2g = &arcturus_kfd2kgd; 322 break; 323 /* Aldebaran */ 324 case IP_VERSION(9, 4, 2): 325 gfx_target_version = 90010; 326 f2g = &aldebaran_kfd2kgd; 327 break; 328 /* Navi10 */ 329 case IP_VERSION(10, 1, 10): 330 gfx_target_version = 100100; 331 if (!vf) 332 f2g = &gfx_v10_kfd2kgd; 333 break; 334 /* Navi12 */ 335 case IP_VERSION(10, 1, 2): 336 gfx_target_version = 100101; 337 f2g = &gfx_v10_kfd2kgd; 338 break; 339 /* Navi14 */ 340 case IP_VERSION(10, 1, 1): 341 gfx_target_version = 100102; 342 if (!vf) 343 f2g = &gfx_v10_kfd2kgd; 344 break; 345 /* Cyan Skillfish */ 346 case IP_VERSION(10, 1, 3): 347 case IP_VERSION(10, 1, 4): 348 gfx_target_version = 100103; 349 if (!vf) 350 f2g = &gfx_v10_kfd2kgd; 351 break; 352 /* Sienna Cichlid */ 353 case IP_VERSION(10, 3, 0): 354 gfx_target_version = 100300; 355 f2g = &gfx_v10_3_kfd2kgd; 356 break; 357 /* Navy Flounder */ 358 case IP_VERSION(10, 3, 2): 359 gfx_target_version = 100301; 360 f2g = &gfx_v10_3_kfd2kgd; 361 break; 362 /* Van Gogh */ 363 case IP_VERSION(10, 3, 1): 364 gfx_target_version = 100303; 365 if (!vf) 366 f2g = &gfx_v10_3_kfd2kgd; 367 break; 368 /* Dimgrey Cavefish */ 369 case IP_VERSION(10, 3, 4): 370 gfx_target_version = 100302; 371 f2g = &gfx_v10_3_kfd2kgd; 372 break; 373 /* Beige Goby */ 374 case IP_VERSION(10, 3, 5): 375 gfx_target_version = 100304; 376 f2g = &gfx_v10_3_kfd2kgd; 377 break; 378 /* Yellow Carp */ 379 case IP_VERSION(10, 3, 3): 380 gfx_target_version = 100305; 381 if (!vf) 382 f2g = &gfx_v10_3_kfd2kgd; 383 break; 384 case IP_VERSION(10, 3, 6): 385 case IP_VERSION(10, 3, 7): 386 gfx_target_version = 100306; 387 if (!vf) 388 f2g = &gfx_v10_3_kfd2kgd; 389 break; 390 case IP_VERSION(11, 0, 0): 391 gfx_target_version = 110000; 392 f2g = &gfx_v11_kfd2kgd; 393 break; 394 case IP_VERSION(11, 0, 1): 395 gfx_target_version = 110003; 396 f2g = &gfx_v11_kfd2kgd; 397 break; 398 case IP_VERSION(11, 0, 2): 399 gfx_target_version = 110002; 400 f2g = &gfx_v11_kfd2kgd; 401 break; 402 default: 403 break; 404 } 405 break; 406 } 407 408 if (!f2g) { 409 if (adev->ip_versions[GC_HWIP][0]) 410 dev_err(kfd_device, "GC IP %06x %s not supported in kfd\n", 411 adev->ip_versions[GC_HWIP][0], vf ? "VF" : ""); 412 else 413 dev_err(kfd_device, "%s %s not supported in kfd\n", 414 amdgpu_asic_name[adev->asic_type], vf ? "VF" : ""); 415 return NULL; 416 } 417 418 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 419 if (!kfd) 420 return NULL; 421 422 kfd->adev = adev; 423 kfd_device_info_init(kfd, vf, gfx_target_version); 424 kfd->pdev = pdev; 425 kfd->init_complete = false; 426 kfd->kfd2kgd = f2g; 427 atomic_set(&kfd->compute_profile, 0); 428 429 mutex_init(&kfd->doorbell_mutex); 430 memset(&kfd->doorbell_available_index, 0, 431 sizeof(kfd->doorbell_available_index)); 432 433 atomic_set(&kfd->sram_ecc_flag, 0); 434 435 ida_init(&kfd->doorbell_ida); 436 437 return kfd; 438 } 439 440 static void kfd_cwsr_init(struct kfd_dev *kfd) 441 { 442 if (cwsr_enable && kfd->device_info.supports_cwsr) { 443 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) { 444 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE); 445 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 446 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 447 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) { 448 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE); 449 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 450 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 451 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) { 452 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) > PAGE_SIZE); 453 kfd->cwsr_isa = cwsr_trap_aldebaran_hex; 454 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); 455 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) { 456 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE); 457 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 458 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 459 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) { 460 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE); 461 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 462 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 463 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) { 464 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE); 465 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 466 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 467 } else { 468 BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE); 469 kfd->cwsr_isa = cwsr_trap_gfx11_hex; 470 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex); 471 } 472 473 kfd->cwsr_enabled = true; 474 } 475 } 476 477 static int kfd_gws_init(struct kfd_dev *kfd) 478 { 479 int ret = 0; 480 481 if (kfd->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 482 return 0; 483 484 if (hws_gws_support || (KFD_IS_SOC15(kfd) && 485 ((KFD_GC_VERSION(kfd) == IP_VERSION(9, 0, 1) 486 && kfd->mec2_fw_version >= 0x81b3) || 487 (KFD_GC_VERSION(kfd) <= IP_VERSION(9, 4, 0) 488 && kfd->mec2_fw_version >= 0x1b3) || 489 (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1) 490 && kfd->mec2_fw_version >= 0x30) || 491 (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) 492 && kfd->mec2_fw_version >= 0x28)))) 493 ret = amdgpu_amdkfd_alloc_gws(kfd->adev, 494 kfd->adev->gds.gws_size, &kfd->gws); 495 496 return ret; 497 } 498 499 static void kfd_smi_init(struct kfd_dev *dev) 500 { 501 INIT_LIST_HEAD(&dev->smi_clients); 502 spin_lock_init(&dev->smi_lock); 503 } 504 505 bool kgd2kfd_device_init(struct kfd_dev *kfd, 506 struct drm_device *ddev, 507 const struct kgd2kfd_shared_resources *gpu_resources) 508 { 509 unsigned int size, map_process_packet_size; 510 511 kfd->ddev = ddev; 512 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 513 KGD_ENGINE_MEC1); 514 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 515 KGD_ENGINE_MEC2); 516 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 517 KGD_ENGINE_SDMA1); 518 kfd->shared_resources = *gpu_resources; 519 520 kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 521 kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 522 kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd 523 - kfd->vm_info.first_vmid_kfd + 1; 524 525 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 526 * 32 and 64-bit requests are possible and must be 527 * supported. 528 */ 529 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev); 530 if (!kfd->pci_atomic_requested && 531 kfd->device_info.needs_pci_atomics && 532 (!kfd->device_info.no_atomic_fw_version || 533 kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) { 534 dev_info(kfd_device, 535 "skipped device %x:%x, PCI rejects atomics %d<%d\n", 536 kfd->pdev->vendor, kfd->pdev->device, 537 kfd->mec_fw_version, 538 kfd->device_info.no_atomic_fw_version); 539 return false; 540 } 541 542 /* Verify module parameters regarding mapped process number*/ 543 if (hws_max_conc_proc >= 0) 544 kfd->max_proc_per_quantum = min((u32)hws_max_conc_proc, kfd->vm_info.vmid_num_kfd); 545 else 546 kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd; 547 548 /* calculate max size of mqds needed for queues */ 549 size = max_num_of_queues_per_device * 550 kfd->device_info.mqd_size_aligned; 551 552 /* 553 * calculate max size of runlist packet. 554 * There can be only 2 packets at once 555 */ 556 map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ? 557 sizeof(struct pm4_mes_map_process_aldebaran) : 558 sizeof(struct pm4_mes_map_process); 559 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + 560 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 561 + sizeof(struct pm4_mes_runlist)) * 2; 562 563 /* Add size of HIQ & DIQ */ 564 size += KFD_KERNEL_QUEUE_SIZE * 2; 565 566 /* add another 512KB for all other allocations on gart (HPD, fences) */ 567 size += 512 * 1024; 568 569 if (amdgpu_amdkfd_alloc_gtt_mem( 570 kfd->adev, size, &kfd->gtt_mem, 571 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 572 false)) { 573 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 574 goto alloc_gtt_mem_failure; 575 } 576 577 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 578 579 /* Initialize GTT sa with 512 byte chunk size */ 580 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 581 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 582 goto kfd_gtt_sa_init_error; 583 } 584 585 if (kfd_doorbell_init(kfd)) { 586 dev_err(kfd_device, 587 "Error initializing doorbell aperture\n"); 588 goto kfd_doorbell_error; 589 } 590 591 if (amdgpu_use_xgmi_p2p) 592 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id; 593 594 kfd->noretry = kfd->adev->gmc.noretry; 595 596 if (kfd_interrupt_init(kfd)) { 597 dev_err(kfd_device, "Error initializing interrupts\n"); 598 goto kfd_interrupt_error; 599 } 600 601 kfd->dqm = device_queue_manager_init(kfd); 602 if (!kfd->dqm) { 603 dev_err(kfd_device, "Error initializing queue manager\n"); 604 goto device_queue_manager_error; 605 } 606 607 /* If supported on this device, allocate global GWS that is shared 608 * by all KFD processes 609 */ 610 if (kfd_gws_init(kfd)) { 611 dev_err(kfd_device, "Could not allocate %d gws\n", 612 kfd->adev->gds.gws_size); 613 goto gws_error; 614 } 615 616 /* If CRAT is broken, won't set iommu enabled */ 617 kfd_double_confirm_iommu_support(kfd); 618 619 if (kfd_iommu_device_init(kfd)) { 620 kfd->use_iommu_v2 = false; 621 dev_err(kfd_device, "Error initializing iommuv2\n"); 622 goto device_iommu_error; 623 } 624 625 kfd_cwsr_init(kfd); 626 627 svm_migrate_init(kfd->adev); 628 629 if (kgd2kfd_resume_iommu(kfd)) 630 goto device_iommu_error; 631 632 if (kfd_resume(kfd)) 633 goto kfd_resume_error; 634 635 amdgpu_amdkfd_get_local_mem_info(kfd->adev, &kfd->local_mem_info); 636 637 if (kfd_topology_add_device(kfd)) { 638 dev_err(kfd_device, "Error adding device to topology\n"); 639 goto kfd_topology_add_device_error; 640 } 641 642 kfd_smi_init(kfd); 643 644 kfd->init_complete = true; 645 dev_info(kfd_device, "added device %x:%x\n", kfd->pdev->vendor, 646 kfd->pdev->device); 647 648 pr_debug("Starting kfd with the following scheduling policy %d\n", 649 kfd->dqm->sched_policy); 650 651 goto out; 652 653 kfd_topology_add_device_error: 654 kfd_resume_error: 655 device_iommu_error: 656 gws_error: 657 device_queue_manager_uninit(kfd->dqm); 658 device_queue_manager_error: 659 kfd_interrupt_exit(kfd); 660 kfd_interrupt_error: 661 kfd_doorbell_fini(kfd); 662 kfd_doorbell_error: 663 kfd_gtt_sa_fini(kfd); 664 kfd_gtt_sa_init_error: 665 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 666 alloc_gtt_mem_failure: 667 if (kfd->gws) 668 amdgpu_amdkfd_free_gws(kfd->adev, kfd->gws); 669 dev_err(kfd_device, 670 "device %x:%x NOT added due to errors\n", 671 kfd->pdev->vendor, kfd->pdev->device); 672 out: 673 return kfd->init_complete; 674 } 675 676 void kgd2kfd_device_exit(struct kfd_dev *kfd) 677 { 678 if (kfd->init_complete) { 679 device_queue_manager_uninit(kfd->dqm); 680 kfd_interrupt_exit(kfd); 681 kfd_topology_remove_device(kfd); 682 kfd_doorbell_fini(kfd); 683 ida_destroy(&kfd->doorbell_ida); 684 kfd_gtt_sa_fini(kfd); 685 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 686 if (kfd->gws) 687 amdgpu_amdkfd_free_gws(kfd->adev, kfd->gws); 688 } 689 690 kfree(kfd); 691 } 692 693 int kgd2kfd_pre_reset(struct kfd_dev *kfd) 694 { 695 if (!kfd->init_complete) 696 return 0; 697 698 kfd_smi_event_update_gpu_reset(kfd, false); 699 700 kfd->dqm->ops.pre_reset(kfd->dqm); 701 702 kgd2kfd_suspend(kfd, false); 703 704 kfd_signal_reset_event(kfd); 705 return 0; 706 } 707 708 /* 709 * Fix me. KFD won't be able to resume existing process for now. 710 * We will keep all existing process in a evicted state and 711 * wait the process to be terminated. 712 */ 713 714 int kgd2kfd_post_reset(struct kfd_dev *kfd) 715 { 716 int ret; 717 718 if (!kfd->init_complete) 719 return 0; 720 721 ret = kfd_resume(kfd); 722 if (ret) 723 return ret; 724 atomic_dec(&kfd_locked); 725 726 atomic_set(&kfd->sram_ecc_flag, 0); 727 728 kfd_smi_event_update_gpu_reset(kfd, true); 729 730 return 0; 731 } 732 733 bool kfd_is_locked(void) 734 { 735 return (atomic_read(&kfd_locked) > 0); 736 } 737 738 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 739 { 740 if (!kfd->init_complete) 741 return; 742 743 /* for runtime suspend, skip locking kfd */ 744 if (!run_pm) { 745 /* For first KFD device suspend all the KFD processes */ 746 if (atomic_inc_return(&kfd_locked) == 1) 747 kfd_suspend_all_processes(); 748 } 749 750 kfd->dqm->ops.stop(kfd->dqm); 751 kfd_iommu_suspend(kfd); 752 } 753 754 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 755 { 756 int ret, count; 757 758 if (!kfd->init_complete) 759 return 0; 760 761 ret = kfd_resume(kfd); 762 if (ret) 763 return ret; 764 765 /* for runtime resume, skip unlocking kfd */ 766 if (!run_pm) { 767 count = atomic_dec_return(&kfd_locked); 768 WARN_ONCE(count < 0, "KFD suspend / resume ref. error"); 769 if (count == 0) 770 ret = kfd_resume_all_processes(); 771 } 772 773 return ret; 774 } 775 776 int kgd2kfd_resume_iommu(struct kfd_dev *kfd) 777 { 778 int err = 0; 779 780 err = kfd_iommu_resume(kfd); 781 if (err) 782 dev_err(kfd_device, 783 "Failed to resume IOMMU for device %x:%x\n", 784 kfd->pdev->vendor, kfd->pdev->device); 785 return err; 786 } 787 788 static int kfd_resume(struct kfd_dev *kfd) 789 { 790 int err = 0; 791 792 err = kfd->dqm->ops.start(kfd->dqm); 793 if (err) 794 dev_err(kfd_device, 795 "Error starting queue manager for device %x:%x\n", 796 kfd->pdev->vendor, kfd->pdev->device); 797 798 return err; 799 } 800 801 static inline void kfd_queue_work(struct workqueue_struct *wq, 802 struct work_struct *work) 803 { 804 int cpu, new_cpu; 805 806 cpu = new_cpu = smp_processor_id(); 807 do { 808 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids; 809 if (cpu_to_node(new_cpu) == numa_node_id()) 810 break; 811 } while (cpu != new_cpu); 812 813 queue_work_on(new_cpu, wq, work); 814 } 815 816 /* This is called directly from KGD at ISR. */ 817 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 818 { 819 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE]; 820 bool is_patched = false; 821 unsigned long flags; 822 823 if (!kfd->init_complete) 824 return; 825 826 if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) { 827 dev_err_once(kfd_device, "Ring entry too small\n"); 828 return; 829 } 830 831 spin_lock_irqsave(&kfd->interrupt_lock, flags); 832 833 if (kfd->interrupts_active 834 && interrupt_is_wanted(kfd, ih_ring_entry, 835 patched_ihre, &is_patched) 836 && enqueue_ih_ring_entry(kfd, 837 is_patched ? patched_ihre : ih_ring_entry)) 838 kfd_queue_work(kfd->ih_wq, &kfd->interrupt_work); 839 840 spin_unlock_irqrestore(&kfd->interrupt_lock, flags); 841 } 842 843 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger) 844 { 845 struct kfd_process *p; 846 int r; 847 848 /* Because we are called from arbitrary context (workqueue) as opposed 849 * to process context, kfd_process could attempt to exit while we are 850 * running so the lookup function increments the process ref count. 851 */ 852 p = kfd_lookup_process_by_mm(mm); 853 if (!p) 854 return -ESRCH; 855 856 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 857 r = kfd_process_evict_queues(p, trigger); 858 859 kfd_unref_process(p); 860 return r; 861 } 862 863 int kgd2kfd_resume_mm(struct mm_struct *mm) 864 { 865 struct kfd_process *p; 866 int r; 867 868 /* Because we are called from arbitrary context (workqueue) as opposed 869 * to process context, kfd_process could attempt to exit while we are 870 * running so the lookup function increments the process ref count. 871 */ 872 p = kfd_lookup_process_by_mm(mm); 873 if (!p) 874 return -ESRCH; 875 876 r = kfd_process_restore_queues(p); 877 878 kfd_unref_process(p); 879 return r; 880 } 881 882 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 883 * prepare for safe eviction of KFD BOs that belong to the specified 884 * process. 885 * 886 * @mm: mm_struct that identifies the specified KFD process 887 * @fence: eviction fence attached to KFD process BOs 888 * 889 */ 890 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 891 struct dma_fence *fence) 892 { 893 struct kfd_process *p; 894 unsigned long active_time; 895 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 896 897 if (!fence) 898 return -EINVAL; 899 900 if (dma_fence_is_signaled(fence)) 901 return 0; 902 903 p = kfd_lookup_process_by_mm(mm); 904 if (!p) 905 return -ENODEV; 906 907 if (fence->seqno == p->last_eviction_seqno) 908 goto out; 909 910 p->last_eviction_seqno = fence->seqno; 911 912 /* Avoid KFD process starvation. Wait for at least 913 * PROCESS_ACTIVE_TIME_MS before evicting the process again 914 */ 915 active_time = get_jiffies_64() - p->last_restore_timestamp; 916 if (delay_jiffies > active_time) 917 delay_jiffies -= active_time; 918 else 919 delay_jiffies = 0; 920 921 /* During process initialization eviction_work.dwork is initialized 922 * to kfd_evict_bo_worker 923 */ 924 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 925 p->lead_thread->pid, delay_jiffies); 926 schedule_delayed_work(&p->eviction_work, delay_jiffies); 927 out: 928 kfd_unref_process(p); 929 return 0; 930 } 931 932 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 933 unsigned int chunk_size) 934 { 935 if (WARN_ON(buf_size < chunk_size)) 936 return -EINVAL; 937 if (WARN_ON(buf_size == 0)) 938 return -EINVAL; 939 if (WARN_ON(chunk_size == 0)) 940 return -EINVAL; 941 942 kfd->gtt_sa_chunk_size = chunk_size; 943 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 944 945 kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks, 946 GFP_KERNEL); 947 if (!kfd->gtt_sa_bitmap) 948 return -ENOMEM; 949 950 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 951 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 952 953 mutex_init(&kfd->gtt_sa_lock); 954 955 return 0; 956 } 957 958 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 959 { 960 mutex_destroy(&kfd->gtt_sa_lock); 961 bitmap_free(kfd->gtt_sa_bitmap); 962 } 963 964 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 965 unsigned int bit_num, 966 unsigned int chunk_size) 967 { 968 return start_addr + bit_num * chunk_size; 969 } 970 971 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 972 unsigned int bit_num, 973 unsigned int chunk_size) 974 { 975 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 976 } 977 978 int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size, 979 struct kfd_mem_obj **mem_obj) 980 { 981 unsigned int found, start_search, cur_size; 982 983 if (size == 0) 984 return -EINVAL; 985 986 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 987 return -ENOMEM; 988 989 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 990 if (!(*mem_obj)) 991 return -ENOMEM; 992 993 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 994 995 start_search = 0; 996 997 mutex_lock(&kfd->gtt_sa_lock); 998 999 kfd_gtt_restart_search: 1000 /* Find the first chunk that is free */ 1001 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1002 kfd->gtt_sa_num_of_chunks, 1003 start_search); 1004 1005 pr_debug("Found = %d\n", found); 1006 1007 /* If there wasn't any free chunk, bail out */ 1008 if (found == kfd->gtt_sa_num_of_chunks) 1009 goto kfd_gtt_no_free_chunk; 1010 1011 /* Update fields of mem_obj */ 1012 (*mem_obj)->range_start = found; 1013 (*mem_obj)->range_end = found; 1014 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1015 kfd->gtt_start_gpu_addr, 1016 found, 1017 kfd->gtt_sa_chunk_size); 1018 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1019 kfd->gtt_start_cpu_ptr, 1020 found, 1021 kfd->gtt_sa_chunk_size); 1022 1023 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1024 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1025 1026 /* If we need only one chunk, mark it as allocated and get out */ 1027 if (size <= kfd->gtt_sa_chunk_size) { 1028 pr_debug("Single bit\n"); 1029 __set_bit(found, kfd->gtt_sa_bitmap); 1030 goto kfd_gtt_out; 1031 } 1032 1033 /* Otherwise, try to see if we have enough contiguous chunks */ 1034 cur_size = size - kfd->gtt_sa_chunk_size; 1035 do { 1036 (*mem_obj)->range_end = 1037 find_next_zero_bit(kfd->gtt_sa_bitmap, 1038 kfd->gtt_sa_num_of_chunks, ++found); 1039 /* 1040 * If next free chunk is not contiguous than we need to 1041 * restart our search from the last free chunk we found (which 1042 * wasn't contiguous to the previous ones 1043 */ 1044 if ((*mem_obj)->range_end != found) { 1045 start_search = found; 1046 goto kfd_gtt_restart_search; 1047 } 1048 1049 /* 1050 * If we reached end of buffer, bail out with error 1051 */ 1052 if (found == kfd->gtt_sa_num_of_chunks) 1053 goto kfd_gtt_no_free_chunk; 1054 1055 /* Check if we don't need another chunk */ 1056 if (cur_size <= kfd->gtt_sa_chunk_size) 1057 cur_size = 0; 1058 else 1059 cur_size -= kfd->gtt_sa_chunk_size; 1060 1061 } while (cur_size > 0); 1062 1063 pr_debug("range_start = %d, range_end = %d\n", 1064 (*mem_obj)->range_start, (*mem_obj)->range_end); 1065 1066 /* Mark the chunks as allocated */ 1067 bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start, 1068 (*mem_obj)->range_end - (*mem_obj)->range_start + 1); 1069 1070 kfd_gtt_out: 1071 mutex_unlock(&kfd->gtt_sa_lock); 1072 return 0; 1073 1074 kfd_gtt_no_free_chunk: 1075 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1076 mutex_unlock(&kfd->gtt_sa_lock); 1077 kfree(*mem_obj); 1078 return -ENOMEM; 1079 } 1080 1081 int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj) 1082 { 1083 /* Act like kfree when trying to free a NULL object */ 1084 if (!mem_obj) 1085 return 0; 1086 1087 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1088 mem_obj, mem_obj->range_start, mem_obj->range_end); 1089 1090 mutex_lock(&kfd->gtt_sa_lock); 1091 1092 /* Mark the chunks as free */ 1093 bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start, 1094 mem_obj->range_end - mem_obj->range_start + 1); 1095 1096 mutex_unlock(&kfd->gtt_sa_lock); 1097 1098 kfree(mem_obj); 1099 return 0; 1100 } 1101 1102 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1103 { 1104 if (kfd) 1105 atomic_inc(&kfd->sram_ecc_flag); 1106 } 1107 1108 void kfd_inc_compute_active(struct kfd_dev *kfd) 1109 { 1110 if (atomic_inc_return(&kfd->compute_profile) == 1) 1111 amdgpu_amdkfd_set_compute_idle(kfd->adev, false); 1112 } 1113 1114 void kfd_dec_compute_active(struct kfd_dev *kfd) 1115 { 1116 int count = atomic_dec_return(&kfd->compute_profile); 1117 1118 if (count == 0) 1119 amdgpu_amdkfd_set_compute_idle(kfd->adev, true); 1120 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1121 } 1122 1123 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 1124 { 1125 if (kfd && kfd->init_complete) 1126 kfd_smi_event_update_thermal_throttling(kfd, throttle_bitmask); 1127 } 1128 1129 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and 1130 * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA. 1131 * When the device has more than two engines, we reserve two for PCIe to enable 1132 * full-duplex and the rest are used as XGMI. 1133 */ 1134 unsigned int kfd_get_num_sdma_engines(struct kfd_dev *kdev) 1135 { 1136 /* If XGMI is not supported, all SDMA engines are PCIe */ 1137 if (!kdev->adev->gmc.xgmi.supported) 1138 return kdev->adev->sdma.num_instances; 1139 1140 return min(kdev->adev->sdma.num_instances, 2); 1141 } 1142 1143 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_dev *kdev) 1144 { 1145 /* After reserved for PCIe, the rest of engines are XGMI */ 1146 return kdev->adev->sdma.num_instances - kfd_get_num_sdma_engines(kdev); 1147 } 1148 1149 #if defined(CONFIG_DEBUG_FS) 1150 1151 /* This function will send a package to HIQ to hang the HWS 1152 * which will trigger a GPU reset and bring the HWS back to normal state 1153 */ 1154 int kfd_debugfs_hang_hws(struct kfd_dev *dev) 1155 { 1156 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1157 pr_err("HWS is not enabled"); 1158 return -EINVAL; 1159 } 1160 1161 return dqm_debugfs_hang_hws(dev->dqm); 1162 } 1163 1164 #endif 1165