1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/bsearch.h> 25 #include <linux/pci.h> 26 #include <linux/slab.h> 27 #include "kfd_priv.h" 28 #include "kfd_device_queue_manager.h" 29 #include "kfd_pm4_headers_vi.h" 30 #include "kfd_pm4_headers_aldebaran.h" 31 #include "cwsr_trap_handler.h" 32 #include "kfd_iommu.h" 33 #include "amdgpu_amdkfd.h" 34 #include "kfd_smi_events.h" 35 #include "kfd_svm.h" 36 #include "kfd_migrate.h" 37 #include "amdgpu.h" 38 #include "amdgpu_xcp.h" 39 40 #define MQD_SIZE_ALIGNED 768 41 42 /* 43 * kfd_locked is used to lock the kfd driver during suspend or reset 44 * once locked, kfd driver will stop any further GPU execution. 45 * create process (open) will return -EAGAIN. 46 */ 47 static int kfd_locked; 48 49 #ifdef CONFIG_DRM_AMDGPU_CIK 50 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 51 #endif 52 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 53 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 54 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 55 extern const struct kfd2kgd_calls aldebaran_kfd2kgd; 56 extern const struct kfd2kgd_calls gc_9_4_3_kfd2kgd; 57 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 58 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 59 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd; 60 61 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 62 unsigned int chunk_size); 63 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 64 65 static int kfd_resume_iommu(struct kfd_dev *kfd); 66 static int kfd_resume(struct kfd_node *kfd); 67 68 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) 69 { 70 uint32_t sdma_version = kfd->adev->ip_versions[SDMA0_HWIP][0]; 71 72 switch (sdma_version) { 73 case IP_VERSION(4, 0, 0):/* VEGA10 */ 74 case IP_VERSION(4, 0, 1):/* VEGA12 */ 75 case IP_VERSION(4, 1, 0):/* RAVEN */ 76 case IP_VERSION(4, 1, 1):/* RAVEN */ 77 case IP_VERSION(4, 1, 2):/* RENOIR */ 78 case IP_VERSION(5, 2, 1):/* VANGOGH */ 79 case IP_VERSION(5, 2, 3):/* YELLOW_CARP */ 80 case IP_VERSION(5, 2, 6):/* GC 10.3.6 */ 81 case IP_VERSION(5, 2, 7):/* GC 10.3.7 */ 82 kfd->device_info.num_sdma_queues_per_engine = 2; 83 break; 84 case IP_VERSION(4, 2, 0):/* VEGA20 */ 85 case IP_VERSION(4, 2, 2):/* ARCTURUS */ 86 case IP_VERSION(4, 4, 0):/* ALDEBARAN */ 87 case IP_VERSION(4, 4, 2): 88 case IP_VERSION(5, 0, 0):/* NAVI10 */ 89 case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */ 90 case IP_VERSION(5, 0, 2):/* NAVI14 */ 91 case IP_VERSION(5, 0, 5):/* NAVI12 */ 92 case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */ 93 case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */ 94 case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */ 95 case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */ 96 case IP_VERSION(6, 0, 0): 97 case IP_VERSION(6, 0, 1): 98 case IP_VERSION(6, 0, 2): 99 case IP_VERSION(6, 0, 3): 100 kfd->device_info.num_sdma_queues_per_engine = 8; 101 break; 102 default: 103 dev_warn(kfd_device, 104 "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n", 105 sdma_version); 106 kfd->device_info.num_sdma_queues_per_engine = 8; 107 } 108 109 switch (sdma_version) { 110 case IP_VERSION(6, 0, 0): 111 case IP_VERSION(6, 0, 2): 112 case IP_VERSION(6, 0, 3): 113 /* Reserve 1 for paging and 1 for gfx */ 114 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 115 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */ 116 kfd->device_info.reserved_sdma_queues_bitmap = 0xFULL; 117 break; 118 case IP_VERSION(6, 0, 1): 119 /* Reserve 1 for paging and 1 for gfx */ 120 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 121 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-0 queue-1; ... */ 122 kfd->device_info.reserved_sdma_queues_bitmap = 0x3ULL; 123 break; 124 default: 125 break; 126 } 127 } 128 129 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) 130 { 131 uint32_t gc_version = KFD_GC_VERSION(kfd); 132 133 switch (gc_version) { 134 case IP_VERSION(9, 0, 1): /* VEGA10 */ 135 case IP_VERSION(9, 1, 0): /* RAVEN */ 136 case IP_VERSION(9, 2, 1): /* VEGA12 */ 137 case IP_VERSION(9, 2, 2): /* RAVEN */ 138 case IP_VERSION(9, 3, 0): /* RENOIR */ 139 case IP_VERSION(9, 4, 0): /* VEGA20 */ 140 case IP_VERSION(9, 4, 1): /* ARCTURUS */ 141 case IP_VERSION(9, 4, 2): /* ALDEBARAN */ 142 case IP_VERSION(9, 4, 3): /* GC 9.4.3 */ 143 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 144 break; 145 case IP_VERSION(10, 3, 1): /* VANGOGH */ 146 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */ 147 case IP_VERSION(10, 3, 6): /* GC 10.3.6 */ 148 case IP_VERSION(10, 3, 7): /* GC 10.3.7 */ 149 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */ 150 case IP_VERSION(10, 1, 4): 151 case IP_VERSION(10, 1, 10): /* NAVI10 */ 152 case IP_VERSION(10, 1, 2): /* NAVI12 */ 153 case IP_VERSION(10, 1, 1): /* NAVI14 */ 154 case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */ 155 case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */ 156 case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */ 157 case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */ 158 kfd->device_info.event_interrupt_class = &event_interrupt_class_v10; 159 break; 160 case IP_VERSION(11, 0, 0): 161 case IP_VERSION(11, 0, 1): 162 case IP_VERSION(11, 0, 2): 163 case IP_VERSION(11, 0, 3): 164 case IP_VERSION(11, 0, 4): 165 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 166 break; 167 default: 168 dev_warn(kfd_device, "v9 event interrupt handler is set due to " 169 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version); 170 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 171 } 172 } 173 174 static void kfd_device_info_init(struct kfd_dev *kfd, 175 bool vf, uint32_t gfx_target_version) 176 { 177 uint32_t gc_version = KFD_GC_VERSION(kfd); 178 uint32_t asic_type = kfd->adev->asic_type; 179 180 kfd->device_info.max_pasid_bits = 16; 181 kfd->device_info.max_no_of_hqd = 24; 182 kfd->device_info.num_of_watch_points = 4; 183 kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED; 184 kfd->device_info.gfx_target_version = gfx_target_version; 185 186 if (KFD_IS_SOC15(kfd)) { 187 kfd->device_info.doorbell_size = 8; 188 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t); 189 kfd->device_info.supports_cwsr = true; 190 191 kfd_device_info_set_sdma_info(kfd); 192 193 kfd_device_info_set_event_interrupt_class(kfd); 194 195 /* Raven */ 196 if (gc_version == IP_VERSION(9, 1, 0) || 197 gc_version == IP_VERSION(9, 2, 2)) 198 kfd->device_info.needs_iommu_device = true; 199 200 if (gc_version < IP_VERSION(11, 0, 0)) { 201 /* Navi2x+, Navi1x+ */ 202 if (gc_version == IP_VERSION(10, 3, 6)) 203 kfd->device_info.no_atomic_fw_version = 14; 204 else if (gc_version == IP_VERSION(10, 3, 7)) 205 kfd->device_info.no_atomic_fw_version = 3; 206 else if (gc_version >= IP_VERSION(10, 3, 0)) 207 kfd->device_info.no_atomic_fw_version = 92; 208 else if (gc_version >= IP_VERSION(10, 1, 1)) 209 kfd->device_info.no_atomic_fw_version = 145; 210 211 /* Navi1x+ */ 212 if (gc_version >= IP_VERSION(10, 1, 1)) 213 kfd->device_info.needs_pci_atomics = true; 214 } else if (gc_version < IP_VERSION(12, 0, 0)) { 215 /* 216 * PCIe atomics support acknowledgment in GFX11 RS64 CPFW requires 217 * MEC version >= 509. Prior RS64 CPFW versions (and all F32) require 218 * PCIe atomics support. 219 */ 220 kfd->device_info.needs_pci_atomics = true; 221 kfd->device_info.no_atomic_fw_version = kfd->adev->gfx.rs64_enable ? 509 : 0; 222 } 223 } else { 224 kfd->device_info.doorbell_size = 4; 225 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t); 226 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik; 227 kfd->device_info.num_sdma_queues_per_engine = 2; 228 229 if (asic_type != CHIP_KAVERI && 230 asic_type != CHIP_HAWAII && 231 asic_type != CHIP_TONGA) 232 kfd->device_info.supports_cwsr = true; 233 234 if (asic_type == CHIP_KAVERI || 235 asic_type == CHIP_CARRIZO) 236 kfd->device_info.needs_iommu_device = true; 237 238 if (asic_type != CHIP_HAWAII && !vf) 239 kfd->device_info.needs_pci_atomics = true; 240 } 241 } 242 243 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 244 { 245 struct kfd_dev *kfd = NULL; 246 const struct kfd2kgd_calls *f2g = NULL; 247 uint32_t gfx_target_version = 0; 248 249 switch (adev->asic_type) { 250 #ifdef KFD_SUPPORT_IOMMU_V2 251 #ifdef CONFIG_DRM_AMDGPU_CIK 252 case CHIP_KAVERI: 253 gfx_target_version = 70000; 254 if (!vf) 255 f2g = &gfx_v7_kfd2kgd; 256 break; 257 #endif 258 case CHIP_CARRIZO: 259 gfx_target_version = 80001; 260 if (!vf) 261 f2g = &gfx_v8_kfd2kgd; 262 break; 263 #endif 264 #ifdef CONFIG_DRM_AMDGPU_CIK 265 case CHIP_HAWAII: 266 gfx_target_version = 70001; 267 if (!amdgpu_exp_hw_support) 268 pr_info( 269 "KFD support on Hawaii is experimental. See modparam exp_hw_support\n" 270 ); 271 else if (!vf) 272 f2g = &gfx_v7_kfd2kgd; 273 break; 274 #endif 275 case CHIP_TONGA: 276 gfx_target_version = 80002; 277 if (!vf) 278 f2g = &gfx_v8_kfd2kgd; 279 break; 280 case CHIP_FIJI: 281 case CHIP_POLARIS10: 282 gfx_target_version = 80003; 283 f2g = &gfx_v8_kfd2kgd; 284 break; 285 case CHIP_POLARIS11: 286 case CHIP_POLARIS12: 287 case CHIP_VEGAM: 288 gfx_target_version = 80003; 289 if (!vf) 290 f2g = &gfx_v8_kfd2kgd; 291 break; 292 default: 293 switch (adev->ip_versions[GC_HWIP][0]) { 294 /* Vega 10 */ 295 case IP_VERSION(9, 0, 1): 296 gfx_target_version = 90000; 297 f2g = &gfx_v9_kfd2kgd; 298 break; 299 #ifdef KFD_SUPPORT_IOMMU_V2 300 /* Raven */ 301 case IP_VERSION(9, 1, 0): 302 case IP_VERSION(9, 2, 2): 303 gfx_target_version = 90002; 304 if (!vf) 305 f2g = &gfx_v9_kfd2kgd; 306 break; 307 #endif 308 /* Vega12 */ 309 case IP_VERSION(9, 2, 1): 310 gfx_target_version = 90004; 311 if (!vf) 312 f2g = &gfx_v9_kfd2kgd; 313 break; 314 /* Renoir */ 315 case IP_VERSION(9, 3, 0): 316 gfx_target_version = 90012; 317 if (!vf) 318 f2g = &gfx_v9_kfd2kgd; 319 break; 320 /* Vega20 */ 321 case IP_VERSION(9, 4, 0): 322 gfx_target_version = 90006; 323 if (!vf) 324 f2g = &gfx_v9_kfd2kgd; 325 break; 326 /* Arcturus */ 327 case IP_VERSION(9, 4, 1): 328 gfx_target_version = 90008; 329 f2g = &arcturus_kfd2kgd; 330 break; 331 /* Aldebaran */ 332 case IP_VERSION(9, 4, 2): 333 gfx_target_version = 90010; 334 f2g = &aldebaran_kfd2kgd; 335 break; 336 case IP_VERSION(9, 4, 3): 337 gfx_target_version = adev->rev_id >= 1 ? 90402 338 : adev->flags & AMD_IS_APU ? 90400 339 : 90401; 340 f2g = &gc_9_4_3_kfd2kgd; 341 break; 342 /* Navi10 */ 343 case IP_VERSION(10, 1, 10): 344 gfx_target_version = 100100; 345 if (!vf) 346 f2g = &gfx_v10_kfd2kgd; 347 break; 348 /* Navi12 */ 349 case IP_VERSION(10, 1, 2): 350 gfx_target_version = 100101; 351 f2g = &gfx_v10_kfd2kgd; 352 break; 353 /* Navi14 */ 354 case IP_VERSION(10, 1, 1): 355 gfx_target_version = 100102; 356 if (!vf) 357 f2g = &gfx_v10_kfd2kgd; 358 break; 359 /* Cyan Skillfish */ 360 case IP_VERSION(10, 1, 3): 361 case IP_VERSION(10, 1, 4): 362 gfx_target_version = 100103; 363 if (!vf) 364 f2g = &gfx_v10_kfd2kgd; 365 break; 366 /* Sienna Cichlid */ 367 case IP_VERSION(10, 3, 0): 368 gfx_target_version = 100300; 369 f2g = &gfx_v10_3_kfd2kgd; 370 break; 371 /* Navy Flounder */ 372 case IP_VERSION(10, 3, 2): 373 gfx_target_version = 100301; 374 f2g = &gfx_v10_3_kfd2kgd; 375 break; 376 /* Van Gogh */ 377 case IP_VERSION(10, 3, 1): 378 gfx_target_version = 100303; 379 if (!vf) 380 f2g = &gfx_v10_3_kfd2kgd; 381 break; 382 /* Dimgrey Cavefish */ 383 case IP_VERSION(10, 3, 4): 384 gfx_target_version = 100302; 385 f2g = &gfx_v10_3_kfd2kgd; 386 break; 387 /* Beige Goby */ 388 case IP_VERSION(10, 3, 5): 389 gfx_target_version = 100304; 390 f2g = &gfx_v10_3_kfd2kgd; 391 break; 392 /* Yellow Carp */ 393 case IP_VERSION(10, 3, 3): 394 gfx_target_version = 100305; 395 if (!vf) 396 f2g = &gfx_v10_3_kfd2kgd; 397 break; 398 case IP_VERSION(10, 3, 6): 399 case IP_VERSION(10, 3, 7): 400 gfx_target_version = 100306; 401 if (!vf) 402 f2g = &gfx_v10_3_kfd2kgd; 403 break; 404 case IP_VERSION(11, 0, 0): 405 gfx_target_version = 110000; 406 f2g = &gfx_v11_kfd2kgd; 407 break; 408 case IP_VERSION(11, 0, 1): 409 case IP_VERSION(11, 0, 4): 410 gfx_target_version = 110003; 411 f2g = &gfx_v11_kfd2kgd; 412 break; 413 case IP_VERSION(11, 0, 2): 414 gfx_target_version = 110002; 415 f2g = &gfx_v11_kfd2kgd; 416 break; 417 case IP_VERSION(11, 0, 3): 418 if ((adev->pdev->device == 0x7460 && 419 adev->pdev->revision == 0x00) || 420 (adev->pdev->device == 0x7461 && 421 adev->pdev->revision == 0x00)) 422 /* Note: Compiler version is 11.0.5 while HW version is 11.0.3 */ 423 gfx_target_version = 110005; 424 else 425 /* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */ 426 gfx_target_version = 110001; 427 f2g = &gfx_v11_kfd2kgd; 428 break; 429 default: 430 break; 431 } 432 break; 433 } 434 435 if (!f2g) { 436 if (adev->ip_versions[GC_HWIP][0]) 437 dev_err(kfd_device, "GC IP %06x %s not supported in kfd\n", 438 adev->ip_versions[GC_HWIP][0], vf ? "VF" : ""); 439 else 440 dev_err(kfd_device, "%s %s not supported in kfd\n", 441 amdgpu_asic_name[adev->asic_type], vf ? "VF" : ""); 442 return NULL; 443 } 444 445 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 446 if (!kfd) 447 return NULL; 448 449 kfd->adev = adev; 450 kfd_device_info_init(kfd, vf, gfx_target_version); 451 kfd->init_complete = false; 452 kfd->kfd2kgd = f2g; 453 atomic_set(&kfd->compute_profile, 0); 454 455 mutex_init(&kfd->doorbell_mutex); 456 memset(&kfd->doorbell_available_index, 0, 457 sizeof(kfd->doorbell_available_index)); 458 459 ida_init(&kfd->doorbell_ida); 460 461 return kfd; 462 } 463 464 static void kfd_cwsr_init(struct kfd_dev *kfd) 465 { 466 if (cwsr_enable && kfd->device_info.supports_cwsr) { 467 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) { 468 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE); 469 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 470 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 471 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) { 472 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE); 473 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 474 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 475 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) { 476 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) > PAGE_SIZE); 477 kfd->cwsr_isa = cwsr_trap_aldebaran_hex; 478 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); 479 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3)) { 480 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_4_3_hex) > PAGE_SIZE); 481 kfd->cwsr_isa = cwsr_trap_gfx9_4_3_hex; 482 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_4_3_hex); 483 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) { 484 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE); 485 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 486 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 487 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) { 488 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE); 489 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 490 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 491 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) { 492 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE); 493 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 494 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 495 } else { 496 BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE); 497 kfd->cwsr_isa = cwsr_trap_gfx11_hex; 498 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex); 499 } 500 501 kfd->cwsr_enabled = true; 502 } 503 } 504 505 static int kfd_gws_init(struct kfd_node *node) 506 { 507 int ret = 0; 508 struct kfd_dev *kfd = node->kfd; 509 510 if (node->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 511 return 0; 512 513 if (hws_gws_support || (KFD_IS_SOC15(node) && 514 ((KFD_GC_VERSION(node) == IP_VERSION(9, 0, 1) 515 && kfd->mec2_fw_version >= 0x81b3) || 516 (KFD_GC_VERSION(node) <= IP_VERSION(9, 4, 0) 517 && kfd->mec2_fw_version >= 0x1b3) || 518 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 1) 519 && kfd->mec2_fw_version >= 0x30) || 520 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 2) 521 && kfd->mec2_fw_version >= 0x28) || 522 (KFD_GC_VERSION(node) >= IP_VERSION(10, 3, 0) 523 && KFD_GC_VERSION(node) < IP_VERSION(11, 0, 0) 524 && kfd->mec2_fw_version >= 0x6b)))) 525 ret = amdgpu_amdkfd_alloc_gws(node->adev, 526 node->adev->gds.gws_size, &node->gws); 527 528 return ret; 529 } 530 531 static void kfd_smi_init(struct kfd_node *dev) 532 { 533 INIT_LIST_HEAD(&dev->smi_clients); 534 spin_lock_init(&dev->smi_lock); 535 } 536 537 static int kfd_init_node(struct kfd_node *node) 538 { 539 int err = -1; 540 541 if (kfd_interrupt_init(node)) { 542 dev_err(kfd_device, "Error initializing interrupts\n"); 543 goto kfd_interrupt_error; 544 } 545 546 node->dqm = device_queue_manager_init(node); 547 if (!node->dqm) { 548 dev_err(kfd_device, "Error initializing queue manager\n"); 549 goto device_queue_manager_error; 550 } 551 552 if (kfd_gws_init(node)) { 553 dev_err(kfd_device, "Could not allocate %d gws\n", 554 node->adev->gds.gws_size); 555 goto gws_error; 556 } 557 558 if (kfd_resume(node)) 559 goto kfd_resume_error; 560 561 if (kfd_topology_add_device(node)) { 562 dev_err(kfd_device, "Error adding device to topology\n"); 563 goto kfd_topology_add_device_error; 564 } 565 566 kfd_smi_init(node); 567 568 return 0; 569 570 kfd_topology_add_device_error: 571 kfd_resume_error: 572 gws_error: 573 device_queue_manager_uninit(node->dqm); 574 device_queue_manager_error: 575 kfd_interrupt_exit(node); 576 kfd_interrupt_error: 577 if (node->gws) 578 amdgpu_amdkfd_free_gws(node->adev, node->gws); 579 580 /* Cleanup the node memory here */ 581 kfree(node); 582 return err; 583 } 584 585 static void kfd_cleanup_nodes(struct kfd_dev *kfd, unsigned int num_nodes) 586 { 587 struct kfd_node *knode; 588 unsigned int i; 589 590 for (i = 0; i < num_nodes; i++) { 591 knode = kfd->nodes[i]; 592 device_queue_manager_uninit(knode->dqm); 593 kfd_interrupt_exit(knode); 594 kfd_topology_remove_device(knode); 595 if (knode->gws) 596 amdgpu_amdkfd_free_gws(knode->adev, knode->gws); 597 kfree(knode); 598 kfd->nodes[i] = NULL; 599 } 600 } 601 602 bool kgd2kfd_device_init(struct kfd_dev *kfd, 603 const struct kgd2kfd_shared_resources *gpu_resources) 604 { 605 unsigned int size, map_process_packet_size, i; 606 struct kfd_node *node; 607 uint32_t first_vmid_kfd, last_vmid_kfd, vmid_num_kfd; 608 unsigned int max_proc_per_quantum; 609 int partition_mode; 610 int xcp_idx; 611 612 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 613 KGD_ENGINE_MEC1); 614 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 615 KGD_ENGINE_MEC2); 616 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 617 KGD_ENGINE_SDMA1); 618 kfd->shared_resources = *gpu_resources; 619 620 kfd->num_nodes = amdgpu_xcp_get_num_xcp(kfd->adev->xcp_mgr); 621 622 if (kfd->num_nodes == 0) { 623 dev_err(kfd_device, 624 "KFD num nodes cannot be 0, num_xcc_in_node: %d\n", 625 kfd->adev->gfx.num_xcc_per_xcp); 626 goto out; 627 } 628 629 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 630 * 32 and 64-bit requests are possible and must be 631 * supported. 632 */ 633 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev); 634 if (!kfd->pci_atomic_requested && 635 kfd->device_info.needs_pci_atomics && 636 (!kfd->device_info.no_atomic_fw_version || 637 kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) { 638 dev_info(kfd_device, 639 "skipped device %x:%x, PCI rejects atomics %d<%d\n", 640 kfd->adev->pdev->vendor, kfd->adev->pdev->device, 641 kfd->mec_fw_version, 642 kfd->device_info.no_atomic_fw_version); 643 return false; 644 } 645 646 first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 647 last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 648 vmid_num_kfd = last_vmid_kfd - first_vmid_kfd + 1; 649 650 /* For GFX9.4.3, we need special handling for VMIDs depending on 651 * partition mode. 652 * In CPX mode, the VMID range needs to be shared between XCDs. 653 * Additionally, there are 13 VMIDs (3-15) available for KFD. To 654 * divide them equally, we change starting VMID to 4 and not use 655 * VMID 3. 656 * If the VMID range changes for GFX9.4.3, then this code MUST be 657 * revisited. 658 */ 659 if (kfd->adev->xcp_mgr) { 660 partition_mode = amdgpu_xcp_query_partition_mode(kfd->adev->xcp_mgr, 661 AMDGPU_XCP_FL_LOCKED); 662 if (partition_mode == AMDGPU_CPX_PARTITION_MODE && 663 kfd->num_nodes != 1) { 664 vmid_num_kfd /= 2; 665 first_vmid_kfd = last_vmid_kfd + 1 - vmid_num_kfd*2; 666 } 667 } 668 669 /* Verify module parameters regarding mapped process number*/ 670 if (hws_max_conc_proc >= 0) 671 max_proc_per_quantum = min((u32)hws_max_conc_proc, vmid_num_kfd); 672 else 673 max_proc_per_quantum = vmid_num_kfd; 674 675 /* calculate max size of mqds needed for queues */ 676 size = max_num_of_queues_per_device * 677 kfd->device_info.mqd_size_aligned; 678 679 /* 680 * calculate max size of runlist packet. 681 * There can be only 2 packets at once 682 */ 683 map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ? 684 sizeof(struct pm4_mes_map_process_aldebaran) : 685 sizeof(struct pm4_mes_map_process); 686 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + 687 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 688 + sizeof(struct pm4_mes_runlist)) * 2; 689 690 /* Add size of HIQ & DIQ */ 691 size += KFD_KERNEL_QUEUE_SIZE * 2; 692 693 /* add another 512KB for all other allocations on gart (HPD, fences) */ 694 size += 512 * 1024; 695 696 if (amdgpu_amdkfd_alloc_gtt_mem( 697 kfd->adev, size, &kfd->gtt_mem, 698 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 699 false)) { 700 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 701 goto alloc_gtt_mem_failure; 702 } 703 704 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 705 706 /* Initialize GTT sa with 512 byte chunk size */ 707 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 708 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 709 goto kfd_gtt_sa_init_error; 710 } 711 712 if (kfd_doorbell_init(kfd)) { 713 dev_err(kfd_device, 714 "Error initializing doorbell aperture\n"); 715 goto kfd_doorbell_error; 716 } 717 718 if (amdgpu_use_xgmi_p2p) 719 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id; 720 721 /* 722 * For GFX9.4.3, the KFD abstracts all partitions within a socket as 723 * xGMI connected in the topology so assign a unique hive id per 724 * device based on the pci device location if device is in PCIe mode. 725 */ 726 if (!kfd->hive_id && (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3)) && kfd->num_nodes > 1) 727 kfd->hive_id = pci_dev_id(kfd->adev->pdev); 728 729 kfd->noretry = kfd->adev->gmc.noretry; 730 731 /* If CRAT is broken, won't set iommu enabled */ 732 kfd_double_confirm_iommu_support(kfd); 733 734 if (kfd_iommu_device_init(kfd)) { 735 kfd->use_iommu_v2 = false; 736 dev_err(kfd_device, "Error initializing iommuv2\n"); 737 goto device_iommu_error; 738 } 739 740 kfd_cwsr_init(kfd); 741 742 dev_info(kfd_device, "Total number of KFD nodes to be created: %d\n", 743 kfd->num_nodes); 744 745 /* Allocate the KFD nodes */ 746 for (i = 0, xcp_idx = 0; i < kfd->num_nodes; i++) { 747 node = kzalloc(sizeof(struct kfd_node), GFP_KERNEL); 748 if (!node) 749 goto node_alloc_error; 750 751 node->node_id = i; 752 node->adev = kfd->adev; 753 node->kfd = kfd; 754 node->kfd2kgd = kfd->kfd2kgd; 755 node->vm_info.vmid_num_kfd = vmid_num_kfd; 756 node->xcp = amdgpu_get_next_xcp(kfd->adev->xcp_mgr, &xcp_idx); 757 /* TODO : Check if error handling is needed */ 758 if (node->xcp) { 759 amdgpu_xcp_get_inst_details(node->xcp, AMDGPU_XCP_GFX, 760 &node->xcc_mask); 761 ++xcp_idx; 762 } else { 763 node->xcc_mask = 764 (1U << NUM_XCC(kfd->adev->gfx.xcc_mask)) - 1; 765 } 766 767 if (node->xcp) { 768 dev_info(kfd_device, "KFD node %d partition %d size %lldM\n", 769 node->node_id, node->xcp->mem_id, 770 KFD_XCP_MEMORY_SIZE(node->adev, node->node_id) >> 20); 771 } 772 773 if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) && 774 partition_mode == AMDGPU_CPX_PARTITION_MODE && 775 kfd->num_nodes != 1) { 776 /* For GFX9.4.3 and CPX mode, first XCD gets VMID range 777 * 4-9 and second XCD gets VMID range 10-15. 778 */ 779 780 node->vm_info.first_vmid_kfd = (i%2 == 0) ? 781 first_vmid_kfd : 782 first_vmid_kfd+vmid_num_kfd; 783 node->vm_info.last_vmid_kfd = (i%2 == 0) ? 784 last_vmid_kfd-vmid_num_kfd : 785 last_vmid_kfd; 786 node->compute_vmid_bitmap = 787 ((0x1 << (node->vm_info.last_vmid_kfd + 1)) - 1) - 788 ((0x1 << (node->vm_info.first_vmid_kfd)) - 1); 789 } else { 790 node->vm_info.first_vmid_kfd = first_vmid_kfd; 791 node->vm_info.last_vmid_kfd = last_vmid_kfd; 792 node->compute_vmid_bitmap = 793 gpu_resources->compute_vmid_bitmap; 794 } 795 node->max_proc_per_quantum = max_proc_per_quantum; 796 atomic_set(&node->sram_ecc_flag, 0); 797 798 amdgpu_amdkfd_get_local_mem_info(kfd->adev, 799 &node->local_mem_info, node->xcp); 800 801 /* Initialize the KFD node */ 802 if (kfd_init_node(node)) { 803 dev_err(kfd_device, "Error initializing KFD node\n"); 804 goto node_init_error; 805 } 806 kfd->nodes[i] = node; 807 } 808 809 svm_range_set_max_pages(kfd->adev); 810 811 if (kfd_resume_iommu(kfd)) 812 goto kfd_resume_iommu_error; 813 814 kfd->init_complete = true; 815 dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, 816 kfd->adev->pdev->device); 817 818 pr_debug("Starting kfd with the following scheduling policy %d\n", 819 node->dqm->sched_policy); 820 821 goto out; 822 823 kfd_resume_iommu_error: 824 node_init_error: 825 node_alloc_error: 826 kfd_cleanup_nodes(kfd, i); 827 device_iommu_error: 828 kfd_doorbell_fini(kfd); 829 kfd_doorbell_error: 830 kfd_gtt_sa_fini(kfd); 831 kfd_gtt_sa_init_error: 832 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 833 alloc_gtt_mem_failure: 834 dev_err(kfd_device, 835 "device %x:%x NOT added due to errors\n", 836 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 837 out: 838 return kfd->init_complete; 839 } 840 841 void kgd2kfd_device_exit(struct kfd_dev *kfd) 842 { 843 if (kfd->init_complete) { 844 /* Cleanup KFD nodes */ 845 kfd_cleanup_nodes(kfd, kfd->num_nodes); 846 /* Cleanup common/shared resources */ 847 kfd_doorbell_fini(kfd); 848 ida_destroy(&kfd->doorbell_ida); 849 kfd_gtt_sa_fini(kfd); 850 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 851 } 852 853 kfree(kfd); 854 } 855 856 int kgd2kfd_pre_reset(struct kfd_dev *kfd) 857 { 858 struct kfd_node *node; 859 int i; 860 861 if (!kfd->init_complete) 862 return 0; 863 864 for (i = 0; i < kfd->num_nodes; i++) { 865 node = kfd->nodes[i]; 866 kfd_smi_event_update_gpu_reset(node, false); 867 node->dqm->ops.pre_reset(node->dqm); 868 } 869 870 kgd2kfd_suspend(kfd, false); 871 872 for (i = 0; i < kfd->num_nodes; i++) 873 kfd_signal_reset_event(kfd->nodes[i]); 874 875 return 0; 876 } 877 878 /* 879 * Fix me. KFD won't be able to resume existing process for now. 880 * We will keep all existing process in a evicted state and 881 * wait the process to be terminated. 882 */ 883 884 int kgd2kfd_post_reset(struct kfd_dev *kfd) 885 { 886 int ret; 887 struct kfd_node *node; 888 int i; 889 890 if (!kfd->init_complete) 891 return 0; 892 893 for (i = 0; i < kfd->num_nodes; i++) { 894 ret = kfd_resume(kfd->nodes[i]); 895 if (ret) 896 return ret; 897 } 898 899 mutex_lock(&kfd_processes_mutex); 900 --kfd_locked; 901 mutex_unlock(&kfd_processes_mutex); 902 903 for (i = 0; i < kfd->num_nodes; i++) { 904 node = kfd->nodes[i]; 905 atomic_set(&node->sram_ecc_flag, 0); 906 kfd_smi_event_update_gpu_reset(node, true); 907 } 908 909 return 0; 910 } 911 912 bool kfd_is_locked(void) 913 { 914 lockdep_assert_held(&kfd_processes_mutex); 915 return (kfd_locked > 0); 916 } 917 918 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 919 { 920 struct kfd_node *node; 921 int i; 922 int count; 923 924 if (!kfd->init_complete) 925 return; 926 927 /* for runtime suspend, skip locking kfd */ 928 if (!run_pm) { 929 mutex_lock(&kfd_processes_mutex); 930 count = ++kfd_locked; 931 mutex_unlock(&kfd_processes_mutex); 932 933 /* For first KFD device suspend all the KFD processes */ 934 if (count == 1) 935 kfd_suspend_all_processes(); 936 } 937 938 for (i = 0; i < kfd->num_nodes; i++) { 939 node = kfd->nodes[i]; 940 node->dqm->ops.stop(node->dqm); 941 } 942 kfd_iommu_suspend(kfd); 943 } 944 945 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 946 { 947 int ret, count, i; 948 949 if (!kfd->init_complete) 950 return 0; 951 952 for (i = 0; i < kfd->num_nodes; i++) { 953 ret = kfd_resume(kfd->nodes[i]); 954 if (ret) 955 return ret; 956 } 957 958 /* for runtime resume, skip unlocking kfd */ 959 if (!run_pm) { 960 mutex_lock(&kfd_processes_mutex); 961 count = --kfd_locked; 962 mutex_unlock(&kfd_processes_mutex); 963 964 WARN_ONCE(count < 0, "KFD suspend / resume ref. error"); 965 if (count == 0) 966 ret = kfd_resume_all_processes(); 967 } 968 969 return ret; 970 } 971 972 int kgd2kfd_resume_iommu(struct kfd_dev *kfd) 973 { 974 if (!kfd->init_complete) 975 return 0; 976 977 return kfd_resume_iommu(kfd); 978 } 979 980 static int kfd_resume_iommu(struct kfd_dev *kfd) 981 { 982 int err = 0; 983 984 err = kfd_iommu_resume(kfd); 985 if (err) 986 dev_err(kfd_device, 987 "Failed to resume IOMMU for device %x:%x\n", 988 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 989 return err; 990 } 991 992 static int kfd_resume(struct kfd_node *node) 993 { 994 int err = 0; 995 996 err = node->dqm->ops.start(node->dqm); 997 if (err) 998 dev_err(kfd_device, 999 "Error starting queue manager for device %x:%x\n", 1000 node->adev->pdev->vendor, node->adev->pdev->device); 1001 1002 return err; 1003 } 1004 1005 static inline void kfd_queue_work(struct workqueue_struct *wq, 1006 struct work_struct *work) 1007 { 1008 int cpu, new_cpu; 1009 1010 cpu = new_cpu = smp_processor_id(); 1011 do { 1012 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids; 1013 if (cpu_to_node(new_cpu) == numa_node_id()) 1014 break; 1015 } while (cpu != new_cpu); 1016 1017 queue_work_on(new_cpu, wq, work); 1018 } 1019 1020 /* This is called directly from KGD at ISR. */ 1021 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 1022 { 1023 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE], i; 1024 bool is_patched = false; 1025 unsigned long flags; 1026 struct kfd_node *node; 1027 1028 if (!kfd->init_complete) 1029 return; 1030 1031 if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) { 1032 dev_err_once(kfd_device, "Ring entry too small\n"); 1033 return; 1034 } 1035 1036 for (i = 0; i < kfd->num_nodes; i++) { 1037 node = kfd->nodes[i]; 1038 spin_lock_irqsave(&node->interrupt_lock, flags); 1039 1040 if (node->interrupts_active 1041 && interrupt_is_wanted(node, ih_ring_entry, 1042 patched_ihre, &is_patched) 1043 && enqueue_ih_ring_entry(node, 1044 is_patched ? patched_ihre : ih_ring_entry)) { 1045 kfd_queue_work(node->ih_wq, &node->interrupt_work); 1046 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1047 return; 1048 } 1049 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1050 } 1051 1052 } 1053 1054 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger) 1055 { 1056 struct kfd_process *p; 1057 int r; 1058 1059 /* Because we are called from arbitrary context (workqueue) as opposed 1060 * to process context, kfd_process could attempt to exit while we are 1061 * running so the lookup function increments the process ref count. 1062 */ 1063 p = kfd_lookup_process_by_mm(mm); 1064 if (!p) 1065 return -ESRCH; 1066 1067 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 1068 r = kfd_process_evict_queues(p, trigger); 1069 1070 kfd_unref_process(p); 1071 return r; 1072 } 1073 1074 int kgd2kfd_resume_mm(struct mm_struct *mm) 1075 { 1076 struct kfd_process *p; 1077 int r; 1078 1079 /* Because we are called from arbitrary context (workqueue) as opposed 1080 * to process context, kfd_process could attempt to exit while we are 1081 * running so the lookup function increments the process ref count. 1082 */ 1083 p = kfd_lookup_process_by_mm(mm); 1084 if (!p) 1085 return -ESRCH; 1086 1087 r = kfd_process_restore_queues(p); 1088 1089 kfd_unref_process(p); 1090 return r; 1091 } 1092 1093 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 1094 * prepare for safe eviction of KFD BOs that belong to the specified 1095 * process. 1096 * 1097 * @mm: mm_struct that identifies the specified KFD process 1098 * @fence: eviction fence attached to KFD process BOs 1099 * 1100 */ 1101 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 1102 struct dma_fence *fence) 1103 { 1104 struct kfd_process *p; 1105 unsigned long active_time; 1106 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 1107 1108 if (!fence) 1109 return -EINVAL; 1110 1111 if (dma_fence_is_signaled(fence)) 1112 return 0; 1113 1114 p = kfd_lookup_process_by_mm(mm); 1115 if (!p) 1116 return -ENODEV; 1117 1118 if (fence->seqno == p->last_eviction_seqno) 1119 goto out; 1120 1121 p->last_eviction_seqno = fence->seqno; 1122 1123 /* Avoid KFD process starvation. Wait for at least 1124 * PROCESS_ACTIVE_TIME_MS before evicting the process again 1125 */ 1126 active_time = get_jiffies_64() - p->last_restore_timestamp; 1127 if (delay_jiffies > active_time) 1128 delay_jiffies -= active_time; 1129 else 1130 delay_jiffies = 0; 1131 1132 /* During process initialization eviction_work.dwork is initialized 1133 * to kfd_evict_bo_worker 1134 */ 1135 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 1136 p->lead_thread->pid, delay_jiffies); 1137 schedule_delayed_work(&p->eviction_work, delay_jiffies); 1138 out: 1139 kfd_unref_process(p); 1140 return 0; 1141 } 1142 1143 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 1144 unsigned int chunk_size) 1145 { 1146 if (WARN_ON(buf_size < chunk_size)) 1147 return -EINVAL; 1148 if (WARN_ON(buf_size == 0)) 1149 return -EINVAL; 1150 if (WARN_ON(chunk_size == 0)) 1151 return -EINVAL; 1152 1153 kfd->gtt_sa_chunk_size = chunk_size; 1154 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 1155 1156 kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks, 1157 GFP_KERNEL); 1158 if (!kfd->gtt_sa_bitmap) 1159 return -ENOMEM; 1160 1161 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 1162 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 1163 1164 mutex_init(&kfd->gtt_sa_lock); 1165 1166 return 0; 1167 } 1168 1169 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 1170 { 1171 mutex_destroy(&kfd->gtt_sa_lock); 1172 bitmap_free(kfd->gtt_sa_bitmap); 1173 } 1174 1175 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 1176 unsigned int bit_num, 1177 unsigned int chunk_size) 1178 { 1179 return start_addr + bit_num * chunk_size; 1180 } 1181 1182 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 1183 unsigned int bit_num, 1184 unsigned int chunk_size) 1185 { 1186 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 1187 } 1188 1189 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size, 1190 struct kfd_mem_obj **mem_obj) 1191 { 1192 unsigned int found, start_search, cur_size; 1193 struct kfd_dev *kfd = node->kfd; 1194 1195 if (size == 0) 1196 return -EINVAL; 1197 1198 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 1199 return -ENOMEM; 1200 1201 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 1202 if (!(*mem_obj)) 1203 return -ENOMEM; 1204 1205 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 1206 1207 start_search = 0; 1208 1209 mutex_lock(&kfd->gtt_sa_lock); 1210 1211 kfd_gtt_restart_search: 1212 /* Find the first chunk that is free */ 1213 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1214 kfd->gtt_sa_num_of_chunks, 1215 start_search); 1216 1217 pr_debug("Found = %d\n", found); 1218 1219 /* If there wasn't any free chunk, bail out */ 1220 if (found == kfd->gtt_sa_num_of_chunks) 1221 goto kfd_gtt_no_free_chunk; 1222 1223 /* Update fields of mem_obj */ 1224 (*mem_obj)->range_start = found; 1225 (*mem_obj)->range_end = found; 1226 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1227 kfd->gtt_start_gpu_addr, 1228 found, 1229 kfd->gtt_sa_chunk_size); 1230 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1231 kfd->gtt_start_cpu_ptr, 1232 found, 1233 kfd->gtt_sa_chunk_size); 1234 1235 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1236 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1237 1238 /* If we need only one chunk, mark it as allocated and get out */ 1239 if (size <= kfd->gtt_sa_chunk_size) { 1240 pr_debug("Single bit\n"); 1241 __set_bit(found, kfd->gtt_sa_bitmap); 1242 goto kfd_gtt_out; 1243 } 1244 1245 /* Otherwise, try to see if we have enough contiguous chunks */ 1246 cur_size = size - kfd->gtt_sa_chunk_size; 1247 do { 1248 (*mem_obj)->range_end = 1249 find_next_zero_bit(kfd->gtt_sa_bitmap, 1250 kfd->gtt_sa_num_of_chunks, ++found); 1251 /* 1252 * If next free chunk is not contiguous than we need to 1253 * restart our search from the last free chunk we found (which 1254 * wasn't contiguous to the previous ones 1255 */ 1256 if ((*mem_obj)->range_end != found) { 1257 start_search = found; 1258 goto kfd_gtt_restart_search; 1259 } 1260 1261 /* 1262 * If we reached end of buffer, bail out with error 1263 */ 1264 if (found == kfd->gtt_sa_num_of_chunks) 1265 goto kfd_gtt_no_free_chunk; 1266 1267 /* Check if we don't need another chunk */ 1268 if (cur_size <= kfd->gtt_sa_chunk_size) 1269 cur_size = 0; 1270 else 1271 cur_size -= kfd->gtt_sa_chunk_size; 1272 1273 } while (cur_size > 0); 1274 1275 pr_debug("range_start = %d, range_end = %d\n", 1276 (*mem_obj)->range_start, (*mem_obj)->range_end); 1277 1278 /* Mark the chunks as allocated */ 1279 bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start, 1280 (*mem_obj)->range_end - (*mem_obj)->range_start + 1); 1281 1282 kfd_gtt_out: 1283 mutex_unlock(&kfd->gtt_sa_lock); 1284 return 0; 1285 1286 kfd_gtt_no_free_chunk: 1287 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1288 mutex_unlock(&kfd->gtt_sa_lock); 1289 kfree(*mem_obj); 1290 return -ENOMEM; 1291 } 1292 1293 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj) 1294 { 1295 struct kfd_dev *kfd = node->kfd; 1296 1297 /* Act like kfree when trying to free a NULL object */ 1298 if (!mem_obj) 1299 return 0; 1300 1301 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1302 mem_obj, mem_obj->range_start, mem_obj->range_end); 1303 1304 mutex_lock(&kfd->gtt_sa_lock); 1305 1306 /* Mark the chunks as free */ 1307 bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start, 1308 mem_obj->range_end - mem_obj->range_start + 1); 1309 1310 mutex_unlock(&kfd->gtt_sa_lock); 1311 1312 kfree(mem_obj); 1313 return 0; 1314 } 1315 1316 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1317 { 1318 /* 1319 * TODO: Currently update SRAM ECC flag for first node. 1320 * This needs to be updated later when we can 1321 * identify SRAM ECC error on other nodes also. 1322 */ 1323 if (kfd) 1324 atomic_inc(&kfd->nodes[0]->sram_ecc_flag); 1325 } 1326 1327 void kfd_inc_compute_active(struct kfd_node *node) 1328 { 1329 if (atomic_inc_return(&node->kfd->compute_profile) == 1) 1330 amdgpu_amdkfd_set_compute_idle(node->adev, false); 1331 } 1332 1333 void kfd_dec_compute_active(struct kfd_node *node) 1334 { 1335 int count = atomic_dec_return(&node->kfd->compute_profile); 1336 1337 if (count == 0) 1338 amdgpu_amdkfd_set_compute_idle(node->adev, true); 1339 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1340 } 1341 1342 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 1343 { 1344 /* 1345 * TODO: For now, raise the throttling event only on first node. 1346 * This will need to change after we are able to determine 1347 * which node raised the throttling event. 1348 */ 1349 if (kfd && kfd->init_complete) 1350 kfd_smi_event_update_thermal_throttling(kfd->nodes[0], 1351 throttle_bitmask); 1352 } 1353 1354 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and 1355 * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA. 1356 * When the device has more than two engines, we reserve two for PCIe to enable 1357 * full-duplex and the rest are used as XGMI. 1358 */ 1359 unsigned int kfd_get_num_sdma_engines(struct kfd_node *node) 1360 { 1361 /* If XGMI is not supported, all SDMA engines are PCIe */ 1362 if (!node->adev->gmc.xgmi.supported) 1363 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes; 1364 1365 return min(node->adev->sdma.num_instances/(int)node->kfd->num_nodes, 2); 1366 } 1367 1368 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *node) 1369 { 1370 /* After reserved for PCIe, the rest of engines are XGMI */ 1371 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes - 1372 kfd_get_num_sdma_engines(node); 1373 } 1374 1375 int kgd2kfd_check_and_lock_kfd(void) 1376 { 1377 mutex_lock(&kfd_processes_mutex); 1378 if (!hash_empty(kfd_processes_table) || kfd_is_locked()) { 1379 mutex_unlock(&kfd_processes_mutex); 1380 return -EBUSY; 1381 } 1382 1383 ++kfd_locked; 1384 mutex_unlock(&kfd_processes_mutex); 1385 1386 return 0; 1387 } 1388 1389 void kgd2kfd_unlock_kfd(void) 1390 { 1391 mutex_lock(&kfd_processes_mutex); 1392 --kfd_locked; 1393 mutex_unlock(&kfd_processes_mutex); 1394 } 1395 1396 #if defined(CONFIG_DEBUG_FS) 1397 1398 /* This function will send a package to HIQ to hang the HWS 1399 * which will trigger a GPU reset and bring the HWS back to normal state 1400 */ 1401 int kfd_debugfs_hang_hws(struct kfd_node *dev) 1402 { 1403 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1404 pr_err("HWS is not enabled"); 1405 return -EINVAL; 1406 } 1407 1408 return dqm_debugfs_hang_hws(dev->dqm); 1409 } 1410 1411 #endif 1412