1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/bsearch.h> 24 #include <linux/pci.h> 25 #include <linux/slab.h> 26 #include "kfd_priv.h" 27 #include "kfd_device_queue_manager.h" 28 #include "kfd_pm4_headers_vi.h" 29 #include "cwsr_trap_handler.h" 30 #include "kfd_iommu.h" 31 32 #define MQD_SIZE_ALIGNED 768 33 34 /* 35 * kfd_locked is used to lock the kfd driver during suspend or reset 36 * once locked, kfd driver will stop any further GPU execution. 37 * create process (open) will return -EAGAIN. 38 */ 39 static atomic_t kfd_locked = ATOMIC_INIT(0); 40 41 #ifdef KFD_SUPPORT_IOMMU_V2 42 static const struct kfd_device_info kaveri_device_info = { 43 .asic_family = CHIP_KAVERI, 44 .max_pasid_bits = 16, 45 /* max num of queues for KV.TODO should be a dynamic value */ 46 .max_no_of_hqd = 24, 47 .doorbell_size = 4, 48 .ih_ring_entry_size = 4 * sizeof(uint32_t), 49 .event_interrupt_class = &event_interrupt_class_cik, 50 .num_of_watch_points = 4, 51 .mqd_size_aligned = MQD_SIZE_ALIGNED, 52 .supports_cwsr = false, 53 .needs_iommu_device = true, 54 .needs_pci_atomics = false, 55 .num_sdma_engines = 2, 56 .num_sdma_queues_per_engine = 2, 57 }; 58 59 static const struct kfd_device_info carrizo_device_info = { 60 .asic_family = CHIP_CARRIZO, 61 .max_pasid_bits = 16, 62 /* max num of queues for CZ.TODO should be a dynamic value */ 63 .max_no_of_hqd = 24, 64 .doorbell_size = 4, 65 .ih_ring_entry_size = 4 * sizeof(uint32_t), 66 .event_interrupt_class = &event_interrupt_class_cik, 67 .num_of_watch_points = 4, 68 .mqd_size_aligned = MQD_SIZE_ALIGNED, 69 .supports_cwsr = true, 70 .needs_iommu_device = true, 71 .needs_pci_atomics = false, 72 .num_sdma_engines = 2, 73 .num_sdma_queues_per_engine = 2, 74 }; 75 76 static const struct kfd_device_info raven_device_info = { 77 .asic_family = CHIP_RAVEN, 78 .max_pasid_bits = 16, 79 .max_no_of_hqd = 24, 80 .doorbell_size = 8, 81 .ih_ring_entry_size = 8 * sizeof(uint32_t), 82 .event_interrupt_class = &event_interrupt_class_v9, 83 .num_of_watch_points = 4, 84 .mqd_size_aligned = MQD_SIZE_ALIGNED, 85 .supports_cwsr = true, 86 .needs_iommu_device = true, 87 .needs_pci_atomics = true, 88 .num_sdma_engines = 1, 89 .num_sdma_queues_per_engine = 2, 90 }; 91 #endif 92 93 static const struct kfd_device_info hawaii_device_info = { 94 .asic_family = CHIP_HAWAII, 95 .max_pasid_bits = 16, 96 /* max num of queues for KV.TODO should be a dynamic value */ 97 .max_no_of_hqd = 24, 98 .doorbell_size = 4, 99 .ih_ring_entry_size = 4 * sizeof(uint32_t), 100 .event_interrupt_class = &event_interrupt_class_cik, 101 .num_of_watch_points = 4, 102 .mqd_size_aligned = MQD_SIZE_ALIGNED, 103 .supports_cwsr = false, 104 .needs_iommu_device = false, 105 .needs_pci_atomics = false, 106 .num_sdma_engines = 2, 107 .num_sdma_queues_per_engine = 2, 108 }; 109 110 static const struct kfd_device_info tonga_device_info = { 111 .asic_family = CHIP_TONGA, 112 .max_pasid_bits = 16, 113 .max_no_of_hqd = 24, 114 .doorbell_size = 4, 115 .ih_ring_entry_size = 4 * sizeof(uint32_t), 116 .event_interrupt_class = &event_interrupt_class_cik, 117 .num_of_watch_points = 4, 118 .mqd_size_aligned = MQD_SIZE_ALIGNED, 119 .supports_cwsr = false, 120 .needs_iommu_device = false, 121 .needs_pci_atomics = true, 122 .num_sdma_engines = 2, 123 .num_sdma_queues_per_engine = 2, 124 }; 125 126 static const struct kfd_device_info fiji_device_info = { 127 .asic_family = CHIP_FIJI, 128 .max_pasid_bits = 16, 129 .max_no_of_hqd = 24, 130 .doorbell_size = 4, 131 .ih_ring_entry_size = 4 * sizeof(uint32_t), 132 .event_interrupt_class = &event_interrupt_class_cik, 133 .num_of_watch_points = 4, 134 .mqd_size_aligned = MQD_SIZE_ALIGNED, 135 .supports_cwsr = true, 136 .needs_iommu_device = false, 137 .needs_pci_atomics = true, 138 .num_sdma_engines = 2, 139 .num_sdma_queues_per_engine = 2, 140 }; 141 142 static const struct kfd_device_info fiji_vf_device_info = { 143 .asic_family = CHIP_FIJI, 144 .max_pasid_bits = 16, 145 .max_no_of_hqd = 24, 146 .doorbell_size = 4, 147 .ih_ring_entry_size = 4 * sizeof(uint32_t), 148 .event_interrupt_class = &event_interrupt_class_cik, 149 .num_of_watch_points = 4, 150 .mqd_size_aligned = MQD_SIZE_ALIGNED, 151 .supports_cwsr = true, 152 .needs_iommu_device = false, 153 .needs_pci_atomics = false, 154 .num_sdma_engines = 2, 155 .num_sdma_queues_per_engine = 2, 156 }; 157 158 159 static const struct kfd_device_info polaris10_device_info = { 160 .asic_family = CHIP_POLARIS10, 161 .max_pasid_bits = 16, 162 .max_no_of_hqd = 24, 163 .doorbell_size = 4, 164 .ih_ring_entry_size = 4 * sizeof(uint32_t), 165 .event_interrupt_class = &event_interrupt_class_cik, 166 .num_of_watch_points = 4, 167 .mqd_size_aligned = MQD_SIZE_ALIGNED, 168 .supports_cwsr = true, 169 .needs_iommu_device = false, 170 .needs_pci_atomics = true, 171 .num_sdma_engines = 2, 172 .num_sdma_queues_per_engine = 2, 173 }; 174 175 static const struct kfd_device_info polaris10_vf_device_info = { 176 .asic_family = CHIP_POLARIS10, 177 .max_pasid_bits = 16, 178 .max_no_of_hqd = 24, 179 .doorbell_size = 4, 180 .ih_ring_entry_size = 4 * sizeof(uint32_t), 181 .event_interrupt_class = &event_interrupt_class_cik, 182 .num_of_watch_points = 4, 183 .mqd_size_aligned = MQD_SIZE_ALIGNED, 184 .supports_cwsr = true, 185 .needs_iommu_device = false, 186 .needs_pci_atomics = false, 187 .num_sdma_engines = 2, 188 .num_sdma_queues_per_engine = 2, 189 }; 190 191 static const struct kfd_device_info polaris11_device_info = { 192 .asic_family = CHIP_POLARIS11, 193 .max_pasid_bits = 16, 194 .max_no_of_hqd = 24, 195 .doorbell_size = 4, 196 .ih_ring_entry_size = 4 * sizeof(uint32_t), 197 .event_interrupt_class = &event_interrupt_class_cik, 198 .num_of_watch_points = 4, 199 .mqd_size_aligned = MQD_SIZE_ALIGNED, 200 .supports_cwsr = true, 201 .needs_iommu_device = false, 202 .needs_pci_atomics = true, 203 .num_sdma_engines = 2, 204 .num_sdma_queues_per_engine = 2, 205 }; 206 207 static const struct kfd_device_info vega10_device_info = { 208 .asic_family = CHIP_VEGA10, 209 .max_pasid_bits = 16, 210 .max_no_of_hqd = 24, 211 .doorbell_size = 8, 212 .ih_ring_entry_size = 8 * sizeof(uint32_t), 213 .event_interrupt_class = &event_interrupt_class_v9, 214 .num_of_watch_points = 4, 215 .mqd_size_aligned = MQD_SIZE_ALIGNED, 216 .supports_cwsr = true, 217 .needs_iommu_device = false, 218 .needs_pci_atomics = false, 219 .num_sdma_engines = 2, 220 .num_sdma_queues_per_engine = 2, 221 }; 222 223 static const struct kfd_device_info vega10_vf_device_info = { 224 .asic_family = CHIP_VEGA10, 225 .max_pasid_bits = 16, 226 .max_no_of_hqd = 24, 227 .doorbell_size = 8, 228 .ih_ring_entry_size = 8 * sizeof(uint32_t), 229 .event_interrupt_class = &event_interrupt_class_v9, 230 .num_of_watch_points = 4, 231 .mqd_size_aligned = MQD_SIZE_ALIGNED, 232 .supports_cwsr = true, 233 .needs_iommu_device = false, 234 .needs_pci_atomics = false, 235 .num_sdma_engines = 2, 236 .num_sdma_queues_per_engine = 2, 237 }; 238 239 static const struct kfd_device_info vega20_device_info = { 240 .asic_family = CHIP_VEGA20, 241 .max_pasid_bits = 16, 242 .max_no_of_hqd = 24, 243 .doorbell_size = 8, 244 .ih_ring_entry_size = 8 * sizeof(uint32_t), 245 .event_interrupt_class = &event_interrupt_class_v9, 246 .num_of_watch_points = 4, 247 .mqd_size_aligned = MQD_SIZE_ALIGNED, 248 .supports_cwsr = true, 249 .needs_iommu_device = false, 250 .needs_pci_atomics = false, 251 .num_sdma_engines = 2, 252 .num_sdma_queues_per_engine = 8, 253 }; 254 255 struct kfd_deviceid { 256 unsigned short did; 257 const struct kfd_device_info *device_info; 258 }; 259 260 static const struct kfd_deviceid supported_devices[] = { 261 #ifdef KFD_SUPPORT_IOMMU_V2 262 { 0x1304, &kaveri_device_info }, /* Kaveri */ 263 { 0x1305, &kaveri_device_info }, /* Kaveri */ 264 { 0x1306, &kaveri_device_info }, /* Kaveri */ 265 { 0x1307, &kaveri_device_info }, /* Kaveri */ 266 { 0x1309, &kaveri_device_info }, /* Kaveri */ 267 { 0x130A, &kaveri_device_info }, /* Kaveri */ 268 { 0x130B, &kaveri_device_info }, /* Kaveri */ 269 { 0x130C, &kaveri_device_info }, /* Kaveri */ 270 { 0x130D, &kaveri_device_info }, /* Kaveri */ 271 { 0x130E, &kaveri_device_info }, /* Kaveri */ 272 { 0x130F, &kaveri_device_info }, /* Kaveri */ 273 { 0x1310, &kaveri_device_info }, /* Kaveri */ 274 { 0x1311, &kaveri_device_info }, /* Kaveri */ 275 { 0x1312, &kaveri_device_info }, /* Kaveri */ 276 { 0x1313, &kaveri_device_info }, /* Kaveri */ 277 { 0x1315, &kaveri_device_info }, /* Kaveri */ 278 { 0x1316, &kaveri_device_info }, /* Kaveri */ 279 { 0x1317, &kaveri_device_info }, /* Kaveri */ 280 { 0x1318, &kaveri_device_info }, /* Kaveri */ 281 { 0x131B, &kaveri_device_info }, /* Kaveri */ 282 { 0x131C, &kaveri_device_info }, /* Kaveri */ 283 { 0x131D, &kaveri_device_info }, /* Kaveri */ 284 { 0x9870, &carrizo_device_info }, /* Carrizo */ 285 { 0x9874, &carrizo_device_info }, /* Carrizo */ 286 { 0x9875, &carrizo_device_info }, /* Carrizo */ 287 { 0x9876, &carrizo_device_info }, /* Carrizo */ 288 { 0x9877, &carrizo_device_info }, /* Carrizo */ 289 { 0x15DD, &raven_device_info }, /* Raven */ 290 #endif 291 { 0x67A0, &hawaii_device_info }, /* Hawaii */ 292 { 0x67A1, &hawaii_device_info }, /* Hawaii */ 293 { 0x67A2, &hawaii_device_info }, /* Hawaii */ 294 { 0x67A8, &hawaii_device_info }, /* Hawaii */ 295 { 0x67A9, &hawaii_device_info }, /* Hawaii */ 296 { 0x67AA, &hawaii_device_info }, /* Hawaii */ 297 { 0x67B0, &hawaii_device_info }, /* Hawaii */ 298 { 0x67B1, &hawaii_device_info }, /* Hawaii */ 299 { 0x67B8, &hawaii_device_info }, /* Hawaii */ 300 { 0x67B9, &hawaii_device_info }, /* Hawaii */ 301 { 0x67BA, &hawaii_device_info }, /* Hawaii */ 302 { 0x67BE, &hawaii_device_info }, /* Hawaii */ 303 { 0x6920, &tonga_device_info }, /* Tonga */ 304 { 0x6921, &tonga_device_info }, /* Tonga */ 305 { 0x6928, &tonga_device_info }, /* Tonga */ 306 { 0x6929, &tonga_device_info }, /* Tonga */ 307 { 0x692B, &tonga_device_info }, /* Tonga */ 308 { 0x6938, &tonga_device_info }, /* Tonga */ 309 { 0x6939, &tonga_device_info }, /* Tonga */ 310 { 0x7300, &fiji_device_info }, /* Fiji */ 311 { 0x730F, &fiji_vf_device_info }, /* Fiji vf*/ 312 { 0x67C0, &polaris10_device_info }, /* Polaris10 */ 313 { 0x67C1, &polaris10_device_info }, /* Polaris10 */ 314 { 0x67C2, &polaris10_device_info }, /* Polaris10 */ 315 { 0x67C4, &polaris10_device_info }, /* Polaris10 */ 316 { 0x67C7, &polaris10_device_info }, /* Polaris10 */ 317 { 0x67C8, &polaris10_device_info }, /* Polaris10 */ 318 { 0x67C9, &polaris10_device_info }, /* Polaris10 */ 319 { 0x67CA, &polaris10_device_info }, /* Polaris10 */ 320 { 0x67CC, &polaris10_device_info }, /* Polaris10 */ 321 { 0x67CF, &polaris10_device_info }, /* Polaris10 */ 322 { 0x67D0, &polaris10_vf_device_info }, /* Polaris10 vf*/ 323 { 0x67DF, &polaris10_device_info }, /* Polaris10 */ 324 { 0x67E0, &polaris11_device_info }, /* Polaris11 */ 325 { 0x67E1, &polaris11_device_info }, /* Polaris11 */ 326 { 0x67E3, &polaris11_device_info }, /* Polaris11 */ 327 { 0x67E7, &polaris11_device_info }, /* Polaris11 */ 328 { 0x67E8, &polaris11_device_info }, /* Polaris11 */ 329 { 0x67E9, &polaris11_device_info }, /* Polaris11 */ 330 { 0x67EB, &polaris11_device_info }, /* Polaris11 */ 331 { 0x67EF, &polaris11_device_info }, /* Polaris11 */ 332 { 0x67FF, &polaris11_device_info }, /* Polaris11 */ 333 { 0x6860, &vega10_device_info }, /* Vega10 */ 334 { 0x6861, &vega10_device_info }, /* Vega10 */ 335 { 0x6862, &vega10_device_info }, /* Vega10 */ 336 { 0x6863, &vega10_device_info }, /* Vega10 */ 337 { 0x6864, &vega10_device_info }, /* Vega10 */ 338 { 0x6867, &vega10_device_info }, /* Vega10 */ 339 { 0x6868, &vega10_device_info }, /* Vega10 */ 340 { 0x686C, &vega10_vf_device_info }, /* Vega10 vf*/ 341 { 0x687F, &vega10_device_info }, /* Vega10 */ 342 { 0x66a0, &vega20_device_info }, /* Vega20 */ 343 { 0x66a1, &vega20_device_info }, /* Vega20 */ 344 { 0x66a2, &vega20_device_info }, /* Vega20 */ 345 { 0x66a3, &vega20_device_info }, /* Vega20 */ 346 { 0x66a7, &vega20_device_info }, /* Vega20 */ 347 { 0x66af, &vega20_device_info } /* Vega20 */ 348 }; 349 350 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 351 unsigned int chunk_size); 352 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 353 354 static int kfd_resume(struct kfd_dev *kfd); 355 356 static const struct kfd_device_info *lookup_device_info(unsigned short did) 357 { 358 size_t i; 359 360 for (i = 0; i < ARRAY_SIZE(supported_devices); i++) { 361 if (supported_devices[i].did == did) { 362 WARN_ON(!supported_devices[i].device_info); 363 return supported_devices[i].device_info; 364 } 365 } 366 367 dev_warn(kfd_device, "DID %04x is missing in supported_devices\n", 368 did); 369 370 return NULL; 371 } 372 373 struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, 374 struct pci_dev *pdev, const struct kfd2kgd_calls *f2g) 375 { 376 struct kfd_dev *kfd; 377 int ret; 378 const struct kfd_device_info *device_info = 379 lookup_device_info(pdev->device); 380 381 if (!device_info) { 382 dev_err(kfd_device, "kgd2kfd_probe failed\n"); 383 return NULL; 384 } 385 386 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 387 if (!kfd) 388 return NULL; 389 390 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 391 * 32 and 64-bit requests are possible and must be 392 * supported. 393 */ 394 ret = pci_enable_atomic_ops_to_root(pdev, 395 PCI_EXP_DEVCAP2_ATOMIC_COMP32 | 396 PCI_EXP_DEVCAP2_ATOMIC_COMP64); 397 if (device_info->needs_pci_atomics && ret < 0) { 398 dev_info(kfd_device, 399 "skipped device %x:%x, PCI rejects atomics\n", 400 pdev->vendor, pdev->device); 401 kfree(kfd); 402 return NULL; 403 } else if (!ret) 404 kfd->pci_atomic_requested = true; 405 406 kfd->kgd = kgd; 407 kfd->device_info = device_info; 408 kfd->pdev = pdev; 409 kfd->init_complete = false; 410 kfd->kfd2kgd = f2g; 411 412 mutex_init(&kfd->doorbell_mutex); 413 memset(&kfd->doorbell_available_index, 0, 414 sizeof(kfd->doorbell_available_index)); 415 416 return kfd; 417 } 418 419 static void kfd_cwsr_init(struct kfd_dev *kfd) 420 { 421 if (cwsr_enable && kfd->device_info->supports_cwsr) { 422 if (kfd->device_info->asic_family < CHIP_VEGA10) { 423 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE); 424 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 425 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 426 } else { 427 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE); 428 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 429 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 430 } 431 432 kfd->cwsr_enabled = true; 433 } 434 } 435 436 bool kgd2kfd_device_init(struct kfd_dev *kfd, 437 const struct kgd2kfd_shared_resources *gpu_resources) 438 { 439 unsigned int size; 440 441 kfd->mec_fw_version = kfd->kfd2kgd->get_fw_version(kfd->kgd, 442 KGD_ENGINE_MEC1); 443 kfd->sdma_fw_version = kfd->kfd2kgd->get_fw_version(kfd->kgd, 444 KGD_ENGINE_SDMA1); 445 kfd->shared_resources = *gpu_resources; 446 447 kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 448 kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 449 kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd 450 - kfd->vm_info.first_vmid_kfd + 1; 451 452 /* Verify module parameters regarding mapped process number*/ 453 if ((hws_max_conc_proc < 0) 454 || (hws_max_conc_proc > kfd->vm_info.vmid_num_kfd)) { 455 dev_err(kfd_device, 456 "hws_max_conc_proc %d must be between 0 and %d, use %d instead\n", 457 hws_max_conc_proc, kfd->vm_info.vmid_num_kfd, 458 kfd->vm_info.vmid_num_kfd); 459 kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd; 460 } else 461 kfd->max_proc_per_quantum = hws_max_conc_proc; 462 463 /* calculate max size of mqds needed for queues */ 464 size = max_num_of_queues_per_device * 465 kfd->device_info->mqd_size_aligned; 466 467 /* 468 * calculate max size of runlist packet. 469 * There can be only 2 packets at once 470 */ 471 size += (KFD_MAX_NUM_OF_PROCESSES * sizeof(struct pm4_mes_map_process) + 472 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 473 + sizeof(struct pm4_mes_runlist)) * 2; 474 475 /* Add size of HIQ & DIQ */ 476 size += KFD_KERNEL_QUEUE_SIZE * 2; 477 478 /* add another 512KB for all other allocations on gart (HPD, fences) */ 479 size += 512 * 1024; 480 481 if (kfd->kfd2kgd->init_gtt_mem_allocation( 482 kfd->kgd, size, &kfd->gtt_mem, 483 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 484 false)) { 485 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 486 goto out; 487 } 488 489 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 490 491 /* Initialize GTT sa with 512 byte chunk size */ 492 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 493 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 494 goto kfd_gtt_sa_init_error; 495 } 496 497 if (kfd_doorbell_init(kfd)) { 498 dev_err(kfd_device, 499 "Error initializing doorbell aperture\n"); 500 goto kfd_doorbell_error; 501 } 502 503 if (kfd->kfd2kgd->get_hive_id) 504 kfd->hive_id = kfd->kfd2kgd->get_hive_id(kfd->kgd); 505 506 if (kfd_topology_add_device(kfd)) { 507 dev_err(kfd_device, "Error adding device to topology\n"); 508 goto kfd_topology_add_device_error; 509 } 510 511 if (kfd_interrupt_init(kfd)) { 512 dev_err(kfd_device, "Error initializing interrupts\n"); 513 goto kfd_interrupt_error; 514 } 515 516 kfd->dqm = device_queue_manager_init(kfd); 517 if (!kfd->dqm) { 518 dev_err(kfd_device, "Error initializing queue manager\n"); 519 goto device_queue_manager_error; 520 } 521 522 if (kfd_iommu_device_init(kfd)) { 523 dev_err(kfd_device, "Error initializing iommuv2\n"); 524 goto device_iommu_error; 525 } 526 527 kfd_cwsr_init(kfd); 528 529 if (kfd_resume(kfd)) 530 goto kfd_resume_error; 531 532 kfd->dbgmgr = NULL; 533 534 kfd->init_complete = true; 535 dev_info(kfd_device, "added device %x:%x\n", kfd->pdev->vendor, 536 kfd->pdev->device); 537 538 pr_debug("Starting kfd with the following scheduling policy %d\n", 539 kfd->dqm->sched_policy); 540 541 goto out; 542 543 kfd_resume_error: 544 device_iommu_error: 545 device_queue_manager_uninit(kfd->dqm); 546 device_queue_manager_error: 547 kfd_interrupt_exit(kfd); 548 kfd_interrupt_error: 549 kfd_topology_remove_device(kfd); 550 kfd_topology_add_device_error: 551 kfd_doorbell_fini(kfd); 552 kfd_doorbell_error: 553 kfd_gtt_sa_fini(kfd); 554 kfd_gtt_sa_init_error: 555 kfd->kfd2kgd->free_gtt_mem(kfd->kgd, kfd->gtt_mem); 556 dev_err(kfd_device, 557 "device %x:%x NOT added due to errors\n", 558 kfd->pdev->vendor, kfd->pdev->device); 559 out: 560 return kfd->init_complete; 561 } 562 563 void kgd2kfd_device_exit(struct kfd_dev *kfd) 564 { 565 if (kfd->init_complete) { 566 kgd2kfd_suspend(kfd); 567 device_queue_manager_uninit(kfd->dqm); 568 kfd_interrupt_exit(kfd); 569 kfd_topology_remove_device(kfd); 570 kfd_doorbell_fini(kfd); 571 kfd_gtt_sa_fini(kfd); 572 kfd->kfd2kgd->free_gtt_mem(kfd->kgd, kfd->gtt_mem); 573 } 574 575 kfree(kfd); 576 } 577 578 int kgd2kfd_pre_reset(struct kfd_dev *kfd) 579 { 580 if (!kfd->init_complete) 581 return 0; 582 kgd2kfd_suspend(kfd); 583 584 /* hold dqm->lock to prevent further execution*/ 585 dqm_lock(kfd->dqm); 586 587 kfd_signal_reset_event(kfd); 588 return 0; 589 } 590 591 /* 592 * Fix me. KFD won't be able to resume existing process for now. 593 * We will keep all existing process in a evicted state and 594 * wait the process to be terminated. 595 */ 596 597 int kgd2kfd_post_reset(struct kfd_dev *kfd) 598 { 599 int ret, count; 600 601 if (!kfd->init_complete) 602 return 0; 603 604 dqm_unlock(kfd->dqm); 605 606 ret = kfd_resume(kfd); 607 if (ret) 608 return ret; 609 count = atomic_dec_return(&kfd_locked); 610 WARN_ONCE(count != 0, "KFD reset ref. error"); 611 return 0; 612 } 613 614 bool kfd_is_locked(void) 615 { 616 return (atomic_read(&kfd_locked) > 0); 617 } 618 619 void kgd2kfd_suspend(struct kfd_dev *kfd) 620 { 621 if (!kfd->init_complete) 622 return; 623 624 /* For first KFD device suspend all the KFD processes */ 625 if (atomic_inc_return(&kfd_locked) == 1) 626 kfd_suspend_all_processes(); 627 628 kfd->dqm->ops.stop(kfd->dqm); 629 630 kfd_iommu_suspend(kfd); 631 } 632 633 int kgd2kfd_resume(struct kfd_dev *kfd) 634 { 635 int ret, count; 636 637 if (!kfd->init_complete) 638 return 0; 639 640 ret = kfd_resume(kfd); 641 if (ret) 642 return ret; 643 644 count = atomic_dec_return(&kfd_locked); 645 WARN_ONCE(count < 0, "KFD suspend / resume ref. error"); 646 if (count == 0) 647 ret = kfd_resume_all_processes(); 648 649 return ret; 650 } 651 652 static int kfd_resume(struct kfd_dev *kfd) 653 { 654 int err = 0; 655 656 err = kfd_iommu_resume(kfd); 657 if (err) { 658 dev_err(kfd_device, 659 "Failed to resume IOMMU for device %x:%x\n", 660 kfd->pdev->vendor, kfd->pdev->device); 661 return err; 662 } 663 664 err = kfd->dqm->ops.start(kfd->dqm); 665 if (err) { 666 dev_err(kfd_device, 667 "Error starting queue manager for device %x:%x\n", 668 kfd->pdev->vendor, kfd->pdev->device); 669 goto dqm_start_error; 670 } 671 672 return err; 673 674 dqm_start_error: 675 kfd_iommu_suspend(kfd); 676 return err; 677 } 678 679 /* This is called directly from KGD at ISR. */ 680 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 681 { 682 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE]; 683 bool is_patched = false; 684 685 if (!kfd->init_complete) 686 return; 687 688 if (kfd->device_info->ih_ring_entry_size > sizeof(patched_ihre)) { 689 dev_err_once(kfd_device, "Ring entry too small\n"); 690 return; 691 } 692 693 spin_lock(&kfd->interrupt_lock); 694 695 if (kfd->interrupts_active 696 && interrupt_is_wanted(kfd, ih_ring_entry, 697 patched_ihre, &is_patched) 698 && enqueue_ih_ring_entry(kfd, 699 is_patched ? patched_ihre : ih_ring_entry)) 700 queue_work(kfd->ih_wq, &kfd->interrupt_work); 701 702 spin_unlock(&kfd->interrupt_lock); 703 } 704 705 int kgd2kfd_quiesce_mm(struct mm_struct *mm) 706 { 707 struct kfd_process *p; 708 int r; 709 710 /* Because we are called from arbitrary context (workqueue) as opposed 711 * to process context, kfd_process could attempt to exit while we are 712 * running so the lookup function increments the process ref count. 713 */ 714 p = kfd_lookup_process_by_mm(mm); 715 if (!p) 716 return -ESRCH; 717 718 r = kfd_process_evict_queues(p); 719 720 kfd_unref_process(p); 721 return r; 722 } 723 724 int kgd2kfd_resume_mm(struct mm_struct *mm) 725 { 726 struct kfd_process *p; 727 int r; 728 729 /* Because we are called from arbitrary context (workqueue) as opposed 730 * to process context, kfd_process could attempt to exit while we are 731 * running so the lookup function increments the process ref count. 732 */ 733 p = kfd_lookup_process_by_mm(mm); 734 if (!p) 735 return -ESRCH; 736 737 r = kfd_process_restore_queues(p); 738 739 kfd_unref_process(p); 740 return r; 741 } 742 743 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 744 * prepare for safe eviction of KFD BOs that belong to the specified 745 * process. 746 * 747 * @mm: mm_struct that identifies the specified KFD process 748 * @fence: eviction fence attached to KFD process BOs 749 * 750 */ 751 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 752 struct dma_fence *fence) 753 { 754 struct kfd_process *p; 755 unsigned long active_time; 756 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 757 758 if (!fence) 759 return -EINVAL; 760 761 if (dma_fence_is_signaled(fence)) 762 return 0; 763 764 p = kfd_lookup_process_by_mm(mm); 765 if (!p) 766 return -ENODEV; 767 768 if (fence->seqno == p->last_eviction_seqno) 769 goto out; 770 771 p->last_eviction_seqno = fence->seqno; 772 773 /* Avoid KFD process starvation. Wait for at least 774 * PROCESS_ACTIVE_TIME_MS before evicting the process again 775 */ 776 active_time = get_jiffies_64() - p->last_restore_timestamp; 777 if (delay_jiffies > active_time) 778 delay_jiffies -= active_time; 779 else 780 delay_jiffies = 0; 781 782 /* During process initialization eviction_work.dwork is initialized 783 * to kfd_evict_bo_worker 784 */ 785 schedule_delayed_work(&p->eviction_work, delay_jiffies); 786 out: 787 kfd_unref_process(p); 788 return 0; 789 } 790 791 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 792 unsigned int chunk_size) 793 { 794 unsigned int num_of_longs; 795 796 if (WARN_ON(buf_size < chunk_size)) 797 return -EINVAL; 798 if (WARN_ON(buf_size == 0)) 799 return -EINVAL; 800 if (WARN_ON(chunk_size == 0)) 801 return -EINVAL; 802 803 kfd->gtt_sa_chunk_size = chunk_size; 804 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 805 806 num_of_longs = (kfd->gtt_sa_num_of_chunks + BITS_PER_LONG - 1) / 807 BITS_PER_LONG; 808 809 kfd->gtt_sa_bitmap = kcalloc(num_of_longs, sizeof(long), GFP_KERNEL); 810 811 if (!kfd->gtt_sa_bitmap) 812 return -ENOMEM; 813 814 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 815 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 816 817 mutex_init(&kfd->gtt_sa_lock); 818 819 return 0; 820 821 } 822 823 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 824 { 825 mutex_destroy(&kfd->gtt_sa_lock); 826 kfree(kfd->gtt_sa_bitmap); 827 } 828 829 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 830 unsigned int bit_num, 831 unsigned int chunk_size) 832 { 833 return start_addr + bit_num * chunk_size; 834 } 835 836 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 837 unsigned int bit_num, 838 unsigned int chunk_size) 839 { 840 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 841 } 842 843 int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size, 844 struct kfd_mem_obj **mem_obj) 845 { 846 unsigned int found, start_search, cur_size; 847 848 if (size == 0) 849 return -EINVAL; 850 851 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 852 return -ENOMEM; 853 854 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 855 if (!(*mem_obj)) 856 return -ENOMEM; 857 858 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 859 860 start_search = 0; 861 862 mutex_lock(&kfd->gtt_sa_lock); 863 864 kfd_gtt_restart_search: 865 /* Find the first chunk that is free */ 866 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 867 kfd->gtt_sa_num_of_chunks, 868 start_search); 869 870 pr_debug("Found = %d\n", found); 871 872 /* If there wasn't any free chunk, bail out */ 873 if (found == kfd->gtt_sa_num_of_chunks) 874 goto kfd_gtt_no_free_chunk; 875 876 /* Update fields of mem_obj */ 877 (*mem_obj)->range_start = found; 878 (*mem_obj)->range_end = found; 879 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 880 kfd->gtt_start_gpu_addr, 881 found, 882 kfd->gtt_sa_chunk_size); 883 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 884 kfd->gtt_start_cpu_ptr, 885 found, 886 kfd->gtt_sa_chunk_size); 887 888 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 889 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 890 891 /* If we need only one chunk, mark it as allocated and get out */ 892 if (size <= kfd->gtt_sa_chunk_size) { 893 pr_debug("Single bit\n"); 894 set_bit(found, kfd->gtt_sa_bitmap); 895 goto kfd_gtt_out; 896 } 897 898 /* Otherwise, try to see if we have enough contiguous chunks */ 899 cur_size = size - kfd->gtt_sa_chunk_size; 900 do { 901 (*mem_obj)->range_end = 902 find_next_zero_bit(kfd->gtt_sa_bitmap, 903 kfd->gtt_sa_num_of_chunks, ++found); 904 /* 905 * If next free chunk is not contiguous than we need to 906 * restart our search from the last free chunk we found (which 907 * wasn't contiguous to the previous ones 908 */ 909 if ((*mem_obj)->range_end != found) { 910 start_search = found; 911 goto kfd_gtt_restart_search; 912 } 913 914 /* 915 * If we reached end of buffer, bail out with error 916 */ 917 if (found == kfd->gtt_sa_num_of_chunks) 918 goto kfd_gtt_no_free_chunk; 919 920 /* Check if we don't need another chunk */ 921 if (cur_size <= kfd->gtt_sa_chunk_size) 922 cur_size = 0; 923 else 924 cur_size -= kfd->gtt_sa_chunk_size; 925 926 } while (cur_size > 0); 927 928 pr_debug("range_start = %d, range_end = %d\n", 929 (*mem_obj)->range_start, (*mem_obj)->range_end); 930 931 /* Mark the chunks as allocated */ 932 for (found = (*mem_obj)->range_start; 933 found <= (*mem_obj)->range_end; 934 found++) 935 set_bit(found, kfd->gtt_sa_bitmap); 936 937 kfd_gtt_out: 938 mutex_unlock(&kfd->gtt_sa_lock); 939 return 0; 940 941 kfd_gtt_no_free_chunk: 942 pr_debug("Allocation failed with mem_obj = %p\n", mem_obj); 943 mutex_unlock(&kfd->gtt_sa_lock); 944 kfree(mem_obj); 945 return -ENOMEM; 946 } 947 948 int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj) 949 { 950 unsigned int bit; 951 952 /* Act like kfree when trying to free a NULL object */ 953 if (!mem_obj) 954 return 0; 955 956 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 957 mem_obj, mem_obj->range_start, mem_obj->range_end); 958 959 mutex_lock(&kfd->gtt_sa_lock); 960 961 /* Mark the chunks as free */ 962 for (bit = mem_obj->range_start; 963 bit <= mem_obj->range_end; 964 bit++) 965 clear_bit(bit, kfd->gtt_sa_bitmap); 966 967 mutex_unlock(&kfd->gtt_sa_lock); 968 969 kfree(mem_obj); 970 return 0; 971 } 972 973 #if defined(CONFIG_DEBUG_FS) 974 975 /* This function will send a package to HIQ to hang the HWS 976 * which will trigger a GPU reset and bring the HWS back to normal state 977 */ 978 int kfd_debugfs_hang_hws(struct kfd_dev *dev) 979 { 980 int r = 0; 981 982 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 983 pr_err("HWS is not enabled"); 984 return -EINVAL; 985 } 986 987 r = pm_debugfs_hang_hws(&dev->dqm->packets); 988 if (!r) 989 r = dqm_debugfs_execute_queues(dev->dqm); 990 991 return r; 992 } 993 994 #endif 995