1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */ 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef KFD_CRAT_H_INCLUDED 25 #define KFD_CRAT_H_INCLUDED 26 27 #include <linux/types.h> 28 29 #pragma pack(1) 30 31 /* 32 * 4CC signature value for the CRAT ACPI table 33 */ 34 35 #define CRAT_SIGNATURE "CRAT" 36 37 /* 38 * Component Resource Association Table (CRAT) 39 */ 40 41 #define CRAT_OEMID_LENGTH 6 42 #define CRAT_OEMTABLEID_LENGTH 8 43 #define CRAT_RESERVED_LENGTH 6 44 45 #define CRAT_OEMID_64BIT_MASK ((1ULL << (CRAT_OEMID_LENGTH * 8)) - 1) 46 47 /* Compute Unit flags */ 48 #define COMPUTE_UNIT_CPU (1 << 0) /* Create Virtual CRAT for CPU */ 49 #define COMPUTE_UNIT_GPU (1 << 1) /* Create Virtual CRAT for GPU */ 50 51 struct crat_header { 52 uint32_t signature; 53 uint32_t length; 54 uint8_t revision; 55 uint8_t checksum; 56 uint8_t oem_id[CRAT_OEMID_LENGTH]; 57 uint8_t oem_table_id[CRAT_OEMTABLEID_LENGTH]; 58 uint32_t oem_revision; 59 uint32_t creator_id; 60 uint32_t creator_revision; 61 uint32_t total_entries; 62 uint16_t num_domains; 63 uint8_t reserved[CRAT_RESERVED_LENGTH]; 64 }; 65 66 /* 67 * The header structure is immediately followed by total_entries of the 68 * data definitions 69 */ 70 71 /* 72 * The currently defined subtype entries in the CRAT 73 */ 74 #define CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY 0 75 #define CRAT_SUBTYPE_MEMORY_AFFINITY 1 76 #define CRAT_SUBTYPE_CACHE_AFFINITY 2 77 #define CRAT_SUBTYPE_TLB_AFFINITY 3 78 #define CRAT_SUBTYPE_CCOMPUTE_AFFINITY 4 79 #define CRAT_SUBTYPE_IOLINK_AFFINITY 5 80 #define CRAT_SUBTYPE_MAX 6 81 82 #define CRAT_SIBLINGMAP_SIZE 32 83 84 /* 85 * ComputeUnit Affinity structure and definitions 86 */ 87 #define CRAT_CU_FLAGS_ENABLED 0x00000001 88 #define CRAT_CU_FLAGS_HOT_PLUGGABLE 0x00000002 89 #define CRAT_CU_FLAGS_CPU_PRESENT 0x00000004 90 #define CRAT_CU_FLAGS_GPU_PRESENT 0x00000008 91 #define CRAT_CU_FLAGS_IOMMU_PRESENT 0x00000010 92 #define CRAT_CU_FLAGS_RESERVED 0xffffffe0 93 94 #define CRAT_COMPUTEUNIT_RESERVED_LENGTH 4 95 96 struct crat_subtype_computeunit { 97 uint8_t type; 98 uint8_t length; 99 uint16_t reserved; 100 uint32_t flags; 101 uint32_t proximity_domain; 102 uint32_t processor_id_low; 103 uint16_t num_cpu_cores; 104 uint16_t num_simd_cores; 105 uint16_t max_waves_simd; 106 uint16_t io_count; 107 uint16_t hsa_capability; 108 uint16_t lds_size_in_kb; 109 uint8_t wave_front_size; 110 uint8_t num_banks; 111 uint16_t micro_engine_id; 112 uint8_t array_count; 113 uint8_t num_cu_per_array; 114 uint8_t num_simd_per_cu; 115 uint8_t max_slots_scatch_cu; 116 uint8_t reserved2[CRAT_COMPUTEUNIT_RESERVED_LENGTH]; 117 }; 118 119 /* 120 * HSA Memory Affinity structure and definitions 121 */ 122 #define CRAT_MEM_FLAGS_ENABLED 0x00000001 123 #define CRAT_MEM_FLAGS_HOT_PLUGGABLE 0x00000002 124 #define CRAT_MEM_FLAGS_NON_VOLATILE 0x00000004 125 #define CRAT_MEM_FLAGS_RESERVED 0xfffffff8 126 127 #define CRAT_MEMORY_RESERVED_LENGTH 8 128 129 struct crat_subtype_memory { 130 uint8_t type; 131 uint8_t length; 132 uint16_t reserved; 133 uint32_t flags; 134 uint32_t proximity_domain; 135 uint32_t base_addr_low; 136 uint32_t base_addr_high; 137 uint32_t length_low; 138 uint32_t length_high; 139 uint32_t width; 140 uint8_t visibility_type; /* for virtual (dGPU) CRAT */ 141 uint8_t reserved2[CRAT_MEMORY_RESERVED_LENGTH - 1]; 142 }; 143 144 /* 145 * HSA Cache Affinity structure and definitions 146 */ 147 #define CRAT_CACHE_FLAGS_ENABLED 0x00000001 148 #define CRAT_CACHE_FLAGS_DATA_CACHE 0x00000002 149 #define CRAT_CACHE_FLAGS_INST_CACHE 0x00000004 150 #define CRAT_CACHE_FLAGS_CPU_CACHE 0x00000008 151 #define CRAT_CACHE_FLAGS_SIMD_CACHE 0x00000010 152 #define CRAT_CACHE_FLAGS_RESERVED 0xffffffe0 153 154 #define CRAT_CACHE_RESERVED_LENGTH 8 155 156 struct crat_subtype_cache { 157 uint8_t type; 158 uint8_t length; 159 uint16_t reserved; 160 uint32_t flags; 161 uint32_t processor_id_low; 162 uint8_t sibling_map[CRAT_SIBLINGMAP_SIZE]; 163 uint32_t cache_size; 164 uint8_t cache_level; 165 uint8_t lines_per_tag; 166 uint16_t cache_line_size; 167 uint8_t associativity; 168 uint8_t cache_properties; 169 uint16_t cache_latency; 170 uint8_t reserved2[CRAT_CACHE_RESERVED_LENGTH]; 171 }; 172 173 /* 174 * HSA TLB Affinity structure and definitions 175 */ 176 #define CRAT_TLB_FLAGS_ENABLED 0x00000001 177 #define CRAT_TLB_FLAGS_DATA_TLB 0x00000002 178 #define CRAT_TLB_FLAGS_INST_TLB 0x00000004 179 #define CRAT_TLB_FLAGS_CPU_TLB 0x00000008 180 #define CRAT_TLB_FLAGS_SIMD_TLB 0x00000010 181 #define CRAT_TLB_FLAGS_RESERVED 0xffffffe0 182 183 #define CRAT_TLB_RESERVED_LENGTH 4 184 185 struct crat_subtype_tlb { 186 uint8_t type; 187 uint8_t length; 188 uint16_t reserved; 189 uint32_t flags; 190 uint32_t processor_id_low; 191 uint8_t sibling_map[CRAT_SIBLINGMAP_SIZE]; 192 uint32_t tlb_level; 193 uint8_t data_tlb_associativity_2mb; 194 uint8_t data_tlb_size_2mb; 195 uint8_t instruction_tlb_associativity_2mb; 196 uint8_t instruction_tlb_size_2mb; 197 uint8_t data_tlb_associativity_4k; 198 uint8_t data_tlb_size_4k; 199 uint8_t instruction_tlb_associativity_4k; 200 uint8_t instruction_tlb_size_4k; 201 uint8_t data_tlb_associativity_1gb; 202 uint8_t data_tlb_size_1gb; 203 uint8_t instruction_tlb_associativity_1gb; 204 uint8_t instruction_tlb_size_1gb; 205 uint8_t reserved2[CRAT_TLB_RESERVED_LENGTH]; 206 }; 207 208 /* 209 * HSA CCompute/APU Affinity structure and definitions 210 */ 211 #define CRAT_CCOMPUTE_FLAGS_ENABLED 0x00000001 212 #define CRAT_CCOMPUTE_FLAGS_RESERVED 0xfffffffe 213 214 #define CRAT_CCOMPUTE_RESERVED_LENGTH 16 215 216 struct crat_subtype_ccompute { 217 uint8_t type; 218 uint8_t length; 219 uint16_t reserved; 220 uint32_t flags; 221 uint32_t processor_id_low; 222 uint8_t sibling_map[CRAT_SIBLINGMAP_SIZE]; 223 uint32_t apu_size; 224 uint8_t reserved2[CRAT_CCOMPUTE_RESERVED_LENGTH]; 225 }; 226 227 /* 228 * HSA IO Link Affinity structure and definitions 229 */ 230 #define CRAT_IOLINK_FLAGS_ENABLED (1 << 0) 231 #define CRAT_IOLINK_FLAGS_NON_COHERENT (1 << 1) 232 #define CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT (1 << 2) 233 #define CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT (1 << 3) 234 #define CRAT_IOLINK_FLAGS_NO_PEER_TO_PEER_DMA (1 << 4) 235 #define CRAT_IOLINK_FLAGS_BI_DIRECTIONAL (1 << 31) 236 #define CRAT_IOLINK_FLAGS_RESERVED_MASK 0x7fffffe0 237 238 /* 239 * IO interface types 240 */ 241 #define CRAT_IOLINK_TYPE_UNDEFINED 0 242 #define CRAT_IOLINK_TYPE_HYPERTRANSPORT 1 243 #define CRAT_IOLINK_TYPE_PCIEXPRESS 2 244 #define CRAT_IOLINK_TYPE_AMBA 3 245 #define CRAT_IOLINK_TYPE_MIPI 4 246 #define CRAT_IOLINK_TYPE_QPI_1_1 5 247 #define CRAT_IOLINK_TYPE_RESERVED1 6 248 #define CRAT_IOLINK_TYPE_RESERVED2 7 249 #define CRAT_IOLINK_TYPE_RAPID_IO 8 250 #define CRAT_IOLINK_TYPE_INFINIBAND 9 251 #define CRAT_IOLINK_TYPE_RESERVED3 10 252 #define CRAT_IOLINK_TYPE_XGMI 11 253 #define CRAT_IOLINK_TYPE_XGOP 12 254 #define CRAT_IOLINK_TYPE_GZ 13 255 #define CRAT_IOLINK_TYPE_ETHERNET_RDMA 14 256 #define CRAT_IOLINK_TYPE_RDMA_OTHER 15 257 #define CRAT_IOLINK_TYPE_OTHER 16 258 #define CRAT_IOLINK_TYPE_MAX 255 259 260 #define CRAT_IOLINK_RESERVED_LENGTH 24 261 262 struct crat_subtype_iolink { 263 uint8_t type; 264 uint8_t length; 265 uint16_t reserved; 266 uint32_t flags; 267 uint32_t proximity_domain_from; 268 uint32_t proximity_domain_to; 269 uint8_t io_interface_type; 270 uint8_t version_major; 271 uint16_t version_minor; 272 uint32_t minimum_latency; 273 uint32_t maximum_latency; 274 uint32_t minimum_bandwidth_mbs; 275 uint32_t maximum_bandwidth_mbs; 276 uint32_t recommended_transfer_size; 277 uint8_t reserved2[CRAT_IOLINK_RESERVED_LENGTH - 1]; 278 uint8_t num_hops_xgmi; 279 }; 280 281 /* 282 * HSA generic sub-type header 283 */ 284 285 #define CRAT_SUBTYPE_FLAGS_ENABLED 0x00000001 286 287 struct crat_subtype_generic { 288 uint8_t type; 289 uint8_t length; 290 uint16_t reserved; 291 uint32_t flags; 292 }; 293 294 #pragma pack() 295 296 struct kfd_dev; 297 298 int kfd_create_crat_image_acpi(void **crat_image, size_t *size); 299 void kfd_destroy_crat_image(void *crat_image); 300 int kfd_parse_crat_table(void *crat_image, struct list_head *device_list, 301 uint32_t proximity_domain); 302 int kfd_create_crat_image_virtual(void **crat_image, size_t *size, 303 int flags, struct kfd_dev *kdev, 304 uint32_t proximity_domain); 305 306 #endif /* KFD_CRAT_H_INCLUDED */ 307