1 /* 2 * Copyright 2015-2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/pci.h> 24 #include <linux/acpi.h> 25 #include "kfd_crat.h" 26 #include "kfd_priv.h" 27 #include "kfd_topology.h" 28 #include "kfd_iommu.h" 29 #include "amdgpu.h" 30 #include "amdgpu_amdkfd.h" 31 32 /* GPU Processor ID base for dGPUs for which VCRAT needs to be created. 33 * GPU processor ID are expressed with Bit[31]=1. 34 * The base is set to 0x8000_0000 + 0x1000 to avoid collision with GPU IDs 35 * used in the CRAT. 36 */ 37 static uint32_t gpu_processor_id_low = 0x80001000; 38 39 /* Return the next available gpu_processor_id and increment it for next GPU 40 * @total_cu_count - Total CUs present in the GPU including ones 41 * masked off 42 */ 43 static inline unsigned int get_and_inc_gpu_processor_id( 44 unsigned int total_cu_count) 45 { 46 int current_id = gpu_processor_id_low; 47 48 gpu_processor_id_low += total_cu_count; 49 return current_id; 50 } 51 52 /* Static table to describe GPU Cache information */ 53 struct kfd_gpu_cache_info { 54 uint32_t cache_size; 55 uint32_t cache_level; 56 uint32_t flags; 57 /* Indicates how many Compute Units share this cache 58 * within a SA. Value = 1 indicates the cache is not shared 59 */ 60 uint32_t num_cu_shared; 61 }; 62 63 static struct kfd_gpu_cache_info kaveri_cache_info[] = { 64 { 65 /* TCP L1 Cache per CU */ 66 .cache_size = 16, 67 .cache_level = 1, 68 .flags = (CRAT_CACHE_FLAGS_ENABLED | 69 CRAT_CACHE_FLAGS_DATA_CACHE | 70 CRAT_CACHE_FLAGS_SIMD_CACHE), 71 .num_cu_shared = 1, 72 }, 73 { 74 /* Scalar L1 Instruction Cache (in SQC module) per bank */ 75 .cache_size = 16, 76 .cache_level = 1, 77 .flags = (CRAT_CACHE_FLAGS_ENABLED | 78 CRAT_CACHE_FLAGS_INST_CACHE | 79 CRAT_CACHE_FLAGS_SIMD_CACHE), 80 .num_cu_shared = 2, 81 }, 82 { 83 /* Scalar L1 Data Cache (in SQC module) per bank */ 84 .cache_size = 8, 85 .cache_level = 1, 86 .flags = (CRAT_CACHE_FLAGS_ENABLED | 87 CRAT_CACHE_FLAGS_DATA_CACHE | 88 CRAT_CACHE_FLAGS_SIMD_CACHE), 89 .num_cu_shared = 2, 90 }, 91 92 /* TODO: Add L2 Cache information */ 93 }; 94 95 96 static struct kfd_gpu_cache_info carrizo_cache_info[] = { 97 { 98 /* TCP L1 Cache per CU */ 99 .cache_size = 16, 100 .cache_level = 1, 101 .flags = (CRAT_CACHE_FLAGS_ENABLED | 102 CRAT_CACHE_FLAGS_DATA_CACHE | 103 CRAT_CACHE_FLAGS_SIMD_CACHE), 104 .num_cu_shared = 1, 105 }, 106 { 107 /* Scalar L1 Instruction Cache (in SQC module) per bank */ 108 .cache_size = 8, 109 .cache_level = 1, 110 .flags = (CRAT_CACHE_FLAGS_ENABLED | 111 CRAT_CACHE_FLAGS_INST_CACHE | 112 CRAT_CACHE_FLAGS_SIMD_CACHE), 113 .num_cu_shared = 4, 114 }, 115 { 116 /* Scalar L1 Data Cache (in SQC module) per bank. */ 117 .cache_size = 4, 118 .cache_level = 1, 119 .flags = (CRAT_CACHE_FLAGS_ENABLED | 120 CRAT_CACHE_FLAGS_DATA_CACHE | 121 CRAT_CACHE_FLAGS_SIMD_CACHE), 122 .num_cu_shared = 4, 123 }, 124 125 /* TODO: Add L2 Cache information */ 126 }; 127 128 #define hawaii_cache_info kaveri_cache_info 129 #define tonga_cache_info carrizo_cache_info 130 #define fiji_cache_info carrizo_cache_info 131 #define polaris10_cache_info carrizo_cache_info 132 #define polaris11_cache_info carrizo_cache_info 133 #define polaris12_cache_info carrizo_cache_info 134 #define vegam_cache_info carrizo_cache_info 135 136 /* NOTE: L1 cache information has been updated and L2/L3 137 * cache information has been added for Vega10 and 138 * newer ASICs. The unit for cache_size is KiB. 139 * In future, check & update cache details 140 * for every new ASIC is required. 141 */ 142 143 static struct kfd_gpu_cache_info vega10_cache_info[] = { 144 { 145 /* TCP L1 Cache per CU */ 146 .cache_size = 16, 147 .cache_level = 1, 148 .flags = (CRAT_CACHE_FLAGS_ENABLED | 149 CRAT_CACHE_FLAGS_DATA_CACHE | 150 CRAT_CACHE_FLAGS_SIMD_CACHE), 151 .num_cu_shared = 1, 152 }, 153 { 154 /* Scalar L1 Instruction Cache per SQC */ 155 .cache_size = 32, 156 .cache_level = 1, 157 .flags = (CRAT_CACHE_FLAGS_ENABLED | 158 CRAT_CACHE_FLAGS_INST_CACHE | 159 CRAT_CACHE_FLAGS_SIMD_CACHE), 160 .num_cu_shared = 3, 161 }, 162 { 163 /* Scalar L1 Data Cache per SQC */ 164 .cache_size = 16, 165 .cache_level = 1, 166 .flags = (CRAT_CACHE_FLAGS_ENABLED | 167 CRAT_CACHE_FLAGS_DATA_CACHE | 168 CRAT_CACHE_FLAGS_SIMD_CACHE), 169 .num_cu_shared = 3, 170 }, 171 { 172 /* L2 Data Cache per GPU (Total Tex Cache) */ 173 .cache_size = 4096, 174 .cache_level = 2, 175 .flags = (CRAT_CACHE_FLAGS_ENABLED | 176 CRAT_CACHE_FLAGS_DATA_CACHE | 177 CRAT_CACHE_FLAGS_SIMD_CACHE), 178 .num_cu_shared = 16, 179 }, 180 }; 181 182 static struct kfd_gpu_cache_info raven_cache_info[] = { 183 { 184 /* TCP L1 Cache per CU */ 185 .cache_size = 16, 186 .cache_level = 1, 187 .flags = (CRAT_CACHE_FLAGS_ENABLED | 188 CRAT_CACHE_FLAGS_DATA_CACHE | 189 CRAT_CACHE_FLAGS_SIMD_CACHE), 190 .num_cu_shared = 1, 191 }, 192 { 193 /* Scalar L1 Instruction Cache per SQC */ 194 .cache_size = 32, 195 .cache_level = 1, 196 .flags = (CRAT_CACHE_FLAGS_ENABLED | 197 CRAT_CACHE_FLAGS_INST_CACHE | 198 CRAT_CACHE_FLAGS_SIMD_CACHE), 199 .num_cu_shared = 3, 200 }, 201 { 202 /* Scalar L1 Data Cache per SQC */ 203 .cache_size = 16, 204 .cache_level = 1, 205 .flags = (CRAT_CACHE_FLAGS_ENABLED | 206 CRAT_CACHE_FLAGS_DATA_CACHE | 207 CRAT_CACHE_FLAGS_SIMD_CACHE), 208 .num_cu_shared = 3, 209 }, 210 { 211 /* L2 Data Cache per GPU (Total Tex Cache) */ 212 .cache_size = 1024, 213 .cache_level = 2, 214 .flags = (CRAT_CACHE_FLAGS_ENABLED | 215 CRAT_CACHE_FLAGS_DATA_CACHE | 216 CRAT_CACHE_FLAGS_SIMD_CACHE), 217 .num_cu_shared = 11, 218 }, 219 }; 220 221 static struct kfd_gpu_cache_info renoir_cache_info[] = { 222 { 223 /* TCP L1 Cache per CU */ 224 .cache_size = 16, 225 .cache_level = 1, 226 .flags = (CRAT_CACHE_FLAGS_ENABLED | 227 CRAT_CACHE_FLAGS_DATA_CACHE | 228 CRAT_CACHE_FLAGS_SIMD_CACHE), 229 .num_cu_shared = 1, 230 }, 231 { 232 /* Scalar L1 Instruction Cache per SQC */ 233 .cache_size = 32, 234 .cache_level = 1, 235 .flags = (CRAT_CACHE_FLAGS_ENABLED | 236 CRAT_CACHE_FLAGS_INST_CACHE | 237 CRAT_CACHE_FLAGS_SIMD_CACHE), 238 .num_cu_shared = 3, 239 }, 240 { 241 /* Scalar L1 Data Cache per SQC */ 242 .cache_size = 16, 243 .cache_level = 1, 244 .flags = (CRAT_CACHE_FLAGS_ENABLED | 245 CRAT_CACHE_FLAGS_DATA_CACHE | 246 CRAT_CACHE_FLAGS_SIMD_CACHE), 247 .num_cu_shared = 3, 248 }, 249 { 250 /* L2 Data Cache per GPU (Total Tex Cache) */ 251 .cache_size = 1024, 252 .cache_level = 2, 253 .flags = (CRAT_CACHE_FLAGS_ENABLED | 254 CRAT_CACHE_FLAGS_DATA_CACHE | 255 CRAT_CACHE_FLAGS_SIMD_CACHE), 256 .num_cu_shared = 8, 257 }, 258 }; 259 260 static struct kfd_gpu_cache_info vega12_cache_info[] = { 261 { 262 /* TCP L1 Cache per CU */ 263 .cache_size = 16, 264 .cache_level = 1, 265 .flags = (CRAT_CACHE_FLAGS_ENABLED | 266 CRAT_CACHE_FLAGS_DATA_CACHE | 267 CRAT_CACHE_FLAGS_SIMD_CACHE), 268 .num_cu_shared = 1, 269 }, 270 { 271 /* Scalar L1 Instruction Cache per SQC */ 272 .cache_size = 32, 273 .cache_level = 1, 274 .flags = (CRAT_CACHE_FLAGS_ENABLED | 275 CRAT_CACHE_FLAGS_INST_CACHE | 276 CRAT_CACHE_FLAGS_SIMD_CACHE), 277 .num_cu_shared = 3, 278 }, 279 { 280 /* Scalar L1 Data Cache per SQC */ 281 .cache_size = 16, 282 .cache_level = 1, 283 .flags = (CRAT_CACHE_FLAGS_ENABLED | 284 CRAT_CACHE_FLAGS_DATA_CACHE | 285 CRAT_CACHE_FLAGS_SIMD_CACHE), 286 .num_cu_shared = 3, 287 }, 288 { 289 /* L2 Data Cache per GPU (Total Tex Cache) */ 290 .cache_size = 2048, 291 .cache_level = 2, 292 .flags = (CRAT_CACHE_FLAGS_ENABLED | 293 CRAT_CACHE_FLAGS_DATA_CACHE | 294 CRAT_CACHE_FLAGS_SIMD_CACHE), 295 .num_cu_shared = 5, 296 }, 297 }; 298 299 static struct kfd_gpu_cache_info vega20_cache_info[] = { 300 { 301 /* TCP L1 Cache per CU */ 302 .cache_size = 16, 303 .cache_level = 1, 304 .flags = (CRAT_CACHE_FLAGS_ENABLED | 305 CRAT_CACHE_FLAGS_DATA_CACHE | 306 CRAT_CACHE_FLAGS_SIMD_CACHE), 307 .num_cu_shared = 1, 308 }, 309 { 310 /* Scalar L1 Instruction Cache per SQC */ 311 .cache_size = 32, 312 .cache_level = 1, 313 .flags = (CRAT_CACHE_FLAGS_ENABLED | 314 CRAT_CACHE_FLAGS_INST_CACHE | 315 CRAT_CACHE_FLAGS_SIMD_CACHE), 316 .num_cu_shared = 3, 317 }, 318 { 319 /* Scalar L1 Data Cache per SQC */ 320 .cache_size = 16, 321 .cache_level = 1, 322 .flags = (CRAT_CACHE_FLAGS_ENABLED | 323 CRAT_CACHE_FLAGS_DATA_CACHE | 324 CRAT_CACHE_FLAGS_SIMD_CACHE), 325 .num_cu_shared = 3, 326 }, 327 { 328 /* L2 Data Cache per GPU (Total Tex Cache) */ 329 .cache_size = 8192, 330 .cache_level = 2, 331 .flags = (CRAT_CACHE_FLAGS_ENABLED | 332 CRAT_CACHE_FLAGS_DATA_CACHE | 333 CRAT_CACHE_FLAGS_SIMD_CACHE), 334 .num_cu_shared = 16, 335 }, 336 }; 337 338 static struct kfd_gpu_cache_info aldebaran_cache_info[] = { 339 { 340 /* TCP L1 Cache per CU */ 341 .cache_size = 16, 342 .cache_level = 1, 343 .flags = (CRAT_CACHE_FLAGS_ENABLED | 344 CRAT_CACHE_FLAGS_DATA_CACHE | 345 CRAT_CACHE_FLAGS_SIMD_CACHE), 346 .num_cu_shared = 1, 347 }, 348 { 349 /* Scalar L1 Instruction Cache per SQC */ 350 .cache_size = 32, 351 .cache_level = 1, 352 .flags = (CRAT_CACHE_FLAGS_ENABLED | 353 CRAT_CACHE_FLAGS_INST_CACHE | 354 CRAT_CACHE_FLAGS_SIMD_CACHE), 355 .num_cu_shared = 2, 356 }, 357 { 358 /* Scalar L1 Data Cache per SQC */ 359 .cache_size = 16, 360 .cache_level = 1, 361 .flags = (CRAT_CACHE_FLAGS_ENABLED | 362 CRAT_CACHE_FLAGS_DATA_CACHE | 363 CRAT_CACHE_FLAGS_SIMD_CACHE), 364 .num_cu_shared = 2, 365 }, 366 { 367 /* L2 Data Cache per GPU (Total Tex Cache) */ 368 .cache_size = 8192, 369 .cache_level = 2, 370 .flags = (CRAT_CACHE_FLAGS_ENABLED | 371 CRAT_CACHE_FLAGS_DATA_CACHE | 372 CRAT_CACHE_FLAGS_SIMD_CACHE), 373 .num_cu_shared = 14, 374 }, 375 }; 376 377 static struct kfd_gpu_cache_info navi10_cache_info[] = { 378 { 379 /* TCP L1 Cache per CU */ 380 .cache_size = 16, 381 .cache_level = 1, 382 .flags = (CRAT_CACHE_FLAGS_ENABLED | 383 CRAT_CACHE_FLAGS_DATA_CACHE | 384 CRAT_CACHE_FLAGS_SIMD_CACHE), 385 .num_cu_shared = 1, 386 }, 387 { 388 /* Scalar L1 Instruction Cache per SQC */ 389 .cache_size = 32, 390 .cache_level = 1, 391 .flags = (CRAT_CACHE_FLAGS_ENABLED | 392 CRAT_CACHE_FLAGS_INST_CACHE | 393 CRAT_CACHE_FLAGS_SIMD_CACHE), 394 .num_cu_shared = 2, 395 }, 396 { 397 /* Scalar L1 Data Cache per SQC */ 398 .cache_size = 16, 399 .cache_level = 1, 400 .flags = (CRAT_CACHE_FLAGS_ENABLED | 401 CRAT_CACHE_FLAGS_DATA_CACHE | 402 CRAT_CACHE_FLAGS_SIMD_CACHE), 403 .num_cu_shared = 2, 404 }, 405 { 406 /* GL1 Data Cache per SA */ 407 .cache_size = 128, 408 .cache_level = 1, 409 .flags = (CRAT_CACHE_FLAGS_ENABLED | 410 CRAT_CACHE_FLAGS_DATA_CACHE | 411 CRAT_CACHE_FLAGS_SIMD_CACHE), 412 .num_cu_shared = 10, 413 }, 414 { 415 /* L2 Data Cache per GPU (Total Tex Cache) */ 416 .cache_size = 4096, 417 .cache_level = 2, 418 .flags = (CRAT_CACHE_FLAGS_ENABLED | 419 CRAT_CACHE_FLAGS_DATA_CACHE | 420 CRAT_CACHE_FLAGS_SIMD_CACHE), 421 .num_cu_shared = 10, 422 }, 423 }; 424 425 static struct kfd_gpu_cache_info vangogh_cache_info[] = { 426 { 427 /* TCP L1 Cache per CU */ 428 .cache_size = 16, 429 .cache_level = 1, 430 .flags = (CRAT_CACHE_FLAGS_ENABLED | 431 CRAT_CACHE_FLAGS_DATA_CACHE | 432 CRAT_CACHE_FLAGS_SIMD_CACHE), 433 .num_cu_shared = 1, 434 }, 435 { 436 /* Scalar L1 Instruction Cache per SQC */ 437 .cache_size = 32, 438 .cache_level = 1, 439 .flags = (CRAT_CACHE_FLAGS_ENABLED | 440 CRAT_CACHE_FLAGS_INST_CACHE | 441 CRAT_CACHE_FLAGS_SIMD_CACHE), 442 .num_cu_shared = 2, 443 }, 444 { 445 /* Scalar L1 Data Cache per SQC */ 446 .cache_size = 16, 447 .cache_level = 1, 448 .flags = (CRAT_CACHE_FLAGS_ENABLED | 449 CRAT_CACHE_FLAGS_DATA_CACHE | 450 CRAT_CACHE_FLAGS_SIMD_CACHE), 451 .num_cu_shared = 2, 452 }, 453 { 454 /* GL1 Data Cache per SA */ 455 .cache_size = 128, 456 .cache_level = 1, 457 .flags = (CRAT_CACHE_FLAGS_ENABLED | 458 CRAT_CACHE_FLAGS_DATA_CACHE | 459 CRAT_CACHE_FLAGS_SIMD_CACHE), 460 .num_cu_shared = 8, 461 }, 462 { 463 /* L2 Data Cache per GPU (Total Tex Cache) */ 464 .cache_size = 1024, 465 .cache_level = 2, 466 .flags = (CRAT_CACHE_FLAGS_ENABLED | 467 CRAT_CACHE_FLAGS_DATA_CACHE | 468 CRAT_CACHE_FLAGS_SIMD_CACHE), 469 .num_cu_shared = 8, 470 }, 471 }; 472 473 static struct kfd_gpu_cache_info navi14_cache_info[] = { 474 { 475 /* TCP L1 Cache per CU */ 476 .cache_size = 16, 477 .cache_level = 1, 478 .flags = (CRAT_CACHE_FLAGS_ENABLED | 479 CRAT_CACHE_FLAGS_DATA_CACHE | 480 CRAT_CACHE_FLAGS_SIMD_CACHE), 481 .num_cu_shared = 1, 482 }, 483 { 484 /* Scalar L1 Instruction Cache per SQC */ 485 .cache_size = 32, 486 .cache_level = 1, 487 .flags = (CRAT_CACHE_FLAGS_ENABLED | 488 CRAT_CACHE_FLAGS_INST_CACHE | 489 CRAT_CACHE_FLAGS_SIMD_CACHE), 490 .num_cu_shared = 2, 491 }, 492 { 493 /* Scalar L1 Data Cache per SQC */ 494 .cache_size = 16, 495 .cache_level = 1, 496 .flags = (CRAT_CACHE_FLAGS_ENABLED | 497 CRAT_CACHE_FLAGS_DATA_CACHE | 498 CRAT_CACHE_FLAGS_SIMD_CACHE), 499 .num_cu_shared = 2, 500 }, 501 { 502 /* GL1 Data Cache per SA */ 503 .cache_size = 128, 504 .cache_level = 1, 505 .flags = (CRAT_CACHE_FLAGS_ENABLED | 506 CRAT_CACHE_FLAGS_DATA_CACHE | 507 CRAT_CACHE_FLAGS_SIMD_CACHE), 508 .num_cu_shared = 12, 509 }, 510 { 511 /* L2 Data Cache per GPU (Total Tex Cache) */ 512 .cache_size = 2048, 513 .cache_level = 2, 514 .flags = (CRAT_CACHE_FLAGS_ENABLED | 515 CRAT_CACHE_FLAGS_DATA_CACHE | 516 CRAT_CACHE_FLAGS_SIMD_CACHE), 517 .num_cu_shared = 12, 518 }, 519 }; 520 521 static struct kfd_gpu_cache_info sienna_cichlid_cache_info[] = { 522 { 523 /* TCP L1 Cache per CU */ 524 .cache_size = 16, 525 .cache_level = 1, 526 .flags = (CRAT_CACHE_FLAGS_ENABLED | 527 CRAT_CACHE_FLAGS_DATA_CACHE | 528 CRAT_CACHE_FLAGS_SIMD_CACHE), 529 .num_cu_shared = 1, 530 }, 531 { 532 /* Scalar L1 Instruction Cache per SQC */ 533 .cache_size = 32, 534 .cache_level = 1, 535 .flags = (CRAT_CACHE_FLAGS_ENABLED | 536 CRAT_CACHE_FLAGS_INST_CACHE | 537 CRAT_CACHE_FLAGS_SIMD_CACHE), 538 .num_cu_shared = 2, 539 }, 540 { 541 /* Scalar L1 Data Cache per SQC */ 542 .cache_size = 16, 543 .cache_level = 1, 544 .flags = (CRAT_CACHE_FLAGS_ENABLED | 545 CRAT_CACHE_FLAGS_DATA_CACHE | 546 CRAT_CACHE_FLAGS_SIMD_CACHE), 547 .num_cu_shared = 2, 548 }, 549 { 550 /* GL1 Data Cache per SA */ 551 .cache_size = 128, 552 .cache_level = 1, 553 .flags = (CRAT_CACHE_FLAGS_ENABLED | 554 CRAT_CACHE_FLAGS_DATA_CACHE | 555 CRAT_CACHE_FLAGS_SIMD_CACHE), 556 .num_cu_shared = 10, 557 }, 558 { 559 /* L2 Data Cache per GPU (Total Tex Cache) */ 560 .cache_size = 4096, 561 .cache_level = 2, 562 .flags = (CRAT_CACHE_FLAGS_ENABLED | 563 CRAT_CACHE_FLAGS_DATA_CACHE | 564 CRAT_CACHE_FLAGS_SIMD_CACHE), 565 .num_cu_shared = 10, 566 }, 567 { 568 /* L3 Data Cache per GPU */ 569 .cache_size = 128*1024, 570 .cache_level = 3, 571 .flags = (CRAT_CACHE_FLAGS_ENABLED | 572 CRAT_CACHE_FLAGS_DATA_CACHE | 573 CRAT_CACHE_FLAGS_SIMD_CACHE), 574 .num_cu_shared = 10, 575 }, 576 }; 577 578 static struct kfd_gpu_cache_info navy_flounder_cache_info[] = { 579 { 580 /* TCP L1 Cache per CU */ 581 .cache_size = 16, 582 .cache_level = 1, 583 .flags = (CRAT_CACHE_FLAGS_ENABLED | 584 CRAT_CACHE_FLAGS_DATA_CACHE | 585 CRAT_CACHE_FLAGS_SIMD_CACHE), 586 .num_cu_shared = 1, 587 }, 588 { 589 /* Scalar L1 Instruction Cache per SQC */ 590 .cache_size = 32, 591 .cache_level = 1, 592 .flags = (CRAT_CACHE_FLAGS_ENABLED | 593 CRAT_CACHE_FLAGS_INST_CACHE | 594 CRAT_CACHE_FLAGS_SIMD_CACHE), 595 .num_cu_shared = 2, 596 }, 597 { 598 /* Scalar L1 Data Cache per SQC */ 599 .cache_size = 16, 600 .cache_level = 1, 601 .flags = (CRAT_CACHE_FLAGS_ENABLED | 602 CRAT_CACHE_FLAGS_DATA_CACHE | 603 CRAT_CACHE_FLAGS_SIMD_CACHE), 604 .num_cu_shared = 2, 605 }, 606 { 607 /* GL1 Data Cache per SA */ 608 .cache_size = 128, 609 .cache_level = 1, 610 .flags = (CRAT_CACHE_FLAGS_ENABLED | 611 CRAT_CACHE_FLAGS_DATA_CACHE | 612 CRAT_CACHE_FLAGS_SIMD_CACHE), 613 .num_cu_shared = 10, 614 }, 615 { 616 /* L2 Data Cache per GPU (Total Tex Cache) */ 617 .cache_size = 3072, 618 .cache_level = 2, 619 .flags = (CRAT_CACHE_FLAGS_ENABLED | 620 CRAT_CACHE_FLAGS_DATA_CACHE | 621 CRAT_CACHE_FLAGS_SIMD_CACHE), 622 .num_cu_shared = 10, 623 }, 624 { 625 /* L3 Data Cache per GPU */ 626 .cache_size = 96*1024, 627 .cache_level = 3, 628 .flags = (CRAT_CACHE_FLAGS_ENABLED | 629 CRAT_CACHE_FLAGS_DATA_CACHE | 630 CRAT_CACHE_FLAGS_SIMD_CACHE), 631 .num_cu_shared = 10, 632 }, 633 }; 634 635 static struct kfd_gpu_cache_info dimgrey_cavefish_cache_info[] = { 636 { 637 /* TCP L1 Cache per CU */ 638 .cache_size = 16, 639 .cache_level = 1, 640 .flags = (CRAT_CACHE_FLAGS_ENABLED | 641 CRAT_CACHE_FLAGS_DATA_CACHE | 642 CRAT_CACHE_FLAGS_SIMD_CACHE), 643 .num_cu_shared = 1, 644 }, 645 { 646 /* Scalar L1 Instruction Cache per SQC */ 647 .cache_size = 32, 648 .cache_level = 1, 649 .flags = (CRAT_CACHE_FLAGS_ENABLED | 650 CRAT_CACHE_FLAGS_INST_CACHE | 651 CRAT_CACHE_FLAGS_SIMD_CACHE), 652 .num_cu_shared = 2, 653 }, 654 { 655 /* Scalar L1 Data Cache per SQC */ 656 .cache_size = 16, 657 .cache_level = 1, 658 .flags = (CRAT_CACHE_FLAGS_ENABLED | 659 CRAT_CACHE_FLAGS_DATA_CACHE | 660 CRAT_CACHE_FLAGS_SIMD_CACHE), 661 .num_cu_shared = 2, 662 }, 663 { 664 /* GL1 Data Cache per SA */ 665 .cache_size = 128, 666 .cache_level = 1, 667 .flags = (CRAT_CACHE_FLAGS_ENABLED | 668 CRAT_CACHE_FLAGS_DATA_CACHE | 669 CRAT_CACHE_FLAGS_SIMD_CACHE), 670 .num_cu_shared = 8, 671 }, 672 { 673 /* L2 Data Cache per GPU (Total Tex Cache) */ 674 .cache_size = 2048, 675 .cache_level = 2, 676 .flags = (CRAT_CACHE_FLAGS_ENABLED | 677 CRAT_CACHE_FLAGS_DATA_CACHE | 678 CRAT_CACHE_FLAGS_SIMD_CACHE), 679 .num_cu_shared = 8, 680 }, 681 { 682 /* L3 Data Cache per GPU */ 683 .cache_size = 32*1024, 684 .cache_level = 3, 685 .flags = (CRAT_CACHE_FLAGS_ENABLED | 686 CRAT_CACHE_FLAGS_DATA_CACHE | 687 CRAT_CACHE_FLAGS_SIMD_CACHE), 688 .num_cu_shared = 8, 689 }, 690 }; 691 692 static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev, 693 struct crat_subtype_computeunit *cu) 694 { 695 dev->node_props.cpu_cores_count = cu->num_cpu_cores; 696 dev->node_props.cpu_core_id_base = cu->processor_id_low; 697 if (cu->hsa_capability & CRAT_CU_FLAGS_IOMMU_PRESENT) 698 dev->node_props.capability |= HSA_CAP_ATS_PRESENT; 699 700 pr_debug("CU CPU: cores=%d id_base=%d\n", cu->num_cpu_cores, 701 cu->processor_id_low); 702 } 703 704 static void kfd_populated_cu_info_gpu(struct kfd_topology_device *dev, 705 struct crat_subtype_computeunit *cu) 706 { 707 dev->node_props.simd_id_base = cu->processor_id_low; 708 dev->node_props.simd_count = cu->num_simd_cores; 709 dev->node_props.lds_size_in_kb = cu->lds_size_in_kb; 710 dev->node_props.max_waves_per_simd = cu->max_waves_simd; 711 dev->node_props.wave_front_size = cu->wave_front_size; 712 dev->node_props.array_count = cu->array_count; 713 dev->node_props.cu_per_simd_array = cu->num_cu_per_array; 714 dev->node_props.simd_per_cu = cu->num_simd_per_cu; 715 dev->node_props.max_slots_scratch_cu = cu->max_slots_scatch_cu; 716 if (cu->hsa_capability & CRAT_CU_FLAGS_HOT_PLUGGABLE) 717 dev->node_props.capability |= HSA_CAP_HOT_PLUGGABLE; 718 pr_debug("CU GPU: id_base=%d\n", cu->processor_id_low); 719 } 720 721 /* kfd_parse_subtype_cu - parse compute unit subtypes and attach it to correct 722 * topology device present in the device_list 723 */ 724 static int kfd_parse_subtype_cu(struct crat_subtype_computeunit *cu, 725 struct list_head *device_list) 726 { 727 struct kfd_topology_device *dev; 728 729 pr_debug("Found CU entry in CRAT table with proximity_domain=%d caps=%x\n", 730 cu->proximity_domain, cu->hsa_capability); 731 list_for_each_entry(dev, device_list, list) { 732 if (cu->proximity_domain == dev->proximity_domain) { 733 if (cu->flags & CRAT_CU_FLAGS_CPU_PRESENT) 734 kfd_populated_cu_info_cpu(dev, cu); 735 736 if (cu->flags & CRAT_CU_FLAGS_GPU_PRESENT) 737 kfd_populated_cu_info_gpu(dev, cu); 738 break; 739 } 740 } 741 742 return 0; 743 } 744 745 static struct kfd_mem_properties * 746 find_subtype_mem(uint32_t heap_type, uint32_t flags, uint32_t width, 747 struct kfd_topology_device *dev) 748 { 749 struct kfd_mem_properties *props; 750 751 list_for_each_entry(props, &dev->mem_props, list) { 752 if (props->heap_type == heap_type 753 && props->flags == flags 754 && props->width == width) 755 return props; 756 } 757 758 return NULL; 759 } 760 /* kfd_parse_subtype_mem - parse memory subtypes and attach it to correct 761 * topology device present in the device_list 762 */ 763 static int kfd_parse_subtype_mem(struct crat_subtype_memory *mem, 764 struct list_head *device_list) 765 { 766 struct kfd_mem_properties *props; 767 struct kfd_topology_device *dev; 768 uint32_t heap_type; 769 uint64_t size_in_bytes; 770 uint32_t flags = 0; 771 uint32_t width; 772 773 pr_debug("Found memory entry in CRAT table with proximity_domain=%d\n", 774 mem->proximity_domain); 775 list_for_each_entry(dev, device_list, list) { 776 if (mem->proximity_domain == dev->proximity_domain) { 777 /* We're on GPU node */ 778 if (dev->node_props.cpu_cores_count == 0) { 779 /* APU */ 780 if (mem->visibility_type == 0) 781 heap_type = 782 HSA_MEM_HEAP_TYPE_FB_PRIVATE; 783 /* dGPU */ 784 else 785 heap_type = mem->visibility_type; 786 } else 787 heap_type = HSA_MEM_HEAP_TYPE_SYSTEM; 788 789 if (mem->flags & CRAT_MEM_FLAGS_HOT_PLUGGABLE) 790 flags |= HSA_MEM_FLAGS_HOT_PLUGGABLE; 791 if (mem->flags & CRAT_MEM_FLAGS_NON_VOLATILE) 792 flags |= HSA_MEM_FLAGS_NON_VOLATILE; 793 794 size_in_bytes = 795 ((uint64_t)mem->length_high << 32) + 796 mem->length_low; 797 width = mem->width; 798 799 /* Multiple banks of the same type are aggregated into 800 * one. User mode doesn't care about multiple physical 801 * memory segments. It's managed as a single virtual 802 * heap for user mode. 803 */ 804 props = find_subtype_mem(heap_type, flags, width, dev); 805 if (props) { 806 props->size_in_bytes += size_in_bytes; 807 break; 808 } 809 810 props = kfd_alloc_struct(props); 811 if (!props) 812 return -ENOMEM; 813 814 props->heap_type = heap_type; 815 props->flags = flags; 816 props->size_in_bytes = size_in_bytes; 817 props->width = width; 818 819 dev->node_props.mem_banks_count++; 820 list_add_tail(&props->list, &dev->mem_props); 821 822 break; 823 } 824 } 825 826 return 0; 827 } 828 829 /* kfd_parse_subtype_cache - parse cache subtypes and attach it to correct 830 * topology device present in the device_list 831 */ 832 static int kfd_parse_subtype_cache(struct crat_subtype_cache *cache, 833 struct list_head *device_list) 834 { 835 struct kfd_cache_properties *props; 836 struct kfd_topology_device *dev; 837 uint32_t id; 838 uint32_t total_num_of_cu; 839 840 id = cache->processor_id_low; 841 842 pr_debug("Found cache entry in CRAT table with processor_id=%d\n", id); 843 list_for_each_entry(dev, device_list, list) { 844 total_num_of_cu = (dev->node_props.array_count * 845 dev->node_props.cu_per_simd_array); 846 847 /* Cache infomration in CRAT doesn't have proximity_domain 848 * information as it is associated with a CPU core or GPU 849 * Compute Unit. So map the cache using CPU core Id or SIMD 850 * (GPU) ID. 851 * TODO: This works because currently we can safely assume that 852 * Compute Units are parsed before caches are parsed. In 853 * future, remove this dependency 854 */ 855 if ((id >= dev->node_props.cpu_core_id_base && 856 id <= dev->node_props.cpu_core_id_base + 857 dev->node_props.cpu_cores_count) || 858 (id >= dev->node_props.simd_id_base && 859 id < dev->node_props.simd_id_base + 860 total_num_of_cu)) { 861 props = kfd_alloc_struct(props); 862 if (!props) 863 return -ENOMEM; 864 865 props->processor_id_low = id; 866 props->cache_level = cache->cache_level; 867 props->cache_size = cache->cache_size; 868 props->cacheline_size = cache->cache_line_size; 869 props->cachelines_per_tag = cache->lines_per_tag; 870 props->cache_assoc = cache->associativity; 871 props->cache_latency = cache->cache_latency; 872 memcpy(props->sibling_map, cache->sibling_map, 873 sizeof(props->sibling_map)); 874 875 if (cache->flags & CRAT_CACHE_FLAGS_DATA_CACHE) 876 props->cache_type |= HSA_CACHE_TYPE_DATA; 877 if (cache->flags & CRAT_CACHE_FLAGS_INST_CACHE) 878 props->cache_type |= HSA_CACHE_TYPE_INSTRUCTION; 879 if (cache->flags & CRAT_CACHE_FLAGS_CPU_CACHE) 880 props->cache_type |= HSA_CACHE_TYPE_CPU; 881 if (cache->flags & CRAT_CACHE_FLAGS_SIMD_CACHE) 882 props->cache_type |= HSA_CACHE_TYPE_HSACU; 883 884 dev->cache_count++; 885 dev->node_props.caches_count++; 886 list_add_tail(&props->list, &dev->cache_props); 887 888 break; 889 } 890 } 891 892 return 0; 893 } 894 895 /* kfd_parse_subtype_iolink - parse iolink subtypes and attach it to correct 896 * topology device present in the device_list 897 */ 898 static int kfd_parse_subtype_iolink(struct crat_subtype_iolink *iolink, 899 struct list_head *device_list) 900 { 901 struct kfd_iolink_properties *props = NULL, *props2; 902 struct kfd_topology_device *dev, *to_dev; 903 uint32_t id_from; 904 uint32_t id_to; 905 906 id_from = iolink->proximity_domain_from; 907 id_to = iolink->proximity_domain_to; 908 909 pr_debug("Found IO link entry in CRAT table with id_from=%d, id_to %d\n", 910 id_from, id_to); 911 list_for_each_entry(dev, device_list, list) { 912 if (id_from == dev->proximity_domain) { 913 props = kfd_alloc_struct(props); 914 if (!props) 915 return -ENOMEM; 916 917 props->node_from = id_from; 918 props->node_to = id_to; 919 props->ver_maj = iolink->version_major; 920 props->ver_min = iolink->version_minor; 921 props->iolink_type = iolink->io_interface_type; 922 923 if (props->iolink_type == CRAT_IOLINK_TYPE_PCIEXPRESS) 924 props->weight = 20; 925 else if (props->iolink_type == CRAT_IOLINK_TYPE_XGMI) 926 props->weight = 15 * iolink->num_hops_xgmi; 927 else 928 props->weight = node_distance(id_from, id_to); 929 930 props->min_latency = iolink->minimum_latency; 931 props->max_latency = iolink->maximum_latency; 932 props->min_bandwidth = iolink->minimum_bandwidth_mbs; 933 props->max_bandwidth = iolink->maximum_bandwidth_mbs; 934 props->rec_transfer_size = 935 iolink->recommended_transfer_size; 936 937 dev->io_link_count++; 938 dev->node_props.io_links_count++; 939 list_add_tail(&props->list, &dev->io_link_props); 940 break; 941 } 942 } 943 944 /* CPU topology is created before GPUs are detected, so CPU->GPU 945 * links are not built at that time. If a PCIe type is discovered, it 946 * means a GPU is detected and we are adding GPU->CPU to the topology. 947 * At this time, also add the corresponded CPU->GPU link if GPU 948 * is large bar. 949 * For xGMI, we only added the link with one direction in the crat 950 * table, add corresponded reversed direction link now. 951 */ 952 if (props && (iolink->flags & CRAT_IOLINK_FLAGS_BI_DIRECTIONAL)) { 953 to_dev = kfd_topology_device_by_proximity_domain(id_to); 954 if (!to_dev) 955 return -ENODEV; 956 /* same everything but the other direction */ 957 props2 = kmemdup(props, sizeof(*props2), GFP_KERNEL); 958 props2->node_from = id_to; 959 props2->node_to = id_from; 960 props2->kobj = NULL; 961 to_dev->io_link_count++; 962 to_dev->node_props.io_links_count++; 963 list_add_tail(&props2->list, &to_dev->io_link_props); 964 } 965 966 return 0; 967 } 968 969 /* kfd_parse_subtype - parse subtypes and attach it to correct topology device 970 * present in the device_list 971 * @sub_type_hdr - subtype section of crat_image 972 * @device_list - list of topology devices present in this crat_image 973 */ 974 static int kfd_parse_subtype(struct crat_subtype_generic *sub_type_hdr, 975 struct list_head *device_list) 976 { 977 struct crat_subtype_computeunit *cu; 978 struct crat_subtype_memory *mem; 979 struct crat_subtype_cache *cache; 980 struct crat_subtype_iolink *iolink; 981 int ret = 0; 982 983 switch (sub_type_hdr->type) { 984 case CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY: 985 cu = (struct crat_subtype_computeunit *)sub_type_hdr; 986 ret = kfd_parse_subtype_cu(cu, device_list); 987 break; 988 case CRAT_SUBTYPE_MEMORY_AFFINITY: 989 mem = (struct crat_subtype_memory *)sub_type_hdr; 990 ret = kfd_parse_subtype_mem(mem, device_list); 991 break; 992 case CRAT_SUBTYPE_CACHE_AFFINITY: 993 cache = (struct crat_subtype_cache *)sub_type_hdr; 994 ret = kfd_parse_subtype_cache(cache, device_list); 995 break; 996 case CRAT_SUBTYPE_TLB_AFFINITY: 997 /* 998 * For now, nothing to do here 999 */ 1000 pr_debug("Found TLB entry in CRAT table (not processing)\n"); 1001 break; 1002 case CRAT_SUBTYPE_CCOMPUTE_AFFINITY: 1003 /* 1004 * For now, nothing to do here 1005 */ 1006 pr_debug("Found CCOMPUTE entry in CRAT table (not processing)\n"); 1007 break; 1008 case CRAT_SUBTYPE_IOLINK_AFFINITY: 1009 iolink = (struct crat_subtype_iolink *)sub_type_hdr; 1010 ret = kfd_parse_subtype_iolink(iolink, device_list); 1011 break; 1012 default: 1013 pr_warn("Unknown subtype %d in CRAT\n", 1014 sub_type_hdr->type); 1015 } 1016 1017 return ret; 1018 } 1019 1020 /* kfd_parse_crat_table - parse CRAT table. For each node present in CRAT 1021 * create a kfd_topology_device and add in to device_list. Also parse 1022 * CRAT subtypes and attach it to appropriate kfd_topology_device 1023 * @crat_image - input image containing CRAT 1024 * @device_list - [OUT] list of kfd_topology_device generated after 1025 * parsing crat_image 1026 * @proximity_domain - Proximity domain of the first device in the table 1027 * 1028 * Return - 0 if successful else -ve value 1029 */ 1030 int kfd_parse_crat_table(void *crat_image, struct list_head *device_list, 1031 uint32_t proximity_domain) 1032 { 1033 struct kfd_topology_device *top_dev = NULL; 1034 struct crat_subtype_generic *sub_type_hdr; 1035 uint16_t node_id; 1036 int ret = 0; 1037 struct crat_header *crat_table = (struct crat_header *)crat_image; 1038 uint16_t num_nodes; 1039 uint32_t image_len; 1040 1041 if (!crat_image) 1042 return -EINVAL; 1043 1044 if (!list_empty(device_list)) { 1045 pr_warn("Error device list should be empty\n"); 1046 return -EINVAL; 1047 } 1048 1049 num_nodes = crat_table->num_domains; 1050 image_len = crat_table->length; 1051 1052 pr_debug("Parsing CRAT table with %d nodes\n", num_nodes); 1053 1054 for (node_id = 0; node_id < num_nodes; node_id++) { 1055 top_dev = kfd_create_topology_device(device_list); 1056 if (!top_dev) 1057 break; 1058 top_dev->proximity_domain = proximity_domain++; 1059 } 1060 1061 if (!top_dev) { 1062 ret = -ENOMEM; 1063 goto err; 1064 } 1065 1066 memcpy(top_dev->oem_id, crat_table->oem_id, CRAT_OEMID_LENGTH); 1067 memcpy(top_dev->oem_table_id, crat_table->oem_table_id, 1068 CRAT_OEMTABLEID_LENGTH); 1069 top_dev->oem_revision = crat_table->oem_revision; 1070 1071 sub_type_hdr = (struct crat_subtype_generic *)(crat_table+1); 1072 while ((char *)sub_type_hdr + sizeof(struct crat_subtype_generic) < 1073 ((char *)crat_image) + image_len) { 1074 if (sub_type_hdr->flags & CRAT_SUBTYPE_FLAGS_ENABLED) { 1075 ret = kfd_parse_subtype(sub_type_hdr, device_list); 1076 if (ret) 1077 break; 1078 } 1079 1080 sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr + 1081 sub_type_hdr->length); 1082 } 1083 1084 err: 1085 if (ret) 1086 kfd_release_topology_device_list(device_list); 1087 1088 return ret; 1089 } 1090 1091 /* Helper function. See kfd_fill_gpu_cache_info for parameter description */ 1092 static int fill_in_l1_pcache(struct crat_subtype_cache *pcache, 1093 struct kfd_gpu_cache_info *pcache_info, 1094 struct kfd_cu_info *cu_info, 1095 int mem_available, 1096 int cu_bitmask, 1097 int cache_type, unsigned int cu_processor_id, 1098 int cu_block) 1099 { 1100 unsigned int cu_sibling_map_mask; 1101 int first_active_cu; 1102 1103 /* First check if enough memory is available */ 1104 if (sizeof(struct crat_subtype_cache) > mem_available) 1105 return -ENOMEM; 1106 1107 cu_sibling_map_mask = cu_bitmask; 1108 cu_sibling_map_mask >>= cu_block; 1109 cu_sibling_map_mask &= 1110 ((1 << pcache_info[cache_type].num_cu_shared) - 1); 1111 first_active_cu = ffs(cu_sibling_map_mask); 1112 1113 /* CU could be inactive. In case of shared cache find the first active 1114 * CU. and incase of non-shared cache check if the CU is inactive. If 1115 * inactive active skip it 1116 */ 1117 if (first_active_cu) { 1118 memset(pcache, 0, sizeof(struct crat_subtype_cache)); 1119 pcache->type = CRAT_SUBTYPE_CACHE_AFFINITY; 1120 pcache->length = sizeof(struct crat_subtype_cache); 1121 pcache->flags = pcache_info[cache_type].flags; 1122 pcache->processor_id_low = cu_processor_id 1123 + (first_active_cu - 1); 1124 pcache->cache_level = pcache_info[cache_type].cache_level; 1125 pcache->cache_size = pcache_info[cache_type].cache_size; 1126 1127 /* Sibling map is w.r.t processor_id_low, so shift out 1128 * inactive CU 1129 */ 1130 cu_sibling_map_mask = 1131 cu_sibling_map_mask >> (first_active_cu - 1); 1132 1133 pcache->sibling_map[0] = (uint8_t)(cu_sibling_map_mask & 0xFF); 1134 pcache->sibling_map[1] = 1135 (uint8_t)((cu_sibling_map_mask >> 8) & 0xFF); 1136 pcache->sibling_map[2] = 1137 (uint8_t)((cu_sibling_map_mask >> 16) & 0xFF); 1138 pcache->sibling_map[3] = 1139 (uint8_t)((cu_sibling_map_mask >> 24) & 0xFF); 1140 return 0; 1141 } 1142 return 1; 1143 } 1144 1145 /* Helper function. See kfd_fill_gpu_cache_info for parameter description */ 1146 static int fill_in_l2_l3_pcache(struct crat_subtype_cache *pcache, 1147 struct kfd_gpu_cache_info *pcache_info, 1148 struct kfd_cu_info *cu_info, 1149 int mem_available, 1150 int cache_type, unsigned int cu_processor_id) 1151 { 1152 unsigned int cu_sibling_map_mask; 1153 int first_active_cu; 1154 int i, j, k; 1155 1156 /* First check if enough memory is available */ 1157 if (sizeof(struct crat_subtype_cache) > mem_available) 1158 return -ENOMEM; 1159 1160 cu_sibling_map_mask = cu_info->cu_bitmap[0][0]; 1161 cu_sibling_map_mask &= 1162 ((1 << pcache_info[cache_type].num_cu_shared) - 1); 1163 first_active_cu = ffs(cu_sibling_map_mask); 1164 1165 /* CU could be inactive. In case of shared cache find the first active 1166 * CU. and incase of non-shared cache check if the CU is inactive. If 1167 * inactive active skip it 1168 */ 1169 if (first_active_cu) { 1170 memset(pcache, 0, sizeof(struct crat_subtype_cache)); 1171 pcache->type = CRAT_SUBTYPE_CACHE_AFFINITY; 1172 pcache->length = sizeof(struct crat_subtype_cache); 1173 pcache->flags = pcache_info[cache_type].flags; 1174 pcache->processor_id_low = cu_processor_id 1175 + (first_active_cu - 1); 1176 pcache->cache_level = pcache_info[cache_type].cache_level; 1177 pcache->cache_size = pcache_info[cache_type].cache_size; 1178 1179 /* Sibling map is w.r.t processor_id_low, so shift out 1180 * inactive CU 1181 */ 1182 cu_sibling_map_mask = 1183 cu_sibling_map_mask >> (first_active_cu - 1); 1184 k = 0; 1185 for (i = 0; i < cu_info->num_shader_engines; i++) { 1186 for (j = 0; j < cu_info->num_shader_arrays_per_engine; 1187 j++) { 1188 pcache->sibling_map[k] = 1189 (uint8_t)(cu_sibling_map_mask & 0xFF); 1190 pcache->sibling_map[k+1] = 1191 (uint8_t)((cu_sibling_map_mask >> 8) & 0xFF); 1192 pcache->sibling_map[k+2] = 1193 (uint8_t)((cu_sibling_map_mask >> 16) & 0xFF); 1194 pcache->sibling_map[k+3] = 1195 (uint8_t)((cu_sibling_map_mask >> 24) & 0xFF); 1196 k += 4; 1197 cu_sibling_map_mask = 1198 cu_info->cu_bitmap[i % 4][j + i / 4]; 1199 cu_sibling_map_mask &= ( 1200 (1 << pcache_info[cache_type].num_cu_shared) 1201 - 1); 1202 } 1203 } 1204 return 0; 1205 } 1206 return 1; 1207 } 1208 1209 /* kfd_fill_gpu_cache_info - Fill GPU cache info using kfd_gpu_cache_info 1210 * tables 1211 * 1212 * @kdev - [IN] GPU device 1213 * @gpu_processor_id - [IN] GPU processor ID to which these caches 1214 * associate 1215 * @available_size - [IN] Amount of memory available in pcache 1216 * @cu_info - [IN] Compute Unit info obtained from KGD 1217 * @pcache - [OUT] memory into which cache data is to be filled in. 1218 * @size_filled - [OUT] amount of data used up in pcache. 1219 * @num_of_entries - [OUT] number of caches added 1220 */ 1221 static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev, 1222 int gpu_processor_id, 1223 int available_size, 1224 struct kfd_cu_info *cu_info, 1225 struct crat_subtype_cache *pcache, 1226 int *size_filled, 1227 int *num_of_entries) 1228 { 1229 struct kfd_gpu_cache_info *pcache_info; 1230 int num_of_cache_types = 0; 1231 int i, j, k; 1232 int ct = 0; 1233 int mem_available = available_size; 1234 unsigned int cu_processor_id; 1235 int ret; 1236 unsigned int num_cu_shared; 1237 1238 switch (kdev->device_info->asic_family) { 1239 case CHIP_KAVERI: 1240 pcache_info = kaveri_cache_info; 1241 num_of_cache_types = ARRAY_SIZE(kaveri_cache_info); 1242 break; 1243 case CHIP_HAWAII: 1244 pcache_info = hawaii_cache_info; 1245 num_of_cache_types = ARRAY_SIZE(hawaii_cache_info); 1246 break; 1247 case CHIP_CARRIZO: 1248 pcache_info = carrizo_cache_info; 1249 num_of_cache_types = ARRAY_SIZE(carrizo_cache_info); 1250 break; 1251 case CHIP_TONGA: 1252 pcache_info = tonga_cache_info; 1253 num_of_cache_types = ARRAY_SIZE(tonga_cache_info); 1254 break; 1255 case CHIP_FIJI: 1256 pcache_info = fiji_cache_info; 1257 num_of_cache_types = ARRAY_SIZE(fiji_cache_info); 1258 break; 1259 case CHIP_POLARIS10: 1260 pcache_info = polaris10_cache_info; 1261 num_of_cache_types = ARRAY_SIZE(polaris10_cache_info); 1262 break; 1263 case CHIP_POLARIS11: 1264 pcache_info = polaris11_cache_info; 1265 num_of_cache_types = ARRAY_SIZE(polaris11_cache_info); 1266 break; 1267 case CHIP_POLARIS12: 1268 pcache_info = polaris12_cache_info; 1269 num_of_cache_types = ARRAY_SIZE(polaris12_cache_info); 1270 break; 1271 case CHIP_VEGAM: 1272 pcache_info = vegam_cache_info; 1273 num_of_cache_types = ARRAY_SIZE(vegam_cache_info); 1274 break; 1275 case CHIP_VEGA10: 1276 pcache_info = vega10_cache_info; 1277 num_of_cache_types = ARRAY_SIZE(vega10_cache_info); 1278 break; 1279 case CHIP_VEGA12: 1280 pcache_info = vega12_cache_info; 1281 num_of_cache_types = ARRAY_SIZE(vega12_cache_info); 1282 break; 1283 case CHIP_VEGA20: 1284 case CHIP_ARCTURUS: 1285 pcache_info = vega20_cache_info; 1286 num_of_cache_types = ARRAY_SIZE(vega20_cache_info); 1287 break; 1288 case CHIP_ALDEBARAN: 1289 pcache_info = aldebaran_cache_info; 1290 num_of_cache_types = ARRAY_SIZE(aldebaran_cache_info); 1291 break; 1292 case CHIP_RAVEN: 1293 pcache_info = raven_cache_info; 1294 num_of_cache_types = ARRAY_SIZE(raven_cache_info); 1295 break; 1296 case CHIP_RENOIR: 1297 pcache_info = renoir_cache_info; 1298 num_of_cache_types = ARRAY_SIZE(renoir_cache_info); 1299 break; 1300 case CHIP_NAVI10: 1301 case CHIP_NAVI12: 1302 pcache_info = navi10_cache_info; 1303 num_of_cache_types = ARRAY_SIZE(navi10_cache_info); 1304 break; 1305 case CHIP_NAVI14: 1306 pcache_info = navi14_cache_info; 1307 num_of_cache_types = ARRAY_SIZE(navi14_cache_info); 1308 break; 1309 case CHIP_SIENNA_CICHLID: 1310 pcache_info = sienna_cichlid_cache_info; 1311 num_of_cache_types = ARRAY_SIZE(sienna_cichlid_cache_info); 1312 break; 1313 case CHIP_NAVY_FLOUNDER: 1314 pcache_info = navy_flounder_cache_info; 1315 num_of_cache_types = ARRAY_SIZE(navy_flounder_cache_info); 1316 break; 1317 case CHIP_DIMGREY_CAVEFISH: 1318 pcache_info = dimgrey_cavefish_cache_info; 1319 num_of_cache_types = ARRAY_SIZE(dimgrey_cavefish_cache_info); 1320 break; 1321 case CHIP_VANGOGH: 1322 pcache_info = vangogh_cache_info; 1323 num_of_cache_types = ARRAY_SIZE(vangogh_cache_info); 1324 break; 1325 default: 1326 return -EINVAL; 1327 } 1328 1329 *size_filled = 0; 1330 *num_of_entries = 0; 1331 1332 /* For each type of cache listed in the kfd_gpu_cache_info table, 1333 * go through all available Compute Units. 1334 * The [i,j,k] loop will 1335 * if kfd_gpu_cache_info.num_cu_shared = 1 1336 * will parse through all available CU 1337 * If (kfd_gpu_cache_info.num_cu_shared != 1) 1338 * then it will consider only one CU from 1339 * the shared unit 1340 */ 1341 1342 for (ct = 0; ct < num_of_cache_types; ct++) { 1343 cu_processor_id = gpu_processor_id; 1344 if (pcache_info[ct].cache_level == 1) { 1345 for (i = 0; i < cu_info->num_shader_engines; i++) { 1346 for (j = 0; j < cu_info->num_shader_arrays_per_engine; j++) { 1347 for (k = 0; k < cu_info->num_cu_per_sh; 1348 k += pcache_info[ct].num_cu_shared) { 1349 ret = fill_in_l1_pcache(pcache, 1350 pcache_info, 1351 cu_info, 1352 mem_available, 1353 cu_info->cu_bitmap[i % 4][j + i / 4], 1354 ct, 1355 cu_processor_id, 1356 k); 1357 1358 if (ret < 0) 1359 break; 1360 1361 if (!ret) { 1362 pcache++; 1363 (*num_of_entries)++; 1364 mem_available -= sizeof(*pcache); 1365 (*size_filled) += sizeof(*pcache); 1366 } 1367 1368 /* Move to next CU block */ 1369 num_cu_shared = ((k + pcache_info[ct].num_cu_shared) <= 1370 cu_info->num_cu_per_sh) ? 1371 pcache_info[ct].num_cu_shared : 1372 (cu_info->num_cu_per_sh - k); 1373 cu_processor_id += num_cu_shared; 1374 } 1375 } 1376 } 1377 } else { 1378 ret = fill_in_l2_l3_pcache(pcache, 1379 pcache_info, 1380 cu_info, 1381 mem_available, 1382 ct, 1383 cu_processor_id); 1384 1385 if (ret < 0) 1386 break; 1387 1388 if (!ret) { 1389 pcache++; 1390 (*num_of_entries)++; 1391 mem_available -= sizeof(*pcache); 1392 (*size_filled) += sizeof(*pcache); 1393 } 1394 } 1395 } 1396 1397 pr_debug("Added [%d] GPU cache entries\n", *num_of_entries); 1398 1399 return 0; 1400 } 1401 1402 static bool kfd_ignore_crat(void) 1403 { 1404 bool ret; 1405 1406 if (ignore_crat) 1407 return true; 1408 1409 #ifndef KFD_SUPPORT_IOMMU_V2 1410 ret = true; 1411 #else 1412 ret = false; 1413 #endif 1414 1415 return ret; 1416 } 1417 1418 /* 1419 * kfd_create_crat_image_acpi - Allocates memory for CRAT image and 1420 * copies CRAT from ACPI (if available). 1421 * NOTE: Call kfd_destroy_crat_image to free CRAT image memory 1422 * 1423 * @crat_image: CRAT read from ACPI. If no CRAT in ACPI then 1424 * crat_image will be NULL 1425 * @size: [OUT] size of crat_image 1426 * 1427 * Return 0 if successful else return error code 1428 */ 1429 int kfd_create_crat_image_acpi(void **crat_image, size_t *size) 1430 { 1431 struct acpi_table_header *crat_table; 1432 acpi_status status; 1433 void *pcrat_image; 1434 int rc = 0; 1435 1436 if (!crat_image) 1437 return -EINVAL; 1438 1439 *crat_image = NULL; 1440 1441 if (kfd_ignore_crat()) { 1442 pr_info("CRAT table disabled by module option\n"); 1443 return -ENODATA; 1444 } 1445 1446 /* Fetch the CRAT table from ACPI */ 1447 status = acpi_get_table(CRAT_SIGNATURE, 0, &crat_table); 1448 if (status == AE_NOT_FOUND) { 1449 pr_warn("CRAT table not found\n"); 1450 return -ENODATA; 1451 } else if (ACPI_FAILURE(status)) { 1452 const char *err = acpi_format_exception(status); 1453 1454 pr_err("CRAT table error: %s\n", err); 1455 return -EINVAL; 1456 } 1457 1458 pcrat_image = kvmalloc(crat_table->length, GFP_KERNEL); 1459 if (!pcrat_image) { 1460 rc = -ENOMEM; 1461 goto out; 1462 } 1463 1464 memcpy(pcrat_image, crat_table, crat_table->length); 1465 *crat_image = pcrat_image; 1466 *size = crat_table->length; 1467 out: 1468 acpi_put_table(crat_table); 1469 return rc; 1470 } 1471 1472 /* Memory required to create Virtual CRAT. 1473 * Since there is no easy way to predict the amount of memory required, the 1474 * following amount is allocated for GPU Virtual CRAT. This is 1475 * expected to cover all known conditions. But to be safe additional check 1476 * is put in the code to ensure we don't overwrite. 1477 */ 1478 #define VCRAT_SIZE_FOR_GPU (4 * PAGE_SIZE) 1479 1480 /* kfd_fill_cu_for_cpu - Fill in Compute info for the given CPU NUMA node 1481 * 1482 * @numa_node_id: CPU NUMA node id 1483 * @avail_size: Available size in the memory 1484 * @sub_type_hdr: Memory into which compute info will be filled in 1485 * 1486 * Return 0 if successful else return -ve value 1487 */ 1488 static int kfd_fill_cu_for_cpu(int numa_node_id, int *avail_size, 1489 int proximity_domain, 1490 struct crat_subtype_computeunit *sub_type_hdr) 1491 { 1492 const struct cpumask *cpumask; 1493 1494 *avail_size -= sizeof(struct crat_subtype_computeunit); 1495 if (*avail_size < 0) 1496 return -ENOMEM; 1497 1498 memset(sub_type_hdr, 0, sizeof(struct crat_subtype_computeunit)); 1499 1500 /* Fill in subtype header data */ 1501 sub_type_hdr->type = CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY; 1502 sub_type_hdr->length = sizeof(struct crat_subtype_computeunit); 1503 sub_type_hdr->flags = CRAT_SUBTYPE_FLAGS_ENABLED; 1504 1505 cpumask = cpumask_of_node(numa_node_id); 1506 1507 /* Fill in CU data */ 1508 sub_type_hdr->flags |= CRAT_CU_FLAGS_CPU_PRESENT; 1509 sub_type_hdr->proximity_domain = proximity_domain; 1510 sub_type_hdr->processor_id_low = kfd_numa_node_to_apic_id(numa_node_id); 1511 if (sub_type_hdr->processor_id_low == -1) 1512 return -EINVAL; 1513 1514 sub_type_hdr->num_cpu_cores = cpumask_weight(cpumask); 1515 1516 return 0; 1517 } 1518 1519 /* kfd_fill_mem_info_for_cpu - Fill in Memory info for the given CPU NUMA node 1520 * 1521 * @numa_node_id: CPU NUMA node id 1522 * @avail_size: Available size in the memory 1523 * @sub_type_hdr: Memory into which compute info will be filled in 1524 * 1525 * Return 0 if successful else return -ve value 1526 */ 1527 static int kfd_fill_mem_info_for_cpu(int numa_node_id, int *avail_size, 1528 int proximity_domain, 1529 struct crat_subtype_memory *sub_type_hdr) 1530 { 1531 uint64_t mem_in_bytes = 0; 1532 pg_data_t *pgdat; 1533 int zone_type; 1534 1535 *avail_size -= sizeof(struct crat_subtype_memory); 1536 if (*avail_size < 0) 1537 return -ENOMEM; 1538 1539 memset(sub_type_hdr, 0, sizeof(struct crat_subtype_memory)); 1540 1541 /* Fill in subtype header data */ 1542 sub_type_hdr->type = CRAT_SUBTYPE_MEMORY_AFFINITY; 1543 sub_type_hdr->length = sizeof(struct crat_subtype_memory); 1544 sub_type_hdr->flags = CRAT_SUBTYPE_FLAGS_ENABLED; 1545 1546 /* Fill in Memory Subunit data */ 1547 1548 /* Unlike si_meminfo, si_meminfo_node is not exported. So 1549 * the following lines are duplicated from si_meminfo_node 1550 * function 1551 */ 1552 pgdat = NODE_DATA(numa_node_id); 1553 for (zone_type = 0; zone_type < MAX_NR_ZONES; zone_type++) 1554 mem_in_bytes += zone_managed_pages(&pgdat->node_zones[zone_type]); 1555 mem_in_bytes <<= PAGE_SHIFT; 1556 1557 sub_type_hdr->length_low = lower_32_bits(mem_in_bytes); 1558 sub_type_hdr->length_high = upper_32_bits(mem_in_bytes); 1559 sub_type_hdr->proximity_domain = proximity_domain; 1560 1561 return 0; 1562 } 1563 1564 #ifdef CONFIG_X86_64 1565 static int kfd_fill_iolink_info_for_cpu(int numa_node_id, int *avail_size, 1566 uint32_t *num_entries, 1567 struct crat_subtype_iolink *sub_type_hdr) 1568 { 1569 int nid; 1570 struct cpuinfo_x86 *c = &cpu_data(0); 1571 uint8_t link_type; 1572 1573 if (c->x86_vendor == X86_VENDOR_AMD) 1574 link_type = CRAT_IOLINK_TYPE_HYPERTRANSPORT; 1575 else 1576 link_type = CRAT_IOLINK_TYPE_QPI_1_1; 1577 1578 *num_entries = 0; 1579 1580 /* Create IO links from this node to other CPU nodes */ 1581 for_each_online_node(nid) { 1582 if (nid == numa_node_id) /* node itself */ 1583 continue; 1584 1585 *avail_size -= sizeof(struct crat_subtype_iolink); 1586 if (*avail_size < 0) 1587 return -ENOMEM; 1588 1589 memset(sub_type_hdr, 0, sizeof(struct crat_subtype_iolink)); 1590 1591 /* Fill in subtype header data */ 1592 sub_type_hdr->type = CRAT_SUBTYPE_IOLINK_AFFINITY; 1593 sub_type_hdr->length = sizeof(struct crat_subtype_iolink); 1594 sub_type_hdr->flags = CRAT_SUBTYPE_FLAGS_ENABLED; 1595 1596 /* Fill in IO link data */ 1597 sub_type_hdr->proximity_domain_from = numa_node_id; 1598 sub_type_hdr->proximity_domain_to = nid; 1599 sub_type_hdr->io_interface_type = link_type; 1600 1601 (*num_entries)++; 1602 sub_type_hdr++; 1603 } 1604 1605 return 0; 1606 } 1607 #endif 1608 1609 /* kfd_create_vcrat_image_cpu - Create Virtual CRAT for CPU 1610 * 1611 * @pcrat_image: Fill in VCRAT for CPU 1612 * @size: [IN] allocated size of crat_image. 1613 * [OUT] actual size of data filled in crat_image 1614 */ 1615 static int kfd_create_vcrat_image_cpu(void *pcrat_image, size_t *size) 1616 { 1617 struct crat_header *crat_table = (struct crat_header *)pcrat_image; 1618 struct acpi_table_header *acpi_table; 1619 acpi_status status; 1620 struct crat_subtype_generic *sub_type_hdr; 1621 int avail_size = *size; 1622 int numa_node_id; 1623 #ifdef CONFIG_X86_64 1624 uint32_t entries = 0; 1625 #endif 1626 int ret = 0; 1627 1628 if (!pcrat_image) 1629 return -EINVAL; 1630 1631 /* Fill in CRAT Header. 1632 * Modify length and total_entries as subunits are added. 1633 */ 1634 avail_size -= sizeof(struct crat_header); 1635 if (avail_size < 0) 1636 return -ENOMEM; 1637 1638 memset(crat_table, 0, sizeof(struct crat_header)); 1639 memcpy(&crat_table->signature, CRAT_SIGNATURE, 1640 sizeof(crat_table->signature)); 1641 crat_table->length = sizeof(struct crat_header); 1642 1643 status = acpi_get_table("DSDT", 0, &acpi_table); 1644 if (status != AE_OK) 1645 pr_warn("DSDT table not found for OEM information\n"); 1646 else { 1647 crat_table->oem_revision = acpi_table->revision; 1648 memcpy(crat_table->oem_id, acpi_table->oem_id, 1649 CRAT_OEMID_LENGTH); 1650 memcpy(crat_table->oem_table_id, acpi_table->oem_table_id, 1651 CRAT_OEMTABLEID_LENGTH); 1652 acpi_put_table(acpi_table); 1653 } 1654 crat_table->total_entries = 0; 1655 crat_table->num_domains = 0; 1656 1657 sub_type_hdr = (struct crat_subtype_generic *)(crat_table+1); 1658 1659 for_each_online_node(numa_node_id) { 1660 if (kfd_numa_node_to_apic_id(numa_node_id) == -1) 1661 continue; 1662 1663 /* Fill in Subtype: Compute Unit */ 1664 ret = kfd_fill_cu_for_cpu(numa_node_id, &avail_size, 1665 crat_table->num_domains, 1666 (struct crat_subtype_computeunit *)sub_type_hdr); 1667 if (ret < 0) 1668 return ret; 1669 crat_table->length += sub_type_hdr->length; 1670 crat_table->total_entries++; 1671 1672 sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr + 1673 sub_type_hdr->length); 1674 1675 /* Fill in Subtype: Memory */ 1676 ret = kfd_fill_mem_info_for_cpu(numa_node_id, &avail_size, 1677 crat_table->num_domains, 1678 (struct crat_subtype_memory *)sub_type_hdr); 1679 if (ret < 0) 1680 return ret; 1681 crat_table->length += sub_type_hdr->length; 1682 crat_table->total_entries++; 1683 1684 sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr + 1685 sub_type_hdr->length); 1686 1687 /* Fill in Subtype: IO Link */ 1688 #ifdef CONFIG_X86_64 1689 ret = kfd_fill_iolink_info_for_cpu(numa_node_id, &avail_size, 1690 &entries, 1691 (struct crat_subtype_iolink *)sub_type_hdr); 1692 if (ret < 0) 1693 return ret; 1694 1695 if (entries) { 1696 crat_table->length += (sub_type_hdr->length * entries); 1697 crat_table->total_entries += entries; 1698 1699 sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr + 1700 sub_type_hdr->length * entries); 1701 } 1702 #else 1703 pr_info("IO link not available for non x86 platforms\n"); 1704 #endif 1705 1706 crat_table->num_domains++; 1707 } 1708 1709 /* TODO: Add cache Subtype for CPU. 1710 * Currently, CPU cache information is available in function 1711 * detect_cache_attributes(cpu) defined in the file 1712 * ./arch/x86/kernel/cpu/intel_cacheinfo.c. This function is not 1713 * exported and to get the same information the code needs to be 1714 * duplicated. 1715 */ 1716 1717 *size = crat_table->length; 1718 pr_info("Virtual CRAT table created for CPU\n"); 1719 1720 return 0; 1721 } 1722 1723 static int kfd_fill_gpu_memory_affinity(int *avail_size, 1724 struct kfd_dev *kdev, uint8_t type, uint64_t size, 1725 struct crat_subtype_memory *sub_type_hdr, 1726 uint32_t proximity_domain, 1727 const struct kfd_local_mem_info *local_mem_info) 1728 { 1729 *avail_size -= sizeof(struct crat_subtype_memory); 1730 if (*avail_size < 0) 1731 return -ENOMEM; 1732 1733 memset((void *)sub_type_hdr, 0, sizeof(struct crat_subtype_memory)); 1734 sub_type_hdr->type = CRAT_SUBTYPE_MEMORY_AFFINITY; 1735 sub_type_hdr->length = sizeof(struct crat_subtype_memory); 1736 sub_type_hdr->flags |= CRAT_SUBTYPE_FLAGS_ENABLED; 1737 1738 sub_type_hdr->proximity_domain = proximity_domain; 1739 1740 pr_debug("Fill gpu memory affinity - type 0x%x size 0x%llx\n", 1741 type, size); 1742 1743 sub_type_hdr->length_low = lower_32_bits(size); 1744 sub_type_hdr->length_high = upper_32_bits(size); 1745 1746 sub_type_hdr->width = local_mem_info->vram_width; 1747 sub_type_hdr->visibility_type = type; 1748 1749 return 0; 1750 } 1751 1752 #ifdef CONFIG_ACPI_NUMA 1753 static void kfd_find_numa_node_in_srat(struct kfd_dev *kdev) 1754 { 1755 struct acpi_table_header *table_header = NULL; 1756 struct acpi_subtable_header *sub_header = NULL; 1757 unsigned long table_end, subtable_len; 1758 u32 pci_id = pci_domain_nr(kdev->pdev->bus) << 16 | 1759 pci_dev_id(kdev->pdev); 1760 u32 bdf; 1761 acpi_status status; 1762 struct acpi_srat_cpu_affinity *cpu; 1763 struct acpi_srat_generic_affinity *gpu; 1764 int pxm = 0, max_pxm = 0; 1765 int numa_node = NUMA_NO_NODE; 1766 bool found = false; 1767 1768 /* Fetch the SRAT table from ACPI */ 1769 status = acpi_get_table(ACPI_SIG_SRAT, 0, &table_header); 1770 if (status == AE_NOT_FOUND) { 1771 pr_warn("SRAT table not found\n"); 1772 return; 1773 } else if (ACPI_FAILURE(status)) { 1774 const char *err = acpi_format_exception(status); 1775 pr_err("SRAT table error: %s\n", err); 1776 return; 1777 } 1778 1779 table_end = (unsigned long)table_header + table_header->length; 1780 1781 /* Parse all entries looking for a match. */ 1782 sub_header = (struct acpi_subtable_header *) 1783 ((unsigned long)table_header + 1784 sizeof(struct acpi_table_srat)); 1785 subtable_len = sub_header->length; 1786 1787 while (((unsigned long)sub_header) + subtable_len < table_end) { 1788 /* 1789 * If length is 0, break from this loop to avoid 1790 * infinite loop. 1791 */ 1792 if (subtable_len == 0) { 1793 pr_err("SRAT invalid zero length\n"); 1794 break; 1795 } 1796 1797 switch (sub_header->type) { 1798 case ACPI_SRAT_TYPE_CPU_AFFINITY: 1799 cpu = (struct acpi_srat_cpu_affinity *)sub_header; 1800 pxm = *((u32 *)cpu->proximity_domain_hi) << 8 | 1801 cpu->proximity_domain_lo; 1802 if (pxm > max_pxm) 1803 max_pxm = pxm; 1804 break; 1805 case ACPI_SRAT_TYPE_GENERIC_AFFINITY: 1806 gpu = (struct acpi_srat_generic_affinity *)sub_header; 1807 bdf = *((u16 *)(&gpu->device_handle[0])) << 16 | 1808 *((u16 *)(&gpu->device_handle[2])); 1809 if (bdf == pci_id) { 1810 found = true; 1811 numa_node = pxm_to_node(gpu->proximity_domain); 1812 } 1813 break; 1814 default: 1815 break; 1816 } 1817 1818 if (found) 1819 break; 1820 1821 sub_header = (struct acpi_subtable_header *) 1822 ((unsigned long)sub_header + subtable_len); 1823 subtable_len = sub_header->length; 1824 } 1825 1826 acpi_put_table(table_header); 1827 1828 /* Workaround bad cpu-gpu binding case */ 1829 if (found && (numa_node < 0 || 1830 numa_node > pxm_to_node(max_pxm))) 1831 numa_node = 0; 1832 1833 if (numa_node != NUMA_NO_NODE) 1834 set_dev_node(&kdev->pdev->dev, numa_node); 1835 } 1836 #endif 1837 1838 /* kfd_fill_gpu_direct_io_link - Fill in direct io link from GPU 1839 * to its NUMA node 1840 * @avail_size: Available size in the memory 1841 * @kdev - [IN] GPU device 1842 * @sub_type_hdr: Memory into which io link info will be filled in 1843 * @proximity_domain - proximity domain of the GPU node 1844 * 1845 * Return 0 if successful else return -ve value 1846 */ 1847 static int kfd_fill_gpu_direct_io_link_to_cpu(int *avail_size, 1848 struct kfd_dev *kdev, 1849 struct crat_subtype_iolink *sub_type_hdr, 1850 uint32_t proximity_domain) 1851 { 1852 struct amdgpu_device *adev = (struct amdgpu_device *)kdev->kgd; 1853 1854 *avail_size -= sizeof(struct crat_subtype_iolink); 1855 if (*avail_size < 0) 1856 return -ENOMEM; 1857 1858 memset((void *)sub_type_hdr, 0, sizeof(struct crat_subtype_iolink)); 1859 1860 /* Fill in subtype header data */ 1861 sub_type_hdr->type = CRAT_SUBTYPE_IOLINK_AFFINITY; 1862 sub_type_hdr->length = sizeof(struct crat_subtype_iolink); 1863 sub_type_hdr->flags |= CRAT_SUBTYPE_FLAGS_ENABLED; 1864 if (kfd_dev_is_large_bar(kdev)) 1865 sub_type_hdr->flags |= CRAT_IOLINK_FLAGS_BI_DIRECTIONAL; 1866 1867 /* Fill in IOLINK subtype. 1868 * TODO: Fill-in other fields of iolink subtype 1869 */ 1870 if (adev->gmc.xgmi.connected_to_cpu) { 1871 /* 1872 * with host gpu xgmi link, host can access gpu memory whether 1873 * or not pcie bar type is large, so always create bidirectional 1874 * io link. 1875 */ 1876 sub_type_hdr->flags |= CRAT_IOLINK_FLAGS_BI_DIRECTIONAL; 1877 sub_type_hdr->io_interface_type = CRAT_IOLINK_TYPE_XGMI; 1878 sub_type_hdr->num_hops_xgmi = 1; 1879 } else { 1880 sub_type_hdr->io_interface_type = CRAT_IOLINK_TYPE_PCIEXPRESS; 1881 } 1882 1883 sub_type_hdr->proximity_domain_from = proximity_domain; 1884 1885 #ifdef CONFIG_ACPI_NUMA 1886 if (kdev->pdev->dev.numa_node == NUMA_NO_NODE) 1887 kfd_find_numa_node_in_srat(kdev); 1888 #endif 1889 #ifdef CONFIG_NUMA 1890 if (kdev->pdev->dev.numa_node == NUMA_NO_NODE) 1891 sub_type_hdr->proximity_domain_to = 0; 1892 else 1893 sub_type_hdr->proximity_domain_to = kdev->pdev->dev.numa_node; 1894 #else 1895 sub_type_hdr->proximity_domain_to = 0; 1896 #endif 1897 return 0; 1898 } 1899 1900 static int kfd_fill_gpu_xgmi_link_to_gpu(int *avail_size, 1901 struct kfd_dev *kdev, 1902 struct kfd_dev *peer_kdev, 1903 struct crat_subtype_iolink *sub_type_hdr, 1904 uint32_t proximity_domain_from, 1905 uint32_t proximity_domain_to) 1906 { 1907 *avail_size -= sizeof(struct crat_subtype_iolink); 1908 if (*avail_size < 0) 1909 return -ENOMEM; 1910 1911 memset((void *)sub_type_hdr, 0, sizeof(struct crat_subtype_iolink)); 1912 1913 sub_type_hdr->type = CRAT_SUBTYPE_IOLINK_AFFINITY; 1914 sub_type_hdr->length = sizeof(struct crat_subtype_iolink); 1915 sub_type_hdr->flags |= CRAT_SUBTYPE_FLAGS_ENABLED | 1916 CRAT_IOLINK_FLAGS_BI_DIRECTIONAL; 1917 1918 sub_type_hdr->io_interface_type = CRAT_IOLINK_TYPE_XGMI; 1919 sub_type_hdr->proximity_domain_from = proximity_domain_from; 1920 sub_type_hdr->proximity_domain_to = proximity_domain_to; 1921 sub_type_hdr->num_hops_xgmi = 1922 amdgpu_amdkfd_get_xgmi_hops_count(kdev->kgd, peer_kdev->kgd); 1923 return 0; 1924 } 1925 1926 /* kfd_create_vcrat_image_gpu - Create Virtual CRAT for CPU 1927 * 1928 * @pcrat_image: Fill in VCRAT for GPU 1929 * @size: [IN] allocated size of crat_image. 1930 * [OUT] actual size of data filled in crat_image 1931 */ 1932 static int kfd_create_vcrat_image_gpu(void *pcrat_image, 1933 size_t *size, struct kfd_dev *kdev, 1934 uint32_t proximity_domain) 1935 { 1936 struct crat_header *crat_table = (struct crat_header *)pcrat_image; 1937 struct crat_subtype_generic *sub_type_hdr; 1938 struct kfd_local_mem_info local_mem_info; 1939 struct kfd_topology_device *peer_dev; 1940 struct crat_subtype_computeunit *cu; 1941 struct kfd_cu_info cu_info; 1942 int avail_size = *size; 1943 uint32_t total_num_of_cu; 1944 int num_of_cache_entries = 0; 1945 int cache_mem_filled = 0; 1946 uint32_t nid = 0; 1947 int ret = 0; 1948 1949 if (!pcrat_image || avail_size < VCRAT_SIZE_FOR_GPU) 1950 return -EINVAL; 1951 1952 /* Fill the CRAT Header. 1953 * Modify length and total_entries as subunits are added. 1954 */ 1955 avail_size -= sizeof(struct crat_header); 1956 if (avail_size < 0) 1957 return -ENOMEM; 1958 1959 memset(crat_table, 0, sizeof(struct crat_header)); 1960 1961 memcpy(&crat_table->signature, CRAT_SIGNATURE, 1962 sizeof(crat_table->signature)); 1963 /* Change length as we add more subtypes*/ 1964 crat_table->length = sizeof(struct crat_header); 1965 crat_table->num_domains = 1; 1966 crat_table->total_entries = 0; 1967 1968 /* Fill in Subtype: Compute Unit 1969 * First fill in the sub type header and then sub type data 1970 */ 1971 avail_size -= sizeof(struct crat_subtype_computeunit); 1972 if (avail_size < 0) 1973 return -ENOMEM; 1974 1975 sub_type_hdr = (struct crat_subtype_generic *)(crat_table + 1); 1976 memset(sub_type_hdr, 0, sizeof(struct crat_subtype_computeunit)); 1977 1978 sub_type_hdr->type = CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY; 1979 sub_type_hdr->length = sizeof(struct crat_subtype_computeunit); 1980 sub_type_hdr->flags = CRAT_SUBTYPE_FLAGS_ENABLED; 1981 1982 /* Fill CU subtype data */ 1983 cu = (struct crat_subtype_computeunit *)sub_type_hdr; 1984 cu->flags |= CRAT_CU_FLAGS_GPU_PRESENT; 1985 cu->proximity_domain = proximity_domain; 1986 1987 amdgpu_amdkfd_get_cu_info(kdev->kgd, &cu_info); 1988 cu->num_simd_per_cu = cu_info.simd_per_cu; 1989 cu->num_simd_cores = cu_info.simd_per_cu * cu_info.cu_active_number; 1990 cu->max_waves_simd = cu_info.max_waves_per_simd; 1991 1992 cu->wave_front_size = cu_info.wave_front_size; 1993 cu->array_count = cu_info.num_shader_arrays_per_engine * 1994 cu_info.num_shader_engines; 1995 total_num_of_cu = (cu->array_count * cu_info.num_cu_per_sh); 1996 cu->processor_id_low = get_and_inc_gpu_processor_id(total_num_of_cu); 1997 cu->num_cu_per_array = cu_info.num_cu_per_sh; 1998 cu->max_slots_scatch_cu = cu_info.max_scratch_slots_per_cu; 1999 cu->num_banks = cu_info.num_shader_engines; 2000 cu->lds_size_in_kb = cu_info.lds_size; 2001 2002 cu->hsa_capability = 0; 2003 2004 /* Check if this node supports IOMMU. During parsing this flag will 2005 * translate to HSA_CAP_ATS_PRESENT 2006 */ 2007 if (!kfd_iommu_check_device(kdev)) 2008 cu->hsa_capability |= CRAT_CU_FLAGS_IOMMU_PRESENT; 2009 2010 crat_table->length += sub_type_hdr->length; 2011 crat_table->total_entries++; 2012 2013 /* Fill in Subtype: Memory. Only on systems with large BAR (no 2014 * private FB), report memory as public. On other systems 2015 * report the total FB size (public+private) as a single 2016 * private heap. 2017 */ 2018 amdgpu_amdkfd_get_local_mem_info(kdev->kgd, &local_mem_info); 2019 sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr + 2020 sub_type_hdr->length); 2021 2022 if (debug_largebar) 2023 local_mem_info.local_mem_size_private = 0; 2024 2025 if (local_mem_info.local_mem_size_private == 0) 2026 ret = kfd_fill_gpu_memory_affinity(&avail_size, 2027 kdev, HSA_MEM_HEAP_TYPE_FB_PUBLIC, 2028 local_mem_info.local_mem_size_public, 2029 (struct crat_subtype_memory *)sub_type_hdr, 2030 proximity_domain, 2031 &local_mem_info); 2032 else 2033 ret = kfd_fill_gpu_memory_affinity(&avail_size, 2034 kdev, HSA_MEM_HEAP_TYPE_FB_PRIVATE, 2035 local_mem_info.local_mem_size_public + 2036 local_mem_info.local_mem_size_private, 2037 (struct crat_subtype_memory *)sub_type_hdr, 2038 proximity_domain, 2039 &local_mem_info); 2040 if (ret < 0) 2041 return ret; 2042 2043 crat_table->length += sizeof(struct crat_subtype_memory); 2044 crat_table->total_entries++; 2045 2046 /* TODO: Fill in cache information. This information is NOT readily 2047 * available in KGD 2048 */ 2049 sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr + 2050 sub_type_hdr->length); 2051 ret = kfd_fill_gpu_cache_info(kdev, cu->processor_id_low, 2052 avail_size, 2053 &cu_info, 2054 (struct crat_subtype_cache *)sub_type_hdr, 2055 &cache_mem_filled, 2056 &num_of_cache_entries); 2057 2058 if (ret < 0) 2059 return ret; 2060 2061 crat_table->length += cache_mem_filled; 2062 crat_table->total_entries += num_of_cache_entries; 2063 avail_size -= cache_mem_filled; 2064 2065 /* Fill in Subtype: IO_LINKS 2066 * Only direct links are added here which is Link from GPU to 2067 * to its NUMA node. Indirect links are added by userspace. 2068 */ 2069 sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr + 2070 cache_mem_filled); 2071 ret = kfd_fill_gpu_direct_io_link_to_cpu(&avail_size, kdev, 2072 (struct crat_subtype_iolink *)sub_type_hdr, proximity_domain); 2073 2074 if (ret < 0) 2075 return ret; 2076 2077 crat_table->length += sub_type_hdr->length; 2078 crat_table->total_entries++; 2079 2080 2081 /* Fill in Subtype: IO_LINKS 2082 * Direct links from GPU to other GPUs through xGMI. 2083 * We will loop GPUs that already be processed (with lower value 2084 * of proximity_domain), add the link for the GPUs with same 2085 * hive id (from this GPU to other GPU) . The reversed iolink 2086 * (from other GPU to this GPU) will be added 2087 * in kfd_parse_subtype_iolink. 2088 */ 2089 if (kdev->hive_id) { 2090 for (nid = 0; nid < proximity_domain; ++nid) { 2091 peer_dev = kfd_topology_device_by_proximity_domain(nid); 2092 if (!peer_dev->gpu) 2093 continue; 2094 if (peer_dev->gpu->hive_id != kdev->hive_id) 2095 continue; 2096 sub_type_hdr = (typeof(sub_type_hdr))( 2097 (char *)sub_type_hdr + 2098 sizeof(struct crat_subtype_iolink)); 2099 ret = kfd_fill_gpu_xgmi_link_to_gpu( 2100 &avail_size, kdev, peer_dev->gpu, 2101 (struct crat_subtype_iolink *)sub_type_hdr, 2102 proximity_domain, nid); 2103 if (ret < 0) 2104 return ret; 2105 crat_table->length += sub_type_hdr->length; 2106 crat_table->total_entries++; 2107 } 2108 } 2109 *size = crat_table->length; 2110 pr_info("Virtual CRAT table created for GPU\n"); 2111 2112 return ret; 2113 } 2114 2115 /* kfd_create_crat_image_virtual - Allocates memory for CRAT image and 2116 * creates a Virtual CRAT (VCRAT) image 2117 * 2118 * NOTE: Call kfd_destroy_crat_image to free CRAT image memory 2119 * 2120 * @crat_image: VCRAT image created because ACPI does not have a 2121 * CRAT for this device 2122 * @size: [OUT] size of virtual crat_image 2123 * @flags: COMPUTE_UNIT_CPU - Create VCRAT for CPU device 2124 * COMPUTE_UNIT_GPU - Create VCRAT for GPU 2125 * (COMPUTE_UNIT_CPU | COMPUTE_UNIT_GPU) - Create VCRAT for APU 2126 * -- this option is not currently implemented. 2127 * The assumption is that all AMD APUs will have CRAT 2128 * @kdev: Valid kfd_device required if flags contain COMPUTE_UNIT_GPU 2129 * 2130 * Return 0 if successful else return -ve value 2131 */ 2132 int kfd_create_crat_image_virtual(void **crat_image, size_t *size, 2133 int flags, struct kfd_dev *kdev, 2134 uint32_t proximity_domain) 2135 { 2136 void *pcrat_image = NULL; 2137 int ret = 0, num_nodes; 2138 size_t dyn_size; 2139 2140 if (!crat_image) 2141 return -EINVAL; 2142 2143 *crat_image = NULL; 2144 2145 /* Allocate the CPU Virtual CRAT size based on the number of online 2146 * nodes. Allocate VCRAT_SIZE_FOR_GPU for GPU virtual CRAT image. 2147 * This should cover all the current conditions. A check is put not 2148 * to overwrite beyond allocated size for GPUs 2149 */ 2150 switch (flags) { 2151 case COMPUTE_UNIT_CPU: 2152 num_nodes = num_online_nodes(); 2153 dyn_size = sizeof(struct crat_header) + 2154 num_nodes * (sizeof(struct crat_subtype_computeunit) + 2155 sizeof(struct crat_subtype_memory) + 2156 (num_nodes - 1) * sizeof(struct crat_subtype_iolink)); 2157 pcrat_image = kvmalloc(dyn_size, GFP_KERNEL); 2158 if (!pcrat_image) 2159 return -ENOMEM; 2160 *size = dyn_size; 2161 pr_debug("CRAT size is %ld", dyn_size); 2162 ret = kfd_create_vcrat_image_cpu(pcrat_image, size); 2163 break; 2164 case COMPUTE_UNIT_GPU: 2165 if (!kdev) 2166 return -EINVAL; 2167 pcrat_image = kvmalloc(VCRAT_SIZE_FOR_GPU, GFP_KERNEL); 2168 if (!pcrat_image) 2169 return -ENOMEM; 2170 *size = VCRAT_SIZE_FOR_GPU; 2171 ret = kfd_create_vcrat_image_gpu(pcrat_image, size, kdev, 2172 proximity_domain); 2173 break; 2174 case (COMPUTE_UNIT_CPU | COMPUTE_UNIT_GPU): 2175 /* TODO: */ 2176 ret = -EINVAL; 2177 pr_err("VCRAT not implemented for APU\n"); 2178 break; 2179 default: 2180 ret = -EINVAL; 2181 } 2182 2183 if (!ret) 2184 *crat_image = pcrat_image; 2185 else 2186 kvfree(pcrat_image); 2187 2188 return ret; 2189 } 2190 2191 2192 /* kfd_destroy_crat_image 2193 * 2194 * @crat_image: [IN] - crat_image from kfd_create_crat_image_xxx(..) 2195 * 2196 */ 2197 void kfd_destroy_crat_image(void *crat_image) 2198 { 2199 kvfree(crat_image); 2200 } 2201