1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/device.h> 24 #include <linux/export.h> 25 #include <linux/err.h> 26 #include <linux/fs.h> 27 #include <linux/file.h> 28 #include <linux/sched.h> 29 #include <linux/slab.h> 30 #include <linux/uaccess.h> 31 #include <linux/compat.h> 32 #include <uapi/linux/kfd_ioctl.h> 33 #include <linux/time.h> 34 #include <linux/mm.h> 35 #include <linux/mman.h> 36 #include <linux/dma-buf.h> 37 #include <asm/processor.h> 38 #include "kfd_priv.h" 39 #include "kfd_device_queue_manager.h" 40 #include "kfd_dbgmgr.h" 41 #include "amdgpu_amdkfd.h" 42 43 static long kfd_ioctl(struct file *, unsigned int, unsigned long); 44 static int kfd_open(struct inode *, struct file *); 45 static int kfd_release(struct inode *, struct file *); 46 static int kfd_mmap(struct file *, struct vm_area_struct *); 47 48 static const char kfd_dev_name[] = "kfd"; 49 50 static const struct file_operations kfd_fops = { 51 .owner = THIS_MODULE, 52 .unlocked_ioctl = kfd_ioctl, 53 .compat_ioctl = compat_ptr_ioctl, 54 .open = kfd_open, 55 .release = kfd_release, 56 .mmap = kfd_mmap, 57 }; 58 59 static int kfd_char_dev_major = -1; 60 static struct class *kfd_class; 61 struct device *kfd_device; 62 63 int kfd_chardev_init(void) 64 { 65 int err = 0; 66 67 kfd_char_dev_major = register_chrdev(0, kfd_dev_name, &kfd_fops); 68 err = kfd_char_dev_major; 69 if (err < 0) 70 goto err_register_chrdev; 71 72 kfd_class = class_create(THIS_MODULE, kfd_dev_name); 73 err = PTR_ERR(kfd_class); 74 if (IS_ERR(kfd_class)) 75 goto err_class_create; 76 77 kfd_device = device_create(kfd_class, NULL, 78 MKDEV(kfd_char_dev_major, 0), 79 NULL, kfd_dev_name); 80 err = PTR_ERR(kfd_device); 81 if (IS_ERR(kfd_device)) 82 goto err_device_create; 83 84 return 0; 85 86 err_device_create: 87 class_destroy(kfd_class); 88 err_class_create: 89 unregister_chrdev(kfd_char_dev_major, kfd_dev_name); 90 err_register_chrdev: 91 return err; 92 } 93 94 void kfd_chardev_exit(void) 95 { 96 device_destroy(kfd_class, MKDEV(kfd_char_dev_major, 0)); 97 class_destroy(kfd_class); 98 unregister_chrdev(kfd_char_dev_major, kfd_dev_name); 99 } 100 101 struct device *kfd_chardev(void) 102 { 103 return kfd_device; 104 } 105 106 107 static int kfd_open(struct inode *inode, struct file *filep) 108 { 109 struct kfd_process *process; 110 bool is_32bit_user_mode; 111 112 if (iminor(inode) != 0) 113 return -ENODEV; 114 115 is_32bit_user_mode = in_compat_syscall(); 116 117 if (is_32bit_user_mode) { 118 dev_warn(kfd_device, 119 "Process %d (32-bit) failed to open /dev/kfd\n" 120 "32-bit processes are not supported by amdkfd\n", 121 current->pid); 122 return -EPERM; 123 } 124 125 process = kfd_create_process(filep); 126 if (IS_ERR(process)) 127 return PTR_ERR(process); 128 129 if (kfd_is_locked()) { 130 dev_dbg(kfd_device, "kfd is locked!\n" 131 "process %d unreferenced", process->pasid); 132 kfd_unref_process(process); 133 return -EAGAIN; 134 } 135 136 /* filep now owns the reference returned by kfd_create_process */ 137 filep->private_data = process; 138 139 dev_dbg(kfd_device, "process %d opened, compat mode (32 bit) - %d\n", 140 process->pasid, process->is_32bit_user_mode); 141 142 return 0; 143 } 144 145 static int kfd_release(struct inode *inode, struct file *filep) 146 { 147 struct kfd_process *process = filep->private_data; 148 149 if (process) 150 kfd_unref_process(process); 151 152 return 0; 153 } 154 155 static int kfd_ioctl_get_version(struct file *filep, struct kfd_process *p, 156 void *data) 157 { 158 struct kfd_ioctl_get_version_args *args = data; 159 160 args->major_version = KFD_IOCTL_MAJOR_VERSION; 161 args->minor_version = KFD_IOCTL_MINOR_VERSION; 162 163 return 0; 164 } 165 166 static int set_queue_properties_from_user(struct queue_properties *q_properties, 167 struct kfd_ioctl_create_queue_args *args) 168 { 169 if (args->queue_percentage > KFD_MAX_QUEUE_PERCENTAGE) { 170 pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n"); 171 return -EINVAL; 172 } 173 174 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) { 175 pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n"); 176 return -EINVAL; 177 } 178 179 if ((args->ring_base_address) && 180 (!access_ok((const void __user *) args->ring_base_address, 181 sizeof(uint64_t)))) { 182 pr_err("Can't access ring base address\n"); 183 return -EFAULT; 184 } 185 186 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) { 187 pr_err("Ring size must be a power of 2 or 0\n"); 188 return -EINVAL; 189 } 190 191 if (!access_ok((const void __user *) args->read_pointer_address, 192 sizeof(uint32_t))) { 193 pr_err("Can't access read pointer\n"); 194 return -EFAULT; 195 } 196 197 if (!access_ok((const void __user *) args->write_pointer_address, 198 sizeof(uint32_t))) { 199 pr_err("Can't access write pointer\n"); 200 return -EFAULT; 201 } 202 203 if (args->eop_buffer_address && 204 !access_ok((const void __user *) args->eop_buffer_address, 205 sizeof(uint32_t))) { 206 pr_debug("Can't access eop buffer"); 207 return -EFAULT; 208 } 209 210 if (args->ctx_save_restore_address && 211 !access_ok((const void __user *) args->ctx_save_restore_address, 212 sizeof(uint32_t))) { 213 pr_debug("Can't access ctx save restore buffer"); 214 return -EFAULT; 215 } 216 217 q_properties->is_interop = false; 218 q_properties->queue_percent = args->queue_percentage; 219 q_properties->priority = args->queue_priority; 220 q_properties->queue_address = args->ring_base_address; 221 q_properties->queue_size = args->ring_size; 222 q_properties->read_ptr = (uint32_t *) args->read_pointer_address; 223 q_properties->write_ptr = (uint32_t *) args->write_pointer_address; 224 q_properties->eop_ring_buffer_address = args->eop_buffer_address; 225 q_properties->eop_ring_buffer_size = args->eop_buffer_size; 226 q_properties->ctx_save_restore_area_address = 227 args->ctx_save_restore_address; 228 q_properties->ctx_save_restore_area_size = args->ctx_save_restore_size; 229 q_properties->ctl_stack_size = args->ctl_stack_size; 230 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE || 231 args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL) 232 q_properties->type = KFD_QUEUE_TYPE_COMPUTE; 233 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA) 234 q_properties->type = KFD_QUEUE_TYPE_SDMA; 235 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA_XGMI) 236 q_properties->type = KFD_QUEUE_TYPE_SDMA_XGMI; 237 else 238 return -ENOTSUPP; 239 240 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL) 241 q_properties->format = KFD_QUEUE_FORMAT_AQL; 242 else 243 q_properties->format = KFD_QUEUE_FORMAT_PM4; 244 245 pr_debug("Queue Percentage: %d, %d\n", 246 q_properties->queue_percent, args->queue_percentage); 247 248 pr_debug("Queue Priority: %d, %d\n", 249 q_properties->priority, args->queue_priority); 250 251 pr_debug("Queue Address: 0x%llX, 0x%llX\n", 252 q_properties->queue_address, args->ring_base_address); 253 254 pr_debug("Queue Size: 0x%llX, %u\n", 255 q_properties->queue_size, args->ring_size); 256 257 pr_debug("Queue r/w Pointers: %px, %px\n", 258 q_properties->read_ptr, 259 q_properties->write_ptr); 260 261 pr_debug("Queue Format: %d\n", q_properties->format); 262 263 pr_debug("Queue EOP: 0x%llX\n", q_properties->eop_ring_buffer_address); 264 265 pr_debug("Queue CTX save area: 0x%llX\n", 266 q_properties->ctx_save_restore_area_address); 267 268 return 0; 269 } 270 271 static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p, 272 void *data) 273 { 274 struct kfd_ioctl_create_queue_args *args = data; 275 struct kfd_dev *dev; 276 int err = 0; 277 unsigned int queue_id; 278 struct kfd_process_device *pdd; 279 struct queue_properties q_properties; 280 uint32_t doorbell_offset_in_process = 0; 281 282 memset(&q_properties, 0, sizeof(struct queue_properties)); 283 284 pr_debug("Creating queue ioctl\n"); 285 286 err = set_queue_properties_from_user(&q_properties, args); 287 if (err) 288 return err; 289 290 pr_debug("Looking for gpu id 0x%x\n", args->gpu_id); 291 dev = kfd_device_by_id(args->gpu_id); 292 if (!dev) { 293 pr_debug("Could not find gpu id 0x%x\n", args->gpu_id); 294 return -EINVAL; 295 } 296 297 mutex_lock(&p->mutex); 298 299 pdd = kfd_bind_process_to_device(dev, p); 300 if (IS_ERR(pdd)) { 301 err = -ESRCH; 302 goto err_bind_process; 303 } 304 305 pr_debug("Creating queue for PASID 0x%x on gpu 0x%x\n", 306 p->pasid, 307 dev->id); 308 309 err = pqm_create_queue(&p->pqm, dev, filep, &q_properties, &queue_id, 310 &doorbell_offset_in_process); 311 if (err != 0) 312 goto err_create_queue; 313 314 args->queue_id = queue_id; 315 316 317 /* Return gpu_id as doorbell offset for mmap usage */ 318 args->doorbell_offset = KFD_MMAP_TYPE_DOORBELL; 319 args->doorbell_offset |= KFD_MMAP_GPU_ID(args->gpu_id); 320 if (KFD_IS_SOC15(dev->device_info->asic_family)) 321 /* On SOC15 ASICs, include the doorbell offset within the 322 * process doorbell frame, which is 2 pages. 323 */ 324 args->doorbell_offset |= doorbell_offset_in_process; 325 326 mutex_unlock(&p->mutex); 327 328 pr_debug("Queue id %d was created successfully\n", args->queue_id); 329 330 pr_debug("Ring buffer address == 0x%016llX\n", 331 args->ring_base_address); 332 333 pr_debug("Read ptr address == 0x%016llX\n", 334 args->read_pointer_address); 335 336 pr_debug("Write ptr address == 0x%016llX\n", 337 args->write_pointer_address); 338 339 return 0; 340 341 err_create_queue: 342 err_bind_process: 343 mutex_unlock(&p->mutex); 344 return err; 345 } 346 347 static int kfd_ioctl_destroy_queue(struct file *filp, struct kfd_process *p, 348 void *data) 349 { 350 int retval; 351 struct kfd_ioctl_destroy_queue_args *args = data; 352 353 pr_debug("Destroying queue id %d for pasid 0x%x\n", 354 args->queue_id, 355 p->pasid); 356 357 mutex_lock(&p->mutex); 358 359 retval = pqm_destroy_queue(&p->pqm, args->queue_id); 360 361 mutex_unlock(&p->mutex); 362 return retval; 363 } 364 365 static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p, 366 void *data) 367 { 368 int retval; 369 struct kfd_ioctl_update_queue_args *args = data; 370 struct queue_properties properties; 371 372 if (args->queue_percentage > KFD_MAX_QUEUE_PERCENTAGE) { 373 pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n"); 374 return -EINVAL; 375 } 376 377 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) { 378 pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n"); 379 return -EINVAL; 380 } 381 382 if ((args->ring_base_address) && 383 (!access_ok((const void __user *) args->ring_base_address, 384 sizeof(uint64_t)))) { 385 pr_err("Can't access ring base address\n"); 386 return -EFAULT; 387 } 388 389 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) { 390 pr_err("Ring size must be a power of 2 or 0\n"); 391 return -EINVAL; 392 } 393 394 properties.queue_address = args->ring_base_address; 395 properties.queue_size = args->ring_size; 396 properties.queue_percent = args->queue_percentage; 397 properties.priority = args->queue_priority; 398 399 pr_debug("Updating queue id %d for pasid 0x%x\n", 400 args->queue_id, p->pasid); 401 402 mutex_lock(&p->mutex); 403 404 retval = pqm_update_queue(&p->pqm, args->queue_id, &properties); 405 406 mutex_unlock(&p->mutex); 407 408 return retval; 409 } 410 411 static int kfd_ioctl_set_cu_mask(struct file *filp, struct kfd_process *p, 412 void *data) 413 { 414 int retval; 415 const int max_num_cus = 1024; 416 struct kfd_ioctl_set_cu_mask_args *args = data; 417 struct queue_properties properties; 418 uint32_t __user *cu_mask_ptr = (uint32_t __user *)args->cu_mask_ptr; 419 size_t cu_mask_size = sizeof(uint32_t) * (args->num_cu_mask / 32); 420 421 if ((args->num_cu_mask % 32) != 0) { 422 pr_debug("num_cu_mask 0x%x must be a multiple of 32", 423 args->num_cu_mask); 424 return -EINVAL; 425 } 426 427 properties.cu_mask_count = args->num_cu_mask; 428 if (properties.cu_mask_count == 0) { 429 pr_debug("CU mask cannot be 0"); 430 return -EINVAL; 431 } 432 433 /* To prevent an unreasonably large CU mask size, set an arbitrary 434 * limit of max_num_cus bits. We can then just drop any CU mask bits 435 * past max_num_cus bits and just use the first max_num_cus bits. 436 */ 437 if (properties.cu_mask_count > max_num_cus) { 438 pr_debug("CU mask cannot be greater than 1024 bits"); 439 properties.cu_mask_count = max_num_cus; 440 cu_mask_size = sizeof(uint32_t) * (max_num_cus/32); 441 } 442 443 properties.cu_mask = kzalloc(cu_mask_size, GFP_KERNEL); 444 if (!properties.cu_mask) 445 return -ENOMEM; 446 447 retval = copy_from_user(properties.cu_mask, cu_mask_ptr, cu_mask_size); 448 if (retval) { 449 pr_debug("Could not copy CU mask from userspace"); 450 kfree(properties.cu_mask); 451 return -EFAULT; 452 } 453 454 mutex_lock(&p->mutex); 455 456 retval = pqm_set_cu_mask(&p->pqm, args->queue_id, &properties); 457 458 mutex_unlock(&p->mutex); 459 460 if (retval) 461 kfree(properties.cu_mask); 462 463 return retval; 464 } 465 466 static int kfd_ioctl_get_queue_wave_state(struct file *filep, 467 struct kfd_process *p, void *data) 468 { 469 struct kfd_ioctl_get_queue_wave_state_args *args = data; 470 int r; 471 472 mutex_lock(&p->mutex); 473 474 r = pqm_get_wave_state(&p->pqm, args->queue_id, 475 (void __user *)args->ctl_stack_address, 476 &args->ctl_stack_used_size, 477 &args->save_area_used_size); 478 479 mutex_unlock(&p->mutex); 480 481 return r; 482 } 483 484 static int kfd_ioctl_set_memory_policy(struct file *filep, 485 struct kfd_process *p, void *data) 486 { 487 struct kfd_ioctl_set_memory_policy_args *args = data; 488 struct kfd_dev *dev; 489 int err = 0; 490 struct kfd_process_device *pdd; 491 enum cache_policy default_policy, alternate_policy; 492 493 if (args->default_policy != KFD_IOC_CACHE_POLICY_COHERENT 494 && args->default_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) { 495 return -EINVAL; 496 } 497 498 if (args->alternate_policy != KFD_IOC_CACHE_POLICY_COHERENT 499 && args->alternate_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) { 500 return -EINVAL; 501 } 502 503 dev = kfd_device_by_id(args->gpu_id); 504 if (!dev) 505 return -EINVAL; 506 507 mutex_lock(&p->mutex); 508 509 pdd = kfd_bind_process_to_device(dev, p); 510 if (IS_ERR(pdd)) { 511 err = -ESRCH; 512 goto out; 513 } 514 515 default_policy = (args->default_policy == KFD_IOC_CACHE_POLICY_COHERENT) 516 ? cache_policy_coherent : cache_policy_noncoherent; 517 518 alternate_policy = 519 (args->alternate_policy == KFD_IOC_CACHE_POLICY_COHERENT) 520 ? cache_policy_coherent : cache_policy_noncoherent; 521 522 if (!dev->dqm->ops.set_cache_memory_policy(dev->dqm, 523 &pdd->qpd, 524 default_policy, 525 alternate_policy, 526 (void __user *)args->alternate_aperture_base, 527 args->alternate_aperture_size)) 528 err = -EINVAL; 529 530 out: 531 mutex_unlock(&p->mutex); 532 533 return err; 534 } 535 536 static int kfd_ioctl_set_trap_handler(struct file *filep, 537 struct kfd_process *p, void *data) 538 { 539 struct kfd_ioctl_set_trap_handler_args *args = data; 540 struct kfd_dev *dev; 541 int err = 0; 542 struct kfd_process_device *pdd; 543 544 dev = kfd_device_by_id(args->gpu_id); 545 if (!dev) 546 return -EINVAL; 547 548 mutex_lock(&p->mutex); 549 550 pdd = kfd_bind_process_to_device(dev, p); 551 if (IS_ERR(pdd)) { 552 err = -ESRCH; 553 goto out; 554 } 555 556 if (dev->dqm->ops.set_trap_handler(dev->dqm, 557 &pdd->qpd, 558 args->tba_addr, 559 args->tma_addr)) 560 err = -EINVAL; 561 562 out: 563 mutex_unlock(&p->mutex); 564 565 return err; 566 } 567 568 static int kfd_ioctl_dbg_register(struct file *filep, 569 struct kfd_process *p, void *data) 570 { 571 struct kfd_ioctl_dbg_register_args *args = data; 572 struct kfd_dev *dev; 573 struct kfd_dbgmgr *dbgmgr_ptr; 574 struct kfd_process_device *pdd; 575 bool create_ok; 576 long status = 0; 577 578 dev = kfd_device_by_id(args->gpu_id); 579 if (!dev) 580 return -EINVAL; 581 582 if (dev->device_info->asic_family == CHIP_CARRIZO) { 583 pr_debug("kfd_ioctl_dbg_register not supported on CZ\n"); 584 return -EINVAL; 585 } 586 587 mutex_lock(&p->mutex); 588 mutex_lock(kfd_get_dbgmgr_mutex()); 589 590 /* 591 * make sure that we have pdd, if this the first queue created for 592 * this process 593 */ 594 pdd = kfd_bind_process_to_device(dev, p); 595 if (IS_ERR(pdd)) { 596 status = PTR_ERR(pdd); 597 goto out; 598 } 599 600 if (!dev->dbgmgr) { 601 /* In case of a legal call, we have no dbgmgr yet */ 602 create_ok = kfd_dbgmgr_create(&dbgmgr_ptr, dev); 603 if (create_ok) { 604 status = kfd_dbgmgr_register(dbgmgr_ptr, p); 605 if (status != 0) 606 kfd_dbgmgr_destroy(dbgmgr_ptr); 607 else 608 dev->dbgmgr = dbgmgr_ptr; 609 } 610 } else { 611 pr_debug("debugger already registered\n"); 612 status = -EINVAL; 613 } 614 615 out: 616 mutex_unlock(kfd_get_dbgmgr_mutex()); 617 mutex_unlock(&p->mutex); 618 619 return status; 620 } 621 622 static int kfd_ioctl_dbg_unregister(struct file *filep, 623 struct kfd_process *p, void *data) 624 { 625 struct kfd_ioctl_dbg_unregister_args *args = data; 626 struct kfd_dev *dev; 627 long status; 628 629 dev = kfd_device_by_id(args->gpu_id); 630 if (!dev || !dev->dbgmgr) 631 return -EINVAL; 632 633 if (dev->device_info->asic_family == CHIP_CARRIZO) { 634 pr_debug("kfd_ioctl_dbg_unregister not supported on CZ\n"); 635 return -EINVAL; 636 } 637 638 mutex_lock(kfd_get_dbgmgr_mutex()); 639 640 status = kfd_dbgmgr_unregister(dev->dbgmgr, p); 641 if (!status) { 642 kfd_dbgmgr_destroy(dev->dbgmgr); 643 dev->dbgmgr = NULL; 644 } 645 646 mutex_unlock(kfd_get_dbgmgr_mutex()); 647 648 return status; 649 } 650 651 /* 652 * Parse and generate variable size data structure for address watch. 653 * Total size of the buffer and # watch points is limited in order 654 * to prevent kernel abuse. (no bearing to the much smaller HW limitation 655 * which is enforced by dbgdev module) 656 * please also note that the watch address itself are not "copied from user", 657 * since it be set into the HW in user mode values. 658 * 659 */ 660 static int kfd_ioctl_dbg_address_watch(struct file *filep, 661 struct kfd_process *p, void *data) 662 { 663 struct kfd_ioctl_dbg_address_watch_args *args = data; 664 struct kfd_dev *dev; 665 struct dbg_address_watch_info aw_info; 666 unsigned char *args_buff; 667 long status; 668 void __user *cmd_from_user; 669 uint64_t watch_mask_value = 0; 670 unsigned int args_idx = 0; 671 672 memset((void *) &aw_info, 0, sizeof(struct dbg_address_watch_info)); 673 674 dev = kfd_device_by_id(args->gpu_id); 675 if (!dev) 676 return -EINVAL; 677 678 if (dev->device_info->asic_family == CHIP_CARRIZO) { 679 pr_debug("kfd_ioctl_dbg_wave_control not supported on CZ\n"); 680 return -EINVAL; 681 } 682 683 cmd_from_user = (void __user *) args->content_ptr; 684 685 /* Validate arguments */ 686 687 if ((args->buf_size_in_bytes > MAX_ALLOWED_AW_BUFF_SIZE) || 688 (args->buf_size_in_bytes <= sizeof(*args) + sizeof(int) * 2) || 689 (cmd_from_user == NULL)) 690 return -EINVAL; 691 692 /* this is the actual buffer to work with */ 693 args_buff = memdup_user(cmd_from_user, 694 args->buf_size_in_bytes - sizeof(*args)); 695 if (IS_ERR(args_buff)) 696 return PTR_ERR(args_buff); 697 698 aw_info.process = p; 699 700 aw_info.num_watch_points = *((uint32_t *)(&args_buff[args_idx])); 701 args_idx += sizeof(aw_info.num_watch_points); 702 703 aw_info.watch_mode = (enum HSA_DBG_WATCH_MODE *) &args_buff[args_idx]; 704 args_idx += sizeof(enum HSA_DBG_WATCH_MODE) * aw_info.num_watch_points; 705 706 /* 707 * set watch address base pointer to point on the array base 708 * within args_buff 709 */ 710 aw_info.watch_address = (uint64_t *) &args_buff[args_idx]; 711 712 /* skip over the addresses buffer */ 713 args_idx += sizeof(aw_info.watch_address) * aw_info.num_watch_points; 714 715 if (args_idx >= args->buf_size_in_bytes - sizeof(*args)) { 716 status = -EINVAL; 717 goto out; 718 } 719 720 watch_mask_value = (uint64_t) args_buff[args_idx]; 721 722 if (watch_mask_value > 0) { 723 /* 724 * There is an array of masks. 725 * set watch mask base pointer to point on the array base 726 * within args_buff 727 */ 728 aw_info.watch_mask = (uint64_t *) &args_buff[args_idx]; 729 730 /* skip over the masks buffer */ 731 args_idx += sizeof(aw_info.watch_mask) * 732 aw_info.num_watch_points; 733 } else { 734 /* just the NULL mask, set to NULL and skip over it */ 735 aw_info.watch_mask = NULL; 736 args_idx += sizeof(aw_info.watch_mask); 737 } 738 739 if (args_idx >= args->buf_size_in_bytes - sizeof(args)) { 740 status = -EINVAL; 741 goto out; 742 } 743 744 /* Currently HSA Event is not supported for DBG */ 745 aw_info.watch_event = NULL; 746 747 mutex_lock(kfd_get_dbgmgr_mutex()); 748 749 status = kfd_dbgmgr_address_watch(dev->dbgmgr, &aw_info); 750 751 mutex_unlock(kfd_get_dbgmgr_mutex()); 752 753 out: 754 kfree(args_buff); 755 756 return status; 757 } 758 759 /* Parse and generate fixed size data structure for wave control */ 760 static int kfd_ioctl_dbg_wave_control(struct file *filep, 761 struct kfd_process *p, void *data) 762 { 763 struct kfd_ioctl_dbg_wave_control_args *args = data; 764 struct kfd_dev *dev; 765 struct dbg_wave_control_info wac_info; 766 unsigned char *args_buff; 767 uint32_t computed_buff_size; 768 long status; 769 void __user *cmd_from_user; 770 unsigned int args_idx = 0; 771 772 memset((void *) &wac_info, 0, sizeof(struct dbg_wave_control_info)); 773 774 /* we use compact form, independent of the packing attribute value */ 775 computed_buff_size = sizeof(*args) + 776 sizeof(wac_info.mode) + 777 sizeof(wac_info.operand) + 778 sizeof(wac_info.dbgWave_msg.DbgWaveMsg) + 779 sizeof(wac_info.dbgWave_msg.MemoryVA) + 780 sizeof(wac_info.trapId); 781 782 dev = kfd_device_by_id(args->gpu_id); 783 if (!dev) 784 return -EINVAL; 785 786 if (dev->device_info->asic_family == CHIP_CARRIZO) { 787 pr_debug("kfd_ioctl_dbg_wave_control not supported on CZ\n"); 788 return -EINVAL; 789 } 790 791 /* input size must match the computed "compact" size */ 792 if (args->buf_size_in_bytes != computed_buff_size) { 793 pr_debug("size mismatch, computed : actual %u : %u\n", 794 args->buf_size_in_bytes, computed_buff_size); 795 return -EINVAL; 796 } 797 798 cmd_from_user = (void __user *) args->content_ptr; 799 800 if (cmd_from_user == NULL) 801 return -EINVAL; 802 803 /* copy the entire buffer from user */ 804 805 args_buff = memdup_user(cmd_from_user, 806 args->buf_size_in_bytes - sizeof(*args)); 807 if (IS_ERR(args_buff)) 808 return PTR_ERR(args_buff); 809 810 /* move ptr to the start of the "pay-load" area */ 811 wac_info.process = p; 812 813 wac_info.operand = *((enum HSA_DBG_WAVEOP *)(&args_buff[args_idx])); 814 args_idx += sizeof(wac_info.operand); 815 816 wac_info.mode = *((enum HSA_DBG_WAVEMODE *)(&args_buff[args_idx])); 817 args_idx += sizeof(wac_info.mode); 818 819 wac_info.trapId = *((uint32_t *)(&args_buff[args_idx])); 820 args_idx += sizeof(wac_info.trapId); 821 822 wac_info.dbgWave_msg.DbgWaveMsg.WaveMsgInfoGen2.Value = 823 *((uint32_t *)(&args_buff[args_idx])); 824 wac_info.dbgWave_msg.MemoryVA = NULL; 825 826 mutex_lock(kfd_get_dbgmgr_mutex()); 827 828 pr_debug("Calling dbg manager process %p, operand %u, mode %u, trapId %u, message %u\n", 829 wac_info.process, wac_info.operand, 830 wac_info.mode, wac_info.trapId, 831 wac_info.dbgWave_msg.DbgWaveMsg.WaveMsgInfoGen2.Value); 832 833 status = kfd_dbgmgr_wave_control(dev->dbgmgr, &wac_info); 834 835 pr_debug("Returned status of dbg manager is %ld\n", status); 836 837 mutex_unlock(kfd_get_dbgmgr_mutex()); 838 839 kfree(args_buff); 840 841 return status; 842 } 843 844 static int kfd_ioctl_get_clock_counters(struct file *filep, 845 struct kfd_process *p, void *data) 846 { 847 struct kfd_ioctl_get_clock_counters_args *args = data; 848 struct kfd_dev *dev; 849 850 dev = kfd_device_by_id(args->gpu_id); 851 if (dev) 852 /* Reading GPU clock counter from KGD */ 853 args->gpu_clock_counter = amdgpu_amdkfd_get_gpu_clock_counter(dev->kgd); 854 else 855 /* Node without GPU resource */ 856 args->gpu_clock_counter = 0; 857 858 /* No access to rdtsc. Using raw monotonic time */ 859 args->cpu_clock_counter = ktime_get_raw_ns(); 860 args->system_clock_counter = ktime_get_boottime_ns(); 861 862 /* Since the counter is in nano-seconds we use 1GHz frequency */ 863 args->system_clock_freq = 1000000000; 864 865 return 0; 866 } 867 868 869 static int kfd_ioctl_get_process_apertures(struct file *filp, 870 struct kfd_process *p, void *data) 871 { 872 struct kfd_ioctl_get_process_apertures_args *args = data; 873 struct kfd_process_device_apertures *pAperture; 874 struct kfd_process_device *pdd; 875 876 dev_dbg(kfd_device, "get apertures for PASID 0x%x", p->pasid); 877 878 args->num_of_nodes = 0; 879 880 mutex_lock(&p->mutex); 881 882 /*if the process-device list isn't empty*/ 883 if (kfd_has_process_device_data(p)) { 884 /* Run over all pdd of the process */ 885 pdd = kfd_get_first_process_device_data(p); 886 do { 887 pAperture = 888 &args->process_apertures[args->num_of_nodes]; 889 pAperture->gpu_id = pdd->dev->id; 890 pAperture->lds_base = pdd->lds_base; 891 pAperture->lds_limit = pdd->lds_limit; 892 pAperture->gpuvm_base = pdd->gpuvm_base; 893 pAperture->gpuvm_limit = pdd->gpuvm_limit; 894 pAperture->scratch_base = pdd->scratch_base; 895 pAperture->scratch_limit = pdd->scratch_limit; 896 897 dev_dbg(kfd_device, 898 "node id %u\n", args->num_of_nodes); 899 dev_dbg(kfd_device, 900 "gpu id %u\n", pdd->dev->id); 901 dev_dbg(kfd_device, 902 "lds_base %llX\n", pdd->lds_base); 903 dev_dbg(kfd_device, 904 "lds_limit %llX\n", pdd->lds_limit); 905 dev_dbg(kfd_device, 906 "gpuvm_base %llX\n", pdd->gpuvm_base); 907 dev_dbg(kfd_device, 908 "gpuvm_limit %llX\n", pdd->gpuvm_limit); 909 dev_dbg(kfd_device, 910 "scratch_base %llX\n", pdd->scratch_base); 911 dev_dbg(kfd_device, 912 "scratch_limit %llX\n", pdd->scratch_limit); 913 914 args->num_of_nodes++; 915 916 pdd = kfd_get_next_process_device_data(p, pdd); 917 } while (pdd && (args->num_of_nodes < NUM_OF_SUPPORTED_GPUS)); 918 } 919 920 mutex_unlock(&p->mutex); 921 922 return 0; 923 } 924 925 static int kfd_ioctl_get_process_apertures_new(struct file *filp, 926 struct kfd_process *p, void *data) 927 { 928 struct kfd_ioctl_get_process_apertures_new_args *args = data; 929 struct kfd_process_device_apertures *pa; 930 struct kfd_process_device *pdd; 931 uint32_t nodes = 0; 932 int ret; 933 934 dev_dbg(kfd_device, "get apertures for PASID 0x%x", p->pasid); 935 936 if (args->num_of_nodes == 0) { 937 /* Return number of nodes, so that user space can alloacate 938 * sufficient memory 939 */ 940 mutex_lock(&p->mutex); 941 942 if (!kfd_has_process_device_data(p)) 943 goto out_unlock; 944 945 /* Run over all pdd of the process */ 946 pdd = kfd_get_first_process_device_data(p); 947 do { 948 args->num_of_nodes++; 949 pdd = kfd_get_next_process_device_data(p, pdd); 950 } while (pdd); 951 952 goto out_unlock; 953 } 954 955 /* Fill in process-aperture information for all available 956 * nodes, but not more than args->num_of_nodes as that is 957 * the amount of memory allocated by user 958 */ 959 pa = kzalloc((sizeof(struct kfd_process_device_apertures) * 960 args->num_of_nodes), GFP_KERNEL); 961 if (!pa) 962 return -ENOMEM; 963 964 mutex_lock(&p->mutex); 965 966 if (!kfd_has_process_device_data(p)) { 967 args->num_of_nodes = 0; 968 kfree(pa); 969 goto out_unlock; 970 } 971 972 /* Run over all pdd of the process */ 973 pdd = kfd_get_first_process_device_data(p); 974 do { 975 pa[nodes].gpu_id = pdd->dev->id; 976 pa[nodes].lds_base = pdd->lds_base; 977 pa[nodes].lds_limit = pdd->lds_limit; 978 pa[nodes].gpuvm_base = pdd->gpuvm_base; 979 pa[nodes].gpuvm_limit = pdd->gpuvm_limit; 980 pa[nodes].scratch_base = pdd->scratch_base; 981 pa[nodes].scratch_limit = pdd->scratch_limit; 982 983 dev_dbg(kfd_device, 984 "gpu id %u\n", pdd->dev->id); 985 dev_dbg(kfd_device, 986 "lds_base %llX\n", pdd->lds_base); 987 dev_dbg(kfd_device, 988 "lds_limit %llX\n", pdd->lds_limit); 989 dev_dbg(kfd_device, 990 "gpuvm_base %llX\n", pdd->gpuvm_base); 991 dev_dbg(kfd_device, 992 "gpuvm_limit %llX\n", pdd->gpuvm_limit); 993 dev_dbg(kfd_device, 994 "scratch_base %llX\n", pdd->scratch_base); 995 dev_dbg(kfd_device, 996 "scratch_limit %llX\n", pdd->scratch_limit); 997 nodes++; 998 999 pdd = kfd_get_next_process_device_data(p, pdd); 1000 } while (pdd && (nodes < args->num_of_nodes)); 1001 mutex_unlock(&p->mutex); 1002 1003 args->num_of_nodes = nodes; 1004 ret = copy_to_user( 1005 (void __user *)args->kfd_process_device_apertures_ptr, 1006 pa, 1007 (nodes * sizeof(struct kfd_process_device_apertures))); 1008 kfree(pa); 1009 return ret ? -EFAULT : 0; 1010 1011 out_unlock: 1012 mutex_unlock(&p->mutex); 1013 return 0; 1014 } 1015 1016 static int kfd_ioctl_create_event(struct file *filp, struct kfd_process *p, 1017 void *data) 1018 { 1019 struct kfd_ioctl_create_event_args *args = data; 1020 int err; 1021 1022 /* For dGPUs the event page is allocated in user mode. The 1023 * handle is passed to KFD with the first call to this IOCTL 1024 * through the event_page_offset field. 1025 */ 1026 if (args->event_page_offset) { 1027 struct kfd_dev *kfd; 1028 struct kfd_process_device *pdd; 1029 void *mem, *kern_addr; 1030 uint64_t size; 1031 1032 if (p->signal_page) { 1033 pr_err("Event page is already set\n"); 1034 return -EINVAL; 1035 } 1036 1037 kfd = kfd_device_by_id(GET_GPU_ID(args->event_page_offset)); 1038 if (!kfd) { 1039 pr_err("Getting device by id failed in %s\n", __func__); 1040 return -EINVAL; 1041 } 1042 1043 mutex_lock(&p->mutex); 1044 pdd = kfd_bind_process_to_device(kfd, p); 1045 if (IS_ERR(pdd)) { 1046 err = PTR_ERR(pdd); 1047 goto out_unlock; 1048 } 1049 1050 mem = kfd_process_device_translate_handle(pdd, 1051 GET_IDR_HANDLE(args->event_page_offset)); 1052 if (!mem) { 1053 pr_err("Can't find BO, offset is 0x%llx\n", 1054 args->event_page_offset); 1055 err = -EINVAL; 1056 goto out_unlock; 1057 } 1058 mutex_unlock(&p->mutex); 1059 1060 err = amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(kfd->kgd, 1061 mem, &kern_addr, &size); 1062 if (err) { 1063 pr_err("Failed to map event page to kernel\n"); 1064 return err; 1065 } 1066 1067 err = kfd_event_page_set(p, kern_addr, size); 1068 if (err) { 1069 pr_err("Failed to set event page\n"); 1070 return err; 1071 } 1072 } 1073 1074 err = kfd_event_create(filp, p, args->event_type, 1075 args->auto_reset != 0, args->node_id, 1076 &args->event_id, &args->event_trigger_data, 1077 &args->event_page_offset, 1078 &args->event_slot_index); 1079 1080 return err; 1081 1082 out_unlock: 1083 mutex_unlock(&p->mutex); 1084 return err; 1085 } 1086 1087 static int kfd_ioctl_destroy_event(struct file *filp, struct kfd_process *p, 1088 void *data) 1089 { 1090 struct kfd_ioctl_destroy_event_args *args = data; 1091 1092 return kfd_event_destroy(p, args->event_id); 1093 } 1094 1095 static int kfd_ioctl_set_event(struct file *filp, struct kfd_process *p, 1096 void *data) 1097 { 1098 struct kfd_ioctl_set_event_args *args = data; 1099 1100 return kfd_set_event(p, args->event_id); 1101 } 1102 1103 static int kfd_ioctl_reset_event(struct file *filp, struct kfd_process *p, 1104 void *data) 1105 { 1106 struct kfd_ioctl_reset_event_args *args = data; 1107 1108 return kfd_reset_event(p, args->event_id); 1109 } 1110 1111 static int kfd_ioctl_wait_events(struct file *filp, struct kfd_process *p, 1112 void *data) 1113 { 1114 struct kfd_ioctl_wait_events_args *args = data; 1115 int err; 1116 1117 err = kfd_wait_on_events(p, args->num_events, 1118 (void __user *)args->events_ptr, 1119 (args->wait_for_all != 0), 1120 args->timeout, &args->wait_result); 1121 1122 return err; 1123 } 1124 static int kfd_ioctl_set_scratch_backing_va(struct file *filep, 1125 struct kfd_process *p, void *data) 1126 { 1127 struct kfd_ioctl_set_scratch_backing_va_args *args = data; 1128 struct kfd_process_device *pdd; 1129 struct kfd_dev *dev; 1130 long err; 1131 1132 dev = kfd_device_by_id(args->gpu_id); 1133 if (!dev) 1134 return -EINVAL; 1135 1136 mutex_lock(&p->mutex); 1137 1138 pdd = kfd_bind_process_to_device(dev, p); 1139 if (IS_ERR(pdd)) { 1140 err = PTR_ERR(pdd); 1141 goto bind_process_to_device_fail; 1142 } 1143 1144 pdd->qpd.sh_hidden_private_base = args->va_addr; 1145 1146 mutex_unlock(&p->mutex); 1147 1148 if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS && 1149 pdd->qpd.vmid != 0 && dev->kfd2kgd->set_scratch_backing_va) 1150 dev->kfd2kgd->set_scratch_backing_va( 1151 dev->kgd, args->va_addr, pdd->qpd.vmid); 1152 1153 return 0; 1154 1155 bind_process_to_device_fail: 1156 mutex_unlock(&p->mutex); 1157 return err; 1158 } 1159 1160 static int kfd_ioctl_get_tile_config(struct file *filep, 1161 struct kfd_process *p, void *data) 1162 { 1163 struct kfd_ioctl_get_tile_config_args *args = data; 1164 struct kfd_dev *dev; 1165 struct tile_config config; 1166 int err = 0; 1167 1168 dev = kfd_device_by_id(args->gpu_id); 1169 if (!dev) 1170 return -EINVAL; 1171 1172 amdgpu_amdkfd_get_tile_config(dev->kgd, &config); 1173 1174 args->gb_addr_config = config.gb_addr_config; 1175 args->num_banks = config.num_banks; 1176 args->num_ranks = config.num_ranks; 1177 1178 if (args->num_tile_configs > config.num_tile_configs) 1179 args->num_tile_configs = config.num_tile_configs; 1180 err = copy_to_user((void __user *)args->tile_config_ptr, 1181 config.tile_config_ptr, 1182 args->num_tile_configs * sizeof(uint32_t)); 1183 if (err) { 1184 args->num_tile_configs = 0; 1185 return -EFAULT; 1186 } 1187 1188 if (args->num_macro_tile_configs > config.num_macro_tile_configs) 1189 args->num_macro_tile_configs = 1190 config.num_macro_tile_configs; 1191 err = copy_to_user((void __user *)args->macro_tile_config_ptr, 1192 config.macro_tile_config_ptr, 1193 args->num_macro_tile_configs * sizeof(uint32_t)); 1194 if (err) { 1195 args->num_macro_tile_configs = 0; 1196 return -EFAULT; 1197 } 1198 1199 return 0; 1200 } 1201 1202 static int kfd_ioctl_acquire_vm(struct file *filep, struct kfd_process *p, 1203 void *data) 1204 { 1205 struct kfd_ioctl_acquire_vm_args *args = data; 1206 struct kfd_process_device *pdd; 1207 struct kfd_dev *dev; 1208 struct file *drm_file; 1209 int ret; 1210 1211 dev = kfd_device_by_id(args->gpu_id); 1212 if (!dev) 1213 return -EINVAL; 1214 1215 drm_file = fget(args->drm_fd); 1216 if (!drm_file) 1217 return -EINVAL; 1218 1219 mutex_lock(&p->mutex); 1220 1221 pdd = kfd_get_process_device_data(dev, p); 1222 if (!pdd) { 1223 ret = -EINVAL; 1224 goto err_unlock; 1225 } 1226 1227 if (pdd->drm_file) { 1228 ret = pdd->drm_file == drm_file ? 0 : -EBUSY; 1229 goto err_unlock; 1230 } 1231 1232 ret = kfd_process_device_init_vm(pdd, drm_file); 1233 if (ret) 1234 goto err_unlock; 1235 /* On success, the PDD keeps the drm_file reference */ 1236 mutex_unlock(&p->mutex); 1237 1238 return 0; 1239 1240 err_unlock: 1241 mutex_unlock(&p->mutex); 1242 fput(drm_file); 1243 return ret; 1244 } 1245 1246 bool kfd_dev_is_large_bar(struct kfd_dev *dev) 1247 { 1248 struct kfd_local_mem_info mem_info; 1249 1250 if (debug_largebar) { 1251 pr_debug("Simulate large-bar allocation on non large-bar machine\n"); 1252 return true; 1253 } 1254 1255 if (dev->device_info->needs_iommu_device) 1256 return false; 1257 1258 amdgpu_amdkfd_get_local_mem_info(dev->kgd, &mem_info); 1259 if (mem_info.local_mem_size_private == 0 && 1260 mem_info.local_mem_size_public > 0) 1261 return true; 1262 return false; 1263 } 1264 1265 static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, 1266 struct kfd_process *p, void *data) 1267 { 1268 struct kfd_ioctl_alloc_memory_of_gpu_args *args = data; 1269 struct kfd_process_device *pdd; 1270 void *mem; 1271 struct kfd_dev *dev; 1272 int idr_handle; 1273 long err; 1274 uint64_t offset = args->mmap_offset; 1275 uint32_t flags = args->flags; 1276 1277 if (args->size == 0) 1278 return -EINVAL; 1279 1280 dev = kfd_device_by_id(args->gpu_id); 1281 if (!dev) 1282 return -EINVAL; 1283 1284 if ((flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) && 1285 (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) && 1286 !kfd_dev_is_large_bar(dev)) { 1287 pr_err("Alloc host visible vram on small bar is not allowed\n"); 1288 return -EINVAL; 1289 } 1290 1291 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) { 1292 if (args->size != kfd_doorbell_process_slice(dev)) 1293 return -EINVAL; 1294 offset = kfd_get_process_doorbells(dev, p); 1295 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) { 1296 if (args->size != PAGE_SIZE) 1297 return -EINVAL; 1298 offset = amdgpu_amdkfd_get_mmio_remap_phys_addr(dev->kgd); 1299 if (!offset) 1300 return -ENOMEM; 1301 } 1302 1303 mutex_lock(&p->mutex); 1304 1305 pdd = kfd_bind_process_to_device(dev, p); 1306 if (IS_ERR(pdd)) { 1307 err = PTR_ERR(pdd); 1308 goto err_unlock; 1309 } 1310 1311 err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( 1312 dev->kgd, args->va_addr, args->size, 1313 pdd->vm, (struct kgd_mem **) &mem, &offset, 1314 flags); 1315 1316 if (err) 1317 goto err_unlock; 1318 1319 idr_handle = kfd_process_device_create_obj_handle(pdd, mem); 1320 if (idr_handle < 0) { 1321 err = -EFAULT; 1322 goto err_free; 1323 } 1324 1325 mutex_unlock(&p->mutex); 1326 1327 args->handle = MAKE_HANDLE(args->gpu_id, idr_handle); 1328 args->mmap_offset = offset; 1329 1330 /* MMIO is mapped through kfd device 1331 * Generate a kfd mmap offset 1332 */ 1333 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) 1334 args->mmap_offset = KFD_MMAP_TYPE_MMIO 1335 | KFD_MMAP_GPU_ID(args->gpu_id); 1336 1337 return 0; 1338 1339 err_free: 1340 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, (struct kgd_mem *)mem); 1341 err_unlock: 1342 mutex_unlock(&p->mutex); 1343 return err; 1344 } 1345 1346 static int kfd_ioctl_free_memory_of_gpu(struct file *filep, 1347 struct kfd_process *p, void *data) 1348 { 1349 struct kfd_ioctl_free_memory_of_gpu_args *args = data; 1350 struct kfd_process_device *pdd; 1351 void *mem; 1352 struct kfd_dev *dev; 1353 int ret; 1354 1355 dev = kfd_device_by_id(GET_GPU_ID(args->handle)); 1356 if (!dev) 1357 return -EINVAL; 1358 1359 mutex_lock(&p->mutex); 1360 1361 pdd = kfd_get_process_device_data(dev, p); 1362 if (!pdd) { 1363 pr_err("Process device data doesn't exist\n"); 1364 ret = -EINVAL; 1365 goto err_unlock; 1366 } 1367 1368 mem = kfd_process_device_translate_handle( 1369 pdd, GET_IDR_HANDLE(args->handle)); 1370 if (!mem) { 1371 ret = -EINVAL; 1372 goto err_unlock; 1373 } 1374 1375 ret = amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, 1376 (struct kgd_mem *)mem); 1377 1378 /* If freeing the buffer failed, leave the handle in place for 1379 * clean-up during process tear-down. 1380 */ 1381 if (!ret) 1382 kfd_process_device_remove_obj_handle( 1383 pdd, GET_IDR_HANDLE(args->handle)); 1384 1385 err_unlock: 1386 mutex_unlock(&p->mutex); 1387 return ret; 1388 } 1389 1390 static int kfd_ioctl_map_memory_to_gpu(struct file *filep, 1391 struct kfd_process *p, void *data) 1392 { 1393 struct kfd_ioctl_map_memory_to_gpu_args *args = data; 1394 struct kfd_process_device *pdd, *peer_pdd; 1395 void *mem; 1396 struct kfd_dev *dev, *peer; 1397 long err = 0; 1398 int i; 1399 uint32_t *devices_arr = NULL; 1400 1401 dev = kfd_device_by_id(GET_GPU_ID(args->handle)); 1402 if (!dev) 1403 return -EINVAL; 1404 1405 if (!args->n_devices) { 1406 pr_debug("Device IDs array empty\n"); 1407 return -EINVAL; 1408 } 1409 if (args->n_success > args->n_devices) { 1410 pr_debug("n_success exceeds n_devices\n"); 1411 return -EINVAL; 1412 } 1413 1414 devices_arr = kmalloc_array(args->n_devices, sizeof(*devices_arr), 1415 GFP_KERNEL); 1416 if (!devices_arr) 1417 return -ENOMEM; 1418 1419 err = copy_from_user(devices_arr, 1420 (void __user *)args->device_ids_array_ptr, 1421 args->n_devices * sizeof(*devices_arr)); 1422 if (err != 0) { 1423 err = -EFAULT; 1424 goto copy_from_user_failed; 1425 } 1426 1427 mutex_lock(&p->mutex); 1428 1429 pdd = kfd_bind_process_to_device(dev, p); 1430 if (IS_ERR(pdd)) { 1431 err = PTR_ERR(pdd); 1432 goto bind_process_to_device_failed; 1433 } 1434 1435 mem = kfd_process_device_translate_handle(pdd, 1436 GET_IDR_HANDLE(args->handle)); 1437 if (!mem) { 1438 err = -ENOMEM; 1439 goto get_mem_obj_from_handle_failed; 1440 } 1441 1442 for (i = args->n_success; i < args->n_devices; i++) { 1443 peer = kfd_device_by_id(devices_arr[i]); 1444 if (!peer) { 1445 pr_debug("Getting device by id failed for 0x%x\n", 1446 devices_arr[i]); 1447 err = -EINVAL; 1448 goto get_mem_obj_from_handle_failed; 1449 } 1450 1451 peer_pdd = kfd_bind_process_to_device(peer, p); 1452 if (IS_ERR(peer_pdd)) { 1453 err = PTR_ERR(peer_pdd); 1454 goto get_mem_obj_from_handle_failed; 1455 } 1456 err = amdgpu_amdkfd_gpuvm_map_memory_to_gpu( 1457 peer->kgd, (struct kgd_mem *)mem, peer_pdd->vm); 1458 if (err) { 1459 pr_err("Failed to map to gpu %d/%d\n", 1460 i, args->n_devices); 1461 goto map_memory_to_gpu_failed; 1462 } 1463 args->n_success = i+1; 1464 } 1465 1466 mutex_unlock(&p->mutex); 1467 1468 err = amdgpu_amdkfd_gpuvm_sync_memory(dev->kgd, (struct kgd_mem *) mem, true); 1469 if (err) { 1470 pr_debug("Sync memory failed, wait interrupted by user signal\n"); 1471 goto sync_memory_failed; 1472 } 1473 1474 /* Flush TLBs after waiting for the page table updates to complete */ 1475 for (i = 0; i < args->n_devices; i++) { 1476 peer = kfd_device_by_id(devices_arr[i]); 1477 if (WARN_ON_ONCE(!peer)) 1478 continue; 1479 peer_pdd = kfd_get_process_device_data(peer, p); 1480 if (WARN_ON_ONCE(!peer_pdd)) 1481 continue; 1482 kfd_flush_tlb(peer_pdd); 1483 } 1484 1485 kfree(devices_arr); 1486 1487 return err; 1488 1489 bind_process_to_device_failed: 1490 get_mem_obj_from_handle_failed: 1491 map_memory_to_gpu_failed: 1492 mutex_unlock(&p->mutex); 1493 copy_from_user_failed: 1494 sync_memory_failed: 1495 kfree(devices_arr); 1496 1497 return err; 1498 } 1499 1500 static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep, 1501 struct kfd_process *p, void *data) 1502 { 1503 struct kfd_ioctl_unmap_memory_from_gpu_args *args = data; 1504 struct kfd_process_device *pdd, *peer_pdd; 1505 void *mem; 1506 struct kfd_dev *dev, *peer; 1507 long err = 0; 1508 uint32_t *devices_arr = NULL, i; 1509 1510 dev = kfd_device_by_id(GET_GPU_ID(args->handle)); 1511 if (!dev) 1512 return -EINVAL; 1513 1514 if (!args->n_devices) { 1515 pr_debug("Device IDs array empty\n"); 1516 return -EINVAL; 1517 } 1518 if (args->n_success > args->n_devices) { 1519 pr_debug("n_success exceeds n_devices\n"); 1520 return -EINVAL; 1521 } 1522 1523 devices_arr = kmalloc_array(args->n_devices, sizeof(*devices_arr), 1524 GFP_KERNEL); 1525 if (!devices_arr) 1526 return -ENOMEM; 1527 1528 err = copy_from_user(devices_arr, 1529 (void __user *)args->device_ids_array_ptr, 1530 args->n_devices * sizeof(*devices_arr)); 1531 if (err != 0) { 1532 err = -EFAULT; 1533 goto copy_from_user_failed; 1534 } 1535 1536 mutex_lock(&p->mutex); 1537 1538 pdd = kfd_get_process_device_data(dev, p); 1539 if (!pdd) { 1540 err = -EINVAL; 1541 goto bind_process_to_device_failed; 1542 } 1543 1544 mem = kfd_process_device_translate_handle(pdd, 1545 GET_IDR_HANDLE(args->handle)); 1546 if (!mem) { 1547 err = -ENOMEM; 1548 goto get_mem_obj_from_handle_failed; 1549 } 1550 1551 for (i = args->n_success; i < args->n_devices; i++) { 1552 peer = kfd_device_by_id(devices_arr[i]); 1553 if (!peer) { 1554 err = -EINVAL; 1555 goto get_mem_obj_from_handle_failed; 1556 } 1557 1558 peer_pdd = kfd_get_process_device_data(peer, p); 1559 if (!peer_pdd) { 1560 err = -ENODEV; 1561 goto get_mem_obj_from_handle_failed; 1562 } 1563 err = amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( 1564 peer->kgd, (struct kgd_mem *)mem, peer_pdd->vm); 1565 if (err) { 1566 pr_err("Failed to unmap from gpu %d/%d\n", 1567 i, args->n_devices); 1568 goto unmap_memory_from_gpu_failed; 1569 } 1570 args->n_success = i+1; 1571 } 1572 kfree(devices_arr); 1573 1574 mutex_unlock(&p->mutex); 1575 1576 return 0; 1577 1578 bind_process_to_device_failed: 1579 get_mem_obj_from_handle_failed: 1580 unmap_memory_from_gpu_failed: 1581 mutex_unlock(&p->mutex); 1582 copy_from_user_failed: 1583 kfree(devices_arr); 1584 return err; 1585 } 1586 1587 static int kfd_ioctl_get_dmabuf_info(struct file *filep, 1588 struct kfd_process *p, void *data) 1589 { 1590 struct kfd_ioctl_get_dmabuf_info_args *args = data; 1591 struct kfd_dev *dev = NULL; 1592 struct kgd_dev *dma_buf_kgd; 1593 void *metadata_buffer = NULL; 1594 uint32_t flags; 1595 unsigned int i; 1596 int r; 1597 1598 /* Find a KFD GPU device that supports the get_dmabuf_info query */ 1599 for (i = 0; kfd_topology_enum_kfd_devices(i, &dev) == 0; i++) 1600 if (dev) 1601 break; 1602 if (!dev) 1603 return -EINVAL; 1604 1605 if (args->metadata_ptr) { 1606 metadata_buffer = kzalloc(args->metadata_size, GFP_KERNEL); 1607 if (!metadata_buffer) 1608 return -ENOMEM; 1609 } 1610 1611 /* Get dmabuf info from KGD */ 1612 r = amdgpu_amdkfd_get_dmabuf_info(dev->kgd, args->dmabuf_fd, 1613 &dma_buf_kgd, &args->size, 1614 metadata_buffer, args->metadata_size, 1615 &args->metadata_size, &flags); 1616 if (r) 1617 goto exit; 1618 1619 /* Reverse-lookup gpu_id from kgd pointer */ 1620 dev = kfd_device_by_kgd(dma_buf_kgd); 1621 if (!dev) { 1622 r = -EINVAL; 1623 goto exit; 1624 } 1625 args->gpu_id = dev->id; 1626 args->flags = flags; 1627 1628 /* Copy metadata buffer to user mode */ 1629 if (metadata_buffer) { 1630 r = copy_to_user((void __user *)args->metadata_ptr, 1631 metadata_buffer, args->metadata_size); 1632 if (r != 0) 1633 r = -EFAULT; 1634 } 1635 1636 exit: 1637 kfree(metadata_buffer); 1638 1639 return r; 1640 } 1641 1642 static int kfd_ioctl_import_dmabuf(struct file *filep, 1643 struct kfd_process *p, void *data) 1644 { 1645 struct kfd_ioctl_import_dmabuf_args *args = data; 1646 struct kfd_process_device *pdd; 1647 struct dma_buf *dmabuf; 1648 struct kfd_dev *dev; 1649 int idr_handle; 1650 uint64_t size; 1651 void *mem; 1652 int r; 1653 1654 dev = kfd_device_by_id(args->gpu_id); 1655 if (!dev) 1656 return -EINVAL; 1657 1658 dmabuf = dma_buf_get(args->dmabuf_fd); 1659 if (IS_ERR(dmabuf)) 1660 return PTR_ERR(dmabuf); 1661 1662 mutex_lock(&p->mutex); 1663 1664 pdd = kfd_bind_process_to_device(dev, p); 1665 if (IS_ERR(pdd)) { 1666 r = PTR_ERR(pdd); 1667 goto err_unlock; 1668 } 1669 1670 r = amdgpu_amdkfd_gpuvm_import_dmabuf(dev->kgd, dmabuf, 1671 args->va_addr, pdd->vm, 1672 (struct kgd_mem **)&mem, &size, 1673 NULL); 1674 if (r) 1675 goto err_unlock; 1676 1677 idr_handle = kfd_process_device_create_obj_handle(pdd, mem); 1678 if (idr_handle < 0) { 1679 r = -EFAULT; 1680 goto err_free; 1681 } 1682 1683 mutex_unlock(&p->mutex); 1684 1685 args->handle = MAKE_HANDLE(args->gpu_id, idr_handle); 1686 1687 return 0; 1688 1689 err_free: 1690 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, (struct kgd_mem *)mem); 1691 err_unlock: 1692 mutex_unlock(&p->mutex); 1693 return r; 1694 } 1695 1696 #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \ 1697 [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \ 1698 .cmd_drv = 0, .name = #ioctl} 1699 1700 /** Ioctl table */ 1701 static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { 1702 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_VERSION, 1703 kfd_ioctl_get_version, 0), 1704 1705 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_QUEUE, 1706 kfd_ioctl_create_queue, 0), 1707 1708 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_QUEUE, 1709 kfd_ioctl_destroy_queue, 0), 1710 1711 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_MEMORY_POLICY, 1712 kfd_ioctl_set_memory_policy, 0), 1713 1714 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_CLOCK_COUNTERS, 1715 kfd_ioctl_get_clock_counters, 0), 1716 1717 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES, 1718 kfd_ioctl_get_process_apertures, 0), 1719 1720 AMDKFD_IOCTL_DEF(AMDKFD_IOC_UPDATE_QUEUE, 1721 kfd_ioctl_update_queue, 0), 1722 1723 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_EVENT, 1724 kfd_ioctl_create_event, 0), 1725 1726 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_EVENT, 1727 kfd_ioctl_destroy_event, 0), 1728 1729 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_EVENT, 1730 kfd_ioctl_set_event, 0), 1731 1732 AMDKFD_IOCTL_DEF(AMDKFD_IOC_RESET_EVENT, 1733 kfd_ioctl_reset_event, 0), 1734 1735 AMDKFD_IOCTL_DEF(AMDKFD_IOC_WAIT_EVENTS, 1736 kfd_ioctl_wait_events, 0), 1737 1738 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_REGISTER, 1739 kfd_ioctl_dbg_register, 0), 1740 1741 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_UNREGISTER, 1742 kfd_ioctl_dbg_unregister, 0), 1743 1744 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_ADDRESS_WATCH, 1745 kfd_ioctl_dbg_address_watch, 0), 1746 1747 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_WAVE_CONTROL, 1748 kfd_ioctl_dbg_wave_control, 0), 1749 1750 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_SCRATCH_BACKING_VA, 1751 kfd_ioctl_set_scratch_backing_va, 0), 1752 1753 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_TILE_CONFIG, 1754 kfd_ioctl_get_tile_config, 0), 1755 1756 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_TRAP_HANDLER, 1757 kfd_ioctl_set_trap_handler, 0), 1758 1759 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES_NEW, 1760 kfd_ioctl_get_process_apertures_new, 0), 1761 1762 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ACQUIRE_VM, 1763 kfd_ioctl_acquire_vm, 0), 1764 1765 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_MEMORY_OF_GPU, 1766 kfd_ioctl_alloc_memory_of_gpu, 0), 1767 1768 AMDKFD_IOCTL_DEF(AMDKFD_IOC_FREE_MEMORY_OF_GPU, 1769 kfd_ioctl_free_memory_of_gpu, 0), 1770 1771 AMDKFD_IOCTL_DEF(AMDKFD_IOC_MAP_MEMORY_TO_GPU, 1772 kfd_ioctl_map_memory_to_gpu, 0), 1773 1774 AMDKFD_IOCTL_DEF(AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU, 1775 kfd_ioctl_unmap_memory_from_gpu, 0), 1776 1777 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_CU_MASK, 1778 kfd_ioctl_set_cu_mask, 0), 1779 1780 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_QUEUE_WAVE_STATE, 1781 kfd_ioctl_get_queue_wave_state, 0), 1782 1783 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_DMABUF_INFO, 1784 kfd_ioctl_get_dmabuf_info, 0), 1785 1786 AMDKFD_IOCTL_DEF(AMDKFD_IOC_IMPORT_DMABUF, 1787 kfd_ioctl_import_dmabuf, 0), 1788 1789 }; 1790 1791 #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls) 1792 1793 static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) 1794 { 1795 struct kfd_process *process; 1796 amdkfd_ioctl_t *func; 1797 const struct amdkfd_ioctl_desc *ioctl = NULL; 1798 unsigned int nr = _IOC_NR(cmd); 1799 char stack_kdata[128]; 1800 char *kdata = NULL; 1801 unsigned int usize, asize; 1802 int retcode = -EINVAL; 1803 1804 if (nr >= AMDKFD_CORE_IOCTL_COUNT) 1805 goto err_i1; 1806 1807 if ((nr >= AMDKFD_COMMAND_START) && (nr < AMDKFD_COMMAND_END)) { 1808 u32 amdkfd_size; 1809 1810 ioctl = &amdkfd_ioctls[nr]; 1811 1812 amdkfd_size = _IOC_SIZE(ioctl->cmd); 1813 usize = asize = _IOC_SIZE(cmd); 1814 if (amdkfd_size > asize) 1815 asize = amdkfd_size; 1816 1817 cmd = ioctl->cmd; 1818 } else 1819 goto err_i1; 1820 1821 dev_dbg(kfd_device, "ioctl cmd 0x%x (#0x%x), arg 0x%lx\n", cmd, nr, arg); 1822 1823 /* Get the process struct from the filep. Only the process 1824 * that opened /dev/kfd can use the file descriptor. Child 1825 * processes need to create their own KFD device context. 1826 */ 1827 process = filep->private_data; 1828 if (process->lead_thread != current->group_leader) { 1829 dev_dbg(kfd_device, "Using KFD FD in wrong process\n"); 1830 retcode = -EBADF; 1831 goto err_i1; 1832 } 1833 1834 /* Do not trust userspace, use our own definition */ 1835 func = ioctl->func; 1836 1837 if (unlikely(!func)) { 1838 dev_dbg(kfd_device, "no function\n"); 1839 retcode = -EINVAL; 1840 goto err_i1; 1841 } 1842 1843 if (cmd & (IOC_IN | IOC_OUT)) { 1844 if (asize <= sizeof(stack_kdata)) { 1845 kdata = stack_kdata; 1846 } else { 1847 kdata = kmalloc(asize, GFP_KERNEL); 1848 if (!kdata) { 1849 retcode = -ENOMEM; 1850 goto err_i1; 1851 } 1852 } 1853 if (asize > usize) 1854 memset(kdata + usize, 0, asize - usize); 1855 } 1856 1857 if (cmd & IOC_IN) { 1858 if (copy_from_user(kdata, (void __user *)arg, usize) != 0) { 1859 retcode = -EFAULT; 1860 goto err_i1; 1861 } 1862 } else if (cmd & IOC_OUT) { 1863 memset(kdata, 0, usize); 1864 } 1865 1866 retcode = func(filep, process, kdata); 1867 1868 if (cmd & IOC_OUT) 1869 if (copy_to_user((void __user *)arg, kdata, usize) != 0) 1870 retcode = -EFAULT; 1871 1872 err_i1: 1873 if (!ioctl) 1874 dev_dbg(kfd_device, "invalid ioctl: pid=%d, cmd=0x%02x, nr=0x%02x\n", 1875 task_pid_nr(current), cmd, nr); 1876 1877 if (kdata != stack_kdata) 1878 kfree(kdata); 1879 1880 if (retcode) 1881 dev_dbg(kfd_device, "ioctl cmd (#0x%x), arg 0x%lx, ret = %d\n", 1882 nr, arg, retcode); 1883 1884 return retcode; 1885 } 1886 1887 static int kfd_mmio_mmap(struct kfd_dev *dev, struct kfd_process *process, 1888 struct vm_area_struct *vma) 1889 { 1890 phys_addr_t address; 1891 int ret; 1892 1893 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1894 return -EINVAL; 1895 1896 address = amdgpu_amdkfd_get_mmio_remap_phys_addr(dev->kgd); 1897 1898 vma->vm_flags |= VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_NORESERVE | 1899 VM_DONTDUMP | VM_PFNMAP; 1900 1901 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1902 1903 pr_debug("pasid 0x%x mapping mmio page\n" 1904 " target user address == 0x%08llX\n" 1905 " physical address == 0x%08llX\n" 1906 " vm_flags == 0x%04lX\n" 1907 " size == 0x%04lX\n", 1908 process->pasid, (unsigned long long) vma->vm_start, 1909 address, vma->vm_flags, PAGE_SIZE); 1910 1911 ret = io_remap_pfn_range(vma, 1912 vma->vm_start, 1913 address >> PAGE_SHIFT, 1914 PAGE_SIZE, 1915 vma->vm_page_prot); 1916 return ret; 1917 } 1918 1919 1920 static int kfd_mmap(struct file *filp, struct vm_area_struct *vma) 1921 { 1922 struct kfd_process *process; 1923 struct kfd_dev *dev = NULL; 1924 unsigned long mmap_offset; 1925 unsigned int gpu_id; 1926 1927 process = kfd_get_process(current); 1928 if (IS_ERR(process)) 1929 return PTR_ERR(process); 1930 1931 mmap_offset = vma->vm_pgoff << PAGE_SHIFT; 1932 gpu_id = KFD_MMAP_GET_GPU_ID(mmap_offset); 1933 if (gpu_id) 1934 dev = kfd_device_by_id(gpu_id); 1935 1936 switch (mmap_offset & KFD_MMAP_TYPE_MASK) { 1937 case KFD_MMAP_TYPE_DOORBELL: 1938 if (!dev) 1939 return -ENODEV; 1940 return kfd_doorbell_mmap(dev, process, vma); 1941 1942 case KFD_MMAP_TYPE_EVENTS: 1943 return kfd_event_mmap(process, vma); 1944 1945 case KFD_MMAP_TYPE_RESERVED_MEM: 1946 if (!dev) 1947 return -ENODEV; 1948 return kfd_reserved_mem_mmap(dev, process, vma); 1949 case KFD_MMAP_TYPE_MMIO: 1950 if (!dev) 1951 return -ENODEV; 1952 return kfd_mmio_mmap(dev, process, vma); 1953 } 1954 1955 return -EFAULT; 1956 } 1957