1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/device.h> 25 #include <linux/export.h> 26 #include <linux/err.h> 27 #include <linux/fs.h> 28 #include <linux/file.h> 29 #include <linux/sched.h> 30 #include <linux/slab.h> 31 #include <linux/uaccess.h> 32 #include <linux/compat.h> 33 #include <uapi/linux/kfd_ioctl.h> 34 #include <linux/time.h> 35 #include <linux/mm.h> 36 #include <linux/mman.h> 37 #include <linux/ptrace.h> 38 #include <linux/dma-buf.h> 39 #include <linux/fdtable.h> 40 #include <linux/processor.h> 41 #include "kfd_priv.h" 42 #include "kfd_device_queue_manager.h" 43 #include "kfd_svm.h" 44 #include "amdgpu_amdkfd.h" 45 #include "kfd_smi_events.h" 46 #include "amdgpu_dma_buf.h" 47 #include "kfd_debug.h" 48 49 static long kfd_ioctl(struct file *, unsigned int, unsigned long); 50 static int kfd_open(struct inode *, struct file *); 51 static int kfd_release(struct inode *, struct file *); 52 static int kfd_mmap(struct file *, struct vm_area_struct *); 53 54 static const char kfd_dev_name[] = "kfd"; 55 56 static const struct file_operations kfd_fops = { 57 .owner = THIS_MODULE, 58 .unlocked_ioctl = kfd_ioctl, 59 .compat_ioctl = compat_ptr_ioctl, 60 .open = kfd_open, 61 .release = kfd_release, 62 .mmap = kfd_mmap, 63 }; 64 65 static int kfd_char_dev_major = -1; 66 static struct class *kfd_class; 67 struct device *kfd_device; 68 69 static inline struct kfd_process_device *kfd_lock_pdd_by_id(struct kfd_process *p, __u32 gpu_id) 70 { 71 struct kfd_process_device *pdd; 72 73 mutex_lock(&p->mutex); 74 pdd = kfd_process_device_data_by_id(p, gpu_id); 75 76 if (pdd) 77 return pdd; 78 79 mutex_unlock(&p->mutex); 80 return NULL; 81 } 82 83 static inline void kfd_unlock_pdd(struct kfd_process_device *pdd) 84 { 85 mutex_unlock(&pdd->process->mutex); 86 } 87 88 int kfd_chardev_init(void) 89 { 90 int err = 0; 91 92 kfd_char_dev_major = register_chrdev(0, kfd_dev_name, &kfd_fops); 93 err = kfd_char_dev_major; 94 if (err < 0) 95 goto err_register_chrdev; 96 97 kfd_class = class_create(kfd_dev_name); 98 err = PTR_ERR(kfd_class); 99 if (IS_ERR(kfd_class)) 100 goto err_class_create; 101 102 kfd_device = device_create(kfd_class, NULL, 103 MKDEV(kfd_char_dev_major, 0), 104 NULL, kfd_dev_name); 105 err = PTR_ERR(kfd_device); 106 if (IS_ERR(kfd_device)) 107 goto err_device_create; 108 109 return 0; 110 111 err_device_create: 112 class_destroy(kfd_class); 113 err_class_create: 114 unregister_chrdev(kfd_char_dev_major, kfd_dev_name); 115 err_register_chrdev: 116 return err; 117 } 118 119 void kfd_chardev_exit(void) 120 { 121 device_destroy(kfd_class, MKDEV(kfd_char_dev_major, 0)); 122 class_destroy(kfd_class); 123 unregister_chrdev(kfd_char_dev_major, kfd_dev_name); 124 kfd_device = NULL; 125 } 126 127 128 static int kfd_open(struct inode *inode, struct file *filep) 129 { 130 struct kfd_process *process; 131 bool is_32bit_user_mode; 132 133 if (iminor(inode) != 0) 134 return -ENODEV; 135 136 is_32bit_user_mode = in_compat_syscall(); 137 138 if (is_32bit_user_mode) { 139 dev_warn(kfd_device, 140 "Process %d (32-bit) failed to open /dev/kfd\n" 141 "32-bit processes are not supported by amdkfd\n", 142 current->pid); 143 return -EPERM; 144 } 145 146 process = kfd_create_process(current); 147 if (IS_ERR(process)) 148 return PTR_ERR(process); 149 150 if (kfd_process_init_cwsr_apu(process, filep)) { 151 kfd_unref_process(process); 152 return -EFAULT; 153 } 154 155 /* filep now owns the reference returned by kfd_create_process */ 156 filep->private_data = process; 157 158 dev_dbg(kfd_device, "process %d opened, compat mode (32 bit) - %d\n", 159 process->pasid, process->is_32bit_user_mode); 160 161 return 0; 162 } 163 164 static int kfd_release(struct inode *inode, struct file *filep) 165 { 166 struct kfd_process *process = filep->private_data; 167 168 if (process) 169 kfd_unref_process(process); 170 171 return 0; 172 } 173 174 static int kfd_ioctl_get_version(struct file *filep, struct kfd_process *p, 175 void *data) 176 { 177 struct kfd_ioctl_get_version_args *args = data; 178 179 args->major_version = KFD_IOCTL_MAJOR_VERSION; 180 args->minor_version = KFD_IOCTL_MINOR_VERSION; 181 182 return 0; 183 } 184 185 static int set_queue_properties_from_user(struct queue_properties *q_properties, 186 struct kfd_ioctl_create_queue_args *args) 187 { 188 /* 189 * Repurpose queue percentage to accommodate new features: 190 * bit 0-7: queue percentage 191 * bit 8-15: pm4_target_xcc 192 */ 193 if ((args->queue_percentage & 0xFF) > KFD_MAX_QUEUE_PERCENTAGE) { 194 pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n"); 195 return -EINVAL; 196 } 197 198 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) { 199 pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n"); 200 return -EINVAL; 201 } 202 203 if ((args->ring_base_address) && 204 (!access_ok((const void __user *) args->ring_base_address, 205 sizeof(uint64_t)))) { 206 pr_err("Can't access ring base address\n"); 207 return -EFAULT; 208 } 209 210 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) { 211 pr_err("Ring size must be a power of 2 or 0\n"); 212 return -EINVAL; 213 } 214 215 if (!access_ok((const void __user *) args->read_pointer_address, 216 sizeof(uint32_t))) { 217 pr_err("Can't access read pointer\n"); 218 return -EFAULT; 219 } 220 221 if (!access_ok((const void __user *) args->write_pointer_address, 222 sizeof(uint32_t))) { 223 pr_err("Can't access write pointer\n"); 224 return -EFAULT; 225 } 226 227 if (args->eop_buffer_address && 228 !access_ok((const void __user *) args->eop_buffer_address, 229 sizeof(uint32_t))) { 230 pr_debug("Can't access eop buffer"); 231 return -EFAULT; 232 } 233 234 if (args->ctx_save_restore_address && 235 !access_ok((const void __user *) args->ctx_save_restore_address, 236 sizeof(uint32_t))) { 237 pr_debug("Can't access ctx save restore buffer"); 238 return -EFAULT; 239 } 240 241 q_properties->is_interop = false; 242 q_properties->is_gws = false; 243 q_properties->queue_percent = args->queue_percentage & 0xFF; 244 /* bit 8-15 are repurposed to be PM4 target XCC */ 245 q_properties->pm4_target_xcc = (args->queue_percentage >> 8) & 0xFF; 246 q_properties->priority = args->queue_priority; 247 q_properties->queue_address = args->ring_base_address; 248 q_properties->queue_size = args->ring_size; 249 q_properties->read_ptr = (uint32_t *) args->read_pointer_address; 250 q_properties->write_ptr = (uint32_t *) args->write_pointer_address; 251 q_properties->eop_ring_buffer_address = args->eop_buffer_address; 252 q_properties->eop_ring_buffer_size = args->eop_buffer_size; 253 q_properties->ctx_save_restore_area_address = 254 args->ctx_save_restore_address; 255 q_properties->ctx_save_restore_area_size = args->ctx_save_restore_size; 256 q_properties->ctl_stack_size = args->ctl_stack_size; 257 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE || 258 args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL) 259 q_properties->type = KFD_QUEUE_TYPE_COMPUTE; 260 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA) 261 q_properties->type = KFD_QUEUE_TYPE_SDMA; 262 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA_XGMI) 263 q_properties->type = KFD_QUEUE_TYPE_SDMA_XGMI; 264 else 265 return -ENOTSUPP; 266 267 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL) 268 q_properties->format = KFD_QUEUE_FORMAT_AQL; 269 else 270 q_properties->format = KFD_QUEUE_FORMAT_PM4; 271 272 pr_debug("Queue Percentage: %d, %d\n", 273 q_properties->queue_percent, args->queue_percentage); 274 275 pr_debug("Queue Priority: %d, %d\n", 276 q_properties->priority, args->queue_priority); 277 278 pr_debug("Queue Address: 0x%llX, 0x%llX\n", 279 q_properties->queue_address, args->ring_base_address); 280 281 pr_debug("Queue Size: 0x%llX, %u\n", 282 q_properties->queue_size, args->ring_size); 283 284 pr_debug("Queue r/w Pointers: %px, %px\n", 285 q_properties->read_ptr, 286 q_properties->write_ptr); 287 288 pr_debug("Queue Format: %d\n", q_properties->format); 289 290 pr_debug("Queue EOP: 0x%llX\n", q_properties->eop_ring_buffer_address); 291 292 pr_debug("Queue CTX save area: 0x%llX\n", 293 q_properties->ctx_save_restore_area_address); 294 295 return 0; 296 } 297 298 static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p, 299 void *data) 300 { 301 struct kfd_ioctl_create_queue_args *args = data; 302 struct kfd_node *dev; 303 int err = 0; 304 unsigned int queue_id; 305 struct kfd_process_device *pdd; 306 struct queue_properties q_properties; 307 uint32_t doorbell_offset_in_process = 0; 308 struct amdgpu_bo *wptr_bo = NULL; 309 310 memset(&q_properties, 0, sizeof(struct queue_properties)); 311 312 pr_debug("Creating queue ioctl\n"); 313 314 err = set_queue_properties_from_user(&q_properties, args); 315 if (err) 316 return err; 317 318 pr_debug("Looking for gpu id 0x%x\n", args->gpu_id); 319 320 mutex_lock(&p->mutex); 321 322 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 323 if (!pdd) { 324 pr_debug("Could not find gpu id 0x%x\n", args->gpu_id); 325 err = -EINVAL; 326 goto err_pdd; 327 } 328 dev = pdd->dev; 329 330 pdd = kfd_bind_process_to_device(dev, p); 331 if (IS_ERR(pdd)) { 332 err = -ESRCH; 333 goto err_bind_process; 334 } 335 336 if (!pdd->qpd.proc_doorbells) { 337 err = kfd_alloc_process_doorbells(dev->kfd, pdd); 338 if (err) { 339 pr_debug("failed to allocate process doorbells\n"); 340 goto err_bind_process; 341 } 342 } 343 344 /* Starting with GFX11, wptr BOs must be mapped to GART for MES to determine work 345 * on unmapped queues for usermode queue oversubscription (no aggregated doorbell) 346 */ 347 if (dev->kfd->shared_resources.enable_mes && 348 ((dev->adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) 349 >> AMDGPU_MES_API_VERSION_SHIFT) >= 2) { 350 struct amdgpu_bo_va_mapping *wptr_mapping; 351 struct amdgpu_vm *wptr_vm; 352 353 wptr_vm = drm_priv_to_vm(pdd->drm_priv); 354 err = amdgpu_bo_reserve(wptr_vm->root.bo, false); 355 if (err) 356 goto err_wptr_map_gart; 357 358 wptr_mapping = amdgpu_vm_bo_lookup_mapping( 359 wptr_vm, args->write_pointer_address >> PAGE_SHIFT); 360 amdgpu_bo_unreserve(wptr_vm->root.bo); 361 if (!wptr_mapping) { 362 pr_err("Failed to lookup wptr bo\n"); 363 err = -EINVAL; 364 goto err_wptr_map_gart; 365 } 366 367 wptr_bo = wptr_mapping->bo_va->base.bo; 368 if (wptr_bo->tbo.base.size > PAGE_SIZE) { 369 pr_err("Requested GART mapping for wptr bo larger than one page\n"); 370 err = -EINVAL; 371 goto err_wptr_map_gart; 372 } 373 374 err = amdgpu_amdkfd_map_gtt_bo_to_gart(dev->adev, wptr_bo); 375 if (err) { 376 pr_err("Failed to map wptr bo to GART\n"); 377 goto err_wptr_map_gart; 378 } 379 } 380 381 pr_debug("Creating queue for PASID 0x%x on gpu 0x%x\n", 382 p->pasid, 383 dev->id); 384 385 err = pqm_create_queue(&p->pqm, dev, filep, &q_properties, &queue_id, wptr_bo, 386 NULL, NULL, NULL, &doorbell_offset_in_process); 387 if (err != 0) 388 goto err_create_queue; 389 390 args->queue_id = queue_id; 391 392 393 /* Return gpu_id as doorbell offset for mmap usage */ 394 args->doorbell_offset = KFD_MMAP_TYPE_DOORBELL; 395 args->doorbell_offset |= KFD_MMAP_GPU_ID(args->gpu_id); 396 if (KFD_IS_SOC15(dev)) 397 /* On SOC15 ASICs, include the doorbell offset within the 398 * process doorbell frame, which is 2 pages. 399 */ 400 args->doorbell_offset |= doorbell_offset_in_process; 401 402 mutex_unlock(&p->mutex); 403 404 pr_debug("Queue id %d was created successfully\n", args->queue_id); 405 406 pr_debug("Ring buffer address == 0x%016llX\n", 407 args->ring_base_address); 408 409 pr_debug("Read ptr address == 0x%016llX\n", 410 args->read_pointer_address); 411 412 pr_debug("Write ptr address == 0x%016llX\n", 413 args->write_pointer_address); 414 415 kfd_dbg_ev_raise(KFD_EC_MASK(EC_QUEUE_NEW), p, dev, queue_id, false, NULL, 0); 416 return 0; 417 418 err_create_queue: 419 if (wptr_bo) 420 amdgpu_amdkfd_free_gtt_mem(dev->adev, wptr_bo); 421 err_wptr_map_gart: 422 err_bind_process: 423 err_pdd: 424 mutex_unlock(&p->mutex); 425 return err; 426 } 427 428 static int kfd_ioctl_destroy_queue(struct file *filp, struct kfd_process *p, 429 void *data) 430 { 431 int retval; 432 struct kfd_ioctl_destroy_queue_args *args = data; 433 434 pr_debug("Destroying queue id %d for pasid 0x%x\n", 435 args->queue_id, 436 p->pasid); 437 438 mutex_lock(&p->mutex); 439 440 retval = pqm_destroy_queue(&p->pqm, args->queue_id); 441 442 mutex_unlock(&p->mutex); 443 return retval; 444 } 445 446 static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p, 447 void *data) 448 { 449 int retval; 450 struct kfd_ioctl_update_queue_args *args = data; 451 struct queue_properties properties; 452 453 /* 454 * Repurpose queue percentage to accommodate new features: 455 * bit 0-7: queue percentage 456 * bit 8-15: pm4_target_xcc 457 */ 458 if ((args->queue_percentage & 0xFF) > KFD_MAX_QUEUE_PERCENTAGE) { 459 pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n"); 460 return -EINVAL; 461 } 462 463 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) { 464 pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n"); 465 return -EINVAL; 466 } 467 468 if ((args->ring_base_address) && 469 (!access_ok((const void __user *) args->ring_base_address, 470 sizeof(uint64_t)))) { 471 pr_err("Can't access ring base address\n"); 472 return -EFAULT; 473 } 474 475 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) { 476 pr_err("Ring size must be a power of 2 or 0\n"); 477 return -EINVAL; 478 } 479 480 properties.queue_address = args->ring_base_address; 481 properties.queue_size = args->ring_size; 482 properties.queue_percent = args->queue_percentage & 0xFF; 483 /* bit 8-15 are repurposed to be PM4 target XCC */ 484 properties.pm4_target_xcc = (args->queue_percentage >> 8) & 0xFF; 485 properties.priority = args->queue_priority; 486 487 pr_debug("Updating queue id %d for pasid 0x%x\n", 488 args->queue_id, p->pasid); 489 490 mutex_lock(&p->mutex); 491 492 retval = pqm_update_queue_properties(&p->pqm, args->queue_id, &properties); 493 494 mutex_unlock(&p->mutex); 495 496 return retval; 497 } 498 499 static int kfd_ioctl_set_cu_mask(struct file *filp, struct kfd_process *p, 500 void *data) 501 { 502 int retval; 503 const int max_num_cus = 1024; 504 struct kfd_ioctl_set_cu_mask_args *args = data; 505 struct mqd_update_info minfo = {0}; 506 uint32_t __user *cu_mask_ptr = (uint32_t __user *)args->cu_mask_ptr; 507 size_t cu_mask_size = sizeof(uint32_t) * (args->num_cu_mask / 32); 508 509 if ((args->num_cu_mask % 32) != 0) { 510 pr_debug("num_cu_mask 0x%x must be a multiple of 32", 511 args->num_cu_mask); 512 return -EINVAL; 513 } 514 515 minfo.cu_mask.count = args->num_cu_mask; 516 if (minfo.cu_mask.count == 0) { 517 pr_debug("CU mask cannot be 0"); 518 return -EINVAL; 519 } 520 521 /* To prevent an unreasonably large CU mask size, set an arbitrary 522 * limit of max_num_cus bits. We can then just drop any CU mask bits 523 * past max_num_cus bits and just use the first max_num_cus bits. 524 */ 525 if (minfo.cu_mask.count > max_num_cus) { 526 pr_debug("CU mask cannot be greater than 1024 bits"); 527 minfo.cu_mask.count = max_num_cus; 528 cu_mask_size = sizeof(uint32_t) * (max_num_cus/32); 529 } 530 531 minfo.cu_mask.ptr = kzalloc(cu_mask_size, GFP_KERNEL); 532 if (!minfo.cu_mask.ptr) 533 return -ENOMEM; 534 535 retval = copy_from_user(minfo.cu_mask.ptr, cu_mask_ptr, cu_mask_size); 536 if (retval) { 537 pr_debug("Could not copy CU mask from userspace"); 538 retval = -EFAULT; 539 goto out; 540 } 541 542 mutex_lock(&p->mutex); 543 544 retval = pqm_update_mqd(&p->pqm, args->queue_id, &minfo); 545 546 mutex_unlock(&p->mutex); 547 548 out: 549 kfree(minfo.cu_mask.ptr); 550 return retval; 551 } 552 553 static int kfd_ioctl_get_queue_wave_state(struct file *filep, 554 struct kfd_process *p, void *data) 555 { 556 struct kfd_ioctl_get_queue_wave_state_args *args = data; 557 int r; 558 559 mutex_lock(&p->mutex); 560 561 r = pqm_get_wave_state(&p->pqm, args->queue_id, 562 (void __user *)args->ctl_stack_address, 563 &args->ctl_stack_used_size, 564 &args->save_area_used_size); 565 566 mutex_unlock(&p->mutex); 567 568 return r; 569 } 570 571 static int kfd_ioctl_set_memory_policy(struct file *filep, 572 struct kfd_process *p, void *data) 573 { 574 struct kfd_ioctl_set_memory_policy_args *args = data; 575 int err = 0; 576 struct kfd_process_device *pdd; 577 enum cache_policy default_policy, alternate_policy; 578 579 if (args->default_policy != KFD_IOC_CACHE_POLICY_COHERENT 580 && args->default_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) { 581 return -EINVAL; 582 } 583 584 if (args->alternate_policy != KFD_IOC_CACHE_POLICY_COHERENT 585 && args->alternate_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) { 586 return -EINVAL; 587 } 588 589 mutex_lock(&p->mutex); 590 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 591 if (!pdd) { 592 pr_debug("Could not find gpu id 0x%x\n", args->gpu_id); 593 err = -EINVAL; 594 goto err_pdd; 595 } 596 597 pdd = kfd_bind_process_to_device(pdd->dev, p); 598 if (IS_ERR(pdd)) { 599 err = -ESRCH; 600 goto out; 601 } 602 603 default_policy = (args->default_policy == KFD_IOC_CACHE_POLICY_COHERENT) 604 ? cache_policy_coherent : cache_policy_noncoherent; 605 606 alternate_policy = 607 (args->alternate_policy == KFD_IOC_CACHE_POLICY_COHERENT) 608 ? cache_policy_coherent : cache_policy_noncoherent; 609 610 if (!pdd->dev->dqm->ops.set_cache_memory_policy(pdd->dev->dqm, 611 &pdd->qpd, 612 default_policy, 613 alternate_policy, 614 (void __user *)args->alternate_aperture_base, 615 args->alternate_aperture_size)) 616 err = -EINVAL; 617 618 out: 619 err_pdd: 620 mutex_unlock(&p->mutex); 621 622 return err; 623 } 624 625 static int kfd_ioctl_set_trap_handler(struct file *filep, 626 struct kfd_process *p, void *data) 627 { 628 struct kfd_ioctl_set_trap_handler_args *args = data; 629 int err = 0; 630 struct kfd_process_device *pdd; 631 632 mutex_lock(&p->mutex); 633 634 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 635 if (!pdd) { 636 err = -EINVAL; 637 goto err_pdd; 638 } 639 640 pdd = kfd_bind_process_to_device(pdd->dev, p); 641 if (IS_ERR(pdd)) { 642 err = -ESRCH; 643 goto out; 644 } 645 646 kfd_process_set_trap_handler(&pdd->qpd, args->tba_addr, args->tma_addr); 647 648 out: 649 err_pdd: 650 mutex_unlock(&p->mutex); 651 652 return err; 653 } 654 655 static int kfd_ioctl_dbg_register(struct file *filep, 656 struct kfd_process *p, void *data) 657 { 658 return -EPERM; 659 } 660 661 static int kfd_ioctl_dbg_unregister(struct file *filep, 662 struct kfd_process *p, void *data) 663 { 664 return -EPERM; 665 } 666 667 static int kfd_ioctl_dbg_address_watch(struct file *filep, 668 struct kfd_process *p, void *data) 669 { 670 return -EPERM; 671 } 672 673 /* Parse and generate fixed size data structure for wave control */ 674 static int kfd_ioctl_dbg_wave_control(struct file *filep, 675 struct kfd_process *p, void *data) 676 { 677 return -EPERM; 678 } 679 680 static int kfd_ioctl_get_clock_counters(struct file *filep, 681 struct kfd_process *p, void *data) 682 { 683 struct kfd_ioctl_get_clock_counters_args *args = data; 684 struct kfd_process_device *pdd; 685 686 mutex_lock(&p->mutex); 687 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 688 mutex_unlock(&p->mutex); 689 if (pdd) 690 /* Reading GPU clock counter from KGD */ 691 args->gpu_clock_counter = amdgpu_amdkfd_get_gpu_clock_counter(pdd->dev->adev); 692 else 693 /* Node without GPU resource */ 694 args->gpu_clock_counter = 0; 695 696 /* No access to rdtsc. Using raw monotonic time */ 697 args->cpu_clock_counter = ktime_get_raw_ns(); 698 args->system_clock_counter = ktime_get_boottime_ns(); 699 700 /* Since the counter is in nano-seconds we use 1GHz frequency */ 701 args->system_clock_freq = 1000000000; 702 703 return 0; 704 } 705 706 707 static int kfd_ioctl_get_process_apertures(struct file *filp, 708 struct kfd_process *p, void *data) 709 { 710 struct kfd_ioctl_get_process_apertures_args *args = data; 711 struct kfd_process_device_apertures *pAperture; 712 int i; 713 714 dev_dbg(kfd_device, "get apertures for PASID 0x%x", p->pasid); 715 716 args->num_of_nodes = 0; 717 718 mutex_lock(&p->mutex); 719 /* Run over all pdd of the process */ 720 for (i = 0; i < p->n_pdds; i++) { 721 struct kfd_process_device *pdd = p->pdds[i]; 722 723 pAperture = 724 &args->process_apertures[args->num_of_nodes]; 725 pAperture->gpu_id = pdd->dev->id; 726 pAperture->lds_base = pdd->lds_base; 727 pAperture->lds_limit = pdd->lds_limit; 728 pAperture->gpuvm_base = pdd->gpuvm_base; 729 pAperture->gpuvm_limit = pdd->gpuvm_limit; 730 pAperture->scratch_base = pdd->scratch_base; 731 pAperture->scratch_limit = pdd->scratch_limit; 732 733 dev_dbg(kfd_device, 734 "node id %u\n", args->num_of_nodes); 735 dev_dbg(kfd_device, 736 "gpu id %u\n", pdd->dev->id); 737 dev_dbg(kfd_device, 738 "lds_base %llX\n", pdd->lds_base); 739 dev_dbg(kfd_device, 740 "lds_limit %llX\n", pdd->lds_limit); 741 dev_dbg(kfd_device, 742 "gpuvm_base %llX\n", pdd->gpuvm_base); 743 dev_dbg(kfd_device, 744 "gpuvm_limit %llX\n", pdd->gpuvm_limit); 745 dev_dbg(kfd_device, 746 "scratch_base %llX\n", pdd->scratch_base); 747 dev_dbg(kfd_device, 748 "scratch_limit %llX\n", pdd->scratch_limit); 749 750 if (++args->num_of_nodes >= NUM_OF_SUPPORTED_GPUS) 751 break; 752 } 753 mutex_unlock(&p->mutex); 754 755 return 0; 756 } 757 758 static int kfd_ioctl_get_process_apertures_new(struct file *filp, 759 struct kfd_process *p, void *data) 760 { 761 struct kfd_ioctl_get_process_apertures_new_args *args = data; 762 struct kfd_process_device_apertures *pa; 763 int ret; 764 int i; 765 766 dev_dbg(kfd_device, "get apertures for PASID 0x%x", p->pasid); 767 768 if (args->num_of_nodes == 0) { 769 /* Return number of nodes, so that user space can alloacate 770 * sufficient memory 771 */ 772 mutex_lock(&p->mutex); 773 args->num_of_nodes = p->n_pdds; 774 goto out_unlock; 775 } 776 777 /* Fill in process-aperture information for all available 778 * nodes, but not more than args->num_of_nodes as that is 779 * the amount of memory allocated by user 780 */ 781 pa = kzalloc((sizeof(struct kfd_process_device_apertures) * 782 args->num_of_nodes), GFP_KERNEL); 783 if (!pa) 784 return -ENOMEM; 785 786 mutex_lock(&p->mutex); 787 788 if (!p->n_pdds) { 789 args->num_of_nodes = 0; 790 kfree(pa); 791 goto out_unlock; 792 } 793 794 /* Run over all pdd of the process */ 795 for (i = 0; i < min(p->n_pdds, args->num_of_nodes); i++) { 796 struct kfd_process_device *pdd = p->pdds[i]; 797 798 pa[i].gpu_id = pdd->dev->id; 799 pa[i].lds_base = pdd->lds_base; 800 pa[i].lds_limit = pdd->lds_limit; 801 pa[i].gpuvm_base = pdd->gpuvm_base; 802 pa[i].gpuvm_limit = pdd->gpuvm_limit; 803 pa[i].scratch_base = pdd->scratch_base; 804 pa[i].scratch_limit = pdd->scratch_limit; 805 806 dev_dbg(kfd_device, 807 "gpu id %u\n", pdd->dev->id); 808 dev_dbg(kfd_device, 809 "lds_base %llX\n", pdd->lds_base); 810 dev_dbg(kfd_device, 811 "lds_limit %llX\n", pdd->lds_limit); 812 dev_dbg(kfd_device, 813 "gpuvm_base %llX\n", pdd->gpuvm_base); 814 dev_dbg(kfd_device, 815 "gpuvm_limit %llX\n", pdd->gpuvm_limit); 816 dev_dbg(kfd_device, 817 "scratch_base %llX\n", pdd->scratch_base); 818 dev_dbg(kfd_device, 819 "scratch_limit %llX\n", pdd->scratch_limit); 820 } 821 mutex_unlock(&p->mutex); 822 823 args->num_of_nodes = i; 824 ret = copy_to_user( 825 (void __user *)args->kfd_process_device_apertures_ptr, 826 pa, 827 (i * sizeof(struct kfd_process_device_apertures))); 828 kfree(pa); 829 return ret ? -EFAULT : 0; 830 831 out_unlock: 832 mutex_unlock(&p->mutex); 833 return 0; 834 } 835 836 static int kfd_ioctl_create_event(struct file *filp, struct kfd_process *p, 837 void *data) 838 { 839 struct kfd_ioctl_create_event_args *args = data; 840 int err; 841 842 /* For dGPUs the event page is allocated in user mode. The 843 * handle is passed to KFD with the first call to this IOCTL 844 * through the event_page_offset field. 845 */ 846 if (args->event_page_offset) { 847 mutex_lock(&p->mutex); 848 err = kfd_kmap_event_page(p, args->event_page_offset); 849 mutex_unlock(&p->mutex); 850 if (err) 851 return err; 852 } 853 854 err = kfd_event_create(filp, p, args->event_type, 855 args->auto_reset != 0, args->node_id, 856 &args->event_id, &args->event_trigger_data, 857 &args->event_page_offset, 858 &args->event_slot_index); 859 860 pr_debug("Created event (id:0x%08x) (%s)\n", args->event_id, __func__); 861 return err; 862 } 863 864 static int kfd_ioctl_destroy_event(struct file *filp, struct kfd_process *p, 865 void *data) 866 { 867 struct kfd_ioctl_destroy_event_args *args = data; 868 869 return kfd_event_destroy(p, args->event_id); 870 } 871 872 static int kfd_ioctl_set_event(struct file *filp, struct kfd_process *p, 873 void *data) 874 { 875 struct kfd_ioctl_set_event_args *args = data; 876 877 return kfd_set_event(p, args->event_id); 878 } 879 880 static int kfd_ioctl_reset_event(struct file *filp, struct kfd_process *p, 881 void *data) 882 { 883 struct kfd_ioctl_reset_event_args *args = data; 884 885 return kfd_reset_event(p, args->event_id); 886 } 887 888 static int kfd_ioctl_wait_events(struct file *filp, struct kfd_process *p, 889 void *data) 890 { 891 struct kfd_ioctl_wait_events_args *args = data; 892 893 return kfd_wait_on_events(p, args->num_events, 894 (void __user *)args->events_ptr, 895 (args->wait_for_all != 0), 896 &args->timeout, &args->wait_result); 897 } 898 static int kfd_ioctl_set_scratch_backing_va(struct file *filep, 899 struct kfd_process *p, void *data) 900 { 901 struct kfd_ioctl_set_scratch_backing_va_args *args = data; 902 struct kfd_process_device *pdd; 903 struct kfd_node *dev; 904 long err; 905 906 mutex_lock(&p->mutex); 907 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 908 if (!pdd) { 909 err = -EINVAL; 910 goto err_pdd; 911 } 912 dev = pdd->dev; 913 914 pdd = kfd_bind_process_to_device(dev, p); 915 if (IS_ERR(pdd)) { 916 err = PTR_ERR(pdd); 917 goto bind_process_to_device_fail; 918 } 919 920 pdd->qpd.sh_hidden_private_base = args->va_addr; 921 922 mutex_unlock(&p->mutex); 923 924 if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS && 925 pdd->qpd.vmid != 0 && dev->kfd2kgd->set_scratch_backing_va) 926 dev->kfd2kgd->set_scratch_backing_va( 927 dev->adev, args->va_addr, pdd->qpd.vmid); 928 929 return 0; 930 931 bind_process_to_device_fail: 932 err_pdd: 933 mutex_unlock(&p->mutex); 934 return err; 935 } 936 937 static int kfd_ioctl_get_tile_config(struct file *filep, 938 struct kfd_process *p, void *data) 939 { 940 struct kfd_ioctl_get_tile_config_args *args = data; 941 struct kfd_process_device *pdd; 942 struct tile_config config; 943 int err = 0; 944 945 mutex_lock(&p->mutex); 946 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 947 mutex_unlock(&p->mutex); 948 if (!pdd) 949 return -EINVAL; 950 951 amdgpu_amdkfd_get_tile_config(pdd->dev->adev, &config); 952 953 args->gb_addr_config = config.gb_addr_config; 954 args->num_banks = config.num_banks; 955 args->num_ranks = config.num_ranks; 956 957 if (args->num_tile_configs > config.num_tile_configs) 958 args->num_tile_configs = config.num_tile_configs; 959 err = copy_to_user((void __user *)args->tile_config_ptr, 960 config.tile_config_ptr, 961 args->num_tile_configs * sizeof(uint32_t)); 962 if (err) { 963 args->num_tile_configs = 0; 964 return -EFAULT; 965 } 966 967 if (args->num_macro_tile_configs > config.num_macro_tile_configs) 968 args->num_macro_tile_configs = 969 config.num_macro_tile_configs; 970 err = copy_to_user((void __user *)args->macro_tile_config_ptr, 971 config.macro_tile_config_ptr, 972 args->num_macro_tile_configs * sizeof(uint32_t)); 973 if (err) { 974 args->num_macro_tile_configs = 0; 975 return -EFAULT; 976 } 977 978 return 0; 979 } 980 981 static int kfd_ioctl_acquire_vm(struct file *filep, struct kfd_process *p, 982 void *data) 983 { 984 struct kfd_ioctl_acquire_vm_args *args = data; 985 struct kfd_process_device *pdd; 986 struct file *drm_file; 987 int ret; 988 989 drm_file = fget(args->drm_fd); 990 if (!drm_file) 991 return -EINVAL; 992 993 mutex_lock(&p->mutex); 994 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 995 if (!pdd) { 996 ret = -EINVAL; 997 goto err_pdd; 998 } 999 1000 if (pdd->drm_file) { 1001 ret = pdd->drm_file == drm_file ? 0 : -EBUSY; 1002 goto err_drm_file; 1003 } 1004 1005 ret = kfd_process_device_init_vm(pdd, drm_file); 1006 if (ret) 1007 goto err_unlock; 1008 1009 /* On success, the PDD keeps the drm_file reference */ 1010 mutex_unlock(&p->mutex); 1011 1012 return 0; 1013 1014 err_unlock: 1015 err_pdd: 1016 err_drm_file: 1017 mutex_unlock(&p->mutex); 1018 fput(drm_file); 1019 return ret; 1020 } 1021 1022 bool kfd_dev_is_large_bar(struct kfd_node *dev) 1023 { 1024 if (debug_largebar) { 1025 pr_debug("Simulate large-bar allocation on non large-bar machine\n"); 1026 return true; 1027 } 1028 1029 if (dev->kfd->use_iommu_v2) 1030 return false; 1031 1032 if (dev->local_mem_info.local_mem_size_private == 0 && 1033 dev->local_mem_info.local_mem_size_public > 0) 1034 return true; 1035 1036 if (dev->local_mem_info.local_mem_size_public == 0 && 1037 dev->kfd->adev->gmc.is_app_apu) { 1038 pr_debug("APP APU, Consider like a large bar system\n"); 1039 return true; 1040 } 1041 1042 return false; 1043 } 1044 1045 static int kfd_ioctl_get_available_memory(struct file *filep, 1046 struct kfd_process *p, void *data) 1047 { 1048 struct kfd_ioctl_get_available_memory_args *args = data; 1049 struct kfd_process_device *pdd = kfd_lock_pdd_by_id(p, args->gpu_id); 1050 1051 if (!pdd) 1052 return -EINVAL; 1053 args->available = amdgpu_amdkfd_get_available_memory(pdd->dev->adev, 1054 pdd->dev->node_id); 1055 kfd_unlock_pdd(pdd); 1056 return 0; 1057 } 1058 1059 static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, 1060 struct kfd_process *p, void *data) 1061 { 1062 struct kfd_ioctl_alloc_memory_of_gpu_args *args = data; 1063 struct kfd_process_device *pdd; 1064 void *mem; 1065 struct kfd_node *dev; 1066 int idr_handle; 1067 long err; 1068 uint64_t offset = args->mmap_offset; 1069 uint32_t flags = args->flags; 1070 1071 if (args->size == 0) 1072 return -EINVAL; 1073 1074 #if IS_ENABLED(CONFIG_HSA_AMD_SVM) 1075 /* Flush pending deferred work to avoid racing with deferred actions 1076 * from previous memory map changes (e.g. munmap). 1077 */ 1078 svm_range_list_lock_and_flush_work(&p->svms, current->mm); 1079 mutex_lock(&p->svms.lock); 1080 mmap_write_unlock(current->mm); 1081 if (interval_tree_iter_first(&p->svms.objects, 1082 args->va_addr >> PAGE_SHIFT, 1083 (args->va_addr + args->size - 1) >> PAGE_SHIFT)) { 1084 pr_err("Address: 0x%llx already allocated by SVM\n", 1085 args->va_addr); 1086 mutex_unlock(&p->svms.lock); 1087 return -EADDRINUSE; 1088 } 1089 1090 /* When register user buffer check if it has been registered by svm by 1091 * buffer cpu virtual address. 1092 */ 1093 if ((flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) && 1094 interval_tree_iter_first(&p->svms.objects, 1095 args->mmap_offset >> PAGE_SHIFT, 1096 (args->mmap_offset + args->size - 1) >> PAGE_SHIFT)) { 1097 pr_err("User Buffer Address: 0x%llx already allocated by SVM\n", 1098 args->mmap_offset); 1099 mutex_unlock(&p->svms.lock); 1100 return -EADDRINUSE; 1101 } 1102 1103 mutex_unlock(&p->svms.lock); 1104 #endif 1105 mutex_lock(&p->mutex); 1106 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 1107 if (!pdd) { 1108 err = -EINVAL; 1109 goto err_pdd; 1110 } 1111 1112 dev = pdd->dev; 1113 1114 if ((flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) && 1115 (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) && 1116 !kfd_dev_is_large_bar(dev)) { 1117 pr_err("Alloc host visible vram on small bar is not allowed\n"); 1118 err = -EINVAL; 1119 goto err_large_bar; 1120 } 1121 1122 pdd = kfd_bind_process_to_device(dev, p); 1123 if (IS_ERR(pdd)) { 1124 err = PTR_ERR(pdd); 1125 goto err_unlock; 1126 } 1127 1128 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) { 1129 if (args->size != kfd_doorbell_process_slice(dev->kfd)) { 1130 err = -EINVAL; 1131 goto err_unlock; 1132 } 1133 offset = kfd_get_process_doorbells(pdd); 1134 if (!offset) { 1135 err = -ENOMEM; 1136 goto err_unlock; 1137 } 1138 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) { 1139 if (args->size != PAGE_SIZE) { 1140 err = -EINVAL; 1141 goto err_unlock; 1142 } 1143 offset = dev->adev->rmmio_remap.bus_addr; 1144 if (!offset) { 1145 err = -ENOMEM; 1146 goto err_unlock; 1147 } 1148 } 1149 1150 err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( 1151 dev->adev, args->va_addr, args->size, 1152 pdd->drm_priv, (struct kgd_mem **) &mem, &offset, 1153 flags, false); 1154 1155 if (err) 1156 goto err_unlock; 1157 1158 idr_handle = kfd_process_device_create_obj_handle(pdd, mem); 1159 if (idr_handle < 0) { 1160 err = -EFAULT; 1161 goto err_free; 1162 } 1163 1164 /* Update the VRAM usage count */ 1165 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { 1166 uint64_t size = args->size; 1167 1168 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM) 1169 size >>= 1; 1170 WRITE_ONCE(pdd->vram_usage, pdd->vram_usage + PAGE_ALIGN(size)); 1171 } 1172 1173 mutex_unlock(&p->mutex); 1174 1175 args->handle = MAKE_HANDLE(args->gpu_id, idr_handle); 1176 args->mmap_offset = offset; 1177 1178 /* MMIO is mapped through kfd device 1179 * Generate a kfd mmap offset 1180 */ 1181 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) 1182 args->mmap_offset = KFD_MMAP_TYPE_MMIO 1183 | KFD_MMAP_GPU_ID(args->gpu_id); 1184 1185 return 0; 1186 1187 err_free: 1188 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, (struct kgd_mem *)mem, 1189 pdd->drm_priv, NULL); 1190 err_unlock: 1191 err_pdd: 1192 err_large_bar: 1193 mutex_unlock(&p->mutex); 1194 return err; 1195 } 1196 1197 static int kfd_ioctl_free_memory_of_gpu(struct file *filep, 1198 struct kfd_process *p, void *data) 1199 { 1200 struct kfd_ioctl_free_memory_of_gpu_args *args = data; 1201 struct kfd_process_device *pdd; 1202 void *mem; 1203 int ret; 1204 uint64_t size = 0; 1205 1206 mutex_lock(&p->mutex); 1207 /* 1208 * Safeguard to prevent user space from freeing signal BO. 1209 * It will be freed at process termination. 1210 */ 1211 if (p->signal_handle && (p->signal_handle == args->handle)) { 1212 pr_err("Free signal BO is not allowed\n"); 1213 ret = -EPERM; 1214 goto err_unlock; 1215 } 1216 1217 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle)); 1218 if (!pdd) { 1219 pr_err("Process device data doesn't exist\n"); 1220 ret = -EINVAL; 1221 goto err_pdd; 1222 } 1223 1224 mem = kfd_process_device_translate_handle( 1225 pdd, GET_IDR_HANDLE(args->handle)); 1226 if (!mem) { 1227 ret = -EINVAL; 1228 goto err_unlock; 1229 } 1230 1231 ret = amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, 1232 (struct kgd_mem *)mem, pdd->drm_priv, &size); 1233 1234 /* If freeing the buffer failed, leave the handle in place for 1235 * clean-up during process tear-down. 1236 */ 1237 if (!ret) 1238 kfd_process_device_remove_obj_handle( 1239 pdd, GET_IDR_HANDLE(args->handle)); 1240 1241 WRITE_ONCE(pdd->vram_usage, pdd->vram_usage - size); 1242 1243 err_unlock: 1244 err_pdd: 1245 mutex_unlock(&p->mutex); 1246 return ret; 1247 } 1248 1249 static int kfd_ioctl_map_memory_to_gpu(struct file *filep, 1250 struct kfd_process *p, void *data) 1251 { 1252 struct kfd_ioctl_map_memory_to_gpu_args *args = data; 1253 struct kfd_process_device *pdd, *peer_pdd; 1254 void *mem; 1255 struct kfd_node *dev; 1256 long err = 0; 1257 int i; 1258 uint32_t *devices_arr = NULL; 1259 1260 if (!args->n_devices) { 1261 pr_debug("Device IDs array empty\n"); 1262 return -EINVAL; 1263 } 1264 if (args->n_success > args->n_devices) { 1265 pr_debug("n_success exceeds n_devices\n"); 1266 return -EINVAL; 1267 } 1268 1269 devices_arr = kmalloc_array(args->n_devices, sizeof(*devices_arr), 1270 GFP_KERNEL); 1271 if (!devices_arr) 1272 return -ENOMEM; 1273 1274 err = copy_from_user(devices_arr, 1275 (void __user *)args->device_ids_array_ptr, 1276 args->n_devices * sizeof(*devices_arr)); 1277 if (err != 0) { 1278 err = -EFAULT; 1279 goto copy_from_user_failed; 1280 } 1281 1282 mutex_lock(&p->mutex); 1283 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle)); 1284 if (!pdd) { 1285 err = -EINVAL; 1286 goto get_process_device_data_failed; 1287 } 1288 dev = pdd->dev; 1289 1290 pdd = kfd_bind_process_to_device(dev, p); 1291 if (IS_ERR(pdd)) { 1292 err = PTR_ERR(pdd); 1293 goto bind_process_to_device_failed; 1294 } 1295 1296 mem = kfd_process_device_translate_handle(pdd, 1297 GET_IDR_HANDLE(args->handle)); 1298 if (!mem) { 1299 err = -ENOMEM; 1300 goto get_mem_obj_from_handle_failed; 1301 } 1302 1303 for (i = args->n_success; i < args->n_devices; i++) { 1304 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]); 1305 if (!peer_pdd) { 1306 pr_debug("Getting device by id failed for 0x%x\n", 1307 devices_arr[i]); 1308 err = -EINVAL; 1309 goto get_mem_obj_from_handle_failed; 1310 } 1311 1312 peer_pdd = kfd_bind_process_to_device(peer_pdd->dev, p); 1313 if (IS_ERR(peer_pdd)) { 1314 err = PTR_ERR(peer_pdd); 1315 goto get_mem_obj_from_handle_failed; 1316 } 1317 1318 err = amdgpu_amdkfd_gpuvm_map_memory_to_gpu( 1319 peer_pdd->dev->adev, (struct kgd_mem *)mem, 1320 peer_pdd->drm_priv); 1321 if (err) { 1322 struct pci_dev *pdev = peer_pdd->dev->adev->pdev; 1323 1324 dev_err(dev->adev->dev, 1325 "Failed to map peer:%04x:%02x:%02x.%d mem_domain:%d\n", 1326 pci_domain_nr(pdev->bus), 1327 pdev->bus->number, 1328 PCI_SLOT(pdev->devfn), 1329 PCI_FUNC(pdev->devfn), 1330 ((struct kgd_mem *)mem)->domain); 1331 goto map_memory_to_gpu_failed; 1332 } 1333 args->n_success = i+1; 1334 } 1335 1336 err = amdgpu_amdkfd_gpuvm_sync_memory(dev->adev, (struct kgd_mem *) mem, true); 1337 if (err) { 1338 pr_debug("Sync memory failed, wait interrupted by user signal\n"); 1339 goto sync_memory_failed; 1340 } 1341 1342 mutex_unlock(&p->mutex); 1343 1344 /* Flush TLBs after waiting for the page table updates to complete */ 1345 for (i = 0; i < args->n_devices; i++) { 1346 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]); 1347 if (WARN_ON_ONCE(!peer_pdd)) 1348 continue; 1349 kfd_flush_tlb(peer_pdd, TLB_FLUSH_LEGACY); 1350 } 1351 kfree(devices_arr); 1352 1353 return err; 1354 1355 get_process_device_data_failed: 1356 bind_process_to_device_failed: 1357 get_mem_obj_from_handle_failed: 1358 map_memory_to_gpu_failed: 1359 sync_memory_failed: 1360 mutex_unlock(&p->mutex); 1361 copy_from_user_failed: 1362 kfree(devices_arr); 1363 1364 return err; 1365 } 1366 1367 static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep, 1368 struct kfd_process *p, void *data) 1369 { 1370 struct kfd_ioctl_unmap_memory_from_gpu_args *args = data; 1371 struct kfd_process_device *pdd, *peer_pdd; 1372 void *mem; 1373 long err = 0; 1374 uint32_t *devices_arr = NULL, i; 1375 bool flush_tlb; 1376 1377 if (!args->n_devices) { 1378 pr_debug("Device IDs array empty\n"); 1379 return -EINVAL; 1380 } 1381 if (args->n_success > args->n_devices) { 1382 pr_debug("n_success exceeds n_devices\n"); 1383 return -EINVAL; 1384 } 1385 1386 devices_arr = kmalloc_array(args->n_devices, sizeof(*devices_arr), 1387 GFP_KERNEL); 1388 if (!devices_arr) 1389 return -ENOMEM; 1390 1391 err = copy_from_user(devices_arr, 1392 (void __user *)args->device_ids_array_ptr, 1393 args->n_devices * sizeof(*devices_arr)); 1394 if (err != 0) { 1395 err = -EFAULT; 1396 goto copy_from_user_failed; 1397 } 1398 1399 mutex_lock(&p->mutex); 1400 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle)); 1401 if (!pdd) { 1402 err = -EINVAL; 1403 goto bind_process_to_device_failed; 1404 } 1405 1406 mem = kfd_process_device_translate_handle(pdd, 1407 GET_IDR_HANDLE(args->handle)); 1408 if (!mem) { 1409 err = -ENOMEM; 1410 goto get_mem_obj_from_handle_failed; 1411 } 1412 1413 for (i = args->n_success; i < args->n_devices; i++) { 1414 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]); 1415 if (!peer_pdd) { 1416 err = -EINVAL; 1417 goto get_mem_obj_from_handle_failed; 1418 } 1419 err = amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( 1420 peer_pdd->dev->adev, (struct kgd_mem *)mem, peer_pdd->drm_priv); 1421 if (err) { 1422 pr_err("Failed to unmap from gpu %d/%d\n", 1423 i, args->n_devices); 1424 goto unmap_memory_from_gpu_failed; 1425 } 1426 args->n_success = i+1; 1427 } 1428 1429 flush_tlb = kfd_flush_tlb_after_unmap(pdd->dev->kfd); 1430 if (flush_tlb) { 1431 err = amdgpu_amdkfd_gpuvm_sync_memory(pdd->dev->adev, 1432 (struct kgd_mem *) mem, true); 1433 if (err) { 1434 pr_debug("Sync memory failed, wait interrupted by user signal\n"); 1435 goto sync_memory_failed; 1436 } 1437 } 1438 mutex_unlock(&p->mutex); 1439 1440 if (flush_tlb) { 1441 /* Flush TLBs after waiting for the page table updates to complete */ 1442 for (i = 0; i < args->n_devices; i++) { 1443 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]); 1444 if (WARN_ON_ONCE(!peer_pdd)) 1445 continue; 1446 kfd_flush_tlb(peer_pdd, TLB_FLUSH_HEAVYWEIGHT); 1447 } 1448 } 1449 kfree(devices_arr); 1450 1451 return 0; 1452 1453 bind_process_to_device_failed: 1454 get_mem_obj_from_handle_failed: 1455 unmap_memory_from_gpu_failed: 1456 sync_memory_failed: 1457 mutex_unlock(&p->mutex); 1458 copy_from_user_failed: 1459 kfree(devices_arr); 1460 return err; 1461 } 1462 1463 static int kfd_ioctl_alloc_queue_gws(struct file *filep, 1464 struct kfd_process *p, void *data) 1465 { 1466 int retval; 1467 struct kfd_ioctl_alloc_queue_gws_args *args = data; 1468 struct queue *q; 1469 struct kfd_node *dev; 1470 1471 mutex_lock(&p->mutex); 1472 q = pqm_get_user_queue(&p->pqm, args->queue_id); 1473 1474 if (q) { 1475 dev = q->device; 1476 } else { 1477 retval = -EINVAL; 1478 goto out_unlock; 1479 } 1480 1481 if (!dev->gws) { 1482 retval = -ENODEV; 1483 goto out_unlock; 1484 } 1485 1486 if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) { 1487 retval = -ENODEV; 1488 goto out_unlock; 1489 } 1490 1491 if (p->debug_trap_enabled && (!kfd_dbg_has_gws_support(dev) || 1492 kfd_dbg_has_cwsr_workaround(dev))) { 1493 retval = -EBUSY; 1494 goto out_unlock; 1495 } 1496 1497 retval = pqm_set_gws(&p->pqm, args->queue_id, args->num_gws ? dev->gws : NULL); 1498 mutex_unlock(&p->mutex); 1499 1500 args->first_gws = 0; 1501 return retval; 1502 1503 out_unlock: 1504 mutex_unlock(&p->mutex); 1505 return retval; 1506 } 1507 1508 static int kfd_ioctl_get_dmabuf_info(struct file *filep, 1509 struct kfd_process *p, void *data) 1510 { 1511 struct kfd_ioctl_get_dmabuf_info_args *args = data; 1512 struct kfd_node *dev = NULL; 1513 struct amdgpu_device *dmabuf_adev; 1514 void *metadata_buffer = NULL; 1515 uint32_t flags; 1516 int8_t xcp_id; 1517 unsigned int i; 1518 int r; 1519 1520 /* Find a KFD GPU device that supports the get_dmabuf_info query */ 1521 for (i = 0; kfd_topology_enum_kfd_devices(i, &dev) == 0; i++) 1522 if (dev) 1523 break; 1524 if (!dev) 1525 return -EINVAL; 1526 1527 if (args->metadata_ptr) { 1528 metadata_buffer = kzalloc(args->metadata_size, GFP_KERNEL); 1529 if (!metadata_buffer) 1530 return -ENOMEM; 1531 } 1532 1533 /* Get dmabuf info from KGD */ 1534 r = amdgpu_amdkfd_get_dmabuf_info(dev->adev, args->dmabuf_fd, 1535 &dmabuf_adev, &args->size, 1536 metadata_buffer, args->metadata_size, 1537 &args->metadata_size, &flags, &xcp_id); 1538 if (r) 1539 goto exit; 1540 1541 if (xcp_id >= 0) 1542 args->gpu_id = dmabuf_adev->kfd.dev->nodes[xcp_id]->id; 1543 else 1544 args->gpu_id = dmabuf_adev->kfd.dev->nodes[0]->id; 1545 args->flags = flags; 1546 1547 /* Copy metadata buffer to user mode */ 1548 if (metadata_buffer) { 1549 r = copy_to_user((void __user *)args->metadata_ptr, 1550 metadata_buffer, args->metadata_size); 1551 if (r != 0) 1552 r = -EFAULT; 1553 } 1554 1555 exit: 1556 kfree(metadata_buffer); 1557 1558 return r; 1559 } 1560 1561 static int kfd_ioctl_import_dmabuf(struct file *filep, 1562 struct kfd_process *p, void *data) 1563 { 1564 struct kfd_ioctl_import_dmabuf_args *args = data; 1565 struct kfd_process_device *pdd; 1566 struct dma_buf *dmabuf; 1567 int idr_handle; 1568 uint64_t size; 1569 void *mem; 1570 int r; 1571 1572 dmabuf = dma_buf_get(args->dmabuf_fd); 1573 if (IS_ERR(dmabuf)) 1574 return PTR_ERR(dmabuf); 1575 1576 mutex_lock(&p->mutex); 1577 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 1578 if (!pdd) { 1579 r = -EINVAL; 1580 goto err_unlock; 1581 } 1582 1583 pdd = kfd_bind_process_to_device(pdd->dev, p); 1584 if (IS_ERR(pdd)) { 1585 r = PTR_ERR(pdd); 1586 goto err_unlock; 1587 } 1588 1589 r = amdgpu_amdkfd_gpuvm_import_dmabuf(pdd->dev->adev, dmabuf, 1590 args->va_addr, pdd->drm_priv, 1591 (struct kgd_mem **)&mem, &size, 1592 NULL); 1593 if (r) 1594 goto err_unlock; 1595 1596 idr_handle = kfd_process_device_create_obj_handle(pdd, mem); 1597 if (idr_handle < 0) { 1598 r = -EFAULT; 1599 goto err_free; 1600 } 1601 1602 mutex_unlock(&p->mutex); 1603 dma_buf_put(dmabuf); 1604 1605 args->handle = MAKE_HANDLE(args->gpu_id, idr_handle); 1606 1607 return 0; 1608 1609 err_free: 1610 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, (struct kgd_mem *)mem, 1611 pdd->drm_priv, NULL); 1612 err_unlock: 1613 mutex_unlock(&p->mutex); 1614 dma_buf_put(dmabuf); 1615 return r; 1616 } 1617 1618 static int kfd_ioctl_export_dmabuf(struct file *filep, 1619 struct kfd_process *p, void *data) 1620 { 1621 struct kfd_ioctl_export_dmabuf_args *args = data; 1622 struct kfd_process_device *pdd; 1623 struct dma_buf *dmabuf; 1624 struct kfd_node *dev; 1625 void *mem; 1626 int ret = 0; 1627 1628 dev = kfd_device_by_id(GET_GPU_ID(args->handle)); 1629 if (!dev) 1630 return -EINVAL; 1631 1632 mutex_lock(&p->mutex); 1633 1634 pdd = kfd_get_process_device_data(dev, p); 1635 if (!pdd) { 1636 ret = -EINVAL; 1637 goto err_unlock; 1638 } 1639 1640 mem = kfd_process_device_translate_handle(pdd, 1641 GET_IDR_HANDLE(args->handle)); 1642 if (!mem) { 1643 ret = -EINVAL; 1644 goto err_unlock; 1645 } 1646 1647 ret = amdgpu_amdkfd_gpuvm_export_dmabuf(mem, &dmabuf); 1648 mutex_unlock(&p->mutex); 1649 if (ret) 1650 goto err_out; 1651 1652 ret = dma_buf_fd(dmabuf, args->flags); 1653 if (ret < 0) { 1654 dma_buf_put(dmabuf); 1655 goto err_out; 1656 } 1657 /* dma_buf_fd assigns the reference count to the fd, no need to 1658 * put the reference here. 1659 */ 1660 args->dmabuf_fd = ret; 1661 1662 return 0; 1663 1664 err_unlock: 1665 mutex_unlock(&p->mutex); 1666 err_out: 1667 return ret; 1668 } 1669 1670 /* Handle requests for watching SMI events */ 1671 static int kfd_ioctl_smi_events(struct file *filep, 1672 struct kfd_process *p, void *data) 1673 { 1674 struct kfd_ioctl_smi_events_args *args = data; 1675 struct kfd_process_device *pdd; 1676 1677 mutex_lock(&p->mutex); 1678 1679 pdd = kfd_process_device_data_by_id(p, args->gpuid); 1680 mutex_unlock(&p->mutex); 1681 if (!pdd) 1682 return -EINVAL; 1683 1684 return kfd_smi_event_open(pdd->dev, &args->anon_fd); 1685 } 1686 1687 #if IS_ENABLED(CONFIG_HSA_AMD_SVM) 1688 1689 static int kfd_ioctl_set_xnack_mode(struct file *filep, 1690 struct kfd_process *p, void *data) 1691 { 1692 struct kfd_ioctl_set_xnack_mode_args *args = data; 1693 int r = 0; 1694 1695 mutex_lock(&p->mutex); 1696 if (args->xnack_enabled >= 0) { 1697 if (!list_empty(&p->pqm.queues)) { 1698 pr_debug("Process has user queues running\n"); 1699 r = -EBUSY; 1700 goto out_unlock; 1701 } 1702 1703 if (p->xnack_enabled == args->xnack_enabled) 1704 goto out_unlock; 1705 1706 if (args->xnack_enabled && !kfd_process_xnack_mode(p, true)) { 1707 r = -EPERM; 1708 goto out_unlock; 1709 } 1710 1711 r = svm_range_switch_xnack_reserve_mem(p, args->xnack_enabled); 1712 } else { 1713 args->xnack_enabled = p->xnack_enabled; 1714 } 1715 1716 out_unlock: 1717 mutex_unlock(&p->mutex); 1718 1719 return r; 1720 } 1721 1722 static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data) 1723 { 1724 struct kfd_ioctl_svm_args *args = data; 1725 int r = 0; 1726 1727 pr_debug("start 0x%llx size 0x%llx op 0x%x nattr 0x%x\n", 1728 args->start_addr, args->size, args->op, args->nattr); 1729 1730 if ((args->start_addr & ~PAGE_MASK) || (args->size & ~PAGE_MASK)) 1731 return -EINVAL; 1732 if (!args->start_addr || !args->size) 1733 return -EINVAL; 1734 1735 r = svm_ioctl(p, args->op, args->start_addr, args->size, args->nattr, 1736 args->attrs); 1737 1738 return r; 1739 } 1740 #else 1741 static int kfd_ioctl_set_xnack_mode(struct file *filep, 1742 struct kfd_process *p, void *data) 1743 { 1744 return -EPERM; 1745 } 1746 static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data) 1747 { 1748 return -EPERM; 1749 } 1750 #endif 1751 1752 static int criu_checkpoint_process(struct kfd_process *p, 1753 uint8_t __user *user_priv_data, 1754 uint64_t *priv_offset) 1755 { 1756 struct kfd_criu_process_priv_data process_priv; 1757 int ret; 1758 1759 memset(&process_priv, 0, sizeof(process_priv)); 1760 1761 process_priv.version = KFD_CRIU_PRIV_VERSION; 1762 /* For CR, we don't consider negative xnack mode which is used for 1763 * querying without changing it, here 0 simply means disabled and 1 1764 * means enabled so retry for finding a valid PTE. 1765 */ 1766 process_priv.xnack_mode = p->xnack_enabled ? 1 : 0; 1767 1768 ret = copy_to_user(user_priv_data + *priv_offset, 1769 &process_priv, sizeof(process_priv)); 1770 1771 if (ret) { 1772 pr_err("Failed to copy process information to user\n"); 1773 ret = -EFAULT; 1774 } 1775 1776 *priv_offset += sizeof(process_priv); 1777 return ret; 1778 } 1779 1780 static int criu_checkpoint_devices(struct kfd_process *p, 1781 uint32_t num_devices, 1782 uint8_t __user *user_addr, 1783 uint8_t __user *user_priv_data, 1784 uint64_t *priv_offset) 1785 { 1786 struct kfd_criu_device_priv_data *device_priv = NULL; 1787 struct kfd_criu_device_bucket *device_buckets = NULL; 1788 int ret = 0, i; 1789 1790 device_buckets = kvzalloc(num_devices * sizeof(*device_buckets), GFP_KERNEL); 1791 if (!device_buckets) { 1792 ret = -ENOMEM; 1793 goto exit; 1794 } 1795 1796 device_priv = kvzalloc(num_devices * sizeof(*device_priv), GFP_KERNEL); 1797 if (!device_priv) { 1798 ret = -ENOMEM; 1799 goto exit; 1800 } 1801 1802 for (i = 0; i < num_devices; i++) { 1803 struct kfd_process_device *pdd = p->pdds[i]; 1804 1805 device_buckets[i].user_gpu_id = pdd->user_gpu_id; 1806 device_buckets[i].actual_gpu_id = pdd->dev->id; 1807 1808 /* 1809 * priv_data does not contain useful information for now and is reserved for 1810 * future use, so we do not set its contents. 1811 */ 1812 } 1813 1814 ret = copy_to_user(user_addr, device_buckets, num_devices * sizeof(*device_buckets)); 1815 if (ret) { 1816 pr_err("Failed to copy device information to user\n"); 1817 ret = -EFAULT; 1818 goto exit; 1819 } 1820 1821 ret = copy_to_user(user_priv_data + *priv_offset, 1822 device_priv, 1823 num_devices * sizeof(*device_priv)); 1824 if (ret) { 1825 pr_err("Failed to copy device information to user\n"); 1826 ret = -EFAULT; 1827 } 1828 *priv_offset += num_devices * sizeof(*device_priv); 1829 1830 exit: 1831 kvfree(device_buckets); 1832 kvfree(device_priv); 1833 return ret; 1834 } 1835 1836 static uint32_t get_process_num_bos(struct kfd_process *p) 1837 { 1838 uint32_t num_of_bos = 0; 1839 int i; 1840 1841 /* Run over all PDDs of the process */ 1842 for (i = 0; i < p->n_pdds; i++) { 1843 struct kfd_process_device *pdd = p->pdds[i]; 1844 void *mem; 1845 int id; 1846 1847 idr_for_each_entry(&pdd->alloc_idr, mem, id) { 1848 struct kgd_mem *kgd_mem = (struct kgd_mem *)mem; 1849 1850 if (!kgd_mem->va || kgd_mem->va > pdd->gpuvm_base) 1851 num_of_bos++; 1852 } 1853 } 1854 return num_of_bos; 1855 } 1856 1857 static int criu_get_prime_handle(struct kgd_mem *mem, int flags, 1858 u32 *shared_fd) 1859 { 1860 struct dma_buf *dmabuf; 1861 int ret; 1862 1863 ret = amdgpu_amdkfd_gpuvm_export_dmabuf(mem, &dmabuf); 1864 if (ret) { 1865 pr_err("dmabuf export failed for the BO\n"); 1866 return ret; 1867 } 1868 1869 ret = dma_buf_fd(dmabuf, flags); 1870 if (ret < 0) { 1871 pr_err("dmabuf create fd failed, ret:%d\n", ret); 1872 goto out_free_dmabuf; 1873 } 1874 1875 *shared_fd = ret; 1876 return 0; 1877 1878 out_free_dmabuf: 1879 dma_buf_put(dmabuf); 1880 return ret; 1881 } 1882 1883 static int criu_checkpoint_bos(struct kfd_process *p, 1884 uint32_t num_bos, 1885 uint8_t __user *user_bos, 1886 uint8_t __user *user_priv_data, 1887 uint64_t *priv_offset) 1888 { 1889 struct kfd_criu_bo_bucket *bo_buckets; 1890 struct kfd_criu_bo_priv_data *bo_privs; 1891 int ret = 0, pdd_index, bo_index = 0, id; 1892 void *mem; 1893 1894 bo_buckets = kvzalloc(num_bos * sizeof(*bo_buckets), GFP_KERNEL); 1895 if (!bo_buckets) 1896 return -ENOMEM; 1897 1898 bo_privs = kvzalloc(num_bos * sizeof(*bo_privs), GFP_KERNEL); 1899 if (!bo_privs) { 1900 ret = -ENOMEM; 1901 goto exit; 1902 } 1903 1904 for (pdd_index = 0; pdd_index < p->n_pdds; pdd_index++) { 1905 struct kfd_process_device *pdd = p->pdds[pdd_index]; 1906 struct amdgpu_bo *dumper_bo; 1907 struct kgd_mem *kgd_mem; 1908 1909 idr_for_each_entry(&pdd->alloc_idr, mem, id) { 1910 struct kfd_criu_bo_bucket *bo_bucket; 1911 struct kfd_criu_bo_priv_data *bo_priv; 1912 int i, dev_idx = 0; 1913 1914 if (!mem) { 1915 ret = -ENOMEM; 1916 goto exit; 1917 } 1918 1919 kgd_mem = (struct kgd_mem *)mem; 1920 dumper_bo = kgd_mem->bo; 1921 1922 /* Skip checkpointing BOs that are used for Trap handler 1923 * code and state. Currently, these BOs have a VA that 1924 * is less GPUVM Base 1925 */ 1926 if (kgd_mem->va && kgd_mem->va <= pdd->gpuvm_base) 1927 continue; 1928 1929 bo_bucket = &bo_buckets[bo_index]; 1930 bo_priv = &bo_privs[bo_index]; 1931 1932 bo_bucket->gpu_id = pdd->user_gpu_id; 1933 bo_bucket->addr = (uint64_t)kgd_mem->va; 1934 bo_bucket->size = amdgpu_bo_size(dumper_bo); 1935 bo_bucket->alloc_flags = (uint32_t)kgd_mem->alloc_flags; 1936 bo_priv->idr_handle = id; 1937 1938 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) { 1939 ret = amdgpu_ttm_tt_get_userptr(&dumper_bo->tbo, 1940 &bo_priv->user_addr); 1941 if (ret) { 1942 pr_err("Failed to obtain user address for user-pointer bo\n"); 1943 goto exit; 1944 } 1945 } 1946 if (bo_bucket->alloc_flags 1947 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) { 1948 ret = criu_get_prime_handle(kgd_mem, 1949 bo_bucket->alloc_flags & 1950 KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? DRM_RDWR : 0, 1951 &bo_bucket->dmabuf_fd); 1952 if (ret) 1953 goto exit; 1954 } else { 1955 bo_bucket->dmabuf_fd = KFD_INVALID_FD; 1956 } 1957 1958 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) 1959 bo_bucket->offset = KFD_MMAP_TYPE_DOORBELL | 1960 KFD_MMAP_GPU_ID(pdd->dev->id); 1961 else if (bo_bucket->alloc_flags & 1962 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) 1963 bo_bucket->offset = KFD_MMAP_TYPE_MMIO | 1964 KFD_MMAP_GPU_ID(pdd->dev->id); 1965 else 1966 bo_bucket->offset = amdgpu_bo_mmap_offset(dumper_bo); 1967 1968 for (i = 0; i < p->n_pdds; i++) { 1969 if (amdgpu_amdkfd_bo_mapped_to_dev(p->pdds[i]->dev->adev, kgd_mem)) 1970 bo_priv->mapped_gpuids[dev_idx++] = p->pdds[i]->user_gpu_id; 1971 } 1972 1973 pr_debug("bo_size = 0x%llx, bo_addr = 0x%llx bo_offset = 0x%llx\n" 1974 "gpu_id = 0x%x alloc_flags = 0x%x idr_handle = 0x%x", 1975 bo_bucket->size, 1976 bo_bucket->addr, 1977 bo_bucket->offset, 1978 bo_bucket->gpu_id, 1979 bo_bucket->alloc_flags, 1980 bo_priv->idr_handle); 1981 bo_index++; 1982 } 1983 } 1984 1985 ret = copy_to_user(user_bos, bo_buckets, num_bos * sizeof(*bo_buckets)); 1986 if (ret) { 1987 pr_err("Failed to copy BO information to user\n"); 1988 ret = -EFAULT; 1989 goto exit; 1990 } 1991 1992 ret = copy_to_user(user_priv_data + *priv_offset, bo_privs, num_bos * sizeof(*bo_privs)); 1993 if (ret) { 1994 pr_err("Failed to copy BO priv information to user\n"); 1995 ret = -EFAULT; 1996 goto exit; 1997 } 1998 1999 *priv_offset += num_bos * sizeof(*bo_privs); 2000 2001 exit: 2002 while (ret && bo_index--) { 2003 if (bo_buckets[bo_index].alloc_flags 2004 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) 2005 close_fd(bo_buckets[bo_index].dmabuf_fd); 2006 } 2007 2008 kvfree(bo_buckets); 2009 kvfree(bo_privs); 2010 return ret; 2011 } 2012 2013 static int criu_get_process_object_info(struct kfd_process *p, 2014 uint32_t *num_devices, 2015 uint32_t *num_bos, 2016 uint32_t *num_objects, 2017 uint64_t *objs_priv_size) 2018 { 2019 uint64_t queues_priv_data_size, svm_priv_data_size, priv_size; 2020 uint32_t num_queues, num_events, num_svm_ranges; 2021 int ret; 2022 2023 *num_devices = p->n_pdds; 2024 *num_bos = get_process_num_bos(p); 2025 2026 ret = kfd_process_get_queue_info(p, &num_queues, &queues_priv_data_size); 2027 if (ret) 2028 return ret; 2029 2030 num_events = kfd_get_num_events(p); 2031 2032 ret = svm_range_get_info(p, &num_svm_ranges, &svm_priv_data_size); 2033 if (ret) 2034 return ret; 2035 2036 *num_objects = num_queues + num_events + num_svm_ranges; 2037 2038 if (objs_priv_size) { 2039 priv_size = sizeof(struct kfd_criu_process_priv_data); 2040 priv_size += *num_devices * sizeof(struct kfd_criu_device_priv_data); 2041 priv_size += *num_bos * sizeof(struct kfd_criu_bo_priv_data); 2042 priv_size += queues_priv_data_size; 2043 priv_size += num_events * sizeof(struct kfd_criu_event_priv_data); 2044 priv_size += svm_priv_data_size; 2045 *objs_priv_size = priv_size; 2046 } 2047 return 0; 2048 } 2049 2050 static int criu_checkpoint(struct file *filep, 2051 struct kfd_process *p, 2052 struct kfd_ioctl_criu_args *args) 2053 { 2054 int ret; 2055 uint32_t num_devices, num_bos, num_objects; 2056 uint64_t priv_size, priv_offset = 0, bo_priv_offset; 2057 2058 if (!args->devices || !args->bos || !args->priv_data) 2059 return -EINVAL; 2060 2061 mutex_lock(&p->mutex); 2062 2063 if (!p->n_pdds) { 2064 pr_err("No pdd for given process\n"); 2065 ret = -ENODEV; 2066 goto exit_unlock; 2067 } 2068 2069 /* Confirm all process queues are evicted */ 2070 if (!p->queues_paused) { 2071 pr_err("Cannot dump process when queues are not in evicted state\n"); 2072 /* CRIU plugin did not call op PROCESS_INFO before checkpointing */ 2073 ret = -EINVAL; 2074 goto exit_unlock; 2075 } 2076 2077 ret = criu_get_process_object_info(p, &num_devices, &num_bos, &num_objects, &priv_size); 2078 if (ret) 2079 goto exit_unlock; 2080 2081 if (num_devices != args->num_devices || 2082 num_bos != args->num_bos || 2083 num_objects != args->num_objects || 2084 priv_size != args->priv_data_size) { 2085 2086 ret = -EINVAL; 2087 goto exit_unlock; 2088 } 2089 2090 /* each function will store private data inside priv_data and adjust priv_offset */ 2091 ret = criu_checkpoint_process(p, (uint8_t __user *)args->priv_data, &priv_offset); 2092 if (ret) 2093 goto exit_unlock; 2094 2095 ret = criu_checkpoint_devices(p, num_devices, (uint8_t __user *)args->devices, 2096 (uint8_t __user *)args->priv_data, &priv_offset); 2097 if (ret) 2098 goto exit_unlock; 2099 2100 /* Leave room for BOs in the private data. They need to be restored 2101 * before events, but we checkpoint them last to simplify the error 2102 * handling. 2103 */ 2104 bo_priv_offset = priv_offset; 2105 priv_offset += num_bos * sizeof(struct kfd_criu_bo_priv_data); 2106 2107 if (num_objects) { 2108 ret = kfd_criu_checkpoint_queues(p, (uint8_t __user *)args->priv_data, 2109 &priv_offset); 2110 if (ret) 2111 goto exit_unlock; 2112 2113 ret = kfd_criu_checkpoint_events(p, (uint8_t __user *)args->priv_data, 2114 &priv_offset); 2115 if (ret) 2116 goto exit_unlock; 2117 2118 ret = kfd_criu_checkpoint_svm(p, (uint8_t __user *)args->priv_data, &priv_offset); 2119 if (ret) 2120 goto exit_unlock; 2121 } 2122 2123 /* This must be the last thing in this function that can fail. 2124 * Otherwise we leak dmabuf file descriptors. 2125 */ 2126 ret = criu_checkpoint_bos(p, num_bos, (uint8_t __user *)args->bos, 2127 (uint8_t __user *)args->priv_data, &bo_priv_offset); 2128 2129 exit_unlock: 2130 mutex_unlock(&p->mutex); 2131 if (ret) 2132 pr_err("Failed to dump CRIU ret:%d\n", ret); 2133 else 2134 pr_debug("CRIU dump ret:%d\n", ret); 2135 2136 return ret; 2137 } 2138 2139 static int criu_restore_process(struct kfd_process *p, 2140 struct kfd_ioctl_criu_args *args, 2141 uint64_t *priv_offset, 2142 uint64_t max_priv_data_size) 2143 { 2144 int ret = 0; 2145 struct kfd_criu_process_priv_data process_priv; 2146 2147 if (*priv_offset + sizeof(process_priv) > max_priv_data_size) 2148 return -EINVAL; 2149 2150 ret = copy_from_user(&process_priv, 2151 (void __user *)(args->priv_data + *priv_offset), 2152 sizeof(process_priv)); 2153 if (ret) { 2154 pr_err("Failed to copy process private information from user\n"); 2155 ret = -EFAULT; 2156 goto exit; 2157 } 2158 *priv_offset += sizeof(process_priv); 2159 2160 if (process_priv.version != KFD_CRIU_PRIV_VERSION) { 2161 pr_err("Invalid CRIU API version (checkpointed:%d current:%d)\n", 2162 process_priv.version, KFD_CRIU_PRIV_VERSION); 2163 return -EINVAL; 2164 } 2165 2166 pr_debug("Setting XNACK mode\n"); 2167 if (process_priv.xnack_mode && !kfd_process_xnack_mode(p, true)) { 2168 pr_err("xnack mode cannot be set\n"); 2169 ret = -EPERM; 2170 goto exit; 2171 } else { 2172 pr_debug("set xnack mode: %d\n", process_priv.xnack_mode); 2173 p->xnack_enabled = process_priv.xnack_mode; 2174 } 2175 2176 exit: 2177 return ret; 2178 } 2179 2180 static int criu_restore_devices(struct kfd_process *p, 2181 struct kfd_ioctl_criu_args *args, 2182 uint64_t *priv_offset, 2183 uint64_t max_priv_data_size) 2184 { 2185 struct kfd_criu_device_bucket *device_buckets; 2186 struct kfd_criu_device_priv_data *device_privs; 2187 int ret = 0; 2188 uint32_t i; 2189 2190 if (args->num_devices != p->n_pdds) 2191 return -EINVAL; 2192 2193 if (*priv_offset + (args->num_devices * sizeof(*device_privs)) > max_priv_data_size) 2194 return -EINVAL; 2195 2196 device_buckets = kmalloc_array(args->num_devices, sizeof(*device_buckets), GFP_KERNEL); 2197 if (!device_buckets) 2198 return -ENOMEM; 2199 2200 ret = copy_from_user(device_buckets, (void __user *)args->devices, 2201 args->num_devices * sizeof(*device_buckets)); 2202 if (ret) { 2203 pr_err("Failed to copy devices buckets from user\n"); 2204 ret = -EFAULT; 2205 goto exit; 2206 } 2207 2208 for (i = 0; i < args->num_devices; i++) { 2209 struct kfd_node *dev; 2210 struct kfd_process_device *pdd; 2211 struct file *drm_file; 2212 2213 /* device private data is not currently used */ 2214 2215 if (!device_buckets[i].user_gpu_id) { 2216 pr_err("Invalid user gpu_id\n"); 2217 ret = -EINVAL; 2218 goto exit; 2219 } 2220 2221 dev = kfd_device_by_id(device_buckets[i].actual_gpu_id); 2222 if (!dev) { 2223 pr_err("Failed to find device with gpu_id = %x\n", 2224 device_buckets[i].actual_gpu_id); 2225 ret = -EINVAL; 2226 goto exit; 2227 } 2228 2229 pdd = kfd_get_process_device_data(dev, p); 2230 if (!pdd) { 2231 pr_err("Failed to get pdd for gpu_id = %x\n", 2232 device_buckets[i].actual_gpu_id); 2233 ret = -EINVAL; 2234 goto exit; 2235 } 2236 pdd->user_gpu_id = device_buckets[i].user_gpu_id; 2237 2238 drm_file = fget(device_buckets[i].drm_fd); 2239 if (!drm_file) { 2240 pr_err("Invalid render node file descriptor sent from plugin (%d)\n", 2241 device_buckets[i].drm_fd); 2242 ret = -EINVAL; 2243 goto exit; 2244 } 2245 2246 if (pdd->drm_file) { 2247 ret = -EINVAL; 2248 goto exit; 2249 } 2250 2251 /* create the vm using render nodes for kfd pdd */ 2252 if (kfd_process_device_init_vm(pdd, drm_file)) { 2253 pr_err("could not init vm for given pdd\n"); 2254 /* On success, the PDD keeps the drm_file reference */ 2255 fput(drm_file); 2256 ret = -EINVAL; 2257 goto exit; 2258 } 2259 /* 2260 * pdd now already has the vm bound to render node so below api won't create a new 2261 * exclusive kfd mapping but use existing one with renderDXXX but is still needed 2262 * for iommu v2 binding and runtime pm. 2263 */ 2264 pdd = kfd_bind_process_to_device(dev, p); 2265 if (IS_ERR(pdd)) { 2266 ret = PTR_ERR(pdd); 2267 goto exit; 2268 } 2269 2270 if (!pdd->qpd.proc_doorbells) { 2271 ret = kfd_alloc_process_doorbells(dev->kfd, pdd); 2272 if (ret) 2273 goto exit; 2274 } 2275 } 2276 2277 /* 2278 * We are not copying device private data from user as we are not using the data for now, 2279 * but we still adjust for its private data. 2280 */ 2281 *priv_offset += args->num_devices * sizeof(*device_privs); 2282 2283 exit: 2284 kfree(device_buckets); 2285 return ret; 2286 } 2287 2288 static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, 2289 struct kfd_criu_bo_bucket *bo_bucket, 2290 struct kfd_criu_bo_priv_data *bo_priv, 2291 struct kgd_mem **kgd_mem) 2292 { 2293 int idr_handle; 2294 int ret; 2295 const bool criu_resume = true; 2296 u64 offset; 2297 2298 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) { 2299 if (bo_bucket->size != 2300 kfd_doorbell_process_slice(pdd->dev->kfd)) 2301 return -EINVAL; 2302 2303 offset = kfd_get_process_doorbells(pdd); 2304 if (!offset) 2305 return -ENOMEM; 2306 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) { 2307 /* MMIO BOs need remapped bus address */ 2308 if (bo_bucket->size != PAGE_SIZE) { 2309 pr_err("Invalid page size\n"); 2310 return -EINVAL; 2311 } 2312 offset = pdd->dev->adev->rmmio_remap.bus_addr; 2313 if (!offset) { 2314 pr_err("amdgpu_amdkfd_get_mmio_remap_phys_addr failed\n"); 2315 return -ENOMEM; 2316 } 2317 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) { 2318 offset = bo_priv->user_addr; 2319 } 2320 /* Create the BO */ 2321 ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(pdd->dev->adev, bo_bucket->addr, 2322 bo_bucket->size, pdd->drm_priv, kgd_mem, 2323 &offset, bo_bucket->alloc_flags, criu_resume); 2324 if (ret) { 2325 pr_err("Could not create the BO\n"); 2326 return ret; 2327 } 2328 pr_debug("New BO created: size:0x%llx addr:0x%llx offset:0x%llx\n", 2329 bo_bucket->size, bo_bucket->addr, offset); 2330 2331 /* Restore previous IDR handle */ 2332 pr_debug("Restoring old IDR handle for the BO"); 2333 idr_handle = idr_alloc(&pdd->alloc_idr, *kgd_mem, bo_priv->idr_handle, 2334 bo_priv->idr_handle + 1, GFP_KERNEL); 2335 2336 if (idr_handle < 0) { 2337 pr_err("Could not allocate idr\n"); 2338 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, *kgd_mem, pdd->drm_priv, 2339 NULL); 2340 return -ENOMEM; 2341 } 2342 2343 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) 2344 bo_bucket->restored_offset = KFD_MMAP_TYPE_DOORBELL | KFD_MMAP_GPU_ID(pdd->dev->id); 2345 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) { 2346 bo_bucket->restored_offset = KFD_MMAP_TYPE_MMIO | KFD_MMAP_GPU_ID(pdd->dev->id); 2347 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) { 2348 bo_bucket->restored_offset = offset; 2349 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { 2350 bo_bucket->restored_offset = offset; 2351 /* Update the VRAM usage count */ 2352 WRITE_ONCE(pdd->vram_usage, pdd->vram_usage + bo_bucket->size); 2353 } 2354 return 0; 2355 } 2356 2357 static int criu_restore_bo(struct kfd_process *p, 2358 struct kfd_criu_bo_bucket *bo_bucket, 2359 struct kfd_criu_bo_priv_data *bo_priv) 2360 { 2361 struct kfd_process_device *pdd; 2362 struct kgd_mem *kgd_mem; 2363 int ret; 2364 int j; 2365 2366 pr_debug("Restoring BO size:0x%llx addr:0x%llx gpu_id:0x%x flags:0x%x idr_handle:0x%x\n", 2367 bo_bucket->size, bo_bucket->addr, bo_bucket->gpu_id, bo_bucket->alloc_flags, 2368 bo_priv->idr_handle); 2369 2370 pdd = kfd_process_device_data_by_id(p, bo_bucket->gpu_id); 2371 if (!pdd) { 2372 pr_err("Failed to get pdd\n"); 2373 return -ENODEV; 2374 } 2375 2376 ret = criu_restore_memory_of_gpu(pdd, bo_bucket, bo_priv, &kgd_mem); 2377 if (ret) 2378 return ret; 2379 2380 /* now map these BOs to GPU/s */ 2381 for (j = 0; j < p->n_pdds; j++) { 2382 struct kfd_node *peer; 2383 struct kfd_process_device *peer_pdd; 2384 2385 if (!bo_priv->mapped_gpuids[j]) 2386 break; 2387 2388 peer_pdd = kfd_process_device_data_by_id(p, bo_priv->mapped_gpuids[j]); 2389 if (!peer_pdd) 2390 return -EINVAL; 2391 2392 peer = peer_pdd->dev; 2393 2394 peer_pdd = kfd_bind_process_to_device(peer, p); 2395 if (IS_ERR(peer_pdd)) 2396 return PTR_ERR(peer_pdd); 2397 2398 ret = amdgpu_amdkfd_gpuvm_map_memory_to_gpu(peer->adev, kgd_mem, 2399 peer_pdd->drm_priv); 2400 if (ret) { 2401 pr_err("Failed to map to gpu %d/%d\n", j, p->n_pdds); 2402 return ret; 2403 } 2404 } 2405 2406 pr_debug("map memory was successful for the BO\n"); 2407 /* create the dmabuf object and export the bo */ 2408 if (bo_bucket->alloc_flags 2409 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) { 2410 ret = criu_get_prime_handle(kgd_mem, DRM_RDWR, 2411 &bo_bucket->dmabuf_fd); 2412 if (ret) 2413 return ret; 2414 } else { 2415 bo_bucket->dmabuf_fd = KFD_INVALID_FD; 2416 } 2417 2418 return 0; 2419 } 2420 2421 static int criu_restore_bos(struct kfd_process *p, 2422 struct kfd_ioctl_criu_args *args, 2423 uint64_t *priv_offset, 2424 uint64_t max_priv_data_size) 2425 { 2426 struct kfd_criu_bo_bucket *bo_buckets = NULL; 2427 struct kfd_criu_bo_priv_data *bo_privs = NULL; 2428 int ret = 0; 2429 uint32_t i = 0; 2430 2431 if (*priv_offset + (args->num_bos * sizeof(*bo_privs)) > max_priv_data_size) 2432 return -EINVAL; 2433 2434 /* Prevent MMU notifications until stage-4 IOCTL (CRIU_RESUME) is received */ 2435 amdgpu_amdkfd_block_mmu_notifications(p->kgd_process_info); 2436 2437 bo_buckets = kvmalloc_array(args->num_bos, sizeof(*bo_buckets), GFP_KERNEL); 2438 if (!bo_buckets) 2439 return -ENOMEM; 2440 2441 ret = copy_from_user(bo_buckets, (void __user *)args->bos, 2442 args->num_bos * sizeof(*bo_buckets)); 2443 if (ret) { 2444 pr_err("Failed to copy BOs information from user\n"); 2445 ret = -EFAULT; 2446 goto exit; 2447 } 2448 2449 bo_privs = kvmalloc_array(args->num_bos, sizeof(*bo_privs), GFP_KERNEL); 2450 if (!bo_privs) { 2451 ret = -ENOMEM; 2452 goto exit; 2453 } 2454 2455 ret = copy_from_user(bo_privs, (void __user *)args->priv_data + *priv_offset, 2456 args->num_bos * sizeof(*bo_privs)); 2457 if (ret) { 2458 pr_err("Failed to copy BOs information from user\n"); 2459 ret = -EFAULT; 2460 goto exit; 2461 } 2462 *priv_offset += args->num_bos * sizeof(*bo_privs); 2463 2464 /* Create and map new BOs */ 2465 for (; i < args->num_bos; i++) { 2466 ret = criu_restore_bo(p, &bo_buckets[i], &bo_privs[i]); 2467 if (ret) { 2468 pr_debug("Failed to restore BO[%d] ret%d\n", i, ret); 2469 goto exit; 2470 } 2471 } /* done */ 2472 2473 /* Copy only the buckets back so user can read bo_buckets[N].restored_offset */ 2474 ret = copy_to_user((void __user *)args->bos, 2475 bo_buckets, 2476 (args->num_bos * sizeof(*bo_buckets))); 2477 if (ret) 2478 ret = -EFAULT; 2479 2480 exit: 2481 while (ret && i--) { 2482 if (bo_buckets[i].alloc_flags 2483 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) 2484 close_fd(bo_buckets[i].dmabuf_fd); 2485 } 2486 kvfree(bo_buckets); 2487 kvfree(bo_privs); 2488 return ret; 2489 } 2490 2491 static int criu_restore_objects(struct file *filep, 2492 struct kfd_process *p, 2493 struct kfd_ioctl_criu_args *args, 2494 uint64_t *priv_offset, 2495 uint64_t max_priv_data_size) 2496 { 2497 int ret = 0; 2498 uint32_t i; 2499 2500 BUILD_BUG_ON(offsetof(struct kfd_criu_queue_priv_data, object_type)); 2501 BUILD_BUG_ON(offsetof(struct kfd_criu_event_priv_data, object_type)); 2502 BUILD_BUG_ON(offsetof(struct kfd_criu_svm_range_priv_data, object_type)); 2503 2504 for (i = 0; i < args->num_objects; i++) { 2505 uint32_t object_type; 2506 2507 if (*priv_offset + sizeof(object_type) > max_priv_data_size) { 2508 pr_err("Invalid private data size\n"); 2509 return -EINVAL; 2510 } 2511 2512 ret = get_user(object_type, (uint32_t __user *)(args->priv_data + *priv_offset)); 2513 if (ret) { 2514 pr_err("Failed to copy private information from user\n"); 2515 goto exit; 2516 } 2517 2518 switch (object_type) { 2519 case KFD_CRIU_OBJECT_TYPE_QUEUE: 2520 ret = kfd_criu_restore_queue(p, (uint8_t __user *)args->priv_data, 2521 priv_offset, max_priv_data_size); 2522 if (ret) 2523 goto exit; 2524 break; 2525 case KFD_CRIU_OBJECT_TYPE_EVENT: 2526 ret = kfd_criu_restore_event(filep, p, (uint8_t __user *)args->priv_data, 2527 priv_offset, max_priv_data_size); 2528 if (ret) 2529 goto exit; 2530 break; 2531 case KFD_CRIU_OBJECT_TYPE_SVM_RANGE: 2532 ret = kfd_criu_restore_svm(p, (uint8_t __user *)args->priv_data, 2533 priv_offset, max_priv_data_size); 2534 if (ret) 2535 goto exit; 2536 break; 2537 default: 2538 pr_err("Invalid object type:%u at index:%d\n", object_type, i); 2539 ret = -EINVAL; 2540 goto exit; 2541 } 2542 } 2543 exit: 2544 return ret; 2545 } 2546 2547 static int criu_restore(struct file *filep, 2548 struct kfd_process *p, 2549 struct kfd_ioctl_criu_args *args) 2550 { 2551 uint64_t priv_offset = 0; 2552 int ret = 0; 2553 2554 pr_debug("CRIU restore (num_devices:%u num_bos:%u num_objects:%u priv_data_size:%llu)\n", 2555 args->num_devices, args->num_bos, args->num_objects, args->priv_data_size); 2556 2557 if (!args->bos || !args->devices || !args->priv_data || !args->priv_data_size || 2558 !args->num_devices || !args->num_bos) 2559 return -EINVAL; 2560 2561 mutex_lock(&p->mutex); 2562 2563 /* 2564 * Set the process to evicted state to avoid running any new queues before all the memory 2565 * mappings are ready. 2566 */ 2567 ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_RESTORE); 2568 if (ret) 2569 goto exit_unlock; 2570 2571 /* Each function will adjust priv_offset based on how many bytes they consumed */ 2572 ret = criu_restore_process(p, args, &priv_offset, args->priv_data_size); 2573 if (ret) 2574 goto exit_unlock; 2575 2576 ret = criu_restore_devices(p, args, &priv_offset, args->priv_data_size); 2577 if (ret) 2578 goto exit_unlock; 2579 2580 ret = criu_restore_bos(p, args, &priv_offset, args->priv_data_size); 2581 if (ret) 2582 goto exit_unlock; 2583 2584 ret = criu_restore_objects(filep, p, args, &priv_offset, args->priv_data_size); 2585 if (ret) 2586 goto exit_unlock; 2587 2588 if (priv_offset != args->priv_data_size) { 2589 pr_err("Invalid private data size\n"); 2590 ret = -EINVAL; 2591 } 2592 2593 exit_unlock: 2594 mutex_unlock(&p->mutex); 2595 if (ret) 2596 pr_err("Failed to restore CRIU ret:%d\n", ret); 2597 else 2598 pr_debug("CRIU restore successful\n"); 2599 2600 return ret; 2601 } 2602 2603 static int criu_unpause(struct file *filep, 2604 struct kfd_process *p, 2605 struct kfd_ioctl_criu_args *args) 2606 { 2607 int ret; 2608 2609 mutex_lock(&p->mutex); 2610 2611 if (!p->queues_paused) { 2612 mutex_unlock(&p->mutex); 2613 return -EINVAL; 2614 } 2615 2616 ret = kfd_process_restore_queues(p); 2617 if (ret) 2618 pr_err("Failed to unpause queues ret:%d\n", ret); 2619 else 2620 p->queues_paused = false; 2621 2622 mutex_unlock(&p->mutex); 2623 2624 return ret; 2625 } 2626 2627 static int criu_resume(struct file *filep, 2628 struct kfd_process *p, 2629 struct kfd_ioctl_criu_args *args) 2630 { 2631 struct kfd_process *target = NULL; 2632 struct pid *pid = NULL; 2633 int ret = 0; 2634 2635 pr_debug("Inside %s, target pid for criu restore: %d\n", __func__, 2636 args->pid); 2637 2638 pid = find_get_pid(args->pid); 2639 if (!pid) { 2640 pr_err("Cannot find pid info for %i\n", args->pid); 2641 return -ESRCH; 2642 } 2643 2644 pr_debug("calling kfd_lookup_process_by_pid\n"); 2645 target = kfd_lookup_process_by_pid(pid); 2646 2647 put_pid(pid); 2648 2649 if (!target) { 2650 pr_debug("Cannot find process info for %i\n", args->pid); 2651 return -ESRCH; 2652 } 2653 2654 mutex_lock(&target->mutex); 2655 ret = kfd_criu_resume_svm(target); 2656 if (ret) { 2657 pr_err("kfd_criu_resume_svm failed for %i\n", args->pid); 2658 goto exit; 2659 } 2660 2661 ret = amdgpu_amdkfd_criu_resume(target->kgd_process_info); 2662 if (ret) 2663 pr_err("amdgpu_amdkfd_criu_resume failed for %i\n", args->pid); 2664 2665 exit: 2666 mutex_unlock(&target->mutex); 2667 2668 kfd_unref_process(target); 2669 return ret; 2670 } 2671 2672 static int criu_process_info(struct file *filep, 2673 struct kfd_process *p, 2674 struct kfd_ioctl_criu_args *args) 2675 { 2676 int ret = 0; 2677 2678 mutex_lock(&p->mutex); 2679 2680 if (!p->n_pdds) { 2681 pr_err("No pdd for given process\n"); 2682 ret = -ENODEV; 2683 goto err_unlock; 2684 } 2685 2686 ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_CHECKPOINT); 2687 if (ret) 2688 goto err_unlock; 2689 2690 p->queues_paused = true; 2691 2692 args->pid = task_pid_nr_ns(p->lead_thread, 2693 task_active_pid_ns(p->lead_thread)); 2694 2695 ret = criu_get_process_object_info(p, &args->num_devices, &args->num_bos, 2696 &args->num_objects, &args->priv_data_size); 2697 if (ret) 2698 goto err_unlock; 2699 2700 dev_dbg(kfd_device, "Num of devices:%u bos:%u objects:%u priv_data_size:%lld\n", 2701 args->num_devices, args->num_bos, args->num_objects, 2702 args->priv_data_size); 2703 2704 err_unlock: 2705 if (ret) { 2706 kfd_process_restore_queues(p); 2707 p->queues_paused = false; 2708 } 2709 mutex_unlock(&p->mutex); 2710 return ret; 2711 } 2712 2713 static int kfd_ioctl_criu(struct file *filep, struct kfd_process *p, void *data) 2714 { 2715 struct kfd_ioctl_criu_args *args = data; 2716 int ret; 2717 2718 dev_dbg(kfd_device, "CRIU operation: %d\n", args->op); 2719 switch (args->op) { 2720 case KFD_CRIU_OP_PROCESS_INFO: 2721 ret = criu_process_info(filep, p, args); 2722 break; 2723 case KFD_CRIU_OP_CHECKPOINT: 2724 ret = criu_checkpoint(filep, p, args); 2725 break; 2726 case KFD_CRIU_OP_UNPAUSE: 2727 ret = criu_unpause(filep, p, args); 2728 break; 2729 case KFD_CRIU_OP_RESTORE: 2730 ret = criu_restore(filep, p, args); 2731 break; 2732 case KFD_CRIU_OP_RESUME: 2733 ret = criu_resume(filep, p, args); 2734 break; 2735 default: 2736 dev_dbg(kfd_device, "Unsupported CRIU operation:%d\n", args->op); 2737 ret = -EINVAL; 2738 break; 2739 } 2740 2741 if (ret) 2742 dev_dbg(kfd_device, "CRIU operation:%d err:%d\n", args->op, ret); 2743 2744 return ret; 2745 } 2746 2747 static int runtime_enable(struct kfd_process *p, uint64_t r_debug, 2748 bool enable_ttmp_setup) 2749 { 2750 int i = 0, ret = 0; 2751 2752 if (p->is_runtime_retry) 2753 goto retry; 2754 2755 if (p->runtime_info.runtime_state != DEBUG_RUNTIME_STATE_DISABLED) 2756 return -EBUSY; 2757 2758 for (i = 0; i < p->n_pdds; i++) { 2759 struct kfd_process_device *pdd = p->pdds[i]; 2760 2761 if (pdd->qpd.queue_count) 2762 return -EEXIST; 2763 2764 /* 2765 * Setup TTMPs by default. 2766 * Note that this call must remain here for MES ADD QUEUE to 2767 * skip_process_ctx_clear unconditionally as the first call to 2768 * SET_SHADER_DEBUGGER clears any stale process context data 2769 * saved in MES. 2770 */ 2771 if (pdd->dev->kfd->shared_resources.enable_mes) 2772 kfd_dbg_set_mes_debug_mode(pdd, !kfd_dbg_has_cwsr_workaround(pdd->dev)); 2773 } 2774 2775 p->runtime_info.runtime_state = DEBUG_RUNTIME_STATE_ENABLED; 2776 p->runtime_info.r_debug = r_debug; 2777 p->runtime_info.ttmp_setup = enable_ttmp_setup; 2778 2779 if (p->runtime_info.ttmp_setup) { 2780 for (i = 0; i < p->n_pdds; i++) { 2781 struct kfd_process_device *pdd = p->pdds[i]; 2782 2783 if (!kfd_dbg_is_rlc_restore_supported(pdd->dev)) { 2784 amdgpu_gfx_off_ctrl(pdd->dev->adev, false); 2785 pdd->dev->kfd2kgd->enable_debug_trap( 2786 pdd->dev->adev, 2787 true, 2788 pdd->dev->vm_info.last_vmid_kfd); 2789 } else if (kfd_dbg_is_per_vmid_supported(pdd->dev)) { 2790 pdd->spi_dbg_override = pdd->dev->kfd2kgd->enable_debug_trap( 2791 pdd->dev->adev, 2792 false, 2793 0); 2794 } 2795 } 2796 } 2797 2798 retry: 2799 if (p->debug_trap_enabled) { 2800 if (!p->is_runtime_retry) { 2801 kfd_dbg_trap_activate(p); 2802 kfd_dbg_ev_raise(KFD_EC_MASK(EC_PROCESS_RUNTIME), 2803 p, NULL, 0, false, NULL, 0); 2804 } 2805 2806 mutex_unlock(&p->mutex); 2807 ret = down_interruptible(&p->runtime_enable_sema); 2808 mutex_lock(&p->mutex); 2809 2810 p->is_runtime_retry = !!ret; 2811 } 2812 2813 return ret; 2814 } 2815 2816 static int runtime_disable(struct kfd_process *p) 2817 { 2818 int i = 0, ret; 2819 bool was_enabled = p->runtime_info.runtime_state == DEBUG_RUNTIME_STATE_ENABLED; 2820 2821 p->runtime_info.runtime_state = DEBUG_RUNTIME_STATE_DISABLED; 2822 p->runtime_info.r_debug = 0; 2823 2824 if (p->debug_trap_enabled) { 2825 if (was_enabled) 2826 kfd_dbg_trap_deactivate(p, false, 0); 2827 2828 if (!p->is_runtime_retry) 2829 kfd_dbg_ev_raise(KFD_EC_MASK(EC_PROCESS_RUNTIME), 2830 p, NULL, 0, false, NULL, 0); 2831 2832 mutex_unlock(&p->mutex); 2833 ret = down_interruptible(&p->runtime_enable_sema); 2834 mutex_lock(&p->mutex); 2835 2836 p->is_runtime_retry = !!ret; 2837 if (ret) 2838 return ret; 2839 } 2840 2841 if (was_enabled && p->runtime_info.ttmp_setup) { 2842 for (i = 0; i < p->n_pdds; i++) { 2843 struct kfd_process_device *pdd = p->pdds[i]; 2844 2845 if (!kfd_dbg_is_rlc_restore_supported(pdd->dev)) 2846 amdgpu_gfx_off_ctrl(pdd->dev->adev, true); 2847 } 2848 } 2849 2850 p->runtime_info.ttmp_setup = false; 2851 2852 /* disable ttmp setup */ 2853 for (i = 0; i < p->n_pdds; i++) { 2854 struct kfd_process_device *pdd = p->pdds[i]; 2855 2856 if (kfd_dbg_is_per_vmid_supported(pdd->dev)) { 2857 pdd->spi_dbg_override = 2858 pdd->dev->kfd2kgd->disable_debug_trap( 2859 pdd->dev->adev, 2860 false, 2861 pdd->dev->vm_info.last_vmid_kfd); 2862 2863 if (!pdd->dev->kfd->shared_resources.enable_mes) 2864 debug_refresh_runlist(pdd->dev->dqm); 2865 else 2866 kfd_dbg_set_mes_debug_mode(pdd, 2867 !kfd_dbg_has_cwsr_workaround(pdd->dev)); 2868 } 2869 } 2870 2871 return 0; 2872 } 2873 2874 static int kfd_ioctl_runtime_enable(struct file *filep, struct kfd_process *p, void *data) 2875 { 2876 struct kfd_ioctl_runtime_enable_args *args = data; 2877 int r; 2878 2879 mutex_lock(&p->mutex); 2880 2881 if (args->mode_mask & KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK) 2882 r = runtime_enable(p, args->r_debug, 2883 !!(args->mode_mask & KFD_RUNTIME_ENABLE_MODE_TTMP_SAVE_MASK)); 2884 else 2885 r = runtime_disable(p); 2886 2887 mutex_unlock(&p->mutex); 2888 2889 return r; 2890 } 2891 2892 static int kfd_ioctl_set_debug_trap(struct file *filep, struct kfd_process *p, void *data) 2893 { 2894 struct kfd_ioctl_dbg_trap_args *args = data; 2895 struct task_struct *thread = NULL; 2896 struct mm_struct *mm = NULL; 2897 struct pid *pid = NULL; 2898 struct kfd_process *target = NULL; 2899 struct kfd_process_device *pdd = NULL; 2900 int r = 0; 2901 2902 if (sched_policy == KFD_SCHED_POLICY_NO_HWS) { 2903 pr_err("Debugging does not support sched_policy %i", sched_policy); 2904 return -EINVAL; 2905 } 2906 2907 pid = find_get_pid(args->pid); 2908 if (!pid) { 2909 pr_debug("Cannot find pid info for %i\n", args->pid); 2910 r = -ESRCH; 2911 goto out; 2912 } 2913 2914 thread = get_pid_task(pid, PIDTYPE_PID); 2915 if (!thread) { 2916 r = -ESRCH; 2917 goto out; 2918 } 2919 2920 mm = get_task_mm(thread); 2921 if (!mm) { 2922 r = -ESRCH; 2923 goto out; 2924 } 2925 2926 if (args->op == KFD_IOC_DBG_TRAP_ENABLE) { 2927 bool create_process; 2928 2929 rcu_read_lock(); 2930 create_process = thread && thread != current && ptrace_parent(thread) == current; 2931 rcu_read_unlock(); 2932 2933 target = create_process ? kfd_create_process(thread) : 2934 kfd_lookup_process_by_pid(pid); 2935 } else { 2936 target = kfd_lookup_process_by_pid(pid); 2937 } 2938 2939 if (IS_ERR_OR_NULL(target)) { 2940 pr_debug("Cannot find process PID %i to debug\n", args->pid); 2941 r = target ? PTR_ERR(target) : -ESRCH; 2942 goto out; 2943 } 2944 2945 /* Check if target is still PTRACED. */ 2946 rcu_read_lock(); 2947 if (target != p && args->op != KFD_IOC_DBG_TRAP_DISABLE 2948 && ptrace_parent(target->lead_thread) != current) { 2949 pr_err("PID %i is not PTRACED and cannot be debugged\n", args->pid); 2950 r = -EPERM; 2951 } 2952 rcu_read_unlock(); 2953 2954 if (r) 2955 goto out; 2956 2957 mutex_lock(&target->mutex); 2958 2959 if (args->op != KFD_IOC_DBG_TRAP_ENABLE && !target->debug_trap_enabled) { 2960 pr_err("PID %i not debug enabled for op %i\n", args->pid, args->op); 2961 r = -EINVAL; 2962 goto unlock_out; 2963 } 2964 2965 if (target->runtime_info.runtime_state != DEBUG_RUNTIME_STATE_ENABLED && 2966 (args->op == KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE || 2967 args->op == KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE || 2968 args->op == KFD_IOC_DBG_TRAP_SUSPEND_QUEUES || 2969 args->op == KFD_IOC_DBG_TRAP_RESUME_QUEUES || 2970 args->op == KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH || 2971 args->op == KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH || 2972 args->op == KFD_IOC_DBG_TRAP_SET_FLAGS)) { 2973 r = -EPERM; 2974 goto unlock_out; 2975 } 2976 2977 if (args->op == KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH || 2978 args->op == KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH) { 2979 int user_gpu_id = kfd_process_get_user_gpu_id(target, 2980 args->op == KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH ? 2981 args->set_node_address_watch.gpu_id : 2982 args->clear_node_address_watch.gpu_id); 2983 2984 pdd = kfd_process_device_data_by_id(target, user_gpu_id); 2985 if (user_gpu_id == -EINVAL || !pdd) { 2986 r = -ENODEV; 2987 goto unlock_out; 2988 } 2989 } 2990 2991 switch (args->op) { 2992 case KFD_IOC_DBG_TRAP_ENABLE: 2993 if (target != p) 2994 target->debugger_process = p; 2995 2996 r = kfd_dbg_trap_enable(target, 2997 args->enable.dbg_fd, 2998 (void __user *)args->enable.rinfo_ptr, 2999 &args->enable.rinfo_size); 3000 if (!r) 3001 target->exception_enable_mask = args->enable.exception_mask; 3002 3003 break; 3004 case KFD_IOC_DBG_TRAP_DISABLE: 3005 r = kfd_dbg_trap_disable(target); 3006 break; 3007 case KFD_IOC_DBG_TRAP_SEND_RUNTIME_EVENT: 3008 r = kfd_dbg_send_exception_to_runtime(target, 3009 args->send_runtime_event.gpu_id, 3010 args->send_runtime_event.queue_id, 3011 args->send_runtime_event.exception_mask); 3012 break; 3013 case KFD_IOC_DBG_TRAP_SET_EXCEPTIONS_ENABLED: 3014 kfd_dbg_set_enabled_debug_exception_mask(target, 3015 args->set_exceptions_enabled.exception_mask); 3016 break; 3017 case KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE: 3018 r = kfd_dbg_trap_set_wave_launch_override(target, 3019 args->launch_override.override_mode, 3020 args->launch_override.enable_mask, 3021 args->launch_override.support_request_mask, 3022 &args->launch_override.enable_mask, 3023 &args->launch_override.support_request_mask); 3024 break; 3025 case KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE: 3026 r = kfd_dbg_trap_set_wave_launch_mode(target, 3027 args->launch_mode.launch_mode); 3028 break; 3029 case KFD_IOC_DBG_TRAP_SUSPEND_QUEUES: 3030 r = suspend_queues(target, 3031 args->suspend_queues.num_queues, 3032 args->suspend_queues.grace_period, 3033 args->suspend_queues.exception_mask, 3034 (uint32_t *)args->suspend_queues.queue_array_ptr); 3035 3036 break; 3037 case KFD_IOC_DBG_TRAP_RESUME_QUEUES: 3038 r = resume_queues(target, args->resume_queues.num_queues, 3039 (uint32_t *)args->resume_queues.queue_array_ptr); 3040 break; 3041 case KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH: 3042 r = kfd_dbg_trap_set_dev_address_watch(pdd, 3043 args->set_node_address_watch.address, 3044 args->set_node_address_watch.mask, 3045 &args->set_node_address_watch.id, 3046 args->set_node_address_watch.mode); 3047 break; 3048 case KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH: 3049 r = kfd_dbg_trap_clear_dev_address_watch(pdd, 3050 args->clear_node_address_watch.id); 3051 break; 3052 case KFD_IOC_DBG_TRAP_SET_FLAGS: 3053 r = kfd_dbg_trap_set_flags(target, &args->set_flags.flags); 3054 break; 3055 case KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT: 3056 r = kfd_dbg_ev_query_debug_event(target, 3057 &args->query_debug_event.queue_id, 3058 &args->query_debug_event.gpu_id, 3059 args->query_debug_event.exception_mask, 3060 &args->query_debug_event.exception_mask); 3061 break; 3062 case KFD_IOC_DBG_TRAP_QUERY_EXCEPTION_INFO: 3063 r = kfd_dbg_trap_query_exception_info(target, 3064 args->query_exception_info.source_id, 3065 args->query_exception_info.exception_code, 3066 args->query_exception_info.clear_exception, 3067 (void __user *)args->query_exception_info.info_ptr, 3068 &args->query_exception_info.info_size); 3069 break; 3070 case KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT: 3071 r = pqm_get_queue_snapshot(&target->pqm, 3072 args->queue_snapshot.exception_mask, 3073 (void __user *)args->queue_snapshot.snapshot_buf_ptr, 3074 &args->queue_snapshot.num_queues, 3075 &args->queue_snapshot.entry_size); 3076 break; 3077 case KFD_IOC_DBG_TRAP_GET_DEVICE_SNAPSHOT: 3078 r = kfd_dbg_trap_device_snapshot(target, 3079 args->device_snapshot.exception_mask, 3080 (void __user *)args->device_snapshot.snapshot_buf_ptr, 3081 &args->device_snapshot.num_devices, 3082 &args->device_snapshot.entry_size); 3083 break; 3084 default: 3085 pr_err("Invalid option: %i\n", args->op); 3086 r = -EINVAL; 3087 } 3088 3089 unlock_out: 3090 mutex_unlock(&target->mutex); 3091 3092 out: 3093 if (thread) 3094 put_task_struct(thread); 3095 3096 if (mm) 3097 mmput(mm); 3098 3099 if (pid) 3100 put_pid(pid); 3101 3102 if (target) 3103 kfd_unref_process(target); 3104 3105 return r; 3106 } 3107 3108 #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \ 3109 [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \ 3110 .cmd_drv = 0, .name = #ioctl} 3111 3112 /** Ioctl table */ 3113 static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { 3114 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_VERSION, 3115 kfd_ioctl_get_version, 0), 3116 3117 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_QUEUE, 3118 kfd_ioctl_create_queue, 0), 3119 3120 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_QUEUE, 3121 kfd_ioctl_destroy_queue, 0), 3122 3123 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_MEMORY_POLICY, 3124 kfd_ioctl_set_memory_policy, 0), 3125 3126 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_CLOCK_COUNTERS, 3127 kfd_ioctl_get_clock_counters, 0), 3128 3129 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES, 3130 kfd_ioctl_get_process_apertures, 0), 3131 3132 AMDKFD_IOCTL_DEF(AMDKFD_IOC_UPDATE_QUEUE, 3133 kfd_ioctl_update_queue, 0), 3134 3135 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_EVENT, 3136 kfd_ioctl_create_event, 0), 3137 3138 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_EVENT, 3139 kfd_ioctl_destroy_event, 0), 3140 3141 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_EVENT, 3142 kfd_ioctl_set_event, 0), 3143 3144 AMDKFD_IOCTL_DEF(AMDKFD_IOC_RESET_EVENT, 3145 kfd_ioctl_reset_event, 0), 3146 3147 AMDKFD_IOCTL_DEF(AMDKFD_IOC_WAIT_EVENTS, 3148 kfd_ioctl_wait_events, 0), 3149 3150 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_REGISTER_DEPRECATED, 3151 kfd_ioctl_dbg_register, 0), 3152 3153 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_UNREGISTER_DEPRECATED, 3154 kfd_ioctl_dbg_unregister, 0), 3155 3156 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_ADDRESS_WATCH_DEPRECATED, 3157 kfd_ioctl_dbg_address_watch, 0), 3158 3159 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_WAVE_CONTROL_DEPRECATED, 3160 kfd_ioctl_dbg_wave_control, 0), 3161 3162 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_SCRATCH_BACKING_VA, 3163 kfd_ioctl_set_scratch_backing_va, 0), 3164 3165 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_TILE_CONFIG, 3166 kfd_ioctl_get_tile_config, 0), 3167 3168 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_TRAP_HANDLER, 3169 kfd_ioctl_set_trap_handler, 0), 3170 3171 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES_NEW, 3172 kfd_ioctl_get_process_apertures_new, 0), 3173 3174 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ACQUIRE_VM, 3175 kfd_ioctl_acquire_vm, 0), 3176 3177 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_MEMORY_OF_GPU, 3178 kfd_ioctl_alloc_memory_of_gpu, 0), 3179 3180 AMDKFD_IOCTL_DEF(AMDKFD_IOC_FREE_MEMORY_OF_GPU, 3181 kfd_ioctl_free_memory_of_gpu, 0), 3182 3183 AMDKFD_IOCTL_DEF(AMDKFD_IOC_MAP_MEMORY_TO_GPU, 3184 kfd_ioctl_map_memory_to_gpu, 0), 3185 3186 AMDKFD_IOCTL_DEF(AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU, 3187 kfd_ioctl_unmap_memory_from_gpu, 0), 3188 3189 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_CU_MASK, 3190 kfd_ioctl_set_cu_mask, 0), 3191 3192 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_QUEUE_WAVE_STATE, 3193 kfd_ioctl_get_queue_wave_state, 0), 3194 3195 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_DMABUF_INFO, 3196 kfd_ioctl_get_dmabuf_info, 0), 3197 3198 AMDKFD_IOCTL_DEF(AMDKFD_IOC_IMPORT_DMABUF, 3199 kfd_ioctl_import_dmabuf, 0), 3200 3201 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_QUEUE_GWS, 3202 kfd_ioctl_alloc_queue_gws, 0), 3203 3204 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SMI_EVENTS, 3205 kfd_ioctl_smi_events, 0), 3206 3207 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SVM, kfd_ioctl_svm, 0), 3208 3209 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_XNACK_MODE, 3210 kfd_ioctl_set_xnack_mode, 0), 3211 3212 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CRIU_OP, 3213 kfd_ioctl_criu, KFD_IOC_FLAG_CHECKPOINT_RESTORE), 3214 3215 AMDKFD_IOCTL_DEF(AMDKFD_IOC_AVAILABLE_MEMORY, 3216 kfd_ioctl_get_available_memory, 0), 3217 3218 AMDKFD_IOCTL_DEF(AMDKFD_IOC_EXPORT_DMABUF, 3219 kfd_ioctl_export_dmabuf, 0), 3220 3221 AMDKFD_IOCTL_DEF(AMDKFD_IOC_RUNTIME_ENABLE, 3222 kfd_ioctl_runtime_enable, 0), 3223 3224 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_TRAP, 3225 kfd_ioctl_set_debug_trap, 0), 3226 }; 3227 3228 #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls) 3229 3230 static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) 3231 { 3232 struct kfd_process *process; 3233 amdkfd_ioctl_t *func; 3234 const struct amdkfd_ioctl_desc *ioctl = NULL; 3235 unsigned int nr = _IOC_NR(cmd); 3236 char stack_kdata[128]; 3237 char *kdata = NULL; 3238 unsigned int usize, asize; 3239 int retcode = -EINVAL; 3240 bool ptrace_attached = false; 3241 3242 if (nr >= AMDKFD_CORE_IOCTL_COUNT) 3243 goto err_i1; 3244 3245 if ((nr >= AMDKFD_COMMAND_START) && (nr < AMDKFD_COMMAND_END)) { 3246 u32 amdkfd_size; 3247 3248 ioctl = &amdkfd_ioctls[nr]; 3249 3250 amdkfd_size = _IOC_SIZE(ioctl->cmd); 3251 usize = asize = _IOC_SIZE(cmd); 3252 if (amdkfd_size > asize) 3253 asize = amdkfd_size; 3254 3255 cmd = ioctl->cmd; 3256 } else 3257 goto err_i1; 3258 3259 dev_dbg(kfd_device, "ioctl cmd 0x%x (#0x%x), arg 0x%lx\n", cmd, nr, arg); 3260 3261 /* Get the process struct from the filep. Only the process 3262 * that opened /dev/kfd can use the file descriptor. Child 3263 * processes need to create their own KFD device context. 3264 */ 3265 process = filep->private_data; 3266 3267 rcu_read_lock(); 3268 if ((ioctl->flags & KFD_IOC_FLAG_CHECKPOINT_RESTORE) && 3269 ptrace_parent(process->lead_thread) == current) 3270 ptrace_attached = true; 3271 rcu_read_unlock(); 3272 3273 if (process->lead_thread != current->group_leader 3274 && !ptrace_attached) { 3275 dev_dbg(kfd_device, "Using KFD FD in wrong process\n"); 3276 retcode = -EBADF; 3277 goto err_i1; 3278 } 3279 3280 /* Do not trust userspace, use our own definition */ 3281 func = ioctl->func; 3282 3283 if (unlikely(!func)) { 3284 dev_dbg(kfd_device, "no function\n"); 3285 retcode = -EINVAL; 3286 goto err_i1; 3287 } 3288 3289 /* 3290 * Versions of docker shipped in Ubuntu 18.xx and 20.xx do not support 3291 * CAP_CHECKPOINT_RESTORE, so we also allow access if CAP_SYS_ADMIN as CAP_SYS_ADMIN is a 3292 * more priviledged access. 3293 */ 3294 if (unlikely(ioctl->flags & KFD_IOC_FLAG_CHECKPOINT_RESTORE)) { 3295 if (!capable(CAP_CHECKPOINT_RESTORE) && 3296 !capable(CAP_SYS_ADMIN)) { 3297 retcode = -EACCES; 3298 goto err_i1; 3299 } 3300 } 3301 3302 if (cmd & (IOC_IN | IOC_OUT)) { 3303 if (asize <= sizeof(stack_kdata)) { 3304 kdata = stack_kdata; 3305 } else { 3306 kdata = kmalloc(asize, GFP_KERNEL); 3307 if (!kdata) { 3308 retcode = -ENOMEM; 3309 goto err_i1; 3310 } 3311 } 3312 if (asize > usize) 3313 memset(kdata + usize, 0, asize - usize); 3314 } 3315 3316 if (cmd & IOC_IN) { 3317 if (copy_from_user(kdata, (void __user *)arg, usize) != 0) { 3318 retcode = -EFAULT; 3319 goto err_i1; 3320 } 3321 } else if (cmd & IOC_OUT) { 3322 memset(kdata, 0, usize); 3323 } 3324 3325 retcode = func(filep, process, kdata); 3326 3327 if (cmd & IOC_OUT) 3328 if (copy_to_user((void __user *)arg, kdata, usize) != 0) 3329 retcode = -EFAULT; 3330 3331 err_i1: 3332 if (!ioctl) 3333 dev_dbg(kfd_device, "invalid ioctl: pid=%d, cmd=0x%02x, nr=0x%02x\n", 3334 task_pid_nr(current), cmd, nr); 3335 3336 if (kdata != stack_kdata) 3337 kfree(kdata); 3338 3339 if (retcode) 3340 dev_dbg(kfd_device, "ioctl cmd (#0x%x), arg 0x%lx, ret = %d\n", 3341 nr, arg, retcode); 3342 3343 return retcode; 3344 } 3345 3346 static int kfd_mmio_mmap(struct kfd_node *dev, struct kfd_process *process, 3347 struct vm_area_struct *vma) 3348 { 3349 phys_addr_t address; 3350 3351 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 3352 return -EINVAL; 3353 3354 address = dev->adev->rmmio_remap.bus_addr; 3355 3356 vm_flags_set(vma, VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_NORESERVE | 3357 VM_DONTDUMP | VM_PFNMAP); 3358 3359 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 3360 3361 pr_debug("pasid 0x%x mapping mmio page\n" 3362 " target user address == 0x%08llX\n" 3363 " physical address == 0x%08llX\n" 3364 " vm_flags == 0x%04lX\n" 3365 " size == 0x%04lX\n", 3366 process->pasid, (unsigned long long) vma->vm_start, 3367 address, vma->vm_flags, PAGE_SIZE); 3368 3369 return io_remap_pfn_range(vma, 3370 vma->vm_start, 3371 address >> PAGE_SHIFT, 3372 PAGE_SIZE, 3373 vma->vm_page_prot); 3374 } 3375 3376 3377 static int kfd_mmap(struct file *filp, struct vm_area_struct *vma) 3378 { 3379 struct kfd_process *process; 3380 struct kfd_node *dev = NULL; 3381 unsigned long mmap_offset; 3382 unsigned int gpu_id; 3383 3384 process = kfd_get_process(current); 3385 if (IS_ERR(process)) 3386 return PTR_ERR(process); 3387 3388 mmap_offset = vma->vm_pgoff << PAGE_SHIFT; 3389 gpu_id = KFD_MMAP_GET_GPU_ID(mmap_offset); 3390 if (gpu_id) 3391 dev = kfd_device_by_id(gpu_id); 3392 3393 switch (mmap_offset & KFD_MMAP_TYPE_MASK) { 3394 case KFD_MMAP_TYPE_DOORBELL: 3395 if (!dev) 3396 return -ENODEV; 3397 return kfd_doorbell_mmap(dev, process, vma); 3398 3399 case KFD_MMAP_TYPE_EVENTS: 3400 return kfd_event_mmap(process, vma); 3401 3402 case KFD_MMAP_TYPE_RESERVED_MEM: 3403 if (!dev) 3404 return -ENODEV; 3405 return kfd_reserved_mem_mmap(dev, process, vma); 3406 case KFD_MMAP_TYPE_MMIO: 3407 if (!dev) 3408 return -ENODEV; 3409 return kfd_mmio_mmap(dev, process, vma); 3410 } 3411 3412 return -EFAULT; 3413 } 3414