1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/device.h> 25 #include <linux/export.h> 26 #include <linux/err.h> 27 #include <linux/fs.h> 28 #include <linux/file.h> 29 #include <linux/sched.h> 30 #include <linux/slab.h> 31 #include <linux/uaccess.h> 32 #include <linux/compat.h> 33 #include <uapi/linux/kfd_ioctl.h> 34 #include <linux/time.h> 35 #include <linux/mm.h> 36 #include <linux/mman.h> 37 #include <linux/ptrace.h> 38 #include <linux/dma-buf.h> 39 #include <linux/fdtable.h> 40 #include <linux/processor.h> 41 #include "kfd_priv.h" 42 #include "kfd_device_queue_manager.h" 43 #include "kfd_svm.h" 44 #include "amdgpu_amdkfd.h" 45 #include "kfd_smi_events.h" 46 #include "amdgpu_dma_buf.h" 47 48 static long kfd_ioctl(struct file *, unsigned int, unsigned long); 49 static int kfd_open(struct inode *, struct file *); 50 static int kfd_release(struct inode *, struct file *); 51 static int kfd_mmap(struct file *, struct vm_area_struct *); 52 53 static const char kfd_dev_name[] = "kfd"; 54 55 static const struct file_operations kfd_fops = { 56 .owner = THIS_MODULE, 57 .unlocked_ioctl = kfd_ioctl, 58 .compat_ioctl = compat_ptr_ioctl, 59 .open = kfd_open, 60 .release = kfd_release, 61 .mmap = kfd_mmap, 62 }; 63 64 static int kfd_char_dev_major = -1; 65 static struct class *kfd_class; 66 struct device *kfd_device; 67 68 static inline struct kfd_process_device *kfd_lock_pdd_by_id(struct kfd_process *p, __u32 gpu_id) 69 { 70 struct kfd_process_device *pdd; 71 72 mutex_lock(&p->mutex); 73 pdd = kfd_process_device_data_by_id(p, gpu_id); 74 75 if (pdd) 76 return pdd; 77 78 mutex_unlock(&p->mutex); 79 return NULL; 80 } 81 82 static inline void kfd_unlock_pdd(struct kfd_process_device *pdd) 83 { 84 mutex_unlock(&pdd->process->mutex); 85 } 86 87 int kfd_chardev_init(void) 88 { 89 int err = 0; 90 91 kfd_char_dev_major = register_chrdev(0, kfd_dev_name, &kfd_fops); 92 err = kfd_char_dev_major; 93 if (err < 0) 94 goto err_register_chrdev; 95 96 kfd_class = class_create(THIS_MODULE, kfd_dev_name); 97 err = PTR_ERR(kfd_class); 98 if (IS_ERR(kfd_class)) 99 goto err_class_create; 100 101 kfd_device = device_create(kfd_class, NULL, 102 MKDEV(kfd_char_dev_major, 0), 103 NULL, kfd_dev_name); 104 err = PTR_ERR(kfd_device); 105 if (IS_ERR(kfd_device)) 106 goto err_device_create; 107 108 return 0; 109 110 err_device_create: 111 class_destroy(kfd_class); 112 err_class_create: 113 unregister_chrdev(kfd_char_dev_major, kfd_dev_name); 114 err_register_chrdev: 115 return err; 116 } 117 118 void kfd_chardev_exit(void) 119 { 120 device_destroy(kfd_class, MKDEV(kfd_char_dev_major, 0)); 121 class_destroy(kfd_class); 122 unregister_chrdev(kfd_char_dev_major, kfd_dev_name); 123 kfd_device = NULL; 124 } 125 126 127 static int kfd_open(struct inode *inode, struct file *filep) 128 { 129 struct kfd_process *process; 130 bool is_32bit_user_mode; 131 132 if (iminor(inode) != 0) 133 return -ENODEV; 134 135 is_32bit_user_mode = in_compat_syscall(); 136 137 if (is_32bit_user_mode) { 138 dev_warn(kfd_device, 139 "Process %d (32-bit) failed to open /dev/kfd\n" 140 "32-bit processes are not supported by amdkfd\n", 141 current->pid); 142 return -EPERM; 143 } 144 145 process = kfd_create_process(filep); 146 if (IS_ERR(process)) 147 return PTR_ERR(process); 148 149 /* filep now owns the reference returned by kfd_create_process */ 150 filep->private_data = process; 151 152 dev_dbg(kfd_device, "process %d opened, compat mode (32 bit) - %d\n", 153 process->pasid, process->is_32bit_user_mode); 154 155 return 0; 156 } 157 158 static int kfd_release(struct inode *inode, struct file *filep) 159 { 160 struct kfd_process *process = filep->private_data; 161 162 if (process) 163 kfd_unref_process(process); 164 165 return 0; 166 } 167 168 static int kfd_ioctl_get_version(struct file *filep, struct kfd_process *p, 169 void *data) 170 { 171 struct kfd_ioctl_get_version_args *args = data; 172 173 args->major_version = KFD_IOCTL_MAJOR_VERSION; 174 args->minor_version = KFD_IOCTL_MINOR_VERSION; 175 176 return 0; 177 } 178 179 static int set_queue_properties_from_user(struct queue_properties *q_properties, 180 struct kfd_ioctl_create_queue_args *args) 181 { 182 /* 183 * Repurpose queue percentage to accommodate new features: 184 * bit 0-7: queue percentage 185 * bit 8-15: pm4_target_xcc 186 */ 187 if ((args->queue_percentage & 0xFF) > KFD_MAX_QUEUE_PERCENTAGE) { 188 pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n"); 189 return -EINVAL; 190 } 191 192 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) { 193 pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n"); 194 return -EINVAL; 195 } 196 197 if ((args->ring_base_address) && 198 (!access_ok((const void __user *) args->ring_base_address, 199 sizeof(uint64_t)))) { 200 pr_err("Can't access ring base address\n"); 201 return -EFAULT; 202 } 203 204 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) { 205 pr_err("Ring size must be a power of 2 or 0\n"); 206 return -EINVAL; 207 } 208 209 if (!access_ok((const void __user *) args->read_pointer_address, 210 sizeof(uint32_t))) { 211 pr_err("Can't access read pointer\n"); 212 return -EFAULT; 213 } 214 215 if (!access_ok((const void __user *) args->write_pointer_address, 216 sizeof(uint32_t))) { 217 pr_err("Can't access write pointer\n"); 218 return -EFAULT; 219 } 220 221 if (args->eop_buffer_address && 222 !access_ok((const void __user *) args->eop_buffer_address, 223 sizeof(uint32_t))) { 224 pr_debug("Can't access eop buffer"); 225 return -EFAULT; 226 } 227 228 if (args->ctx_save_restore_address && 229 !access_ok((const void __user *) args->ctx_save_restore_address, 230 sizeof(uint32_t))) { 231 pr_debug("Can't access ctx save restore buffer"); 232 return -EFAULT; 233 } 234 235 q_properties->is_interop = false; 236 q_properties->is_gws = false; 237 q_properties->queue_percent = args->queue_percentage & 0xFF; 238 /* bit 8-15 are repurposed to be PM4 target XCC */ 239 q_properties->pm4_target_xcc = (args->queue_percentage >> 8) & 0xFF; 240 q_properties->priority = args->queue_priority; 241 q_properties->queue_address = args->ring_base_address; 242 q_properties->queue_size = args->ring_size; 243 q_properties->read_ptr = (uint32_t *) args->read_pointer_address; 244 q_properties->write_ptr = (uint32_t *) args->write_pointer_address; 245 q_properties->eop_ring_buffer_address = args->eop_buffer_address; 246 q_properties->eop_ring_buffer_size = args->eop_buffer_size; 247 q_properties->ctx_save_restore_area_address = 248 args->ctx_save_restore_address; 249 q_properties->ctx_save_restore_area_size = args->ctx_save_restore_size; 250 q_properties->ctl_stack_size = args->ctl_stack_size; 251 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE || 252 args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL) 253 q_properties->type = KFD_QUEUE_TYPE_COMPUTE; 254 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA) 255 q_properties->type = KFD_QUEUE_TYPE_SDMA; 256 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA_XGMI) 257 q_properties->type = KFD_QUEUE_TYPE_SDMA_XGMI; 258 else 259 return -ENOTSUPP; 260 261 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL) 262 q_properties->format = KFD_QUEUE_FORMAT_AQL; 263 else 264 q_properties->format = KFD_QUEUE_FORMAT_PM4; 265 266 pr_debug("Queue Percentage: %d, %d\n", 267 q_properties->queue_percent, args->queue_percentage); 268 269 pr_debug("Queue Priority: %d, %d\n", 270 q_properties->priority, args->queue_priority); 271 272 pr_debug("Queue Address: 0x%llX, 0x%llX\n", 273 q_properties->queue_address, args->ring_base_address); 274 275 pr_debug("Queue Size: 0x%llX, %u\n", 276 q_properties->queue_size, args->ring_size); 277 278 pr_debug("Queue r/w Pointers: %px, %px\n", 279 q_properties->read_ptr, 280 q_properties->write_ptr); 281 282 pr_debug("Queue Format: %d\n", q_properties->format); 283 284 pr_debug("Queue EOP: 0x%llX\n", q_properties->eop_ring_buffer_address); 285 286 pr_debug("Queue CTX save area: 0x%llX\n", 287 q_properties->ctx_save_restore_area_address); 288 289 return 0; 290 } 291 292 static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p, 293 void *data) 294 { 295 struct kfd_ioctl_create_queue_args *args = data; 296 struct kfd_node *dev; 297 int err = 0; 298 unsigned int queue_id; 299 struct kfd_process_device *pdd; 300 struct queue_properties q_properties; 301 uint32_t doorbell_offset_in_process = 0; 302 struct amdgpu_bo *wptr_bo = NULL; 303 304 memset(&q_properties, 0, sizeof(struct queue_properties)); 305 306 pr_debug("Creating queue ioctl\n"); 307 308 err = set_queue_properties_from_user(&q_properties, args); 309 if (err) 310 return err; 311 312 pr_debug("Looking for gpu id 0x%x\n", args->gpu_id); 313 314 mutex_lock(&p->mutex); 315 316 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 317 if (!pdd) { 318 pr_debug("Could not find gpu id 0x%x\n", args->gpu_id); 319 err = -EINVAL; 320 goto err_pdd; 321 } 322 dev = pdd->dev; 323 324 pdd = kfd_bind_process_to_device(dev, p); 325 if (IS_ERR(pdd)) { 326 err = -ESRCH; 327 goto err_bind_process; 328 } 329 330 if (!pdd->doorbell_index && 331 kfd_alloc_process_doorbells(dev->kfd, &pdd->doorbell_index) < 0) { 332 err = -ENOMEM; 333 goto err_alloc_doorbells; 334 } 335 336 /* Starting with GFX11, wptr BOs must be mapped to GART for MES to determine work 337 * on unmapped queues for usermode queue oversubscription (no aggregated doorbell) 338 */ 339 if (dev->kfd->shared_resources.enable_mes && 340 ((dev->adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) 341 >> AMDGPU_MES_API_VERSION_SHIFT) >= 2) { 342 struct amdgpu_bo_va_mapping *wptr_mapping; 343 struct amdgpu_vm *wptr_vm; 344 345 wptr_vm = drm_priv_to_vm(pdd->drm_priv); 346 err = amdgpu_bo_reserve(wptr_vm->root.bo, false); 347 if (err) 348 goto err_wptr_map_gart; 349 350 wptr_mapping = amdgpu_vm_bo_lookup_mapping( 351 wptr_vm, args->write_pointer_address >> PAGE_SHIFT); 352 amdgpu_bo_unreserve(wptr_vm->root.bo); 353 if (!wptr_mapping) { 354 pr_err("Failed to lookup wptr bo\n"); 355 err = -EINVAL; 356 goto err_wptr_map_gart; 357 } 358 359 wptr_bo = wptr_mapping->bo_va->base.bo; 360 if (wptr_bo->tbo.base.size > PAGE_SIZE) { 361 pr_err("Requested GART mapping for wptr bo larger than one page\n"); 362 err = -EINVAL; 363 goto err_wptr_map_gart; 364 } 365 366 err = amdgpu_amdkfd_map_gtt_bo_to_gart(dev->adev, wptr_bo); 367 if (err) { 368 pr_err("Failed to map wptr bo to GART\n"); 369 goto err_wptr_map_gart; 370 } 371 } 372 373 pr_debug("Creating queue for PASID 0x%x on gpu 0x%x\n", 374 p->pasid, 375 dev->id); 376 377 err = pqm_create_queue(&p->pqm, dev, filep, &q_properties, &queue_id, wptr_bo, 378 NULL, NULL, NULL, &doorbell_offset_in_process); 379 if (err != 0) 380 goto err_create_queue; 381 382 args->queue_id = queue_id; 383 384 385 /* Return gpu_id as doorbell offset for mmap usage */ 386 args->doorbell_offset = KFD_MMAP_TYPE_DOORBELL; 387 args->doorbell_offset |= KFD_MMAP_GPU_ID(args->gpu_id); 388 if (KFD_IS_SOC15(dev)) 389 /* On SOC15 ASICs, include the doorbell offset within the 390 * process doorbell frame, which is 2 pages. 391 */ 392 args->doorbell_offset |= doorbell_offset_in_process; 393 394 mutex_unlock(&p->mutex); 395 396 pr_debug("Queue id %d was created successfully\n", args->queue_id); 397 398 pr_debug("Ring buffer address == 0x%016llX\n", 399 args->ring_base_address); 400 401 pr_debug("Read ptr address == 0x%016llX\n", 402 args->read_pointer_address); 403 404 pr_debug("Write ptr address == 0x%016llX\n", 405 args->write_pointer_address); 406 407 return 0; 408 409 err_create_queue: 410 if (wptr_bo) 411 amdgpu_amdkfd_free_gtt_mem(dev->adev, wptr_bo); 412 err_wptr_map_gart: 413 err_alloc_doorbells: 414 err_bind_process: 415 err_pdd: 416 mutex_unlock(&p->mutex); 417 return err; 418 } 419 420 static int kfd_ioctl_destroy_queue(struct file *filp, struct kfd_process *p, 421 void *data) 422 { 423 int retval; 424 struct kfd_ioctl_destroy_queue_args *args = data; 425 426 pr_debug("Destroying queue id %d for pasid 0x%x\n", 427 args->queue_id, 428 p->pasid); 429 430 mutex_lock(&p->mutex); 431 432 retval = pqm_destroy_queue(&p->pqm, args->queue_id); 433 434 mutex_unlock(&p->mutex); 435 return retval; 436 } 437 438 static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p, 439 void *data) 440 { 441 int retval; 442 struct kfd_ioctl_update_queue_args *args = data; 443 struct queue_properties properties; 444 445 /* 446 * Repurpose queue percentage to accommodate new features: 447 * bit 0-7: queue percentage 448 * bit 8-15: pm4_target_xcc 449 */ 450 if ((args->queue_percentage & 0xFF) > KFD_MAX_QUEUE_PERCENTAGE) { 451 pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n"); 452 return -EINVAL; 453 } 454 455 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) { 456 pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n"); 457 return -EINVAL; 458 } 459 460 if ((args->ring_base_address) && 461 (!access_ok((const void __user *) args->ring_base_address, 462 sizeof(uint64_t)))) { 463 pr_err("Can't access ring base address\n"); 464 return -EFAULT; 465 } 466 467 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) { 468 pr_err("Ring size must be a power of 2 or 0\n"); 469 return -EINVAL; 470 } 471 472 properties.queue_address = args->ring_base_address; 473 properties.queue_size = args->ring_size; 474 properties.queue_percent = args->queue_percentage & 0xFF; 475 /* bit 8-15 are repurposed to be PM4 target XCC */ 476 properties.pm4_target_xcc = (args->queue_percentage >> 8) & 0xFF; 477 properties.priority = args->queue_priority; 478 479 pr_debug("Updating queue id %d for pasid 0x%x\n", 480 args->queue_id, p->pasid); 481 482 mutex_lock(&p->mutex); 483 484 retval = pqm_update_queue_properties(&p->pqm, args->queue_id, &properties); 485 486 mutex_unlock(&p->mutex); 487 488 return retval; 489 } 490 491 static int kfd_ioctl_set_cu_mask(struct file *filp, struct kfd_process *p, 492 void *data) 493 { 494 int retval; 495 const int max_num_cus = 1024; 496 struct kfd_ioctl_set_cu_mask_args *args = data; 497 struct mqd_update_info minfo = {0}; 498 uint32_t __user *cu_mask_ptr = (uint32_t __user *)args->cu_mask_ptr; 499 size_t cu_mask_size = sizeof(uint32_t) * (args->num_cu_mask / 32); 500 501 if ((args->num_cu_mask % 32) != 0) { 502 pr_debug("num_cu_mask 0x%x must be a multiple of 32", 503 args->num_cu_mask); 504 return -EINVAL; 505 } 506 507 minfo.cu_mask.count = args->num_cu_mask; 508 if (minfo.cu_mask.count == 0) { 509 pr_debug("CU mask cannot be 0"); 510 return -EINVAL; 511 } 512 513 /* To prevent an unreasonably large CU mask size, set an arbitrary 514 * limit of max_num_cus bits. We can then just drop any CU mask bits 515 * past max_num_cus bits and just use the first max_num_cus bits. 516 */ 517 if (minfo.cu_mask.count > max_num_cus) { 518 pr_debug("CU mask cannot be greater than 1024 bits"); 519 minfo.cu_mask.count = max_num_cus; 520 cu_mask_size = sizeof(uint32_t) * (max_num_cus/32); 521 } 522 523 minfo.cu_mask.ptr = kzalloc(cu_mask_size, GFP_KERNEL); 524 if (!minfo.cu_mask.ptr) 525 return -ENOMEM; 526 527 retval = copy_from_user(minfo.cu_mask.ptr, cu_mask_ptr, cu_mask_size); 528 if (retval) { 529 pr_debug("Could not copy CU mask from userspace"); 530 retval = -EFAULT; 531 goto out; 532 } 533 534 minfo.update_flag = UPDATE_FLAG_CU_MASK; 535 536 mutex_lock(&p->mutex); 537 538 retval = pqm_update_mqd(&p->pqm, args->queue_id, &minfo); 539 540 mutex_unlock(&p->mutex); 541 542 out: 543 kfree(minfo.cu_mask.ptr); 544 return retval; 545 } 546 547 static int kfd_ioctl_get_queue_wave_state(struct file *filep, 548 struct kfd_process *p, void *data) 549 { 550 struct kfd_ioctl_get_queue_wave_state_args *args = data; 551 int r; 552 553 mutex_lock(&p->mutex); 554 555 r = pqm_get_wave_state(&p->pqm, args->queue_id, 556 (void __user *)args->ctl_stack_address, 557 &args->ctl_stack_used_size, 558 &args->save_area_used_size); 559 560 mutex_unlock(&p->mutex); 561 562 return r; 563 } 564 565 static int kfd_ioctl_set_memory_policy(struct file *filep, 566 struct kfd_process *p, void *data) 567 { 568 struct kfd_ioctl_set_memory_policy_args *args = data; 569 int err = 0; 570 struct kfd_process_device *pdd; 571 enum cache_policy default_policy, alternate_policy; 572 573 if (args->default_policy != KFD_IOC_CACHE_POLICY_COHERENT 574 && args->default_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) { 575 return -EINVAL; 576 } 577 578 if (args->alternate_policy != KFD_IOC_CACHE_POLICY_COHERENT 579 && args->alternate_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) { 580 return -EINVAL; 581 } 582 583 mutex_lock(&p->mutex); 584 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 585 if (!pdd) { 586 pr_debug("Could not find gpu id 0x%x\n", args->gpu_id); 587 err = -EINVAL; 588 goto err_pdd; 589 } 590 591 pdd = kfd_bind_process_to_device(pdd->dev, p); 592 if (IS_ERR(pdd)) { 593 err = -ESRCH; 594 goto out; 595 } 596 597 default_policy = (args->default_policy == KFD_IOC_CACHE_POLICY_COHERENT) 598 ? cache_policy_coherent : cache_policy_noncoherent; 599 600 alternate_policy = 601 (args->alternate_policy == KFD_IOC_CACHE_POLICY_COHERENT) 602 ? cache_policy_coherent : cache_policy_noncoherent; 603 604 if (!pdd->dev->dqm->ops.set_cache_memory_policy(pdd->dev->dqm, 605 &pdd->qpd, 606 default_policy, 607 alternate_policy, 608 (void __user *)args->alternate_aperture_base, 609 args->alternate_aperture_size)) 610 err = -EINVAL; 611 612 out: 613 err_pdd: 614 mutex_unlock(&p->mutex); 615 616 return err; 617 } 618 619 static int kfd_ioctl_set_trap_handler(struct file *filep, 620 struct kfd_process *p, void *data) 621 { 622 struct kfd_ioctl_set_trap_handler_args *args = data; 623 int err = 0; 624 struct kfd_process_device *pdd; 625 626 mutex_lock(&p->mutex); 627 628 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 629 if (!pdd) { 630 err = -EINVAL; 631 goto err_pdd; 632 } 633 634 pdd = kfd_bind_process_to_device(pdd->dev, p); 635 if (IS_ERR(pdd)) { 636 err = -ESRCH; 637 goto out; 638 } 639 640 kfd_process_set_trap_handler(&pdd->qpd, args->tba_addr, args->tma_addr); 641 642 out: 643 err_pdd: 644 mutex_unlock(&p->mutex); 645 646 return err; 647 } 648 649 static int kfd_ioctl_dbg_register(struct file *filep, 650 struct kfd_process *p, void *data) 651 { 652 return -EPERM; 653 } 654 655 static int kfd_ioctl_dbg_unregister(struct file *filep, 656 struct kfd_process *p, void *data) 657 { 658 return -EPERM; 659 } 660 661 static int kfd_ioctl_dbg_address_watch(struct file *filep, 662 struct kfd_process *p, void *data) 663 { 664 return -EPERM; 665 } 666 667 /* Parse and generate fixed size data structure for wave control */ 668 static int kfd_ioctl_dbg_wave_control(struct file *filep, 669 struct kfd_process *p, void *data) 670 { 671 return -EPERM; 672 } 673 674 static int kfd_ioctl_get_clock_counters(struct file *filep, 675 struct kfd_process *p, void *data) 676 { 677 struct kfd_ioctl_get_clock_counters_args *args = data; 678 struct kfd_process_device *pdd; 679 680 mutex_lock(&p->mutex); 681 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 682 mutex_unlock(&p->mutex); 683 if (pdd) 684 /* Reading GPU clock counter from KGD */ 685 args->gpu_clock_counter = amdgpu_amdkfd_get_gpu_clock_counter(pdd->dev->adev); 686 else 687 /* Node without GPU resource */ 688 args->gpu_clock_counter = 0; 689 690 /* No access to rdtsc. Using raw monotonic time */ 691 args->cpu_clock_counter = ktime_get_raw_ns(); 692 args->system_clock_counter = ktime_get_boottime_ns(); 693 694 /* Since the counter is in nano-seconds we use 1GHz frequency */ 695 args->system_clock_freq = 1000000000; 696 697 return 0; 698 } 699 700 701 static int kfd_ioctl_get_process_apertures(struct file *filp, 702 struct kfd_process *p, void *data) 703 { 704 struct kfd_ioctl_get_process_apertures_args *args = data; 705 struct kfd_process_device_apertures *pAperture; 706 int i; 707 708 dev_dbg(kfd_device, "get apertures for PASID 0x%x", p->pasid); 709 710 args->num_of_nodes = 0; 711 712 mutex_lock(&p->mutex); 713 /* Run over all pdd of the process */ 714 for (i = 0; i < p->n_pdds; i++) { 715 struct kfd_process_device *pdd = p->pdds[i]; 716 717 pAperture = 718 &args->process_apertures[args->num_of_nodes]; 719 pAperture->gpu_id = pdd->dev->id; 720 pAperture->lds_base = pdd->lds_base; 721 pAperture->lds_limit = pdd->lds_limit; 722 pAperture->gpuvm_base = pdd->gpuvm_base; 723 pAperture->gpuvm_limit = pdd->gpuvm_limit; 724 pAperture->scratch_base = pdd->scratch_base; 725 pAperture->scratch_limit = pdd->scratch_limit; 726 727 dev_dbg(kfd_device, 728 "node id %u\n", args->num_of_nodes); 729 dev_dbg(kfd_device, 730 "gpu id %u\n", pdd->dev->id); 731 dev_dbg(kfd_device, 732 "lds_base %llX\n", pdd->lds_base); 733 dev_dbg(kfd_device, 734 "lds_limit %llX\n", pdd->lds_limit); 735 dev_dbg(kfd_device, 736 "gpuvm_base %llX\n", pdd->gpuvm_base); 737 dev_dbg(kfd_device, 738 "gpuvm_limit %llX\n", pdd->gpuvm_limit); 739 dev_dbg(kfd_device, 740 "scratch_base %llX\n", pdd->scratch_base); 741 dev_dbg(kfd_device, 742 "scratch_limit %llX\n", pdd->scratch_limit); 743 744 if (++args->num_of_nodes >= NUM_OF_SUPPORTED_GPUS) 745 break; 746 } 747 mutex_unlock(&p->mutex); 748 749 return 0; 750 } 751 752 static int kfd_ioctl_get_process_apertures_new(struct file *filp, 753 struct kfd_process *p, void *data) 754 { 755 struct kfd_ioctl_get_process_apertures_new_args *args = data; 756 struct kfd_process_device_apertures *pa; 757 int ret; 758 int i; 759 760 dev_dbg(kfd_device, "get apertures for PASID 0x%x", p->pasid); 761 762 if (args->num_of_nodes == 0) { 763 /* Return number of nodes, so that user space can alloacate 764 * sufficient memory 765 */ 766 mutex_lock(&p->mutex); 767 args->num_of_nodes = p->n_pdds; 768 goto out_unlock; 769 } 770 771 /* Fill in process-aperture information for all available 772 * nodes, but not more than args->num_of_nodes as that is 773 * the amount of memory allocated by user 774 */ 775 pa = kzalloc((sizeof(struct kfd_process_device_apertures) * 776 args->num_of_nodes), GFP_KERNEL); 777 if (!pa) 778 return -ENOMEM; 779 780 mutex_lock(&p->mutex); 781 782 if (!p->n_pdds) { 783 args->num_of_nodes = 0; 784 kfree(pa); 785 goto out_unlock; 786 } 787 788 /* Run over all pdd of the process */ 789 for (i = 0; i < min(p->n_pdds, args->num_of_nodes); i++) { 790 struct kfd_process_device *pdd = p->pdds[i]; 791 792 pa[i].gpu_id = pdd->dev->id; 793 pa[i].lds_base = pdd->lds_base; 794 pa[i].lds_limit = pdd->lds_limit; 795 pa[i].gpuvm_base = pdd->gpuvm_base; 796 pa[i].gpuvm_limit = pdd->gpuvm_limit; 797 pa[i].scratch_base = pdd->scratch_base; 798 pa[i].scratch_limit = pdd->scratch_limit; 799 800 dev_dbg(kfd_device, 801 "gpu id %u\n", pdd->dev->id); 802 dev_dbg(kfd_device, 803 "lds_base %llX\n", pdd->lds_base); 804 dev_dbg(kfd_device, 805 "lds_limit %llX\n", pdd->lds_limit); 806 dev_dbg(kfd_device, 807 "gpuvm_base %llX\n", pdd->gpuvm_base); 808 dev_dbg(kfd_device, 809 "gpuvm_limit %llX\n", pdd->gpuvm_limit); 810 dev_dbg(kfd_device, 811 "scratch_base %llX\n", pdd->scratch_base); 812 dev_dbg(kfd_device, 813 "scratch_limit %llX\n", pdd->scratch_limit); 814 } 815 mutex_unlock(&p->mutex); 816 817 args->num_of_nodes = i; 818 ret = copy_to_user( 819 (void __user *)args->kfd_process_device_apertures_ptr, 820 pa, 821 (i * sizeof(struct kfd_process_device_apertures))); 822 kfree(pa); 823 return ret ? -EFAULT : 0; 824 825 out_unlock: 826 mutex_unlock(&p->mutex); 827 return 0; 828 } 829 830 static int kfd_ioctl_create_event(struct file *filp, struct kfd_process *p, 831 void *data) 832 { 833 struct kfd_ioctl_create_event_args *args = data; 834 int err; 835 836 /* For dGPUs the event page is allocated in user mode. The 837 * handle is passed to KFD with the first call to this IOCTL 838 * through the event_page_offset field. 839 */ 840 if (args->event_page_offset) { 841 mutex_lock(&p->mutex); 842 err = kfd_kmap_event_page(p, args->event_page_offset); 843 mutex_unlock(&p->mutex); 844 if (err) 845 return err; 846 } 847 848 err = kfd_event_create(filp, p, args->event_type, 849 args->auto_reset != 0, args->node_id, 850 &args->event_id, &args->event_trigger_data, 851 &args->event_page_offset, 852 &args->event_slot_index); 853 854 pr_debug("Created event (id:0x%08x) (%s)\n", args->event_id, __func__); 855 return err; 856 } 857 858 static int kfd_ioctl_destroy_event(struct file *filp, struct kfd_process *p, 859 void *data) 860 { 861 struct kfd_ioctl_destroy_event_args *args = data; 862 863 return kfd_event_destroy(p, args->event_id); 864 } 865 866 static int kfd_ioctl_set_event(struct file *filp, struct kfd_process *p, 867 void *data) 868 { 869 struct kfd_ioctl_set_event_args *args = data; 870 871 return kfd_set_event(p, args->event_id); 872 } 873 874 static int kfd_ioctl_reset_event(struct file *filp, struct kfd_process *p, 875 void *data) 876 { 877 struct kfd_ioctl_reset_event_args *args = data; 878 879 return kfd_reset_event(p, args->event_id); 880 } 881 882 static int kfd_ioctl_wait_events(struct file *filp, struct kfd_process *p, 883 void *data) 884 { 885 struct kfd_ioctl_wait_events_args *args = data; 886 887 return kfd_wait_on_events(p, args->num_events, 888 (void __user *)args->events_ptr, 889 (args->wait_for_all != 0), 890 &args->timeout, &args->wait_result); 891 } 892 static int kfd_ioctl_set_scratch_backing_va(struct file *filep, 893 struct kfd_process *p, void *data) 894 { 895 struct kfd_ioctl_set_scratch_backing_va_args *args = data; 896 struct kfd_process_device *pdd; 897 struct kfd_node *dev; 898 long err; 899 900 mutex_lock(&p->mutex); 901 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 902 if (!pdd) { 903 err = -EINVAL; 904 goto err_pdd; 905 } 906 dev = pdd->dev; 907 908 pdd = kfd_bind_process_to_device(dev, p); 909 if (IS_ERR(pdd)) { 910 err = PTR_ERR(pdd); 911 goto bind_process_to_device_fail; 912 } 913 914 pdd->qpd.sh_hidden_private_base = args->va_addr; 915 916 mutex_unlock(&p->mutex); 917 918 if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS && 919 pdd->qpd.vmid != 0 && dev->kfd2kgd->set_scratch_backing_va) 920 dev->kfd2kgd->set_scratch_backing_va( 921 dev->adev, args->va_addr, pdd->qpd.vmid); 922 923 return 0; 924 925 bind_process_to_device_fail: 926 err_pdd: 927 mutex_unlock(&p->mutex); 928 return err; 929 } 930 931 static int kfd_ioctl_get_tile_config(struct file *filep, 932 struct kfd_process *p, void *data) 933 { 934 struct kfd_ioctl_get_tile_config_args *args = data; 935 struct kfd_process_device *pdd; 936 struct tile_config config; 937 int err = 0; 938 939 mutex_lock(&p->mutex); 940 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 941 mutex_unlock(&p->mutex); 942 if (!pdd) 943 return -EINVAL; 944 945 amdgpu_amdkfd_get_tile_config(pdd->dev->adev, &config); 946 947 args->gb_addr_config = config.gb_addr_config; 948 args->num_banks = config.num_banks; 949 args->num_ranks = config.num_ranks; 950 951 if (args->num_tile_configs > config.num_tile_configs) 952 args->num_tile_configs = config.num_tile_configs; 953 err = copy_to_user((void __user *)args->tile_config_ptr, 954 config.tile_config_ptr, 955 args->num_tile_configs * sizeof(uint32_t)); 956 if (err) { 957 args->num_tile_configs = 0; 958 return -EFAULT; 959 } 960 961 if (args->num_macro_tile_configs > config.num_macro_tile_configs) 962 args->num_macro_tile_configs = 963 config.num_macro_tile_configs; 964 err = copy_to_user((void __user *)args->macro_tile_config_ptr, 965 config.macro_tile_config_ptr, 966 args->num_macro_tile_configs * sizeof(uint32_t)); 967 if (err) { 968 args->num_macro_tile_configs = 0; 969 return -EFAULT; 970 } 971 972 return 0; 973 } 974 975 static int kfd_ioctl_acquire_vm(struct file *filep, struct kfd_process *p, 976 void *data) 977 { 978 struct kfd_ioctl_acquire_vm_args *args = data; 979 struct kfd_process_device *pdd; 980 struct file *drm_file; 981 int ret; 982 983 drm_file = fget(args->drm_fd); 984 if (!drm_file) 985 return -EINVAL; 986 987 mutex_lock(&p->mutex); 988 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 989 if (!pdd) { 990 ret = -EINVAL; 991 goto err_pdd; 992 } 993 994 if (pdd->drm_file) { 995 ret = pdd->drm_file == drm_file ? 0 : -EBUSY; 996 goto err_drm_file; 997 } 998 999 ret = kfd_process_device_init_vm(pdd, drm_file); 1000 if (ret) 1001 goto err_unlock; 1002 1003 /* On success, the PDD keeps the drm_file reference */ 1004 mutex_unlock(&p->mutex); 1005 1006 return 0; 1007 1008 err_unlock: 1009 err_pdd: 1010 err_drm_file: 1011 mutex_unlock(&p->mutex); 1012 fput(drm_file); 1013 return ret; 1014 } 1015 1016 bool kfd_dev_is_large_bar(struct kfd_node *dev) 1017 { 1018 if (debug_largebar) { 1019 pr_debug("Simulate large-bar allocation on non large-bar machine\n"); 1020 return true; 1021 } 1022 1023 if (dev->kfd->use_iommu_v2) 1024 return false; 1025 1026 if (dev->local_mem_info.local_mem_size_private == 0 && 1027 dev->local_mem_info.local_mem_size_public > 0) 1028 return true; 1029 1030 if (dev->local_mem_info.local_mem_size_public == 0 && 1031 dev->kfd->adev->gmc.is_app_apu) { 1032 pr_debug("APP APU, Consider like a large bar system\n"); 1033 return true; 1034 } 1035 1036 return false; 1037 } 1038 1039 static int kfd_ioctl_get_available_memory(struct file *filep, 1040 struct kfd_process *p, void *data) 1041 { 1042 struct kfd_ioctl_get_available_memory_args *args = data; 1043 struct kfd_process_device *pdd = kfd_lock_pdd_by_id(p, args->gpu_id); 1044 1045 if (!pdd) 1046 return -EINVAL; 1047 args->available = amdgpu_amdkfd_get_available_memory(pdd->dev->adev, 1048 pdd->dev->node_id); 1049 kfd_unlock_pdd(pdd); 1050 return 0; 1051 } 1052 1053 static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, 1054 struct kfd_process *p, void *data) 1055 { 1056 struct kfd_ioctl_alloc_memory_of_gpu_args *args = data; 1057 struct kfd_process_device *pdd; 1058 void *mem; 1059 struct kfd_node *dev; 1060 int idr_handle; 1061 long err; 1062 uint64_t offset = args->mmap_offset; 1063 uint32_t flags = args->flags; 1064 1065 if (args->size == 0) 1066 return -EINVAL; 1067 1068 #if IS_ENABLED(CONFIG_HSA_AMD_SVM) 1069 /* Flush pending deferred work to avoid racing with deferred actions 1070 * from previous memory map changes (e.g. munmap). 1071 */ 1072 svm_range_list_lock_and_flush_work(&p->svms, current->mm); 1073 mutex_lock(&p->svms.lock); 1074 mmap_write_unlock(current->mm); 1075 if (interval_tree_iter_first(&p->svms.objects, 1076 args->va_addr >> PAGE_SHIFT, 1077 (args->va_addr + args->size - 1) >> PAGE_SHIFT)) { 1078 pr_err("Address: 0x%llx already allocated by SVM\n", 1079 args->va_addr); 1080 mutex_unlock(&p->svms.lock); 1081 return -EADDRINUSE; 1082 } 1083 1084 /* When register user buffer check if it has been registered by svm by 1085 * buffer cpu virtual address. 1086 */ 1087 if ((flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) && 1088 interval_tree_iter_first(&p->svms.objects, 1089 args->mmap_offset >> PAGE_SHIFT, 1090 (args->mmap_offset + args->size - 1) >> PAGE_SHIFT)) { 1091 pr_err("User Buffer Address: 0x%llx already allocated by SVM\n", 1092 args->mmap_offset); 1093 mutex_unlock(&p->svms.lock); 1094 return -EADDRINUSE; 1095 } 1096 1097 mutex_unlock(&p->svms.lock); 1098 #endif 1099 mutex_lock(&p->mutex); 1100 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 1101 if (!pdd) { 1102 err = -EINVAL; 1103 goto err_pdd; 1104 } 1105 1106 dev = pdd->dev; 1107 1108 if ((flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) && 1109 (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) && 1110 !kfd_dev_is_large_bar(dev)) { 1111 pr_err("Alloc host visible vram on small bar is not allowed\n"); 1112 err = -EINVAL; 1113 goto err_large_bar; 1114 } 1115 1116 pdd = kfd_bind_process_to_device(dev, p); 1117 if (IS_ERR(pdd)) { 1118 err = PTR_ERR(pdd); 1119 goto err_unlock; 1120 } 1121 1122 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) { 1123 if (args->size != kfd_doorbell_process_slice(dev->kfd)) { 1124 err = -EINVAL; 1125 goto err_unlock; 1126 } 1127 offset = kfd_get_process_doorbells(pdd); 1128 if (!offset) { 1129 err = -ENOMEM; 1130 goto err_unlock; 1131 } 1132 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) { 1133 if (args->size != PAGE_SIZE) { 1134 err = -EINVAL; 1135 goto err_unlock; 1136 } 1137 offset = dev->adev->rmmio_remap.bus_addr; 1138 if (!offset) { 1139 err = -ENOMEM; 1140 goto err_unlock; 1141 } 1142 } 1143 1144 err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( 1145 dev->adev, args->va_addr, args->size, 1146 pdd->drm_priv, (struct kgd_mem **) &mem, &offset, 1147 flags, false); 1148 1149 if (err) 1150 goto err_unlock; 1151 1152 idr_handle = kfd_process_device_create_obj_handle(pdd, mem); 1153 if (idr_handle < 0) { 1154 err = -EFAULT; 1155 goto err_free; 1156 } 1157 1158 /* Update the VRAM usage count */ 1159 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { 1160 uint64_t size = args->size; 1161 1162 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM) 1163 size >>= 1; 1164 WRITE_ONCE(pdd->vram_usage, pdd->vram_usage + PAGE_ALIGN(size)); 1165 } 1166 1167 mutex_unlock(&p->mutex); 1168 1169 args->handle = MAKE_HANDLE(args->gpu_id, idr_handle); 1170 args->mmap_offset = offset; 1171 1172 /* MMIO is mapped through kfd device 1173 * Generate a kfd mmap offset 1174 */ 1175 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) 1176 args->mmap_offset = KFD_MMAP_TYPE_MMIO 1177 | KFD_MMAP_GPU_ID(args->gpu_id); 1178 1179 return 0; 1180 1181 err_free: 1182 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, (struct kgd_mem *)mem, 1183 pdd->drm_priv, NULL); 1184 err_unlock: 1185 err_pdd: 1186 err_large_bar: 1187 mutex_unlock(&p->mutex); 1188 return err; 1189 } 1190 1191 static int kfd_ioctl_free_memory_of_gpu(struct file *filep, 1192 struct kfd_process *p, void *data) 1193 { 1194 struct kfd_ioctl_free_memory_of_gpu_args *args = data; 1195 struct kfd_process_device *pdd; 1196 void *mem; 1197 int ret; 1198 uint64_t size = 0; 1199 1200 mutex_lock(&p->mutex); 1201 /* 1202 * Safeguard to prevent user space from freeing signal BO. 1203 * It will be freed at process termination. 1204 */ 1205 if (p->signal_handle && (p->signal_handle == args->handle)) { 1206 pr_err("Free signal BO is not allowed\n"); 1207 ret = -EPERM; 1208 goto err_unlock; 1209 } 1210 1211 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle)); 1212 if (!pdd) { 1213 pr_err("Process device data doesn't exist\n"); 1214 ret = -EINVAL; 1215 goto err_pdd; 1216 } 1217 1218 mem = kfd_process_device_translate_handle( 1219 pdd, GET_IDR_HANDLE(args->handle)); 1220 if (!mem) { 1221 ret = -EINVAL; 1222 goto err_unlock; 1223 } 1224 1225 ret = amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, 1226 (struct kgd_mem *)mem, pdd->drm_priv, &size); 1227 1228 /* If freeing the buffer failed, leave the handle in place for 1229 * clean-up during process tear-down. 1230 */ 1231 if (!ret) 1232 kfd_process_device_remove_obj_handle( 1233 pdd, GET_IDR_HANDLE(args->handle)); 1234 1235 WRITE_ONCE(pdd->vram_usage, pdd->vram_usage - size); 1236 1237 err_unlock: 1238 err_pdd: 1239 mutex_unlock(&p->mutex); 1240 return ret; 1241 } 1242 1243 static int kfd_ioctl_map_memory_to_gpu(struct file *filep, 1244 struct kfd_process *p, void *data) 1245 { 1246 struct kfd_ioctl_map_memory_to_gpu_args *args = data; 1247 struct kfd_process_device *pdd, *peer_pdd; 1248 void *mem; 1249 struct kfd_node *dev; 1250 long err = 0; 1251 int i; 1252 uint32_t *devices_arr = NULL; 1253 1254 if (!args->n_devices) { 1255 pr_debug("Device IDs array empty\n"); 1256 return -EINVAL; 1257 } 1258 if (args->n_success > args->n_devices) { 1259 pr_debug("n_success exceeds n_devices\n"); 1260 return -EINVAL; 1261 } 1262 1263 devices_arr = kmalloc_array(args->n_devices, sizeof(*devices_arr), 1264 GFP_KERNEL); 1265 if (!devices_arr) 1266 return -ENOMEM; 1267 1268 err = copy_from_user(devices_arr, 1269 (void __user *)args->device_ids_array_ptr, 1270 args->n_devices * sizeof(*devices_arr)); 1271 if (err != 0) { 1272 err = -EFAULT; 1273 goto copy_from_user_failed; 1274 } 1275 1276 mutex_lock(&p->mutex); 1277 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle)); 1278 if (!pdd) { 1279 err = -EINVAL; 1280 goto get_process_device_data_failed; 1281 } 1282 dev = pdd->dev; 1283 1284 pdd = kfd_bind_process_to_device(dev, p); 1285 if (IS_ERR(pdd)) { 1286 err = PTR_ERR(pdd); 1287 goto bind_process_to_device_failed; 1288 } 1289 1290 mem = kfd_process_device_translate_handle(pdd, 1291 GET_IDR_HANDLE(args->handle)); 1292 if (!mem) { 1293 err = -ENOMEM; 1294 goto get_mem_obj_from_handle_failed; 1295 } 1296 1297 for (i = args->n_success; i < args->n_devices; i++) { 1298 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]); 1299 if (!peer_pdd) { 1300 pr_debug("Getting device by id failed for 0x%x\n", 1301 devices_arr[i]); 1302 err = -EINVAL; 1303 goto get_mem_obj_from_handle_failed; 1304 } 1305 1306 peer_pdd = kfd_bind_process_to_device(peer_pdd->dev, p); 1307 if (IS_ERR(peer_pdd)) { 1308 err = PTR_ERR(peer_pdd); 1309 goto get_mem_obj_from_handle_failed; 1310 } 1311 1312 err = amdgpu_amdkfd_gpuvm_map_memory_to_gpu( 1313 peer_pdd->dev->adev, (struct kgd_mem *)mem, 1314 peer_pdd->drm_priv); 1315 if (err) { 1316 struct pci_dev *pdev = peer_pdd->dev->adev->pdev; 1317 1318 dev_err(dev->adev->dev, 1319 "Failed to map peer:%04x:%02x:%02x.%d mem_domain:%d\n", 1320 pci_domain_nr(pdev->bus), 1321 pdev->bus->number, 1322 PCI_SLOT(pdev->devfn), 1323 PCI_FUNC(pdev->devfn), 1324 ((struct kgd_mem *)mem)->domain); 1325 goto map_memory_to_gpu_failed; 1326 } 1327 args->n_success = i+1; 1328 } 1329 1330 err = amdgpu_amdkfd_gpuvm_sync_memory(dev->adev, (struct kgd_mem *) mem, true); 1331 if (err) { 1332 pr_debug("Sync memory failed, wait interrupted by user signal\n"); 1333 goto sync_memory_failed; 1334 } 1335 1336 mutex_unlock(&p->mutex); 1337 1338 /* Flush TLBs after waiting for the page table updates to complete */ 1339 for (i = 0; i < args->n_devices; i++) { 1340 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]); 1341 if (WARN_ON_ONCE(!peer_pdd)) 1342 continue; 1343 kfd_flush_tlb(peer_pdd, TLB_FLUSH_LEGACY); 1344 } 1345 kfree(devices_arr); 1346 1347 return err; 1348 1349 get_process_device_data_failed: 1350 bind_process_to_device_failed: 1351 get_mem_obj_from_handle_failed: 1352 map_memory_to_gpu_failed: 1353 sync_memory_failed: 1354 mutex_unlock(&p->mutex); 1355 copy_from_user_failed: 1356 kfree(devices_arr); 1357 1358 return err; 1359 } 1360 1361 static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep, 1362 struct kfd_process *p, void *data) 1363 { 1364 struct kfd_ioctl_unmap_memory_from_gpu_args *args = data; 1365 struct kfd_process_device *pdd, *peer_pdd; 1366 void *mem; 1367 long err = 0; 1368 uint32_t *devices_arr = NULL, i; 1369 bool flush_tlb; 1370 1371 if (!args->n_devices) { 1372 pr_debug("Device IDs array empty\n"); 1373 return -EINVAL; 1374 } 1375 if (args->n_success > args->n_devices) { 1376 pr_debug("n_success exceeds n_devices\n"); 1377 return -EINVAL; 1378 } 1379 1380 devices_arr = kmalloc_array(args->n_devices, sizeof(*devices_arr), 1381 GFP_KERNEL); 1382 if (!devices_arr) 1383 return -ENOMEM; 1384 1385 err = copy_from_user(devices_arr, 1386 (void __user *)args->device_ids_array_ptr, 1387 args->n_devices * sizeof(*devices_arr)); 1388 if (err != 0) { 1389 err = -EFAULT; 1390 goto copy_from_user_failed; 1391 } 1392 1393 mutex_lock(&p->mutex); 1394 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle)); 1395 if (!pdd) { 1396 err = -EINVAL; 1397 goto bind_process_to_device_failed; 1398 } 1399 1400 mem = kfd_process_device_translate_handle(pdd, 1401 GET_IDR_HANDLE(args->handle)); 1402 if (!mem) { 1403 err = -ENOMEM; 1404 goto get_mem_obj_from_handle_failed; 1405 } 1406 1407 for (i = args->n_success; i < args->n_devices; i++) { 1408 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]); 1409 if (!peer_pdd) { 1410 err = -EINVAL; 1411 goto get_mem_obj_from_handle_failed; 1412 } 1413 err = amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( 1414 peer_pdd->dev->adev, (struct kgd_mem *)mem, peer_pdd->drm_priv); 1415 if (err) { 1416 pr_err("Failed to unmap from gpu %d/%d\n", 1417 i, args->n_devices); 1418 goto unmap_memory_from_gpu_failed; 1419 } 1420 args->n_success = i+1; 1421 } 1422 1423 flush_tlb = kfd_flush_tlb_after_unmap(pdd->dev->kfd); 1424 if (flush_tlb) { 1425 err = amdgpu_amdkfd_gpuvm_sync_memory(pdd->dev->adev, 1426 (struct kgd_mem *) mem, true); 1427 if (err) { 1428 pr_debug("Sync memory failed, wait interrupted by user signal\n"); 1429 goto sync_memory_failed; 1430 } 1431 } 1432 mutex_unlock(&p->mutex); 1433 1434 if (flush_tlb) { 1435 /* Flush TLBs after waiting for the page table updates to complete */ 1436 for (i = 0; i < args->n_devices; i++) { 1437 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]); 1438 if (WARN_ON_ONCE(!peer_pdd)) 1439 continue; 1440 kfd_flush_tlb(peer_pdd, TLB_FLUSH_HEAVYWEIGHT); 1441 } 1442 } 1443 kfree(devices_arr); 1444 1445 return 0; 1446 1447 bind_process_to_device_failed: 1448 get_mem_obj_from_handle_failed: 1449 unmap_memory_from_gpu_failed: 1450 sync_memory_failed: 1451 mutex_unlock(&p->mutex); 1452 copy_from_user_failed: 1453 kfree(devices_arr); 1454 return err; 1455 } 1456 1457 static int kfd_ioctl_alloc_queue_gws(struct file *filep, 1458 struct kfd_process *p, void *data) 1459 { 1460 int retval; 1461 struct kfd_ioctl_alloc_queue_gws_args *args = data; 1462 struct queue *q; 1463 struct kfd_node *dev; 1464 1465 mutex_lock(&p->mutex); 1466 q = pqm_get_user_queue(&p->pqm, args->queue_id); 1467 1468 if (q) { 1469 dev = q->device; 1470 } else { 1471 retval = -EINVAL; 1472 goto out_unlock; 1473 } 1474 1475 if (!dev->gws) { 1476 retval = -ENODEV; 1477 goto out_unlock; 1478 } 1479 1480 if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) { 1481 retval = -ENODEV; 1482 goto out_unlock; 1483 } 1484 1485 retval = pqm_set_gws(&p->pqm, args->queue_id, args->num_gws ? dev->gws : NULL); 1486 mutex_unlock(&p->mutex); 1487 1488 args->first_gws = 0; 1489 return retval; 1490 1491 out_unlock: 1492 mutex_unlock(&p->mutex); 1493 return retval; 1494 } 1495 1496 static int kfd_ioctl_get_dmabuf_info(struct file *filep, 1497 struct kfd_process *p, void *data) 1498 { 1499 struct kfd_ioctl_get_dmabuf_info_args *args = data; 1500 struct kfd_node *dev = NULL; 1501 struct amdgpu_device *dmabuf_adev; 1502 void *metadata_buffer = NULL; 1503 uint32_t flags; 1504 int8_t xcp_id; 1505 unsigned int i; 1506 int r; 1507 1508 /* Find a KFD GPU device that supports the get_dmabuf_info query */ 1509 for (i = 0; kfd_topology_enum_kfd_devices(i, &dev) == 0; i++) 1510 if (dev) 1511 break; 1512 if (!dev) 1513 return -EINVAL; 1514 1515 if (args->metadata_ptr) { 1516 metadata_buffer = kzalloc(args->metadata_size, GFP_KERNEL); 1517 if (!metadata_buffer) 1518 return -ENOMEM; 1519 } 1520 1521 /* Get dmabuf info from KGD */ 1522 r = amdgpu_amdkfd_get_dmabuf_info(dev->adev, args->dmabuf_fd, 1523 &dmabuf_adev, &args->size, 1524 metadata_buffer, args->metadata_size, 1525 &args->metadata_size, &flags, &xcp_id); 1526 if (r) 1527 goto exit; 1528 1529 if (xcp_id >= 0) 1530 args->gpu_id = dmabuf_adev->kfd.dev->nodes[xcp_id]->id; 1531 else 1532 args->gpu_id = dmabuf_adev->kfd.dev->nodes[0]->id; 1533 args->flags = flags; 1534 1535 /* Copy metadata buffer to user mode */ 1536 if (metadata_buffer) { 1537 r = copy_to_user((void __user *)args->metadata_ptr, 1538 metadata_buffer, args->metadata_size); 1539 if (r != 0) 1540 r = -EFAULT; 1541 } 1542 1543 exit: 1544 kfree(metadata_buffer); 1545 1546 return r; 1547 } 1548 1549 static int kfd_ioctl_import_dmabuf(struct file *filep, 1550 struct kfd_process *p, void *data) 1551 { 1552 struct kfd_ioctl_import_dmabuf_args *args = data; 1553 struct kfd_process_device *pdd; 1554 struct dma_buf *dmabuf; 1555 int idr_handle; 1556 uint64_t size; 1557 void *mem; 1558 int r; 1559 1560 dmabuf = dma_buf_get(args->dmabuf_fd); 1561 if (IS_ERR(dmabuf)) 1562 return PTR_ERR(dmabuf); 1563 1564 mutex_lock(&p->mutex); 1565 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 1566 if (!pdd) { 1567 r = -EINVAL; 1568 goto err_unlock; 1569 } 1570 1571 pdd = kfd_bind_process_to_device(pdd->dev, p); 1572 if (IS_ERR(pdd)) { 1573 r = PTR_ERR(pdd); 1574 goto err_unlock; 1575 } 1576 1577 r = amdgpu_amdkfd_gpuvm_import_dmabuf(pdd->dev->adev, dmabuf, 1578 args->va_addr, pdd->drm_priv, 1579 (struct kgd_mem **)&mem, &size, 1580 NULL); 1581 if (r) 1582 goto err_unlock; 1583 1584 idr_handle = kfd_process_device_create_obj_handle(pdd, mem); 1585 if (idr_handle < 0) { 1586 r = -EFAULT; 1587 goto err_free; 1588 } 1589 1590 mutex_unlock(&p->mutex); 1591 dma_buf_put(dmabuf); 1592 1593 args->handle = MAKE_HANDLE(args->gpu_id, idr_handle); 1594 1595 return 0; 1596 1597 err_free: 1598 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, (struct kgd_mem *)mem, 1599 pdd->drm_priv, NULL); 1600 err_unlock: 1601 mutex_unlock(&p->mutex); 1602 dma_buf_put(dmabuf); 1603 return r; 1604 } 1605 1606 static int kfd_ioctl_export_dmabuf(struct file *filep, 1607 struct kfd_process *p, void *data) 1608 { 1609 struct kfd_ioctl_export_dmabuf_args *args = data; 1610 struct kfd_process_device *pdd; 1611 struct dma_buf *dmabuf; 1612 struct kfd_node *dev; 1613 void *mem; 1614 int ret = 0; 1615 1616 dev = kfd_device_by_id(GET_GPU_ID(args->handle)); 1617 if (!dev) 1618 return -EINVAL; 1619 1620 mutex_lock(&p->mutex); 1621 1622 pdd = kfd_get_process_device_data(dev, p); 1623 if (!pdd) { 1624 ret = -EINVAL; 1625 goto err_unlock; 1626 } 1627 1628 mem = kfd_process_device_translate_handle(pdd, 1629 GET_IDR_HANDLE(args->handle)); 1630 if (!mem) { 1631 ret = -EINVAL; 1632 goto err_unlock; 1633 } 1634 1635 ret = amdgpu_amdkfd_gpuvm_export_dmabuf(mem, &dmabuf); 1636 mutex_unlock(&p->mutex); 1637 if (ret) 1638 goto err_out; 1639 1640 ret = dma_buf_fd(dmabuf, args->flags); 1641 if (ret < 0) { 1642 dma_buf_put(dmabuf); 1643 goto err_out; 1644 } 1645 /* dma_buf_fd assigns the reference count to the fd, no need to 1646 * put the reference here. 1647 */ 1648 args->dmabuf_fd = ret; 1649 1650 return 0; 1651 1652 err_unlock: 1653 mutex_unlock(&p->mutex); 1654 err_out: 1655 return ret; 1656 } 1657 1658 /* Handle requests for watching SMI events */ 1659 static int kfd_ioctl_smi_events(struct file *filep, 1660 struct kfd_process *p, void *data) 1661 { 1662 struct kfd_ioctl_smi_events_args *args = data; 1663 struct kfd_process_device *pdd; 1664 1665 mutex_lock(&p->mutex); 1666 1667 pdd = kfd_process_device_data_by_id(p, args->gpuid); 1668 mutex_unlock(&p->mutex); 1669 if (!pdd) 1670 return -EINVAL; 1671 1672 return kfd_smi_event_open(pdd->dev, &args->anon_fd); 1673 } 1674 1675 #if IS_ENABLED(CONFIG_HSA_AMD_SVM) 1676 1677 static int kfd_ioctl_set_xnack_mode(struct file *filep, 1678 struct kfd_process *p, void *data) 1679 { 1680 struct kfd_ioctl_set_xnack_mode_args *args = data; 1681 int r = 0; 1682 1683 mutex_lock(&p->mutex); 1684 if (args->xnack_enabled >= 0) { 1685 if (!list_empty(&p->pqm.queues)) { 1686 pr_debug("Process has user queues running\n"); 1687 r = -EBUSY; 1688 goto out_unlock; 1689 } 1690 1691 if (p->xnack_enabled == args->xnack_enabled) 1692 goto out_unlock; 1693 1694 if (args->xnack_enabled && !kfd_process_xnack_mode(p, true)) { 1695 r = -EPERM; 1696 goto out_unlock; 1697 } 1698 1699 r = svm_range_switch_xnack_reserve_mem(p, args->xnack_enabled); 1700 } else { 1701 args->xnack_enabled = p->xnack_enabled; 1702 } 1703 1704 out_unlock: 1705 mutex_unlock(&p->mutex); 1706 1707 return r; 1708 } 1709 1710 static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data) 1711 { 1712 struct kfd_ioctl_svm_args *args = data; 1713 int r = 0; 1714 1715 pr_debug("start 0x%llx size 0x%llx op 0x%x nattr 0x%x\n", 1716 args->start_addr, args->size, args->op, args->nattr); 1717 1718 if ((args->start_addr & ~PAGE_MASK) || (args->size & ~PAGE_MASK)) 1719 return -EINVAL; 1720 if (!args->start_addr || !args->size) 1721 return -EINVAL; 1722 1723 r = svm_ioctl(p, args->op, args->start_addr, args->size, args->nattr, 1724 args->attrs); 1725 1726 return r; 1727 } 1728 #else 1729 static int kfd_ioctl_set_xnack_mode(struct file *filep, 1730 struct kfd_process *p, void *data) 1731 { 1732 return -EPERM; 1733 } 1734 static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data) 1735 { 1736 return -EPERM; 1737 } 1738 #endif 1739 1740 static int criu_checkpoint_process(struct kfd_process *p, 1741 uint8_t __user *user_priv_data, 1742 uint64_t *priv_offset) 1743 { 1744 struct kfd_criu_process_priv_data process_priv; 1745 int ret; 1746 1747 memset(&process_priv, 0, sizeof(process_priv)); 1748 1749 process_priv.version = KFD_CRIU_PRIV_VERSION; 1750 /* For CR, we don't consider negative xnack mode which is used for 1751 * querying without changing it, here 0 simply means disabled and 1 1752 * means enabled so retry for finding a valid PTE. 1753 */ 1754 process_priv.xnack_mode = p->xnack_enabled ? 1 : 0; 1755 1756 ret = copy_to_user(user_priv_data + *priv_offset, 1757 &process_priv, sizeof(process_priv)); 1758 1759 if (ret) { 1760 pr_err("Failed to copy process information to user\n"); 1761 ret = -EFAULT; 1762 } 1763 1764 *priv_offset += sizeof(process_priv); 1765 return ret; 1766 } 1767 1768 static int criu_checkpoint_devices(struct kfd_process *p, 1769 uint32_t num_devices, 1770 uint8_t __user *user_addr, 1771 uint8_t __user *user_priv_data, 1772 uint64_t *priv_offset) 1773 { 1774 struct kfd_criu_device_priv_data *device_priv = NULL; 1775 struct kfd_criu_device_bucket *device_buckets = NULL; 1776 int ret = 0, i; 1777 1778 device_buckets = kvzalloc(num_devices * sizeof(*device_buckets), GFP_KERNEL); 1779 if (!device_buckets) { 1780 ret = -ENOMEM; 1781 goto exit; 1782 } 1783 1784 device_priv = kvzalloc(num_devices * sizeof(*device_priv), GFP_KERNEL); 1785 if (!device_priv) { 1786 ret = -ENOMEM; 1787 goto exit; 1788 } 1789 1790 for (i = 0; i < num_devices; i++) { 1791 struct kfd_process_device *pdd = p->pdds[i]; 1792 1793 device_buckets[i].user_gpu_id = pdd->user_gpu_id; 1794 device_buckets[i].actual_gpu_id = pdd->dev->id; 1795 1796 /* 1797 * priv_data does not contain useful information for now and is reserved for 1798 * future use, so we do not set its contents. 1799 */ 1800 } 1801 1802 ret = copy_to_user(user_addr, device_buckets, num_devices * sizeof(*device_buckets)); 1803 if (ret) { 1804 pr_err("Failed to copy device information to user\n"); 1805 ret = -EFAULT; 1806 goto exit; 1807 } 1808 1809 ret = copy_to_user(user_priv_data + *priv_offset, 1810 device_priv, 1811 num_devices * sizeof(*device_priv)); 1812 if (ret) { 1813 pr_err("Failed to copy device information to user\n"); 1814 ret = -EFAULT; 1815 } 1816 *priv_offset += num_devices * sizeof(*device_priv); 1817 1818 exit: 1819 kvfree(device_buckets); 1820 kvfree(device_priv); 1821 return ret; 1822 } 1823 1824 static uint32_t get_process_num_bos(struct kfd_process *p) 1825 { 1826 uint32_t num_of_bos = 0; 1827 int i; 1828 1829 /* Run over all PDDs of the process */ 1830 for (i = 0; i < p->n_pdds; i++) { 1831 struct kfd_process_device *pdd = p->pdds[i]; 1832 void *mem; 1833 int id; 1834 1835 idr_for_each_entry(&pdd->alloc_idr, mem, id) { 1836 struct kgd_mem *kgd_mem = (struct kgd_mem *)mem; 1837 1838 if ((uint64_t)kgd_mem->va > pdd->gpuvm_base) 1839 num_of_bos++; 1840 } 1841 } 1842 return num_of_bos; 1843 } 1844 1845 static int criu_get_prime_handle(struct drm_gem_object *gobj, int flags, 1846 u32 *shared_fd) 1847 { 1848 struct dma_buf *dmabuf; 1849 int ret; 1850 1851 dmabuf = amdgpu_gem_prime_export(gobj, flags); 1852 if (IS_ERR(dmabuf)) { 1853 ret = PTR_ERR(dmabuf); 1854 pr_err("dmabuf export failed for the BO\n"); 1855 return ret; 1856 } 1857 1858 ret = dma_buf_fd(dmabuf, flags); 1859 if (ret < 0) { 1860 pr_err("dmabuf create fd failed, ret:%d\n", ret); 1861 goto out_free_dmabuf; 1862 } 1863 1864 *shared_fd = ret; 1865 return 0; 1866 1867 out_free_dmabuf: 1868 dma_buf_put(dmabuf); 1869 return ret; 1870 } 1871 1872 static int criu_checkpoint_bos(struct kfd_process *p, 1873 uint32_t num_bos, 1874 uint8_t __user *user_bos, 1875 uint8_t __user *user_priv_data, 1876 uint64_t *priv_offset) 1877 { 1878 struct kfd_criu_bo_bucket *bo_buckets; 1879 struct kfd_criu_bo_priv_data *bo_privs; 1880 int ret = 0, pdd_index, bo_index = 0, id; 1881 void *mem; 1882 1883 bo_buckets = kvzalloc(num_bos * sizeof(*bo_buckets), GFP_KERNEL); 1884 if (!bo_buckets) 1885 return -ENOMEM; 1886 1887 bo_privs = kvzalloc(num_bos * sizeof(*bo_privs), GFP_KERNEL); 1888 if (!bo_privs) { 1889 ret = -ENOMEM; 1890 goto exit; 1891 } 1892 1893 for (pdd_index = 0; pdd_index < p->n_pdds; pdd_index++) { 1894 struct kfd_process_device *pdd = p->pdds[pdd_index]; 1895 struct amdgpu_bo *dumper_bo; 1896 struct kgd_mem *kgd_mem; 1897 1898 idr_for_each_entry(&pdd->alloc_idr, mem, id) { 1899 struct kfd_criu_bo_bucket *bo_bucket; 1900 struct kfd_criu_bo_priv_data *bo_priv; 1901 int i, dev_idx = 0; 1902 1903 if (!mem) { 1904 ret = -ENOMEM; 1905 goto exit; 1906 } 1907 1908 kgd_mem = (struct kgd_mem *)mem; 1909 dumper_bo = kgd_mem->bo; 1910 1911 if ((uint64_t)kgd_mem->va <= pdd->gpuvm_base) 1912 continue; 1913 1914 bo_bucket = &bo_buckets[bo_index]; 1915 bo_priv = &bo_privs[bo_index]; 1916 1917 bo_bucket->gpu_id = pdd->user_gpu_id; 1918 bo_bucket->addr = (uint64_t)kgd_mem->va; 1919 bo_bucket->size = amdgpu_bo_size(dumper_bo); 1920 bo_bucket->alloc_flags = (uint32_t)kgd_mem->alloc_flags; 1921 bo_priv->idr_handle = id; 1922 1923 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) { 1924 ret = amdgpu_ttm_tt_get_userptr(&dumper_bo->tbo, 1925 &bo_priv->user_addr); 1926 if (ret) { 1927 pr_err("Failed to obtain user address for user-pointer bo\n"); 1928 goto exit; 1929 } 1930 } 1931 if (bo_bucket->alloc_flags 1932 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) { 1933 ret = criu_get_prime_handle(&dumper_bo->tbo.base, 1934 bo_bucket->alloc_flags & 1935 KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? DRM_RDWR : 0, 1936 &bo_bucket->dmabuf_fd); 1937 if (ret) 1938 goto exit; 1939 } else { 1940 bo_bucket->dmabuf_fd = KFD_INVALID_FD; 1941 } 1942 1943 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) 1944 bo_bucket->offset = KFD_MMAP_TYPE_DOORBELL | 1945 KFD_MMAP_GPU_ID(pdd->dev->id); 1946 else if (bo_bucket->alloc_flags & 1947 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) 1948 bo_bucket->offset = KFD_MMAP_TYPE_MMIO | 1949 KFD_MMAP_GPU_ID(pdd->dev->id); 1950 else 1951 bo_bucket->offset = amdgpu_bo_mmap_offset(dumper_bo); 1952 1953 for (i = 0; i < p->n_pdds; i++) { 1954 if (amdgpu_amdkfd_bo_mapped_to_dev(p->pdds[i]->dev->adev, kgd_mem)) 1955 bo_priv->mapped_gpuids[dev_idx++] = p->pdds[i]->user_gpu_id; 1956 } 1957 1958 pr_debug("bo_size = 0x%llx, bo_addr = 0x%llx bo_offset = 0x%llx\n" 1959 "gpu_id = 0x%x alloc_flags = 0x%x idr_handle = 0x%x", 1960 bo_bucket->size, 1961 bo_bucket->addr, 1962 bo_bucket->offset, 1963 bo_bucket->gpu_id, 1964 bo_bucket->alloc_flags, 1965 bo_priv->idr_handle); 1966 bo_index++; 1967 } 1968 } 1969 1970 ret = copy_to_user(user_bos, bo_buckets, num_bos * sizeof(*bo_buckets)); 1971 if (ret) { 1972 pr_err("Failed to copy BO information to user\n"); 1973 ret = -EFAULT; 1974 goto exit; 1975 } 1976 1977 ret = copy_to_user(user_priv_data + *priv_offset, bo_privs, num_bos * sizeof(*bo_privs)); 1978 if (ret) { 1979 pr_err("Failed to copy BO priv information to user\n"); 1980 ret = -EFAULT; 1981 goto exit; 1982 } 1983 1984 *priv_offset += num_bos * sizeof(*bo_privs); 1985 1986 exit: 1987 while (ret && bo_index--) { 1988 if (bo_buckets[bo_index].alloc_flags 1989 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) 1990 close_fd(bo_buckets[bo_index].dmabuf_fd); 1991 } 1992 1993 kvfree(bo_buckets); 1994 kvfree(bo_privs); 1995 return ret; 1996 } 1997 1998 static int criu_get_process_object_info(struct kfd_process *p, 1999 uint32_t *num_devices, 2000 uint32_t *num_bos, 2001 uint32_t *num_objects, 2002 uint64_t *objs_priv_size) 2003 { 2004 uint64_t queues_priv_data_size, svm_priv_data_size, priv_size; 2005 uint32_t num_queues, num_events, num_svm_ranges; 2006 int ret; 2007 2008 *num_devices = p->n_pdds; 2009 *num_bos = get_process_num_bos(p); 2010 2011 ret = kfd_process_get_queue_info(p, &num_queues, &queues_priv_data_size); 2012 if (ret) 2013 return ret; 2014 2015 num_events = kfd_get_num_events(p); 2016 2017 ret = svm_range_get_info(p, &num_svm_ranges, &svm_priv_data_size); 2018 if (ret) 2019 return ret; 2020 2021 *num_objects = num_queues + num_events + num_svm_ranges; 2022 2023 if (objs_priv_size) { 2024 priv_size = sizeof(struct kfd_criu_process_priv_data); 2025 priv_size += *num_devices * sizeof(struct kfd_criu_device_priv_data); 2026 priv_size += *num_bos * sizeof(struct kfd_criu_bo_priv_data); 2027 priv_size += queues_priv_data_size; 2028 priv_size += num_events * sizeof(struct kfd_criu_event_priv_data); 2029 priv_size += svm_priv_data_size; 2030 *objs_priv_size = priv_size; 2031 } 2032 return 0; 2033 } 2034 2035 static int criu_checkpoint(struct file *filep, 2036 struct kfd_process *p, 2037 struct kfd_ioctl_criu_args *args) 2038 { 2039 int ret; 2040 uint32_t num_devices, num_bos, num_objects; 2041 uint64_t priv_size, priv_offset = 0, bo_priv_offset; 2042 2043 if (!args->devices || !args->bos || !args->priv_data) 2044 return -EINVAL; 2045 2046 mutex_lock(&p->mutex); 2047 2048 if (!p->n_pdds) { 2049 pr_err("No pdd for given process\n"); 2050 ret = -ENODEV; 2051 goto exit_unlock; 2052 } 2053 2054 /* Confirm all process queues are evicted */ 2055 if (!p->queues_paused) { 2056 pr_err("Cannot dump process when queues are not in evicted state\n"); 2057 /* CRIU plugin did not call op PROCESS_INFO before checkpointing */ 2058 ret = -EINVAL; 2059 goto exit_unlock; 2060 } 2061 2062 ret = criu_get_process_object_info(p, &num_devices, &num_bos, &num_objects, &priv_size); 2063 if (ret) 2064 goto exit_unlock; 2065 2066 if (num_devices != args->num_devices || 2067 num_bos != args->num_bos || 2068 num_objects != args->num_objects || 2069 priv_size != args->priv_data_size) { 2070 2071 ret = -EINVAL; 2072 goto exit_unlock; 2073 } 2074 2075 /* each function will store private data inside priv_data and adjust priv_offset */ 2076 ret = criu_checkpoint_process(p, (uint8_t __user *)args->priv_data, &priv_offset); 2077 if (ret) 2078 goto exit_unlock; 2079 2080 ret = criu_checkpoint_devices(p, num_devices, (uint8_t __user *)args->devices, 2081 (uint8_t __user *)args->priv_data, &priv_offset); 2082 if (ret) 2083 goto exit_unlock; 2084 2085 /* Leave room for BOs in the private data. They need to be restored 2086 * before events, but we checkpoint them last to simplify the error 2087 * handling. 2088 */ 2089 bo_priv_offset = priv_offset; 2090 priv_offset += num_bos * sizeof(struct kfd_criu_bo_priv_data); 2091 2092 if (num_objects) { 2093 ret = kfd_criu_checkpoint_queues(p, (uint8_t __user *)args->priv_data, 2094 &priv_offset); 2095 if (ret) 2096 goto exit_unlock; 2097 2098 ret = kfd_criu_checkpoint_events(p, (uint8_t __user *)args->priv_data, 2099 &priv_offset); 2100 if (ret) 2101 goto exit_unlock; 2102 2103 ret = kfd_criu_checkpoint_svm(p, (uint8_t __user *)args->priv_data, &priv_offset); 2104 if (ret) 2105 goto exit_unlock; 2106 } 2107 2108 /* This must be the last thing in this function that can fail. 2109 * Otherwise we leak dmabuf file descriptors. 2110 */ 2111 ret = criu_checkpoint_bos(p, num_bos, (uint8_t __user *)args->bos, 2112 (uint8_t __user *)args->priv_data, &bo_priv_offset); 2113 2114 exit_unlock: 2115 mutex_unlock(&p->mutex); 2116 if (ret) 2117 pr_err("Failed to dump CRIU ret:%d\n", ret); 2118 else 2119 pr_debug("CRIU dump ret:%d\n", ret); 2120 2121 return ret; 2122 } 2123 2124 static int criu_restore_process(struct kfd_process *p, 2125 struct kfd_ioctl_criu_args *args, 2126 uint64_t *priv_offset, 2127 uint64_t max_priv_data_size) 2128 { 2129 int ret = 0; 2130 struct kfd_criu_process_priv_data process_priv; 2131 2132 if (*priv_offset + sizeof(process_priv) > max_priv_data_size) 2133 return -EINVAL; 2134 2135 ret = copy_from_user(&process_priv, 2136 (void __user *)(args->priv_data + *priv_offset), 2137 sizeof(process_priv)); 2138 if (ret) { 2139 pr_err("Failed to copy process private information from user\n"); 2140 ret = -EFAULT; 2141 goto exit; 2142 } 2143 *priv_offset += sizeof(process_priv); 2144 2145 if (process_priv.version != KFD_CRIU_PRIV_VERSION) { 2146 pr_err("Invalid CRIU API version (checkpointed:%d current:%d)\n", 2147 process_priv.version, KFD_CRIU_PRIV_VERSION); 2148 return -EINVAL; 2149 } 2150 2151 pr_debug("Setting XNACK mode\n"); 2152 if (process_priv.xnack_mode && !kfd_process_xnack_mode(p, true)) { 2153 pr_err("xnack mode cannot be set\n"); 2154 ret = -EPERM; 2155 goto exit; 2156 } else { 2157 pr_debug("set xnack mode: %d\n", process_priv.xnack_mode); 2158 p->xnack_enabled = process_priv.xnack_mode; 2159 } 2160 2161 exit: 2162 return ret; 2163 } 2164 2165 static int criu_restore_devices(struct kfd_process *p, 2166 struct kfd_ioctl_criu_args *args, 2167 uint64_t *priv_offset, 2168 uint64_t max_priv_data_size) 2169 { 2170 struct kfd_criu_device_bucket *device_buckets; 2171 struct kfd_criu_device_priv_data *device_privs; 2172 int ret = 0; 2173 uint32_t i; 2174 2175 if (args->num_devices != p->n_pdds) 2176 return -EINVAL; 2177 2178 if (*priv_offset + (args->num_devices * sizeof(*device_privs)) > max_priv_data_size) 2179 return -EINVAL; 2180 2181 device_buckets = kmalloc_array(args->num_devices, sizeof(*device_buckets), GFP_KERNEL); 2182 if (!device_buckets) 2183 return -ENOMEM; 2184 2185 ret = copy_from_user(device_buckets, (void __user *)args->devices, 2186 args->num_devices * sizeof(*device_buckets)); 2187 if (ret) { 2188 pr_err("Failed to copy devices buckets from user\n"); 2189 ret = -EFAULT; 2190 goto exit; 2191 } 2192 2193 for (i = 0; i < args->num_devices; i++) { 2194 struct kfd_node *dev; 2195 struct kfd_process_device *pdd; 2196 struct file *drm_file; 2197 2198 /* device private data is not currently used */ 2199 2200 if (!device_buckets[i].user_gpu_id) { 2201 pr_err("Invalid user gpu_id\n"); 2202 ret = -EINVAL; 2203 goto exit; 2204 } 2205 2206 dev = kfd_device_by_id(device_buckets[i].actual_gpu_id); 2207 if (!dev) { 2208 pr_err("Failed to find device with gpu_id = %x\n", 2209 device_buckets[i].actual_gpu_id); 2210 ret = -EINVAL; 2211 goto exit; 2212 } 2213 2214 pdd = kfd_get_process_device_data(dev, p); 2215 if (!pdd) { 2216 pr_err("Failed to get pdd for gpu_id = %x\n", 2217 device_buckets[i].actual_gpu_id); 2218 ret = -EINVAL; 2219 goto exit; 2220 } 2221 pdd->user_gpu_id = device_buckets[i].user_gpu_id; 2222 2223 drm_file = fget(device_buckets[i].drm_fd); 2224 if (!drm_file) { 2225 pr_err("Invalid render node file descriptor sent from plugin (%d)\n", 2226 device_buckets[i].drm_fd); 2227 ret = -EINVAL; 2228 goto exit; 2229 } 2230 2231 if (pdd->drm_file) { 2232 ret = -EINVAL; 2233 goto exit; 2234 } 2235 2236 /* create the vm using render nodes for kfd pdd */ 2237 if (kfd_process_device_init_vm(pdd, drm_file)) { 2238 pr_err("could not init vm for given pdd\n"); 2239 /* On success, the PDD keeps the drm_file reference */ 2240 fput(drm_file); 2241 ret = -EINVAL; 2242 goto exit; 2243 } 2244 /* 2245 * pdd now already has the vm bound to render node so below api won't create a new 2246 * exclusive kfd mapping but use existing one with renderDXXX but is still needed 2247 * for iommu v2 binding and runtime pm. 2248 */ 2249 pdd = kfd_bind_process_to_device(dev, p); 2250 if (IS_ERR(pdd)) { 2251 ret = PTR_ERR(pdd); 2252 goto exit; 2253 } 2254 2255 if (!pdd->doorbell_index && 2256 kfd_alloc_process_doorbells(pdd->dev->kfd, &pdd->doorbell_index) < 0) { 2257 ret = -ENOMEM; 2258 goto exit; 2259 } 2260 } 2261 2262 /* 2263 * We are not copying device private data from user as we are not using the data for now, 2264 * but we still adjust for its private data. 2265 */ 2266 *priv_offset += args->num_devices * sizeof(*device_privs); 2267 2268 exit: 2269 kfree(device_buckets); 2270 return ret; 2271 } 2272 2273 static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, 2274 struct kfd_criu_bo_bucket *bo_bucket, 2275 struct kfd_criu_bo_priv_data *bo_priv, 2276 struct kgd_mem **kgd_mem) 2277 { 2278 int idr_handle; 2279 int ret; 2280 const bool criu_resume = true; 2281 u64 offset; 2282 2283 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) { 2284 if (bo_bucket->size != 2285 kfd_doorbell_process_slice(pdd->dev->kfd)) 2286 return -EINVAL; 2287 2288 offset = kfd_get_process_doorbells(pdd); 2289 if (!offset) 2290 return -ENOMEM; 2291 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) { 2292 /* MMIO BOs need remapped bus address */ 2293 if (bo_bucket->size != PAGE_SIZE) { 2294 pr_err("Invalid page size\n"); 2295 return -EINVAL; 2296 } 2297 offset = pdd->dev->adev->rmmio_remap.bus_addr; 2298 if (!offset) { 2299 pr_err("amdgpu_amdkfd_get_mmio_remap_phys_addr failed\n"); 2300 return -ENOMEM; 2301 } 2302 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) { 2303 offset = bo_priv->user_addr; 2304 } 2305 /* Create the BO */ 2306 ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(pdd->dev->adev, bo_bucket->addr, 2307 bo_bucket->size, pdd->drm_priv, kgd_mem, 2308 &offset, bo_bucket->alloc_flags, criu_resume); 2309 if (ret) { 2310 pr_err("Could not create the BO\n"); 2311 return ret; 2312 } 2313 pr_debug("New BO created: size:0x%llx addr:0x%llx offset:0x%llx\n", 2314 bo_bucket->size, bo_bucket->addr, offset); 2315 2316 /* Restore previous IDR handle */ 2317 pr_debug("Restoring old IDR handle for the BO"); 2318 idr_handle = idr_alloc(&pdd->alloc_idr, *kgd_mem, bo_priv->idr_handle, 2319 bo_priv->idr_handle + 1, GFP_KERNEL); 2320 2321 if (idr_handle < 0) { 2322 pr_err("Could not allocate idr\n"); 2323 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, *kgd_mem, pdd->drm_priv, 2324 NULL); 2325 return -ENOMEM; 2326 } 2327 2328 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) 2329 bo_bucket->restored_offset = KFD_MMAP_TYPE_DOORBELL | KFD_MMAP_GPU_ID(pdd->dev->id); 2330 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) { 2331 bo_bucket->restored_offset = KFD_MMAP_TYPE_MMIO | KFD_MMAP_GPU_ID(pdd->dev->id); 2332 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) { 2333 bo_bucket->restored_offset = offset; 2334 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { 2335 bo_bucket->restored_offset = offset; 2336 /* Update the VRAM usage count */ 2337 WRITE_ONCE(pdd->vram_usage, pdd->vram_usage + bo_bucket->size); 2338 } 2339 return 0; 2340 } 2341 2342 static int criu_restore_bo(struct kfd_process *p, 2343 struct kfd_criu_bo_bucket *bo_bucket, 2344 struct kfd_criu_bo_priv_data *bo_priv) 2345 { 2346 struct kfd_process_device *pdd; 2347 struct kgd_mem *kgd_mem; 2348 int ret; 2349 int j; 2350 2351 pr_debug("Restoring BO size:0x%llx addr:0x%llx gpu_id:0x%x flags:0x%x idr_handle:0x%x\n", 2352 bo_bucket->size, bo_bucket->addr, bo_bucket->gpu_id, bo_bucket->alloc_flags, 2353 bo_priv->idr_handle); 2354 2355 pdd = kfd_process_device_data_by_id(p, bo_bucket->gpu_id); 2356 if (!pdd) { 2357 pr_err("Failed to get pdd\n"); 2358 return -ENODEV; 2359 } 2360 2361 ret = criu_restore_memory_of_gpu(pdd, bo_bucket, bo_priv, &kgd_mem); 2362 if (ret) 2363 return ret; 2364 2365 /* now map these BOs to GPU/s */ 2366 for (j = 0; j < p->n_pdds; j++) { 2367 struct kfd_node *peer; 2368 struct kfd_process_device *peer_pdd; 2369 2370 if (!bo_priv->mapped_gpuids[j]) 2371 break; 2372 2373 peer_pdd = kfd_process_device_data_by_id(p, bo_priv->mapped_gpuids[j]); 2374 if (!peer_pdd) 2375 return -EINVAL; 2376 2377 peer = peer_pdd->dev; 2378 2379 peer_pdd = kfd_bind_process_to_device(peer, p); 2380 if (IS_ERR(peer_pdd)) 2381 return PTR_ERR(peer_pdd); 2382 2383 ret = amdgpu_amdkfd_gpuvm_map_memory_to_gpu(peer->adev, kgd_mem, 2384 peer_pdd->drm_priv); 2385 if (ret) { 2386 pr_err("Failed to map to gpu %d/%d\n", j, p->n_pdds); 2387 return ret; 2388 } 2389 } 2390 2391 pr_debug("map memory was successful for the BO\n"); 2392 /* create the dmabuf object and export the bo */ 2393 if (bo_bucket->alloc_flags 2394 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) { 2395 ret = criu_get_prime_handle(&kgd_mem->bo->tbo.base, DRM_RDWR, 2396 &bo_bucket->dmabuf_fd); 2397 if (ret) 2398 return ret; 2399 } else { 2400 bo_bucket->dmabuf_fd = KFD_INVALID_FD; 2401 } 2402 2403 return 0; 2404 } 2405 2406 static int criu_restore_bos(struct kfd_process *p, 2407 struct kfd_ioctl_criu_args *args, 2408 uint64_t *priv_offset, 2409 uint64_t max_priv_data_size) 2410 { 2411 struct kfd_criu_bo_bucket *bo_buckets = NULL; 2412 struct kfd_criu_bo_priv_data *bo_privs = NULL; 2413 int ret = 0; 2414 uint32_t i = 0; 2415 2416 if (*priv_offset + (args->num_bos * sizeof(*bo_privs)) > max_priv_data_size) 2417 return -EINVAL; 2418 2419 /* Prevent MMU notifications until stage-4 IOCTL (CRIU_RESUME) is received */ 2420 amdgpu_amdkfd_block_mmu_notifications(p->kgd_process_info); 2421 2422 bo_buckets = kvmalloc_array(args->num_bos, sizeof(*bo_buckets), GFP_KERNEL); 2423 if (!bo_buckets) 2424 return -ENOMEM; 2425 2426 ret = copy_from_user(bo_buckets, (void __user *)args->bos, 2427 args->num_bos * sizeof(*bo_buckets)); 2428 if (ret) { 2429 pr_err("Failed to copy BOs information from user\n"); 2430 ret = -EFAULT; 2431 goto exit; 2432 } 2433 2434 bo_privs = kvmalloc_array(args->num_bos, sizeof(*bo_privs), GFP_KERNEL); 2435 if (!bo_privs) { 2436 ret = -ENOMEM; 2437 goto exit; 2438 } 2439 2440 ret = copy_from_user(bo_privs, (void __user *)args->priv_data + *priv_offset, 2441 args->num_bos * sizeof(*bo_privs)); 2442 if (ret) { 2443 pr_err("Failed to copy BOs information from user\n"); 2444 ret = -EFAULT; 2445 goto exit; 2446 } 2447 *priv_offset += args->num_bos * sizeof(*bo_privs); 2448 2449 /* Create and map new BOs */ 2450 for (; i < args->num_bos; i++) { 2451 ret = criu_restore_bo(p, &bo_buckets[i], &bo_privs[i]); 2452 if (ret) { 2453 pr_debug("Failed to restore BO[%d] ret%d\n", i, ret); 2454 goto exit; 2455 } 2456 } /* done */ 2457 2458 /* Copy only the buckets back so user can read bo_buckets[N].restored_offset */ 2459 ret = copy_to_user((void __user *)args->bos, 2460 bo_buckets, 2461 (args->num_bos * sizeof(*bo_buckets))); 2462 if (ret) 2463 ret = -EFAULT; 2464 2465 exit: 2466 while (ret && i--) { 2467 if (bo_buckets[i].alloc_flags 2468 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) 2469 close_fd(bo_buckets[i].dmabuf_fd); 2470 } 2471 kvfree(bo_buckets); 2472 kvfree(bo_privs); 2473 return ret; 2474 } 2475 2476 static int criu_restore_objects(struct file *filep, 2477 struct kfd_process *p, 2478 struct kfd_ioctl_criu_args *args, 2479 uint64_t *priv_offset, 2480 uint64_t max_priv_data_size) 2481 { 2482 int ret = 0; 2483 uint32_t i; 2484 2485 BUILD_BUG_ON(offsetof(struct kfd_criu_queue_priv_data, object_type)); 2486 BUILD_BUG_ON(offsetof(struct kfd_criu_event_priv_data, object_type)); 2487 BUILD_BUG_ON(offsetof(struct kfd_criu_svm_range_priv_data, object_type)); 2488 2489 for (i = 0; i < args->num_objects; i++) { 2490 uint32_t object_type; 2491 2492 if (*priv_offset + sizeof(object_type) > max_priv_data_size) { 2493 pr_err("Invalid private data size\n"); 2494 return -EINVAL; 2495 } 2496 2497 ret = get_user(object_type, (uint32_t __user *)(args->priv_data + *priv_offset)); 2498 if (ret) { 2499 pr_err("Failed to copy private information from user\n"); 2500 goto exit; 2501 } 2502 2503 switch (object_type) { 2504 case KFD_CRIU_OBJECT_TYPE_QUEUE: 2505 ret = kfd_criu_restore_queue(p, (uint8_t __user *)args->priv_data, 2506 priv_offset, max_priv_data_size); 2507 if (ret) 2508 goto exit; 2509 break; 2510 case KFD_CRIU_OBJECT_TYPE_EVENT: 2511 ret = kfd_criu_restore_event(filep, p, (uint8_t __user *)args->priv_data, 2512 priv_offset, max_priv_data_size); 2513 if (ret) 2514 goto exit; 2515 break; 2516 case KFD_CRIU_OBJECT_TYPE_SVM_RANGE: 2517 ret = kfd_criu_restore_svm(p, (uint8_t __user *)args->priv_data, 2518 priv_offset, max_priv_data_size); 2519 if (ret) 2520 goto exit; 2521 break; 2522 default: 2523 pr_err("Invalid object type:%u at index:%d\n", object_type, i); 2524 ret = -EINVAL; 2525 goto exit; 2526 } 2527 } 2528 exit: 2529 return ret; 2530 } 2531 2532 static int criu_restore(struct file *filep, 2533 struct kfd_process *p, 2534 struct kfd_ioctl_criu_args *args) 2535 { 2536 uint64_t priv_offset = 0; 2537 int ret = 0; 2538 2539 pr_debug("CRIU restore (num_devices:%u num_bos:%u num_objects:%u priv_data_size:%llu)\n", 2540 args->num_devices, args->num_bos, args->num_objects, args->priv_data_size); 2541 2542 if (!args->bos || !args->devices || !args->priv_data || !args->priv_data_size || 2543 !args->num_devices || !args->num_bos) 2544 return -EINVAL; 2545 2546 mutex_lock(&p->mutex); 2547 2548 /* 2549 * Set the process to evicted state to avoid running any new queues before all the memory 2550 * mappings are ready. 2551 */ 2552 ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_RESTORE); 2553 if (ret) 2554 goto exit_unlock; 2555 2556 /* Each function will adjust priv_offset based on how many bytes they consumed */ 2557 ret = criu_restore_process(p, args, &priv_offset, args->priv_data_size); 2558 if (ret) 2559 goto exit_unlock; 2560 2561 ret = criu_restore_devices(p, args, &priv_offset, args->priv_data_size); 2562 if (ret) 2563 goto exit_unlock; 2564 2565 ret = criu_restore_bos(p, args, &priv_offset, args->priv_data_size); 2566 if (ret) 2567 goto exit_unlock; 2568 2569 ret = criu_restore_objects(filep, p, args, &priv_offset, args->priv_data_size); 2570 if (ret) 2571 goto exit_unlock; 2572 2573 if (priv_offset != args->priv_data_size) { 2574 pr_err("Invalid private data size\n"); 2575 ret = -EINVAL; 2576 } 2577 2578 exit_unlock: 2579 mutex_unlock(&p->mutex); 2580 if (ret) 2581 pr_err("Failed to restore CRIU ret:%d\n", ret); 2582 else 2583 pr_debug("CRIU restore successful\n"); 2584 2585 return ret; 2586 } 2587 2588 static int criu_unpause(struct file *filep, 2589 struct kfd_process *p, 2590 struct kfd_ioctl_criu_args *args) 2591 { 2592 int ret; 2593 2594 mutex_lock(&p->mutex); 2595 2596 if (!p->queues_paused) { 2597 mutex_unlock(&p->mutex); 2598 return -EINVAL; 2599 } 2600 2601 ret = kfd_process_restore_queues(p); 2602 if (ret) 2603 pr_err("Failed to unpause queues ret:%d\n", ret); 2604 else 2605 p->queues_paused = false; 2606 2607 mutex_unlock(&p->mutex); 2608 2609 return ret; 2610 } 2611 2612 static int criu_resume(struct file *filep, 2613 struct kfd_process *p, 2614 struct kfd_ioctl_criu_args *args) 2615 { 2616 struct kfd_process *target = NULL; 2617 struct pid *pid = NULL; 2618 int ret = 0; 2619 2620 pr_debug("Inside %s, target pid for criu restore: %d\n", __func__, 2621 args->pid); 2622 2623 pid = find_get_pid(args->pid); 2624 if (!pid) { 2625 pr_err("Cannot find pid info for %i\n", args->pid); 2626 return -ESRCH; 2627 } 2628 2629 pr_debug("calling kfd_lookup_process_by_pid\n"); 2630 target = kfd_lookup_process_by_pid(pid); 2631 2632 put_pid(pid); 2633 2634 if (!target) { 2635 pr_debug("Cannot find process info for %i\n", args->pid); 2636 return -ESRCH; 2637 } 2638 2639 mutex_lock(&target->mutex); 2640 ret = kfd_criu_resume_svm(target); 2641 if (ret) { 2642 pr_err("kfd_criu_resume_svm failed for %i\n", args->pid); 2643 goto exit; 2644 } 2645 2646 ret = amdgpu_amdkfd_criu_resume(target->kgd_process_info); 2647 if (ret) 2648 pr_err("amdgpu_amdkfd_criu_resume failed for %i\n", args->pid); 2649 2650 exit: 2651 mutex_unlock(&target->mutex); 2652 2653 kfd_unref_process(target); 2654 return ret; 2655 } 2656 2657 static int criu_process_info(struct file *filep, 2658 struct kfd_process *p, 2659 struct kfd_ioctl_criu_args *args) 2660 { 2661 int ret = 0; 2662 2663 mutex_lock(&p->mutex); 2664 2665 if (!p->n_pdds) { 2666 pr_err("No pdd for given process\n"); 2667 ret = -ENODEV; 2668 goto err_unlock; 2669 } 2670 2671 ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_CHECKPOINT); 2672 if (ret) 2673 goto err_unlock; 2674 2675 p->queues_paused = true; 2676 2677 args->pid = task_pid_nr_ns(p->lead_thread, 2678 task_active_pid_ns(p->lead_thread)); 2679 2680 ret = criu_get_process_object_info(p, &args->num_devices, &args->num_bos, 2681 &args->num_objects, &args->priv_data_size); 2682 if (ret) 2683 goto err_unlock; 2684 2685 dev_dbg(kfd_device, "Num of devices:%u bos:%u objects:%u priv_data_size:%lld\n", 2686 args->num_devices, args->num_bos, args->num_objects, 2687 args->priv_data_size); 2688 2689 err_unlock: 2690 if (ret) { 2691 kfd_process_restore_queues(p); 2692 p->queues_paused = false; 2693 } 2694 mutex_unlock(&p->mutex); 2695 return ret; 2696 } 2697 2698 static int kfd_ioctl_criu(struct file *filep, struct kfd_process *p, void *data) 2699 { 2700 struct kfd_ioctl_criu_args *args = data; 2701 int ret; 2702 2703 dev_dbg(kfd_device, "CRIU operation: %d\n", args->op); 2704 switch (args->op) { 2705 case KFD_CRIU_OP_PROCESS_INFO: 2706 ret = criu_process_info(filep, p, args); 2707 break; 2708 case KFD_CRIU_OP_CHECKPOINT: 2709 ret = criu_checkpoint(filep, p, args); 2710 break; 2711 case KFD_CRIU_OP_UNPAUSE: 2712 ret = criu_unpause(filep, p, args); 2713 break; 2714 case KFD_CRIU_OP_RESTORE: 2715 ret = criu_restore(filep, p, args); 2716 break; 2717 case KFD_CRIU_OP_RESUME: 2718 ret = criu_resume(filep, p, args); 2719 break; 2720 default: 2721 dev_dbg(kfd_device, "Unsupported CRIU operation:%d\n", args->op); 2722 ret = -EINVAL; 2723 break; 2724 } 2725 2726 if (ret) 2727 dev_dbg(kfd_device, "CRIU operation:%d err:%d\n", args->op, ret); 2728 2729 return ret; 2730 } 2731 2732 #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \ 2733 [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \ 2734 .cmd_drv = 0, .name = #ioctl} 2735 2736 /** Ioctl table */ 2737 static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { 2738 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_VERSION, 2739 kfd_ioctl_get_version, 0), 2740 2741 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_QUEUE, 2742 kfd_ioctl_create_queue, 0), 2743 2744 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_QUEUE, 2745 kfd_ioctl_destroy_queue, 0), 2746 2747 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_MEMORY_POLICY, 2748 kfd_ioctl_set_memory_policy, 0), 2749 2750 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_CLOCK_COUNTERS, 2751 kfd_ioctl_get_clock_counters, 0), 2752 2753 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES, 2754 kfd_ioctl_get_process_apertures, 0), 2755 2756 AMDKFD_IOCTL_DEF(AMDKFD_IOC_UPDATE_QUEUE, 2757 kfd_ioctl_update_queue, 0), 2758 2759 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_EVENT, 2760 kfd_ioctl_create_event, 0), 2761 2762 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_EVENT, 2763 kfd_ioctl_destroy_event, 0), 2764 2765 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_EVENT, 2766 kfd_ioctl_set_event, 0), 2767 2768 AMDKFD_IOCTL_DEF(AMDKFD_IOC_RESET_EVENT, 2769 kfd_ioctl_reset_event, 0), 2770 2771 AMDKFD_IOCTL_DEF(AMDKFD_IOC_WAIT_EVENTS, 2772 kfd_ioctl_wait_events, 0), 2773 2774 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_REGISTER_DEPRECATED, 2775 kfd_ioctl_dbg_register, 0), 2776 2777 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_UNREGISTER_DEPRECATED, 2778 kfd_ioctl_dbg_unregister, 0), 2779 2780 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_ADDRESS_WATCH_DEPRECATED, 2781 kfd_ioctl_dbg_address_watch, 0), 2782 2783 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_WAVE_CONTROL_DEPRECATED, 2784 kfd_ioctl_dbg_wave_control, 0), 2785 2786 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_SCRATCH_BACKING_VA, 2787 kfd_ioctl_set_scratch_backing_va, 0), 2788 2789 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_TILE_CONFIG, 2790 kfd_ioctl_get_tile_config, 0), 2791 2792 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_TRAP_HANDLER, 2793 kfd_ioctl_set_trap_handler, 0), 2794 2795 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES_NEW, 2796 kfd_ioctl_get_process_apertures_new, 0), 2797 2798 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ACQUIRE_VM, 2799 kfd_ioctl_acquire_vm, 0), 2800 2801 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_MEMORY_OF_GPU, 2802 kfd_ioctl_alloc_memory_of_gpu, 0), 2803 2804 AMDKFD_IOCTL_DEF(AMDKFD_IOC_FREE_MEMORY_OF_GPU, 2805 kfd_ioctl_free_memory_of_gpu, 0), 2806 2807 AMDKFD_IOCTL_DEF(AMDKFD_IOC_MAP_MEMORY_TO_GPU, 2808 kfd_ioctl_map_memory_to_gpu, 0), 2809 2810 AMDKFD_IOCTL_DEF(AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU, 2811 kfd_ioctl_unmap_memory_from_gpu, 0), 2812 2813 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_CU_MASK, 2814 kfd_ioctl_set_cu_mask, 0), 2815 2816 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_QUEUE_WAVE_STATE, 2817 kfd_ioctl_get_queue_wave_state, 0), 2818 2819 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_DMABUF_INFO, 2820 kfd_ioctl_get_dmabuf_info, 0), 2821 2822 AMDKFD_IOCTL_DEF(AMDKFD_IOC_IMPORT_DMABUF, 2823 kfd_ioctl_import_dmabuf, 0), 2824 2825 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_QUEUE_GWS, 2826 kfd_ioctl_alloc_queue_gws, 0), 2827 2828 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SMI_EVENTS, 2829 kfd_ioctl_smi_events, 0), 2830 2831 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SVM, kfd_ioctl_svm, 0), 2832 2833 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_XNACK_MODE, 2834 kfd_ioctl_set_xnack_mode, 0), 2835 2836 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CRIU_OP, 2837 kfd_ioctl_criu, KFD_IOC_FLAG_CHECKPOINT_RESTORE), 2838 2839 AMDKFD_IOCTL_DEF(AMDKFD_IOC_AVAILABLE_MEMORY, 2840 kfd_ioctl_get_available_memory, 0), 2841 2842 AMDKFD_IOCTL_DEF(AMDKFD_IOC_EXPORT_DMABUF, 2843 kfd_ioctl_export_dmabuf, 0), 2844 }; 2845 2846 #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls) 2847 2848 static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) 2849 { 2850 struct kfd_process *process; 2851 amdkfd_ioctl_t *func; 2852 const struct amdkfd_ioctl_desc *ioctl = NULL; 2853 unsigned int nr = _IOC_NR(cmd); 2854 char stack_kdata[128]; 2855 char *kdata = NULL; 2856 unsigned int usize, asize; 2857 int retcode = -EINVAL; 2858 bool ptrace_attached = false; 2859 2860 if (nr >= AMDKFD_CORE_IOCTL_COUNT) 2861 goto err_i1; 2862 2863 if ((nr >= AMDKFD_COMMAND_START) && (nr < AMDKFD_COMMAND_END)) { 2864 u32 amdkfd_size; 2865 2866 ioctl = &amdkfd_ioctls[nr]; 2867 2868 amdkfd_size = _IOC_SIZE(ioctl->cmd); 2869 usize = asize = _IOC_SIZE(cmd); 2870 if (amdkfd_size > asize) 2871 asize = amdkfd_size; 2872 2873 cmd = ioctl->cmd; 2874 } else 2875 goto err_i1; 2876 2877 dev_dbg(kfd_device, "ioctl cmd 0x%x (#0x%x), arg 0x%lx\n", cmd, nr, arg); 2878 2879 /* Get the process struct from the filep. Only the process 2880 * that opened /dev/kfd can use the file descriptor. Child 2881 * processes need to create their own KFD device context. 2882 */ 2883 process = filep->private_data; 2884 2885 rcu_read_lock(); 2886 if ((ioctl->flags & KFD_IOC_FLAG_CHECKPOINT_RESTORE) && 2887 ptrace_parent(process->lead_thread) == current) 2888 ptrace_attached = true; 2889 rcu_read_unlock(); 2890 2891 if (process->lead_thread != current->group_leader 2892 && !ptrace_attached) { 2893 dev_dbg(kfd_device, "Using KFD FD in wrong process\n"); 2894 retcode = -EBADF; 2895 goto err_i1; 2896 } 2897 2898 /* Do not trust userspace, use our own definition */ 2899 func = ioctl->func; 2900 2901 if (unlikely(!func)) { 2902 dev_dbg(kfd_device, "no function\n"); 2903 retcode = -EINVAL; 2904 goto err_i1; 2905 } 2906 2907 /* 2908 * Versions of docker shipped in Ubuntu 18.xx and 20.xx do not support 2909 * CAP_CHECKPOINT_RESTORE, so we also allow access if CAP_SYS_ADMIN as CAP_SYS_ADMIN is a 2910 * more priviledged access. 2911 */ 2912 if (unlikely(ioctl->flags & KFD_IOC_FLAG_CHECKPOINT_RESTORE)) { 2913 if (!capable(CAP_CHECKPOINT_RESTORE) && 2914 !capable(CAP_SYS_ADMIN)) { 2915 retcode = -EACCES; 2916 goto err_i1; 2917 } 2918 } 2919 2920 if (cmd & (IOC_IN | IOC_OUT)) { 2921 if (asize <= sizeof(stack_kdata)) { 2922 kdata = stack_kdata; 2923 } else { 2924 kdata = kmalloc(asize, GFP_KERNEL); 2925 if (!kdata) { 2926 retcode = -ENOMEM; 2927 goto err_i1; 2928 } 2929 } 2930 if (asize > usize) 2931 memset(kdata + usize, 0, asize - usize); 2932 } 2933 2934 if (cmd & IOC_IN) { 2935 if (copy_from_user(kdata, (void __user *)arg, usize) != 0) { 2936 retcode = -EFAULT; 2937 goto err_i1; 2938 } 2939 } else if (cmd & IOC_OUT) { 2940 memset(kdata, 0, usize); 2941 } 2942 2943 retcode = func(filep, process, kdata); 2944 2945 if (cmd & IOC_OUT) 2946 if (copy_to_user((void __user *)arg, kdata, usize) != 0) 2947 retcode = -EFAULT; 2948 2949 err_i1: 2950 if (!ioctl) 2951 dev_dbg(kfd_device, "invalid ioctl: pid=%d, cmd=0x%02x, nr=0x%02x\n", 2952 task_pid_nr(current), cmd, nr); 2953 2954 if (kdata != stack_kdata) 2955 kfree(kdata); 2956 2957 if (retcode) 2958 dev_dbg(kfd_device, "ioctl cmd (#0x%x), arg 0x%lx, ret = %d\n", 2959 nr, arg, retcode); 2960 2961 return retcode; 2962 } 2963 2964 static int kfd_mmio_mmap(struct kfd_node *dev, struct kfd_process *process, 2965 struct vm_area_struct *vma) 2966 { 2967 phys_addr_t address; 2968 2969 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2970 return -EINVAL; 2971 2972 address = dev->adev->rmmio_remap.bus_addr; 2973 2974 vm_flags_set(vma, VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_NORESERVE | 2975 VM_DONTDUMP | VM_PFNMAP); 2976 2977 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 2978 2979 pr_debug("pasid 0x%x mapping mmio page\n" 2980 " target user address == 0x%08llX\n" 2981 " physical address == 0x%08llX\n" 2982 " vm_flags == 0x%04lX\n" 2983 " size == 0x%04lX\n", 2984 process->pasid, (unsigned long long) vma->vm_start, 2985 address, vma->vm_flags, PAGE_SIZE); 2986 2987 return io_remap_pfn_range(vma, 2988 vma->vm_start, 2989 address >> PAGE_SHIFT, 2990 PAGE_SIZE, 2991 vma->vm_page_prot); 2992 } 2993 2994 2995 static int kfd_mmap(struct file *filp, struct vm_area_struct *vma) 2996 { 2997 struct kfd_process *process; 2998 struct kfd_node *dev = NULL; 2999 unsigned long mmap_offset; 3000 unsigned int gpu_id; 3001 3002 process = kfd_get_process(current); 3003 if (IS_ERR(process)) 3004 return PTR_ERR(process); 3005 3006 mmap_offset = vma->vm_pgoff << PAGE_SHIFT; 3007 gpu_id = KFD_MMAP_GET_GPU_ID(mmap_offset); 3008 if (gpu_id) 3009 dev = kfd_device_by_id(gpu_id); 3010 3011 switch (mmap_offset & KFD_MMAP_TYPE_MASK) { 3012 case KFD_MMAP_TYPE_DOORBELL: 3013 if (!dev) 3014 return -ENODEV; 3015 return kfd_doorbell_mmap(dev, process, vma); 3016 3017 case KFD_MMAP_TYPE_EVENTS: 3018 return kfd_event_mmap(process, vma); 3019 3020 case KFD_MMAP_TYPE_RESERVED_MEM: 3021 if (!dev) 3022 return -ENODEV; 3023 return kfd_reserved_mem_mmap(dev, process, vma); 3024 case KFD_MMAP_TYPE_MMIO: 3025 if (!dev) 3026 return -ENODEV; 3027 return kfd_mmio_mmap(dev, process, vma); 3028 } 3029 3030 return -EFAULT; 3031 } 3032