1/* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23/* To compile this assembly code: 24 * PROJECT=greenland ./sp3 cwsr_trap_handler_gfx9.asm -hex tmp.hex 25 */ 26 27/* HW (GFX9) source code for CWSR trap handler */ 28/* Version 18 + multiple trap handler */ 29 30// this performance-optimal version was originally from Seven Xu at SRDC 31 32// Revison #18 --... 33/* Rev History 34** #1. Branch from gc dv. //gfxip/gfx9/main/src/test/suites/block/cs/sr/cs_trap_handler.sp3#1,#50, #51, #52-53(Skip, Already Fixed by PV), #54-56(merged),#57-58(mergerd, skiped-already fixed by PV) 35** #4. SR Memory Layout: 36** 1. VGPR-SGPR-HWREG-{LDS} 37** 2. tba_hi.bits.26 - reconfigured as the first wave in tg bits, for defer Save LDS for a threadgroup.. performance concern.. 38** #5. Update: 1. Accurate g8sr_ts_save_d timestamp 39** #6. Update: 1. Fix s_barrier usage; 2. VGPR s/r using swizzle buffer?(NoNeed, already matched the swizzle pattern, more investigation) 40** #7. Update: 1. don't barrier if noLDS 41** #8. Branch: 1. Branch to ver#0, which is very similar to gc dv version 42** 2. Fix SQ issue by s_sleep 2 43** #9. Update: 1. Fix scc restore failed issue, restore wave_status at last 44** 2. optimize s_buffer save by burst 16sgprs... 45** #10. Update 1. Optimize restore sgpr by busrt 16 sgprs. 46** #11. Update 1. Add 2 more timestamp for debug version 47** #12. Update 1. Add VGPR SR using DWx4, some case improve and some case drop performance 48** #13. Integ 1. Always use MUBUF for PV trap shader... 49** #14. Update 1. s_buffer_store soft clause... 50** #15. Update 1. PERF - sclar write with glc:0/mtype0 to allow L2 combine. perf improvement a lot. 51** #16. Update 1. PRRF - UNROLL LDS_DMA got 2500cycle save in IP tree 52** #17. Update 1. FUNC - LDS_DMA has issues while ATC, replace with ds_read/buffer_store for save part[TODO restore part] 53** 2. PERF - Save LDS before save VGPR to cover LDS save long latency... 54** #18. Update 1. FUNC - Implicitly estore STATUS.VCCZ, which is not writable by s_setreg_b32 55** 2. FUNC - Handle non-CWSR traps 56*/ 57 58var G8SR_WDMEM_HWREG_OFFSET = 0 59var G8SR_WDMEM_SGPR_OFFSET = 128 // in bytes 60 61// Keep definition same as the app shader, These 2 time stamps are part of the app shader... Should before any Save and after restore. 62 63var G8SR_DEBUG_TIMESTAMP = 0 64var G8SR_DEBUG_TS_SAVE_D_OFFSET = 40*4 // ts_save_d timestamp offset relative to SGPR_SR_memory_offset 65var s_g8sr_ts_save_s = s[34:35] // save start 66var s_g8sr_ts_sq_save_msg = s[36:37] // The save shader send SAVEWAVE msg to spi 67var s_g8sr_ts_spi_wrexec = s[38:39] // the SPI write the sr address to SQ 68var s_g8sr_ts_save_d = s[40:41] // save end 69var s_g8sr_ts_restore_s = s[42:43] // restore start 70var s_g8sr_ts_restore_d = s[44:45] // restore end 71 72var G8SR_VGPR_SR_IN_DWX4 = 0 73var G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 = 0x00100000 // DWx4 stride is 4*4Bytes 74var G8SR_RESTORE_BUF_RSRC_WORD1_STRIDE_DWx4 = G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 75 76 77/*************************************************************************/ 78/* control on how to run the shader */ 79/*************************************************************************/ 80//any hack that needs to be made to run this code in EMU (either because various EMU code are not ready or no compute save & restore in EMU run) 81var EMU_RUN_HACK = 0 82var EMU_RUN_HACK_RESTORE_NORMAL = 0 83var EMU_RUN_HACK_SAVE_NORMAL_EXIT = 0 84var EMU_RUN_HACK_SAVE_SINGLE_WAVE = 0 85var EMU_RUN_HACK_SAVE_FIRST_TIME = 0 //for interrupted restore in which the first save is through EMU_RUN_HACK 86var SAVE_LDS = 1 87var WG_BASE_ADDR_LO = 0x9000a000 88var WG_BASE_ADDR_HI = 0x0 89var WAVE_SPACE = 0x5000 //memory size that each wave occupies in workgroup state mem 90var CTX_SAVE_CONTROL = 0x0 91var CTX_RESTORE_CONTROL = CTX_SAVE_CONTROL 92var SIM_RUN_HACK = 0 //any hack that needs to be made to run this code in SIM (either because various RTL code are not ready or no compute save & restore in RTL run) 93var SGPR_SAVE_USE_SQC = 1 //use SQC D$ to do the write 94var USE_MTBUF_INSTEAD_OF_MUBUF = 0 //because TC EMU currently asserts on 0 of // overload DFMT field to carry 4 more bits of stride for MUBUF opcodes 95var SWIZZLE_EN = 0 //whether we use swizzled buffer addressing 96var ACK_SQC_STORE = 1 //workaround for suspected SQC store bug causing incorrect stores under concurrency 97 98/**************************************************************************/ 99/* variables */ 100/**************************************************************************/ 101var SQ_WAVE_STATUS_INST_ATC_SHIFT = 23 102var SQ_WAVE_STATUS_INST_ATC_MASK = 0x00800000 103var SQ_WAVE_STATUS_SPI_PRIO_SHIFT = 1 104var SQ_WAVE_STATUS_SPI_PRIO_MASK = 0x00000006 105var SQ_WAVE_STATUS_HALT_MASK = 0x2000 106 107var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT = 12 108var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE = 9 109var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 8 110var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE = 6 111var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT = 24 112var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE = 3 //FIXME sq.blk still has 4 bits at this time while SQ programming guide has 3 bits 113 114var SQ_WAVE_TRAPSTS_SAVECTX_MASK = 0x400 115var SQ_WAVE_TRAPSTS_EXCE_MASK = 0x1FF // Exception mask 116var SQ_WAVE_TRAPSTS_SAVECTX_SHIFT = 10 117var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK = 0x100 118var SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT = 8 119var SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK = 0x3FF 120var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT = 0x0 121var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE = 10 122var SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK = 0xFFFFF800 123var SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT = 11 124var SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE = 21 125var SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK = 0x800 126 127var SQ_WAVE_IB_STS_RCNT_SHIFT = 16 //FIXME 128var SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT = 15 //FIXME 129var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK = 0x1F8000 130var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG = 0x00007FFF //FIXME 131 132var SQ_BUF_RSRC_WORD1_ATC_SHIFT = 24 133var SQ_BUF_RSRC_WORD3_MTYPE_SHIFT = 27 134 135var TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT = 26 // bits [31:26] unused by SPI debug data 136var TTMP11_SAVE_RCNT_FIRST_REPLAY_MASK = 0xFC000000 137 138/* Save */ 139var S_SAVE_BUF_RSRC_WORD1_STRIDE = 0x00040000 //stride is 4 bytes 140var S_SAVE_BUF_RSRC_WORD3_MISC = 0x00807FAC //SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14] when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE 141 142var S_SAVE_SPI_INIT_ATC_MASK = 0x08000000 //bit[27]: ATC bit 143var S_SAVE_SPI_INIT_ATC_SHIFT = 27 144var S_SAVE_SPI_INIT_MTYPE_MASK = 0x70000000 //bit[30:28]: Mtype 145var S_SAVE_SPI_INIT_MTYPE_SHIFT = 28 146var S_SAVE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG 147var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT = 26 148 149var S_SAVE_PC_HI_RCNT_SHIFT = 28 //FIXME check with Brian to ensure all fields other than PC[47:0] can be used 150var S_SAVE_PC_HI_RCNT_MASK = 0xF0000000 //FIXME 151var S_SAVE_PC_HI_FIRST_REPLAY_SHIFT = 27 //FIXME 152var S_SAVE_PC_HI_FIRST_REPLAY_MASK = 0x08000000 //FIXME 153 154var s_save_spi_init_lo = exec_lo 155var s_save_spi_init_hi = exec_hi 156 157var s_save_pc_lo = ttmp0 //{TTMP1, TTMP0} = {3'h0,pc_rewind[3:0], HT[0],trapID[7:0], PC[47:0]} 158var s_save_pc_hi = ttmp1 159var s_save_exec_lo = ttmp2 160var s_save_exec_hi = ttmp3 161var s_save_tmp = ttmp4 162var s_save_trapsts = ttmp5 //not really used until the end of the SAVE routine 163var s_save_xnack_mask_lo = ttmp6 164var s_save_xnack_mask_hi = ttmp7 165var s_save_buf_rsrc0 = ttmp8 166var s_save_buf_rsrc1 = ttmp9 167var s_save_buf_rsrc2 = ttmp10 168var s_save_buf_rsrc3 = ttmp11 169var s_save_status = ttmp12 170var s_save_mem_offset = ttmp14 171var s_save_alloc_size = s_save_trapsts //conflict 172var s_save_m0 = ttmp15 173var s_save_ttmps_lo = s_save_tmp //no conflict 174var s_save_ttmps_hi = s_save_trapsts //no conflict 175 176/* Restore */ 177var S_RESTORE_BUF_RSRC_WORD1_STRIDE = S_SAVE_BUF_RSRC_WORD1_STRIDE 178var S_RESTORE_BUF_RSRC_WORD3_MISC = S_SAVE_BUF_RSRC_WORD3_MISC 179 180var S_RESTORE_SPI_INIT_ATC_MASK = 0x08000000 //bit[27]: ATC bit 181var S_RESTORE_SPI_INIT_ATC_SHIFT = 27 182var S_RESTORE_SPI_INIT_MTYPE_MASK = 0x70000000 //bit[30:28]: Mtype 183var S_RESTORE_SPI_INIT_MTYPE_SHIFT = 28 184var S_RESTORE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG 185var S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT = 26 186 187var S_RESTORE_PC_HI_RCNT_SHIFT = S_SAVE_PC_HI_RCNT_SHIFT 188var S_RESTORE_PC_HI_RCNT_MASK = S_SAVE_PC_HI_RCNT_MASK 189var S_RESTORE_PC_HI_FIRST_REPLAY_SHIFT = S_SAVE_PC_HI_FIRST_REPLAY_SHIFT 190var S_RESTORE_PC_HI_FIRST_REPLAY_MASK = S_SAVE_PC_HI_FIRST_REPLAY_MASK 191 192var s_restore_spi_init_lo = exec_lo 193var s_restore_spi_init_hi = exec_hi 194 195var s_restore_mem_offset = ttmp12 196var s_restore_alloc_size = ttmp3 197var s_restore_tmp = ttmp2 198var s_restore_mem_offset_save = s_restore_tmp //no conflict 199 200var s_restore_m0 = s_restore_alloc_size //no conflict 201 202var s_restore_mode = ttmp7 203 204var s_restore_pc_lo = ttmp0 205var s_restore_pc_hi = ttmp1 206var s_restore_exec_lo = ttmp14 207var s_restore_exec_hi = ttmp15 208var s_restore_status = ttmp4 209var s_restore_trapsts = ttmp5 210var s_restore_xnack_mask_lo = xnack_mask_lo 211var s_restore_xnack_mask_hi = xnack_mask_hi 212var s_restore_buf_rsrc0 = ttmp8 213var s_restore_buf_rsrc1 = ttmp9 214var s_restore_buf_rsrc2 = ttmp10 215var s_restore_buf_rsrc3 = ttmp11 216var s_restore_ttmps_lo = s_restore_tmp //no conflict 217var s_restore_ttmps_hi = s_restore_alloc_size //no conflict 218 219/**************************************************************************/ 220/* trap handler entry points */ 221/**************************************************************************/ 222/* Shader Main*/ 223 224shader main 225 asic(GFX9) 226 type(CS) 227 228 229 if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL)) //hack to use trap_id for determining save/restore 230 //FIXME VCCZ un-init assertion s_getreg_b32 s_save_status, hwreg(HW_REG_STATUS) //save STATUS since we will change SCC 231 s_and_b32 s_save_tmp, s_save_pc_hi, 0xffff0000 //change SCC 232 s_cmp_eq_u32 s_save_tmp, 0x007e0000 //Save: trap_id = 0x7e. Restore: trap_id = 0x7f. 233 s_cbranch_scc0 L_JUMP_TO_RESTORE //do not need to recover STATUS here since we are going to RESTORE 234 //FIXME s_setreg_b32 hwreg(HW_REG_STATUS), s_save_status //need to recover STATUS since we are going to SAVE 235 s_branch L_SKIP_RESTORE //NOT restore, SAVE actually 236 else 237 s_branch L_SKIP_RESTORE //NOT restore. might be a regular trap or save 238 end 239 240L_JUMP_TO_RESTORE: 241 s_branch L_RESTORE //restore 242 243L_SKIP_RESTORE: 244 245 s_getreg_b32 s_save_status, hwreg(HW_REG_STATUS) //save STATUS since we will change SCC 246 s_andn2_b32 s_save_status, s_save_status, SQ_WAVE_STATUS_SPI_PRIO_MASK //check whether this is for save 247 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 248 s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK //check whether this is for save 249 s_cbranch_scc1 L_SAVE //this is the operation for save 250 251 // ********* Handle non-CWSR traps ******************* 252if (!EMU_RUN_HACK) 253 // Illegal instruction is a non-maskable exception which blocks context save. 254 // Halt the wavefront and return from the trap. 255 s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK 256 s_cbranch_scc1 L_HALT_WAVE 257 258 // If STATUS.MEM_VIOL is asserted then we cannot fetch from the TMA. 259 // Instead, halt the wavefront and return from the trap. 260 s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_MEM_VIOL_MASK 261 s_cbranch_scc0 L_FETCH_2ND_TRAP 262 263L_HALT_WAVE: 264 // If STATUS.HALT is set then this fault must come from SQC instruction fetch. 265 // We cannot prevent further faults so just terminate the wavefront. 266 s_and_b32 ttmp2, s_save_status, SQ_WAVE_STATUS_HALT_MASK 267 s_cbranch_scc0 L_NOT_ALREADY_HALTED 268 s_endpgm 269L_NOT_ALREADY_HALTED: 270 s_or_b32 s_save_status, s_save_status, SQ_WAVE_STATUS_HALT_MASK 271 272 // If the PC points to S_ENDPGM then context save will fail if STATUS.HALT is set. 273 // Rewind the PC to prevent this from occurring. The debugger compensates for this. 274 s_sub_u32 ttmp0, ttmp0, 0x8 275 s_subb_u32 ttmp1, ttmp1, 0x0 276 277L_FETCH_2ND_TRAP: 278 // Preserve and clear scalar XNACK state before issuing scalar reads. 279 // Save IB_STS.FIRST_REPLAY[15] and IB_STS.RCNT[20:16] into unused space ttmp11[31:26]. 280 s_getreg_b32 ttmp2, hwreg(HW_REG_IB_STS) 281 s_and_b32 ttmp3, ttmp2, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK 282 s_lshl_b32 ttmp3, ttmp3, (TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT - SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT) 283 s_andn2_b32 ttmp11, ttmp11, TTMP11_SAVE_RCNT_FIRST_REPLAY_MASK 284 s_or_b32 ttmp11, ttmp11, ttmp3 285 286 s_andn2_b32 ttmp2, ttmp2, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK 287 s_setreg_b32 hwreg(HW_REG_IB_STS), ttmp2 288 289 // Read second-level TBA/TMA from first-level TMA and jump if available. 290 // ttmp[2:5] and ttmp12 can be used (others hold SPI-initialized debug data) 291 // ttmp12 holds SQ_WAVE_STATUS 292 s_getreg_b32 ttmp4, hwreg(HW_REG_SQ_SHADER_TMA_LO) 293 s_getreg_b32 ttmp5, hwreg(HW_REG_SQ_SHADER_TMA_HI) 294 s_lshl_b64 [ttmp4, ttmp5], [ttmp4, ttmp5], 0x8 295 s_load_dwordx2 [ttmp2, ttmp3], [ttmp4, ttmp5], 0x0 glc:1 // second-level TBA 296 s_waitcnt lgkmcnt(0) 297 s_load_dwordx2 [ttmp4, ttmp5], [ttmp4, ttmp5], 0x8 glc:1 // second-level TMA 298 s_waitcnt lgkmcnt(0) 299 s_and_b64 [ttmp2, ttmp3], [ttmp2, ttmp3], [ttmp2, ttmp3] 300 s_cbranch_scc0 L_NO_NEXT_TRAP // second-level trap handler not been set 301 s_setpc_b64 [ttmp2, ttmp3] // jump to second-level trap handler 302 303L_NO_NEXT_TRAP: 304 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 305 s_and_b32 s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_EXCE_MASK // Check whether it is an exception 306 s_cbranch_scc1 L_EXCP_CASE // Exception, jump back to the shader program directly. 307 s_add_u32 ttmp0, ttmp0, 4 // S_TRAP case, add 4 to ttmp0 308 s_addc_u32 ttmp1, ttmp1, 0 309L_EXCP_CASE: 310 s_and_b32 ttmp1, ttmp1, 0xFFFF 311 312 // Restore SQ_WAVE_IB_STS. 313 s_lshr_b32 ttmp2, ttmp11, (TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT - SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT) 314 s_and_b32 ttmp2, ttmp2, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK 315 s_setreg_b32 hwreg(HW_REG_IB_STS), ttmp2 316 317 // Restore SQ_WAVE_STATUS. 318 s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32 319 s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32 320 s_setreg_b32 hwreg(HW_REG_STATUS), s_save_status 321 322 s_rfe_b64 [ttmp0, ttmp1] 323end 324 // ********* End handling of non-CWSR traps ******************* 325 326/**************************************************************************/ 327/* save routine */ 328/**************************************************************************/ 329 330L_SAVE: 331 332if G8SR_DEBUG_TIMESTAMP 333 s_memrealtime s_g8sr_ts_save_s 334 s_waitcnt lgkmcnt(0) //FIXME, will cause xnack?? 335end 336 337 s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff //pc[47:32] 338 339 s_mov_b32 s_save_tmp, 0 //clear saveCtx bit 340 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_SAVECTX_SHIFT, 1), s_save_tmp //clear saveCtx bit 341 342 s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_RCNT_SHIFT, SQ_WAVE_IB_STS_RCNT_SIZE) //save RCNT 343 s_lshl_b32 s_save_tmp, s_save_tmp, S_SAVE_PC_HI_RCNT_SHIFT 344 s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp 345 s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT, SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE) //save FIRST_REPLAY 346 s_lshl_b32 s_save_tmp, s_save_tmp, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT 347 s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp 348 s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS) //clear RCNT and FIRST_REPLAY in IB_STS 349 s_and_b32 s_save_tmp, s_save_tmp, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG 350 351 s_setreg_b32 hwreg(HW_REG_IB_STS), s_save_tmp 352 353 /* inform SPI the readiness and wait for SPI's go signal */ 354 s_mov_b32 s_save_exec_lo, exec_lo //save EXEC and use EXEC for the go signal from SPI 355 s_mov_b32 s_save_exec_hi, exec_hi 356 s_mov_b64 exec, 0x0 //clear EXEC to get ready to receive 357 358if G8SR_DEBUG_TIMESTAMP 359 s_memrealtime s_g8sr_ts_sq_save_msg 360 s_waitcnt lgkmcnt(0) 361end 362 363 if (EMU_RUN_HACK) 364 365 else 366 s_sendmsg sendmsg(MSG_SAVEWAVE) //send SPI a message and wait for SPI's write to EXEC 367 end 368 369 // Set SPI_PRIO=2 to avoid starving instruction fetch in the waves we're waiting for. 370 s_or_b32 s_save_tmp, s_save_status, (2 << SQ_WAVE_STATUS_SPI_PRIO_SHIFT) 371 s_setreg_b32 hwreg(HW_REG_STATUS), s_save_tmp 372 373 L_SLEEP: 374 s_sleep 0x2 // sleep 1 (64clk) is not enough for 8 waves per SIMD, which will cause SQ hang, since the 7,8th wave could not get arbit to exec inst, while other waves are stuck into the sleep-loop and waiting for wrexec!=0 375 376 if (EMU_RUN_HACK) 377 378 else 379 s_cbranch_execz L_SLEEP 380 end 381 382if G8SR_DEBUG_TIMESTAMP 383 s_memrealtime s_g8sr_ts_spi_wrexec 384 s_waitcnt lgkmcnt(0) 385end 386 387 if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_SINGLE_WAVE)) 388 //calculate wd_addr using absolute thread id 389 v_readlane_b32 s_save_tmp, v9, 0 390 s_lshr_b32 s_save_tmp, s_save_tmp, 6 391 s_mul_i32 s_save_tmp, s_save_tmp, WAVE_SPACE 392 s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO 393 s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI 394 s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL 395 else 396 end 397 if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_SINGLE_WAVE)) 398 s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO 399 s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI 400 s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL 401 else 402 end 403 404 // Save trap temporaries 6-11, 13-15 initialized by SPI debug dispatch logic 405 // ttmp SR memory offset : size(VGPR)+size(SGPR)+0x40 406 get_vgpr_size_bytes(s_save_ttmps_lo) 407 get_sgpr_size_bytes(s_save_ttmps_hi) 408 s_add_u32 s_save_ttmps_lo, s_save_ttmps_lo, s_save_ttmps_hi 409 s_add_u32 s_save_ttmps_lo, s_save_ttmps_lo, s_save_spi_init_lo 410 s_addc_u32 s_save_ttmps_hi, s_save_spi_init_hi, 0x0 411 s_and_b32 s_save_ttmps_hi, s_save_ttmps_hi, 0xFFFF 412 s_store_dwordx2 [ttmp6, ttmp7], [s_save_ttmps_lo, s_save_ttmps_hi], 0x40 glc:1 413 ack_sqc_store_workaround() 414 s_store_dwordx4 [ttmp8, ttmp9, ttmp10, ttmp11], [s_save_ttmps_lo, s_save_ttmps_hi], 0x48 glc:1 415 ack_sqc_store_workaround() 416 s_store_dword ttmp13, [s_save_ttmps_lo, s_save_ttmps_hi], 0x58 glc:1 417 ack_sqc_store_workaround() 418 s_store_dwordx2 [ttmp14, ttmp15], [s_save_ttmps_lo, s_save_ttmps_hi], 0x5C glc:1 419 ack_sqc_store_workaround() 420 421 /* setup Resource Contants */ 422 s_mov_b32 s_save_buf_rsrc0, s_save_spi_init_lo //base_addr_lo 423 s_and_b32 s_save_buf_rsrc1, s_save_spi_init_hi, 0x0000FFFF //base_addr_hi 424 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE 425 s_mov_b32 s_save_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) although not neccessarily inited 426 s_mov_b32 s_save_buf_rsrc3, S_SAVE_BUF_RSRC_WORD3_MISC 427 s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_ATC_MASK 428 s_lshr_b32 s_save_tmp, s_save_tmp, (S_SAVE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT) //get ATC bit into position 429 s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, s_save_tmp //or ATC 430 s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_MTYPE_MASK 431 s_lshr_b32 s_save_tmp, s_save_tmp, (S_SAVE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT) //get MTYPE bits into position 432 s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, s_save_tmp //or MTYPE 433 434 //FIXME right now s_save_m0/s_save_mem_offset use tma_lo/tma_hi (might need to save them before using them?) 435 s_mov_b32 s_save_m0, m0 //save M0 436 437 /* global mem offset */ 438 s_mov_b32 s_save_mem_offset, 0x0 //mem offset initial value = 0 439 440 441 442 443 /* save HW registers */ 444 ////////////////////////////// 445 446 L_SAVE_HWREG: 447 // HWREG SR memory offset : size(VGPR)+size(SGPR) 448 get_vgpr_size_bytes(s_save_mem_offset) 449 get_sgpr_size_bytes(s_save_tmp) 450 s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp 451 452 453 s_mov_b32 s_save_buf_rsrc2, 0x4 //NUM_RECORDS in bytes 454 if (SWIZZLE_EN) 455 s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 456 else 457 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 458 end 459 460 461 write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) //M0 462 463 if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_FIRST_TIME)) 464 s_add_u32 s_save_pc_lo, s_save_pc_lo, 4 //pc[31:0]+4 465 s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0 //carry bit over 466 end 467 468 write_hwreg_to_mem(s_save_pc_lo, s_save_buf_rsrc0, s_save_mem_offset) //PC 469 write_hwreg_to_mem(s_save_pc_hi, s_save_buf_rsrc0, s_save_mem_offset) 470 write_hwreg_to_mem(s_save_exec_lo, s_save_buf_rsrc0, s_save_mem_offset) //EXEC 471 write_hwreg_to_mem(s_save_exec_hi, s_save_buf_rsrc0, s_save_mem_offset) 472 write_hwreg_to_mem(s_save_status, s_save_buf_rsrc0, s_save_mem_offset) //STATUS 473 474 //s_save_trapsts conflicts with s_save_alloc_size 475 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 476 write_hwreg_to_mem(s_save_trapsts, s_save_buf_rsrc0, s_save_mem_offset) //TRAPSTS 477 478 write_hwreg_to_mem(xnack_mask_lo, s_save_buf_rsrc0, s_save_mem_offset) //XNACK_MASK_LO 479 write_hwreg_to_mem(xnack_mask_hi, s_save_buf_rsrc0, s_save_mem_offset) //XNACK_MASK_HI 480 481 //use s_save_tmp would introduce conflict here between s_save_tmp and s_save_buf_rsrc2 482 s_getreg_b32 s_save_m0, hwreg(HW_REG_MODE) //MODE 483 write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) 484 485 486 487 /* the first wave in the threadgroup */ 488 s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK // extract fisrt wave bit 489 s_mov_b32 s_save_exec_hi, 0x0 490 s_or_b32 s_save_exec_hi, s_save_tmp, s_save_exec_hi // save first wave bit to s_save_exec_hi.bits[26] 491 492 493 /* save SGPRs */ 494 // Save SGPR before LDS save, then the s0 to s4 can be used during LDS save... 495 ////////////////////////////// 496 497 // SGPR SR memory offset : size(VGPR) 498 get_vgpr_size_bytes(s_save_mem_offset) 499 // TODO, change RSRC word to rearrange memory layout for SGPRS 500 501 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size 502 s_add_u32 s_save_alloc_size, s_save_alloc_size, 1 503 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 4 //Number of SGPRs = (sgpr_size + 1) * 16 (non-zero value) 504 505 if (SGPR_SAVE_USE_SQC) 506 s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 2 //NUM_RECORDS in bytes 507 else 508 s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 8 //NUM_RECORDS in bytes (64 threads) 509 end 510 511 if (SWIZZLE_EN) 512 s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 513 else 514 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 515 end 516 517 518 // backup s_save_buf_rsrc0,1 to s_save_pc_lo/hi, since write_16sgpr_to_mem function will change the rsrc0 519 //s_mov_b64 s_save_pc_lo, s_save_buf_rsrc0 520 s_mov_b64 s_save_xnack_mask_lo, s_save_buf_rsrc0 521 s_add_u32 s_save_buf_rsrc0, s_save_buf_rsrc0, s_save_mem_offset 522 s_addc_u32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0 523 524 s_mov_b32 m0, 0x0 //SGPR initial index value =0 525 s_nop 0x0 //Manually inserted wait states 526 L_SAVE_SGPR_LOOP: 527 // SGPR is allocated in 16 SGPR granularity 528 s_movrels_b64 s0, s0 //s0 = s[0+m0], s1 = s[1+m0] 529 s_movrels_b64 s2, s2 //s2 = s[2+m0], s3 = s[3+m0] 530 s_movrels_b64 s4, s4 //s4 = s[4+m0], s5 = s[5+m0] 531 s_movrels_b64 s6, s6 //s6 = s[6+m0], s7 = s[7+m0] 532 s_movrels_b64 s8, s8 //s8 = s[8+m0], s9 = s[9+m0] 533 s_movrels_b64 s10, s10 //s10 = s[10+m0], s11 = s[11+m0] 534 s_movrels_b64 s12, s12 //s12 = s[12+m0], s13 = s[13+m0] 535 s_movrels_b64 s14, s14 //s14 = s[14+m0], s15 = s[15+m0] 536 537 write_16sgpr_to_mem(s0, s_save_buf_rsrc0, s_save_mem_offset) //PV: the best performance should be using s_buffer_store_dwordx4 538 s_add_u32 m0, m0, 16 //next sgpr index 539 s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 540 s_cbranch_scc1 L_SAVE_SGPR_LOOP //SGPR save is complete? 541 // restore s_save_buf_rsrc0,1 542 //s_mov_b64 s_save_buf_rsrc0, s_save_pc_lo 543 s_mov_b64 s_save_buf_rsrc0, s_save_xnack_mask_lo 544 545 546 547 548 /* save first 4 VGPR, then LDS save could use */ 549 // each wave will alloc 4 vgprs at least... 550 ///////////////////////////////////////////////////////////////////////////////////// 551 552 s_mov_b32 s_save_mem_offset, 0 553 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 554 s_mov_b32 exec_hi, 0xFFFFFFFF 555 s_mov_b32 xnack_mask_lo, 0x0 556 s_mov_b32 xnack_mask_hi, 0x0 557 558 if (SWIZZLE_EN) 559 s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 560 else 561 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 562 end 563 564 565 // VGPR Allocated in 4-GPR granularity 566 567if G8SR_VGPR_SR_IN_DWX4 568 // the const stride for DWx4 is 4*4 bytes 569 s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 570 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 // const stride to 4*4 bytes 571 572 buffer_store_dwordx4 v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 573 574 s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 575 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE // reset const stride to 4 bytes 576else 577 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 578 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256 579 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2 580 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3 581end 582 583 584 585 /* save LDS */ 586 ////////////////////////////// 587 588 L_SAVE_LDS: 589 590 // Change EXEC to all threads... 591 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 592 s_mov_b32 exec_hi, 0xFFFFFFFF 593 594 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) //lds_size 595 s_and_b32 s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF //lds_size is zero? 596 s_cbranch_scc0 L_SAVE_LDS_DONE //no lds used? jump to L_SAVE_DONE 597 598 s_barrier //LDS is used? wait for other waves in the same TG 599 s_and_b32 s_save_tmp, s_save_exec_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK //exec is still used here 600 s_cbranch_scc0 L_SAVE_LDS_DONE 601 602 // first wave do LDS save; 603 604 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 6 //LDS size in dwords = lds_size * 64dw 605 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 2 //LDS size in bytes 606 s_mov_b32 s_save_buf_rsrc2, s_save_alloc_size //NUM_RECORDS in bytes 607 608 // LDS at offset: size(VGPR)+SIZE(SGPR)+SIZE(HWREG) 609 // 610 get_vgpr_size_bytes(s_save_mem_offset) 611 get_sgpr_size_bytes(s_save_tmp) 612 s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp 613 s_add_u32 s_save_mem_offset, s_save_mem_offset, get_hwreg_size_bytes() 614 615 616 if (SWIZZLE_EN) 617 s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 618 else 619 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 620 end 621 622 s_mov_b32 m0, 0x0 //lds_offset initial value = 0 623 624 625var LDS_DMA_ENABLE = 0 626var UNROLL = 0 627if UNROLL==0 && LDS_DMA_ENABLE==1 628 s_mov_b32 s3, 256*2 629 s_nop 0 630 s_nop 0 631 s_nop 0 632 L_SAVE_LDS_LOOP: 633 //TODO: looks the 2 buffer_store/load clause for s/r will hurt performance.??? 634 if (SAVE_LDS) //SPI always alloc LDS space in 128DW granularity 635 buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 // first 64DW 636 buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:256 // second 64DW 637 end 638 639 s_add_u32 m0, m0, s3 //every buffer_store_lds does 256 bytes 640 s_add_u32 s_save_mem_offset, s_save_mem_offset, s3 //mem offset increased by 256 bytes 641 s_cmp_lt_u32 m0, s_save_alloc_size //scc=(m0 < s_save_alloc_size) ? 1 : 0 642 s_cbranch_scc1 L_SAVE_LDS_LOOP //LDS save is complete? 643 644elsif LDS_DMA_ENABLE==1 && UNROLL==1 // UNROOL , has ichace miss 645 // store from higest LDS address to lowest 646 s_mov_b32 s3, 256*2 647 s_sub_u32 m0, s_save_alloc_size, s3 648 s_add_u32 s_save_mem_offset, s_save_mem_offset, m0 649 s_lshr_b32 s_save_alloc_size, s_save_alloc_size, 9 // how many 128 trunks... 650 s_sub_u32 s_save_alloc_size, 128, s_save_alloc_size // store from higheset addr to lowest 651 s_mul_i32 s_save_alloc_size, s_save_alloc_size, 6*4 // PC offset increment, each LDS save block cost 6*4 Bytes instruction 652 s_add_u32 s_save_alloc_size, s_save_alloc_size, 3*4 //2is the below 2 inst...//s_addc and s_setpc 653 s_nop 0 654 s_nop 0 655 s_nop 0 //pad 3 dw to let LDS_DMA align with 64Bytes 656 s_getpc_b64 s[0:1] // reuse s[0:1], since s[0:1] already saved 657 s_add_u32 s0, s0,s_save_alloc_size 658 s_addc_u32 s1, s1, 0 659 s_setpc_b64 s[0:1] 660 661 662 for var i =0; i< 128; i++ 663 // be careful to make here a 64Byte aligned address, which could improve performance... 664 buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:0 // first 64DW 665 buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:256 // second 64DW 666 667 if i!=127 668 s_sub_u32 m0, m0, s3 // use a sgpr to shrink 2DW-inst to 1DW inst to improve performance , i.e. pack more LDS_DMA inst to one Cacheline 669 s_sub_u32 s_save_mem_offset, s_save_mem_offset, s3 670 end 671 end 672 673else // BUFFER_STORE 674 v_mbcnt_lo_u32_b32 v2, 0xffffffff, 0x0 675 v_mbcnt_hi_u32_b32 v3, 0xffffffff, v2 // tid 676 v_mul_i32_i24 v2, v3, 8 // tid*8 677 v_mov_b32 v3, 256*2 678 s_mov_b32 m0, 0x10000 679 s_mov_b32 s0, s_save_buf_rsrc3 680 s_and_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, 0xFF7FFFFF // disable add_tid 681 s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, 0x58000 //DFMT 682 683L_SAVE_LDS_LOOP_VECTOR: 684 ds_read_b64 v[0:1], v2 //x =LDS[a], byte address 685 s_waitcnt lgkmcnt(0) 686 buffer_store_dwordx2 v[0:1], v2, s_save_buf_rsrc0, s_save_mem_offset offen:1 glc:1 slc:1 687// s_waitcnt vmcnt(0) 688// v_add_u32 v2, vcc[0:1], v2, v3 689 v_add_u32 v2, v2, v3 690 v_cmp_lt_u32 vcc[0:1], v2, s_save_alloc_size 691 s_cbranch_vccnz L_SAVE_LDS_LOOP_VECTOR 692 693 // restore rsrc3 694 s_mov_b32 s_save_buf_rsrc3, s0 695 696end 697 698L_SAVE_LDS_DONE: 699 700 701 /* save VGPRs - set the Rest VGPRs */ 702 ////////////////////////////////////////////////////////////////////////////////////// 703 L_SAVE_VGPR: 704 // VGPR SR memory offset: 0 705 // TODO rearrange the RSRC words to use swizzle for VGPR save... 706 707 s_mov_b32 s_save_mem_offset, (0+256*4) // for the rest VGPRs 708 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 709 s_mov_b32 exec_hi, 0xFFFFFFFF 710 711 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) //vpgr_size 712 s_add_u32 s_save_alloc_size, s_save_alloc_size, 1 713 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value) //FIXME for GFX, zero is possible 714 s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 8 //NUM_RECORDS in bytes (64 threads*4) 715 if (SWIZZLE_EN) 716 s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 717 else 718 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 719 end 720 721 722 // VGPR Allocated in 4-GPR granularity 723 724if G8SR_VGPR_SR_IN_DWX4 725 // the const stride for DWx4 is 4*4 bytes 726 s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 727 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 // const stride to 4*4 bytes 728 729 s_mov_b32 m0, 4 // skip first 4 VGPRs 730 s_cmp_lt_u32 m0, s_save_alloc_size 731 s_cbranch_scc0 L_SAVE_VGPR_LOOP_END // no more vgprs 732 733 s_set_gpr_idx_on m0, 0x1 // This will change M0 734 s_add_u32 s_save_alloc_size, s_save_alloc_size, 0x1000 // because above inst change m0 735L_SAVE_VGPR_LOOP: 736 v_mov_b32 v0, v0 // v0 = v[0+m0] 737 v_mov_b32 v1, v1 738 v_mov_b32 v2, v2 739 v_mov_b32 v3, v3 740 741 742 buffer_store_dwordx4 v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 743 s_add_u32 m0, m0, 4 744 s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 745 s_cmp_lt_u32 m0, s_save_alloc_size 746 s_cbranch_scc1 L_SAVE_VGPR_LOOP //VGPR save is complete? 747 s_set_gpr_idx_off 748L_SAVE_VGPR_LOOP_END: 749 750 s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 751 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE // reset const stride to 4 bytes 752else 753 // VGPR store using dw burst 754 s_mov_b32 m0, 0x4 //VGPR initial index value =0 755 s_cmp_lt_u32 m0, s_save_alloc_size 756 s_cbranch_scc0 L_SAVE_VGPR_END 757 758 759 s_set_gpr_idx_on m0, 0x1 //M0[7:0] = M0[7:0] and M0[15:12] = 0x1 760 s_add_u32 s_save_alloc_size, s_save_alloc_size, 0x1000 //add 0x1000 since we compare m0 against it later 761 762 L_SAVE_VGPR_LOOP: 763 v_mov_b32 v0, v0 //v0 = v[0+m0] 764 v_mov_b32 v1, v1 //v0 = v[0+m0] 765 v_mov_b32 v2, v2 //v0 = v[0+m0] 766 v_mov_b32 v3, v3 //v0 = v[0+m0] 767 768 if(USE_MTBUF_INSTEAD_OF_MUBUF) 769 tbuffer_store_format_x v0, v0, s_save_buf_rsrc0, s_save_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1 770 else 771 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 772 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256 773 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2 774 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3 775 end 776 777 s_add_u32 m0, m0, 4 //next vgpr index 778 s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 //every buffer_store_dword does 256 bytes 779 s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 780 s_cbranch_scc1 L_SAVE_VGPR_LOOP //VGPR save is complete? 781 s_set_gpr_idx_off 782end 783 784L_SAVE_VGPR_END: 785 786 787 788 789 790 791 /* S_PGM_END_SAVED */ //FIXME graphics ONLY 792 if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_NORMAL_EXIT)) 793 s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff //pc[47:32] 794 s_add_u32 s_save_pc_lo, s_save_pc_lo, 4 //pc[31:0]+4 795 s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0 //carry bit over 796 s_rfe_b64 s_save_pc_lo //Return to the main shader program 797 else 798 end 799 800// Save Done timestamp 801if G8SR_DEBUG_TIMESTAMP 802 s_memrealtime s_g8sr_ts_save_d 803 // SGPR SR memory offset : size(VGPR) 804 get_vgpr_size_bytes(s_save_mem_offset) 805 s_add_u32 s_save_mem_offset, s_save_mem_offset, G8SR_DEBUG_TS_SAVE_D_OFFSET 806 s_waitcnt lgkmcnt(0) //FIXME, will cause xnack?? 807 // Need reset rsrc2?? 808 s_mov_b32 m0, s_save_mem_offset 809 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 810 s_buffer_store_dwordx2 s_g8sr_ts_save_d, s_save_buf_rsrc0, m0 glc:1 811end 812 813 814 s_branch L_END_PGM 815 816 817 818/**************************************************************************/ 819/* restore routine */ 820/**************************************************************************/ 821 822L_RESTORE: 823 /* Setup Resource Contants */ 824 if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL)) 825 //calculate wd_addr using absolute thread id 826 v_readlane_b32 s_restore_tmp, v9, 0 827 s_lshr_b32 s_restore_tmp, s_restore_tmp, 6 828 s_mul_i32 s_restore_tmp, s_restore_tmp, WAVE_SPACE 829 s_add_i32 s_restore_spi_init_lo, s_restore_tmp, WG_BASE_ADDR_LO 830 s_mov_b32 s_restore_spi_init_hi, WG_BASE_ADDR_HI 831 s_and_b32 s_restore_spi_init_hi, s_restore_spi_init_hi, CTX_RESTORE_CONTROL 832 else 833 end 834 835if G8SR_DEBUG_TIMESTAMP 836 s_memrealtime s_g8sr_ts_restore_s 837 s_waitcnt lgkmcnt(0) //FIXME, will cause xnack?? 838 // tma_lo/hi are sgpr 110, 111, which will not used for 112 SGPR allocated case... 839 s_mov_b32 s_restore_pc_lo, s_g8sr_ts_restore_s[0] 840 s_mov_b32 s_restore_pc_hi, s_g8sr_ts_restore_s[1] //backup ts to ttmp0/1, sicne exec will be finally restored.. 841end 842 843 844 845 s_mov_b32 s_restore_buf_rsrc0, s_restore_spi_init_lo //base_addr_lo 846 s_and_b32 s_restore_buf_rsrc1, s_restore_spi_init_hi, 0x0000FFFF //base_addr_hi 847 s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE 848 s_mov_b32 s_restore_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) 849 s_mov_b32 s_restore_buf_rsrc3, S_RESTORE_BUF_RSRC_WORD3_MISC 850 s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_ATC_MASK 851 s_lshr_b32 s_restore_tmp, s_restore_tmp, (S_RESTORE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT) //get ATC bit into position 852 s_or_b32 s_restore_buf_rsrc3, s_restore_buf_rsrc3, s_restore_tmp //or ATC 853 s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_MTYPE_MASK 854 s_lshr_b32 s_restore_tmp, s_restore_tmp, (S_RESTORE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT) //get MTYPE bits into position 855 s_or_b32 s_restore_buf_rsrc3, s_restore_buf_rsrc3, s_restore_tmp //or MTYPE 856 857 /* global mem offset */ 858// s_mov_b32 s_restore_mem_offset, 0x0 //mem offset initial value = 0 859 860 /* the first wave in the threadgroup */ 861 s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_FIRST_WAVE_MASK 862 s_cbranch_scc0 L_RESTORE_VGPR 863 864 /* restore LDS */ 865 ////////////////////////////// 866 L_RESTORE_LDS: 867 868 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on //be consistent with SAVE although can be moved ahead 869 s_mov_b32 exec_hi, 0xFFFFFFFF 870 871 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) //lds_size 872 s_and_b32 s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF //lds_size is zero? 873 s_cbranch_scc0 L_RESTORE_VGPR //no lds used? jump to L_RESTORE_VGPR 874 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 6 //LDS size in dwords = lds_size * 64dw 875 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 2 //LDS size in bytes 876 s_mov_b32 s_restore_buf_rsrc2, s_restore_alloc_size //NUM_RECORDS in bytes 877 878 // LDS at offset: size(VGPR)+SIZE(SGPR)+SIZE(HWREG) 879 // 880 get_vgpr_size_bytes(s_restore_mem_offset) 881 get_sgpr_size_bytes(s_restore_tmp) 882 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 883 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_hwreg_size_bytes() //FIXME, Check if offset overflow??? 884 885 886 if (SWIZZLE_EN) 887 s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 888 else 889 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 890 end 891 s_mov_b32 m0, 0x0 //lds_offset initial value = 0 892 893 L_RESTORE_LDS_LOOP: 894 if (SAVE_LDS) 895 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 // first 64DW 896 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 offset:256 // second 64DW 897 end 898 s_add_u32 m0, m0, 256*2 // 128 DW 899 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*2 //mem offset increased by 128DW 900 s_cmp_lt_u32 m0, s_restore_alloc_size //scc=(m0 < s_restore_alloc_size) ? 1 : 0 901 s_cbranch_scc1 L_RESTORE_LDS_LOOP //LDS restore is complete? 902 903 904 /* restore VGPRs */ 905 ////////////////////////////// 906 L_RESTORE_VGPR: 907 // VGPR SR memory offset : 0 908 s_mov_b32 s_restore_mem_offset, 0x0 909 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on //be consistent with SAVE although can be moved ahead 910 s_mov_b32 exec_hi, 0xFFFFFFFF 911 912 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) //vpgr_size 913 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 1 914 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value) 915 s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 8 //NUM_RECORDS in bytes (64 threads*4) 916 if (SWIZZLE_EN) 917 s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 918 else 919 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 920 end 921 922if G8SR_VGPR_SR_IN_DWX4 923 get_vgpr_size_bytes(s_restore_mem_offset) 924 s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 925 926 // the const stride for DWx4 is 4*4 bytes 927 s_and_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, 0x0000FFFF // reset const stride to 0 928 s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, G8SR_RESTORE_BUF_RSRC_WORD1_STRIDE_DWx4 // const stride to 4*4 bytes 929 930 s_mov_b32 m0, s_restore_alloc_size 931 s_set_gpr_idx_on m0, 0x8 // Note.. This will change m0 932 933L_RESTORE_VGPR_LOOP: 934 buffer_load_dwordx4 v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 935 s_waitcnt vmcnt(0) 936 s_sub_u32 m0, m0, 4 937 v_mov_b32 v0, v0 // v[0+m0] = v0 938 v_mov_b32 v1, v1 939 v_mov_b32 v2, v2 940 v_mov_b32 v3, v3 941 s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 942 s_cmp_eq_u32 m0, 0x8000 943 s_cbranch_scc0 L_RESTORE_VGPR_LOOP 944 s_set_gpr_idx_off 945 946 s_and_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, 0x0000FFFF // reset const stride to 0 947 s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE // const stride to 4*4 bytes 948 949else 950 // VGPR load using dw burst 951 s_mov_b32 s_restore_mem_offset_save, s_restore_mem_offset // restore start with v1, v0 will be the last 952 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 953 s_mov_b32 m0, 4 //VGPR initial index value = 1 954 s_set_gpr_idx_on m0, 0x8 //M0[7:0] = M0[7:0] and M0[15:12] = 0x8 955 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 0x8000 //add 0x8000 since we compare m0 against it later 956 957 L_RESTORE_VGPR_LOOP: 958 if(USE_MTBUF_INSTEAD_OF_MUBUF) 959 tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1 960 else 961 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 962 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256 963 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*2 964 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*3 965 end 966 s_waitcnt vmcnt(0) //ensure data ready 967 v_mov_b32 v0, v0 //v[0+m0] = v0 968 v_mov_b32 v1, v1 969 v_mov_b32 v2, v2 970 v_mov_b32 v3, v3 971 s_add_u32 m0, m0, 4 //next vgpr index 972 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 //every buffer_load_dword does 256 bytes 973 s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0 974 s_cbranch_scc1 L_RESTORE_VGPR_LOOP //VGPR restore (except v0) is complete? 975 s_set_gpr_idx_off 976 /* VGPR restore on v0 */ 977 if(USE_MTBUF_INSTEAD_OF_MUBUF) 978 tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1 979 else 980 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 981 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256 982 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*2 983 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*3 984 end 985 986end 987 988 /* restore SGPRs */ 989 ////////////////////////////// 990 991 // SGPR SR memory offset : size(VGPR) 992 get_vgpr_size_bytes(s_restore_mem_offset) 993 get_sgpr_size_bytes(s_restore_tmp) 994 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 995 s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 16*4 // restore SGPR from S[n] to S[0], by 16 sgprs group 996 // TODO, change RSRC word to rearrange memory layout for SGPRS 997 998 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size 999 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 1 1000 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 4 //Number of SGPRs = (sgpr_size + 1) * 16 (non-zero value) 1001 1002 if (SGPR_SAVE_USE_SQC) 1003 s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 2 //NUM_RECORDS in bytes 1004 else 1005 s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 8 //NUM_RECORDS in bytes (64 threads) 1006 end 1007 if (SWIZZLE_EN) 1008 s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 1009 else 1010 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 1011 end 1012 1013 s_mov_b32 m0, s_restore_alloc_size 1014 1015 L_RESTORE_SGPR_LOOP: 1016 read_16sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset) //PV: further performance improvement can be made 1017 s_waitcnt lgkmcnt(0) //ensure data ready 1018 1019 s_sub_u32 m0, m0, 16 // Restore from S[n] to S[0] 1020 s_nop 0 // hazard SALU M0=> S_MOVREL 1021 1022 s_movreld_b64 s0, s0 //s[0+m0] = s0 1023 s_movreld_b64 s2, s2 1024 s_movreld_b64 s4, s4 1025 s_movreld_b64 s6, s6 1026 s_movreld_b64 s8, s8 1027 s_movreld_b64 s10, s10 1028 s_movreld_b64 s12, s12 1029 s_movreld_b64 s14, s14 1030 1031 s_cmp_eq_u32 m0, 0 //scc = (m0 < s_restore_alloc_size) ? 1 : 0 1032 s_cbranch_scc0 L_RESTORE_SGPR_LOOP //SGPR restore (except s0) is complete? 1033 1034 /* restore HW registers */ 1035 ////////////////////////////// 1036 L_RESTORE_HWREG: 1037 1038 1039if G8SR_DEBUG_TIMESTAMP 1040 s_mov_b32 s_g8sr_ts_restore_s[0], s_restore_pc_lo 1041 s_mov_b32 s_g8sr_ts_restore_s[1], s_restore_pc_hi 1042end 1043 1044 // HWREG SR memory offset : size(VGPR)+size(SGPR) 1045 get_vgpr_size_bytes(s_restore_mem_offset) 1046 get_sgpr_size_bytes(s_restore_tmp) 1047 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 1048 1049 1050 s_mov_b32 s_restore_buf_rsrc2, 0x4 //NUM_RECORDS in bytes 1051 if (SWIZZLE_EN) 1052 s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 1053 else 1054 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 1055 end 1056 1057 read_hwreg_from_mem(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset) //M0 1058 read_hwreg_from_mem(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //PC 1059 read_hwreg_from_mem(s_restore_pc_hi, s_restore_buf_rsrc0, s_restore_mem_offset) 1060 read_hwreg_from_mem(s_restore_exec_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //EXEC 1061 read_hwreg_from_mem(s_restore_exec_hi, s_restore_buf_rsrc0, s_restore_mem_offset) 1062 read_hwreg_from_mem(s_restore_status, s_restore_buf_rsrc0, s_restore_mem_offset) //STATUS 1063 read_hwreg_from_mem(s_restore_trapsts, s_restore_buf_rsrc0, s_restore_mem_offset) //TRAPSTS 1064 read_hwreg_from_mem(xnack_mask_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //XNACK_MASK_LO 1065 read_hwreg_from_mem(xnack_mask_hi, s_restore_buf_rsrc0, s_restore_mem_offset) //XNACK_MASK_HI 1066 read_hwreg_from_mem(s_restore_mode, s_restore_buf_rsrc0, s_restore_mem_offset) //MODE 1067 1068 s_waitcnt lgkmcnt(0) //from now on, it is safe to restore STATUS and IB_STS 1069 1070 //for normal save & restore, the saved PC points to the next inst to execute, no adjustment needs to be made, otherwise: 1071 if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL)) 1072 s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 8 //pc[31:0]+8 //two back-to-back s_trap are used (first for save and second for restore) 1073 s_addc_u32 s_restore_pc_hi, s_restore_pc_hi, 0x0 //carry bit over 1074 end 1075 if ((EMU_RUN_HACK) && (EMU_RUN_HACK_RESTORE_NORMAL)) 1076 s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 4 //pc[31:0]+4 // save is hack through s_trap but restore is normal 1077 s_addc_u32 s_restore_pc_hi, s_restore_pc_hi, 0x0 //carry bit over 1078 end 1079 1080 s_mov_b32 m0, s_restore_m0 1081 s_mov_b32 exec_lo, s_restore_exec_lo 1082 s_mov_b32 exec_hi, s_restore_exec_hi 1083 1084 s_and_b32 s_restore_m0, SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK, s_restore_trapsts 1085 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE), s_restore_m0 1086 s_and_b32 s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK, s_restore_trapsts 1087 s_lshr_b32 s_restore_m0, s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT 1088 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE), s_restore_m0 1089 //s_setreg_b32 hwreg(HW_REG_TRAPSTS), s_restore_trapsts //don't overwrite SAVECTX bit as it may be set through external SAVECTX during restore 1090 s_setreg_b32 hwreg(HW_REG_MODE), s_restore_mode 1091 1092 // Restore trap temporaries 6-11, 13-15 initialized by SPI debug dispatch logic 1093 // ttmp SR memory offset : size(VGPR)+size(SGPR)+0x40 1094 get_vgpr_size_bytes(s_restore_ttmps_lo) 1095 get_sgpr_size_bytes(s_restore_ttmps_hi) 1096 s_add_u32 s_restore_ttmps_lo, s_restore_ttmps_lo, s_restore_ttmps_hi 1097 s_add_u32 s_restore_ttmps_lo, s_restore_ttmps_lo, s_restore_buf_rsrc0 1098 s_addc_u32 s_restore_ttmps_hi, s_restore_buf_rsrc1, 0x0 1099 s_and_b32 s_restore_ttmps_hi, s_restore_ttmps_hi, 0xFFFF 1100 s_load_dwordx2 [ttmp6, ttmp7], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x40 glc:1 1101 s_load_dwordx4 [ttmp8, ttmp9, ttmp10, ttmp11], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x48 glc:1 1102 s_load_dword ttmp13, [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x58 glc:1 1103 s_load_dwordx2 [ttmp14, ttmp15], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x5C glc:1 1104 s_waitcnt lgkmcnt(0) 1105 1106 //reuse s_restore_m0 as a temp register 1107 s_and_b32 s_restore_m0, s_restore_pc_hi, S_SAVE_PC_HI_RCNT_MASK 1108 s_lshr_b32 s_restore_m0, s_restore_m0, S_SAVE_PC_HI_RCNT_SHIFT 1109 s_lshl_b32 s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_RCNT_SHIFT 1110 s_mov_b32 s_restore_tmp, 0x0 //IB_STS is zero 1111 s_or_b32 s_restore_tmp, s_restore_tmp, s_restore_m0 1112 s_and_b32 s_restore_m0, s_restore_pc_hi, S_SAVE_PC_HI_FIRST_REPLAY_MASK 1113 s_lshr_b32 s_restore_m0, s_restore_m0, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT 1114 s_lshl_b32 s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT 1115 s_or_b32 s_restore_tmp, s_restore_tmp, s_restore_m0 1116 s_and_b32 s_restore_m0, s_restore_status, SQ_WAVE_STATUS_INST_ATC_MASK 1117 s_lshr_b32 s_restore_m0, s_restore_m0, SQ_WAVE_STATUS_INST_ATC_SHIFT 1118 s_setreg_b32 hwreg(HW_REG_IB_STS), s_restore_tmp 1119 1120 s_and_b32 s_restore_pc_hi, s_restore_pc_hi, 0x0000ffff //pc[47:32] //Do it here in order not to affect STATUS 1121 s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32 1122 s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32 1123 s_setreg_b32 hwreg(HW_REG_STATUS), s_restore_status // SCC is included, which is changed by previous salu 1124 1125 s_barrier //barrier to ensure the readiness of LDS before access attempts from any other wave in the same TG //FIXME not performance-optimal at this time 1126 1127if G8SR_DEBUG_TIMESTAMP 1128 s_memrealtime s_g8sr_ts_restore_d 1129 s_waitcnt lgkmcnt(0) 1130end 1131 1132// s_rfe_b64 s_restore_pc_lo //Return to the main shader program and resume execution 1133 s_rfe_restore_b64 s_restore_pc_lo, s_restore_m0 // s_restore_m0[0] is used to set STATUS.inst_atc 1134 1135 1136/**************************************************************************/ 1137/* the END */ 1138/**************************************************************************/ 1139L_END_PGM: 1140 s_endpgm 1141 1142end 1143 1144 1145/**************************************************************************/ 1146/* the helper functions */ 1147/**************************************************************************/ 1148 1149//Only for save hwreg to mem 1150function write_hwreg_to_mem(s, s_rsrc, s_mem_offset) 1151 s_mov_b32 exec_lo, m0 //assuming exec_lo is not needed anymore from this point on 1152 s_mov_b32 m0, s_mem_offset 1153 s_buffer_store_dword s, s_rsrc, m0 glc:1 1154 ack_sqc_store_workaround() 1155 s_add_u32 s_mem_offset, s_mem_offset, 4 1156 s_mov_b32 m0, exec_lo 1157end 1158 1159 1160// HWREG are saved before SGPRs, so all HWREG could be use. 1161function write_16sgpr_to_mem(s, s_rsrc, s_mem_offset) 1162 1163 s_buffer_store_dwordx4 s[0], s_rsrc, 0 glc:1 1164 ack_sqc_store_workaround() 1165 s_buffer_store_dwordx4 s[4], s_rsrc, 16 glc:1 1166 ack_sqc_store_workaround() 1167 s_buffer_store_dwordx4 s[8], s_rsrc, 32 glc:1 1168 ack_sqc_store_workaround() 1169 s_buffer_store_dwordx4 s[12], s_rsrc, 48 glc:1 1170 ack_sqc_store_workaround() 1171 s_add_u32 s_rsrc[0], s_rsrc[0], 4*16 1172 s_addc_u32 s_rsrc[1], s_rsrc[1], 0x0 // +scc 1173end 1174 1175 1176function read_hwreg_from_mem(s, s_rsrc, s_mem_offset) 1177 s_buffer_load_dword s, s_rsrc, s_mem_offset glc:1 1178 s_add_u32 s_mem_offset, s_mem_offset, 4 1179end 1180 1181function read_16sgpr_from_mem(s, s_rsrc, s_mem_offset) 1182 s_buffer_load_dwordx16 s, s_rsrc, s_mem_offset glc:1 1183 s_sub_u32 s_mem_offset, s_mem_offset, 4*16 1184end 1185 1186 1187 1188function get_lds_size_bytes(s_lds_size_byte) 1189 // SQ LDS granularity is 64DW, while PGM_RSRC2.lds_size is in granularity 128DW 1190 s_getreg_b32 s_lds_size_byte, hwreg(HW_REG_LDS_ALLOC, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) // lds_size 1191 s_lshl_b32 s_lds_size_byte, s_lds_size_byte, 8 //LDS size in dwords = lds_size * 64 *4Bytes // granularity 64DW 1192end 1193 1194function get_vgpr_size_bytes(s_vgpr_size_byte) 1195 s_getreg_b32 s_vgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) //vpgr_size 1196 s_add_u32 s_vgpr_size_byte, s_vgpr_size_byte, 1 1197 s_lshl_b32 s_vgpr_size_byte, s_vgpr_size_byte, (2+8) //Number of VGPRs = (vgpr_size + 1) * 4 * 64 * 4 (non-zero value) //FIXME for GFX, zero is possible 1198end 1199 1200function get_sgpr_size_bytes(s_sgpr_size_byte) 1201 s_getreg_b32 s_sgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size 1202 s_add_u32 s_sgpr_size_byte, s_sgpr_size_byte, 1 1203 s_lshl_b32 s_sgpr_size_byte, s_sgpr_size_byte, 6 //Number of SGPRs = (sgpr_size + 1) * 16 *4 (non-zero value) 1204end 1205 1206function get_hwreg_size_bytes 1207 return 128 //HWREG size 128 bytes 1208end 1209 1210function ack_sqc_store_workaround 1211 if ACK_SQC_STORE 1212 s_waitcnt lgkmcnt(0) 1213 end 1214end 1215