1/* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23/* To compile this assembly code: 24 * PROJECT=greenland ./sp3 cwsr_trap_handler_gfx9.asm -hex tmp.hex 25 */ 26 27/* HW (GFX9) source code for CWSR trap handler */ 28/* Version 18 + multiple trap handler */ 29 30// this performance-optimal version was originally from Seven Xu at SRDC 31 32// Revison #18 --... 33/* Rev History 34** #1. Branch from gc dv. //gfxip/gfx9/main/src/test/suites/block/cs/sr/cs_trap_handler.sp3#1,#50, #51, #52-53(Skip, Already Fixed by PV), #54-56(merged),#57-58(mergerd, skiped-already fixed by PV) 35** #4. SR Memory Layout: 36** 1. VGPR-SGPR-HWREG-{LDS} 37** 2. tba_hi.bits.26 - reconfigured as the first wave in tg bits, for defer Save LDS for a threadgroup.. performance concern.. 38** #5. Update: 1. Accurate g8sr_ts_save_d timestamp 39** #6. Update: 1. Fix s_barrier usage; 2. VGPR s/r using swizzle buffer?(NoNeed, already matched the swizzle pattern, more investigation) 40** #7. Update: 1. don't barrier if noLDS 41** #8. Branch: 1. Branch to ver#0, which is very similar to gc dv version 42** 2. Fix SQ issue by s_sleep 2 43** #9. Update: 1. Fix scc restore failed issue, restore wave_status at last 44** 2. optimize s_buffer save by burst 16sgprs... 45** #10. Update 1. Optimize restore sgpr by busrt 16 sgprs. 46** #11. Update 1. Add 2 more timestamp for debug version 47** #12. Update 1. Add VGPR SR using DWx4, some case improve and some case drop performance 48** #13. Integ 1. Always use MUBUF for PV trap shader... 49** #14. Update 1. s_buffer_store soft clause... 50** #15. Update 1. PERF - sclar write with glc:0/mtype0 to allow L2 combine. perf improvement a lot. 51** #16. Update 1. PRRF - UNROLL LDS_DMA got 2500cycle save in IP tree 52** #17. Update 1. FUNC - LDS_DMA has issues while ATC, replace with ds_read/buffer_store for save part[TODO restore part] 53** 2. PERF - Save LDS before save VGPR to cover LDS save long latency... 54** #18. Update 1. FUNC - Implicitly estore STATUS.VCCZ, which is not writable by s_setreg_b32 55** 2. FUNC - Handle non-CWSR traps 56*/ 57 58var G8SR_WDMEM_HWREG_OFFSET = 0 59var G8SR_WDMEM_SGPR_OFFSET = 128 // in bytes 60 61// Keep definition same as the app shader, These 2 time stamps are part of the app shader... Should before any Save and after restore. 62 63var G8SR_DEBUG_TIMESTAMP = 0 64var G8SR_DEBUG_TS_SAVE_D_OFFSET = 40*4 // ts_save_d timestamp offset relative to SGPR_SR_memory_offset 65var s_g8sr_ts_save_s = s[34:35] // save start 66var s_g8sr_ts_sq_save_msg = s[36:37] // The save shader send SAVEWAVE msg to spi 67var s_g8sr_ts_spi_wrexec = s[38:39] // the SPI write the sr address to SQ 68var s_g8sr_ts_save_d = s[40:41] // save end 69var s_g8sr_ts_restore_s = s[42:43] // restore start 70var s_g8sr_ts_restore_d = s[44:45] // restore end 71 72var G8SR_VGPR_SR_IN_DWX4 = 0 73var G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 = 0x00100000 // DWx4 stride is 4*4Bytes 74var G8SR_RESTORE_BUF_RSRC_WORD1_STRIDE_DWx4 = G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 75 76 77/*************************************************************************/ 78/* control on how to run the shader */ 79/*************************************************************************/ 80//any hack that needs to be made to run this code in EMU (either because various EMU code are not ready or no compute save & restore in EMU run) 81var EMU_RUN_HACK = 0 82var EMU_RUN_HACK_RESTORE_NORMAL = 0 83var EMU_RUN_HACK_SAVE_NORMAL_EXIT = 0 84var EMU_RUN_HACK_SAVE_SINGLE_WAVE = 0 85var EMU_RUN_HACK_SAVE_FIRST_TIME = 0 //for interrupted restore in which the first save is through EMU_RUN_HACK 86var SAVE_LDS = 1 87var WG_BASE_ADDR_LO = 0x9000a000 88var WG_BASE_ADDR_HI = 0x0 89var WAVE_SPACE = 0x5000 //memory size that each wave occupies in workgroup state mem 90var CTX_SAVE_CONTROL = 0x0 91var CTX_RESTORE_CONTROL = CTX_SAVE_CONTROL 92var SIM_RUN_HACK = 0 //any hack that needs to be made to run this code in SIM (either because various RTL code are not ready or no compute save & restore in RTL run) 93var SGPR_SAVE_USE_SQC = 1 //use SQC D$ to do the write 94var USE_MTBUF_INSTEAD_OF_MUBUF = 0 //because TC EMU currently asserts on 0 of // overload DFMT field to carry 4 more bits of stride for MUBUF opcodes 95var SWIZZLE_EN = 0 //whether we use swizzled buffer addressing 96var ACK_SQC_STORE = 1 //workaround for suspected SQC store bug causing incorrect stores under concurrency 97 98/**************************************************************************/ 99/* variables */ 100/**************************************************************************/ 101var SQ_WAVE_STATUS_INST_ATC_SHIFT = 23 102var SQ_WAVE_STATUS_INST_ATC_MASK = 0x00800000 103var SQ_WAVE_STATUS_SPI_PRIO_SHIFT = 1 104var SQ_WAVE_STATUS_SPI_PRIO_MASK = 0x00000006 105var SQ_WAVE_STATUS_HALT_MASK = 0x2000 106var SQ_WAVE_STATUS_PRE_SPI_PRIO_SHIFT = 0 107var SQ_WAVE_STATUS_PRE_SPI_PRIO_SIZE = 1 108var SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT = 3 109var SQ_WAVE_STATUS_POST_SPI_PRIO_SIZE = 29 110 111var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT = 12 112var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE = 9 113var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 8 114var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE = 6 115var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT = 24 116var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE = 3 //FIXME sq.blk still has 4 bits at this time while SQ programming guide has 3 bits 117 118var SQ_WAVE_TRAPSTS_SAVECTX_MASK = 0x400 119var SQ_WAVE_TRAPSTS_EXCE_MASK = 0x1FF // Exception mask 120var SQ_WAVE_TRAPSTS_SAVECTX_SHIFT = 10 121var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK = 0x100 122var SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT = 8 123var SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK = 0x3FF 124var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT = 0x0 125var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE = 10 126var SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK = 0xFFFFF800 127var SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT = 11 128var SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE = 21 129var SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK = 0x800 130 131var SQ_WAVE_IB_STS_RCNT_SHIFT = 16 //FIXME 132var SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT = 15 //FIXME 133var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK = 0x1F8000 134var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG = 0x00007FFF //FIXME 135 136var SQ_BUF_RSRC_WORD1_ATC_SHIFT = 24 137var SQ_BUF_RSRC_WORD3_MTYPE_SHIFT = 27 138 139var TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT = 26 // bits [31:26] unused by SPI debug data 140var TTMP11_SAVE_RCNT_FIRST_REPLAY_MASK = 0xFC000000 141 142/* Save */ 143var S_SAVE_BUF_RSRC_WORD1_STRIDE = 0x00040000 //stride is 4 bytes 144var S_SAVE_BUF_RSRC_WORD3_MISC = 0x00807FAC //SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14] when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE 145 146var S_SAVE_SPI_INIT_ATC_MASK = 0x08000000 //bit[27]: ATC bit 147var S_SAVE_SPI_INIT_ATC_SHIFT = 27 148var S_SAVE_SPI_INIT_MTYPE_MASK = 0x70000000 //bit[30:28]: Mtype 149var S_SAVE_SPI_INIT_MTYPE_SHIFT = 28 150var S_SAVE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG 151var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT = 26 152 153var S_SAVE_PC_HI_RCNT_SHIFT = 27 //FIXME check with Brian to ensure all fields other than PC[47:0] can be used 154var S_SAVE_PC_HI_RCNT_MASK = 0xF8000000 //FIXME 155var S_SAVE_PC_HI_FIRST_REPLAY_SHIFT = 26 //FIXME 156var S_SAVE_PC_HI_FIRST_REPLAY_MASK = 0x04000000 //FIXME 157 158var s_save_spi_init_lo = exec_lo 159var s_save_spi_init_hi = exec_hi 160 161var s_save_pc_lo = ttmp0 //{TTMP1, TTMP0} = {3'h0,pc_rewind[3:0], HT[0],trapID[7:0], PC[47:0]} 162var s_save_pc_hi = ttmp1 163var s_save_exec_lo = ttmp2 164var s_save_exec_hi = ttmp3 165var s_save_tmp = ttmp14 166var s_save_trapsts = ttmp15 //not really used until the end of the SAVE routine 167var s_save_xnack_mask_lo = ttmp6 168var s_save_xnack_mask_hi = ttmp7 169var s_save_buf_rsrc0 = ttmp8 170var s_save_buf_rsrc1 = ttmp9 171var s_save_buf_rsrc2 = ttmp10 172var s_save_buf_rsrc3 = ttmp11 173var s_save_status = ttmp12 174var s_save_mem_offset = ttmp4 175var s_save_alloc_size = s_save_trapsts //conflict 176var s_save_m0 = ttmp5 177var s_save_ttmps_lo = s_save_tmp //no conflict 178var s_save_ttmps_hi = s_save_trapsts //no conflict 179 180/* Restore */ 181var S_RESTORE_BUF_RSRC_WORD1_STRIDE = S_SAVE_BUF_RSRC_WORD1_STRIDE 182var S_RESTORE_BUF_RSRC_WORD3_MISC = S_SAVE_BUF_RSRC_WORD3_MISC 183 184var S_RESTORE_SPI_INIT_ATC_MASK = 0x08000000 //bit[27]: ATC bit 185var S_RESTORE_SPI_INIT_ATC_SHIFT = 27 186var S_RESTORE_SPI_INIT_MTYPE_MASK = 0x70000000 //bit[30:28]: Mtype 187var S_RESTORE_SPI_INIT_MTYPE_SHIFT = 28 188var S_RESTORE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG 189var S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT = 26 190 191var S_RESTORE_PC_HI_RCNT_SHIFT = S_SAVE_PC_HI_RCNT_SHIFT 192var S_RESTORE_PC_HI_RCNT_MASK = S_SAVE_PC_HI_RCNT_MASK 193var S_RESTORE_PC_HI_FIRST_REPLAY_SHIFT = S_SAVE_PC_HI_FIRST_REPLAY_SHIFT 194var S_RESTORE_PC_HI_FIRST_REPLAY_MASK = S_SAVE_PC_HI_FIRST_REPLAY_MASK 195 196var s_restore_spi_init_lo = exec_lo 197var s_restore_spi_init_hi = exec_hi 198 199var s_restore_mem_offset = ttmp12 200var s_restore_accvgpr_offset = ttmp13 201var s_restore_alloc_size = ttmp3 202var s_restore_tmp = ttmp2 203var s_restore_mem_offset_save = s_restore_tmp //no conflict 204var s_restore_accvgpr_offset_save = ttmp7 205 206var s_restore_m0 = s_restore_alloc_size //no conflict 207 208var s_restore_mode = s_restore_accvgpr_offset_save 209 210var s_restore_pc_lo = ttmp0 211var s_restore_pc_hi = ttmp1 212var s_restore_exec_lo = ttmp4 213var s_restore_exec_hi = ttmp5 214var s_restore_status = ttmp14 215var s_restore_trapsts = ttmp15 216var s_restore_xnack_mask_lo = xnack_mask_lo 217var s_restore_xnack_mask_hi = xnack_mask_hi 218var s_restore_buf_rsrc0 = ttmp8 219var s_restore_buf_rsrc1 = ttmp9 220var s_restore_buf_rsrc2 = ttmp10 221var s_restore_buf_rsrc3 = ttmp11 222var s_restore_ttmps_lo = s_restore_tmp //no conflict 223var s_restore_ttmps_hi = s_restore_alloc_size //no conflict 224 225/**************************************************************************/ 226/* trap handler entry points */ 227/**************************************************************************/ 228/* Shader Main*/ 229 230shader main 231 asic(DEFAULT) 232 type(CS) 233 234 235 if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL)) //hack to use trap_id for determining save/restore 236 //FIXME VCCZ un-init assertion s_getreg_b32 s_save_status, hwreg(HW_REG_STATUS) //save STATUS since we will change SCC 237 s_and_b32 s_save_tmp, s_save_pc_hi, 0xffff0000 //change SCC 238 s_cmp_eq_u32 s_save_tmp, 0x007e0000 //Save: trap_id = 0x7e. Restore: trap_id = 0x7f. 239 s_cbranch_scc0 L_JUMP_TO_RESTORE //do not need to recover STATUS here since we are going to RESTORE 240 //FIXME s_setreg_b32 hwreg(HW_REG_STATUS), s_save_status //need to recover STATUS since we are going to SAVE 241 s_branch L_SKIP_RESTORE //NOT restore, SAVE actually 242 else 243 s_branch L_SKIP_RESTORE //NOT restore. might be a regular trap or save 244 end 245 246L_JUMP_TO_RESTORE: 247 s_branch L_RESTORE //restore 248 249L_SKIP_RESTORE: 250 251 s_getreg_b32 s_save_status, hwreg(HW_REG_STATUS) //save STATUS since we will change SCC 252 s_andn2_b32 s_save_status, s_save_status, SQ_WAVE_STATUS_SPI_PRIO_MASK //check whether this is for save 253 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 254 s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK //check whether this is for save 255 s_cbranch_scc1 L_SAVE //this is the operation for save 256 257 // ********* Handle non-CWSR traps ******************* 258if (!EMU_RUN_HACK) 259 // Illegal instruction is a non-maskable exception which blocks context save. 260 // Halt the wavefront and return from the trap. 261 s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK 262 s_cbranch_scc1 L_HALT_WAVE 263 264 // If STATUS.MEM_VIOL is asserted then we cannot fetch from the TMA. 265 // Instead, halt the wavefront and return from the trap. 266 s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_MEM_VIOL_MASK 267 s_cbranch_scc0 L_FETCH_2ND_TRAP 268 269L_HALT_WAVE: 270 // If STATUS.HALT is set then this fault must come from SQC instruction fetch. 271 // We cannot prevent further faults. Spin wait until context saved. 272 s_and_b32 ttmp2, s_save_status, SQ_WAVE_STATUS_HALT_MASK 273 s_cbranch_scc0 L_NOT_ALREADY_HALTED 274 275L_WAIT_CTX_SAVE: 276 s_sleep 0x10 277 s_getreg_b32 ttmp2, hwreg(HW_REG_TRAPSTS) 278 s_and_b32 ttmp2, ttmp2, SQ_WAVE_TRAPSTS_SAVECTX_MASK 279 s_cbranch_scc0 L_WAIT_CTX_SAVE 280 281L_NOT_ALREADY_HALTED: 282 s_or_b32 s_save_status, s_save_status, SQ_WAVE_STATUS_HALT_MASK 283 284 // If the PC points to S_ENDPGM then context save will fail if STATUS.HALT is set. 285 // Rewind the PC to prevent this from occurring. The debugger compensates for this. 286 s_sub_u32 ttmp0, ttmp0, 0x8 287 s_subb_u32 ttmp1, ttmp1, 0x0 288 289L_FETCH_2ND_TRAP: 290 // Preserve and clear scalar XNACK state before issuing scalar reads. 291 // Save IB_STS.FIRST_REPLAY[15] and IB_STS.RCNT[20:16] into unused space ttmp11[31:26]. 292 s_getreg_b32 ttmp2, hwreg(HW_REG_IB_STS) 293 s_and_b32 ttmp3, ttmp2, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK 294 s_lshl_b32 ttmp3, ttmp3, (TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT - SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT) 295 s_andn2_b32 ttmp11, ttmp11, TTMP11_SAVE_RCNT_FIRST_REPLAY_MASK 296 s_or_b32 ttmp11, ttmp11, ttmp3 297 298 s_andn2_b32 ttmp2, ttmp2, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK 299 s_setreg_b32 hwreg(HW_REG_IB_STS), ttmp2 300 301 // Read second-level TBA/TMA from first-level TMA and jump if available. 302 // ttmp[2:5] and ttmp12 can be used (others hold SPI-initialized debug data) 303 // ttmp12 holds SQ_WAVE_STATUS 304 s_getreg_b32 ttmp14, hwreg(HW_REG_SQ_SHADER_TMA_LO) 305 s_getreg_b32 ttmp15, hwreg(HW_REG_SQ_SHADER_TMA_HI) 306 s_lshl_b64 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 307 s_load_dwordx2 [ttmp2, ttmp3], [ttmp14, ttmp15], 0x0 glc:1 // second-level TBA 308 s_waitcnt lgkmcnt(0) 309 s_load_dwordx2 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 glc:1 // second-level TMA 310 s_waitcnt lgkmcnt(0) 311 s_and_b64 [ttmp2, ttmp3], [ttmp2, ttmp3], [ttmp2, ttmp3] 312 s_cbranch_scc0 L_NO_NEXT_TRAP // second-level trap handler not been set 313 s_setpc_b64 [ttmp2, ttmp3] // jump to second-level trap handler 314 315L_NO_NEXT_TRAP: 316 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 317 s_and_b32 s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_EXCE_MASK // Check whether it is an exception 318 s_cbranch_scc1 L_EXCP_CASE // Exception, jump back to the shader program directly. 319 s_add_u32 ttmp0, ttmp0, 4 // S_TRAP case, add 4 to ttmp0 320 s_addc_u32 ttmp1, ttmp1, 0 321L_EXCP_CASE: 322 s_and_b32 ttmp1, ttmp1, 0xFFFF 323 324 // Restore SQ_WAVE_IB_STS. 325 s_lshr_b32 ttmp2, ttmp11, (TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT - SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT) 326 s_and_b32 ttmp2, ttmp2, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK 327 s_setreg_b32 hwreg(HW_REG_IB_STS), ttmp2 328 329 // Restore SQ_WAVE_STATUS. 330 s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32 331 s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32 332 set_status_without_spi_prio(s_save_status, ttmp2) 333 334 s_rfe_b64 [ttmp0, ttmp1] 335end 336 // ********* End handling of non-CWSR traps ******************* 337 338/**************************************************************************/ 339/* save routine */ 340/**************************************************************************/ 341 342L_SAVE: 343 344if G8SR_DEBUG_TIMESTAMP 345 s_memrealtime s_g8sr_ts_save_s 346 s_waitcnt lgkmcnt(0) //FIXME, will cause xnack?? 347end 348 349 s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff //pc[47:32] 350 351 s_mov_b32 s_save_tmp, 0 //clear saveCtx bit 352 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_SAVECTX_SHIFT, 1), s_save_tmp //clear saveCtx bit 353 354 s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_RCNT_SHIFT, SQ_WAVE_IB_STS_RCNT_SIZE) //save RCNT 355 s_lshl_b32 s_save_tmp, s_save_tmp, S_SAVE_PC_HI_RCNT_SHIFT 356 s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp 357 s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT, SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE) //save FIRST_REPLAY 358 s_lshl_b32 s_save_tmp, s_save_tmp, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT 359 s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp 360 s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS) //clear RCNT and FIRST_REPLAY in IB_STS 361 s_and_b32 s_save_tmp, s_save_tmp, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG 362 363 s_setreg_b32 hwreg(HW_REG_IB_STS), s_save_tmp 364 365 /* inform SPI the readiness and wait for SPI's go signal */ 366 s_mov_b32 s_save_exec_lo, exec_lo //save EXEC and use EXEC for the go signal from SPI 367 s_mov_b32 s_save_exec_hi, exec_hi 368 s_mov_b64 exec, 0x0 //clear EXEC to get ready to receive 369 370if G8SR_DEBUG_TIMESTAMP 371 s_memrealtime s_g8sr_ts_sq_save_msg 372 s_waitcnt lgkmcnt(0) 373end 374 375 if (EMU_RUN_HACK) 376 377 else 378 s_sendmsg sendmsg(MSG_SAVEWAVE) //send SPI a message and wait for SPI's write to EXEC 379 end 380 381 // Set SPI_PRIO=2 to avoid starving instruction fetch in the waves we're waiting for. 382 s_or_b32 s_save_tmp, s_save_status, (2 << SQ_WAVE_STATUS_SPI_PRIO_SHIFT) 383 s_setreg_b32 hwreg(HW_REG_STATUS), s_save_tmp 384 385 L_SLEEP: 386 s_sleep 0x2 // sleep 1 (64clk) is not enough for 8 waves per SIMD, which will cause SQ hang, since the 7,8th wave could not get arbit to exec inst, while other waves are stuck into the sleep-loop and waiting for wrexec!=0 387 388 if (EMU_RUN_HACK) 389 390 else 391 s_cbranch_execz L_SLEEP 392 end 393 394if G8SR_DEBUG_TIMESTAMP 395 s_memrealtime s_g8sr_ts_spi_wrexec 396 s_waitcnt lgkmcnt(0) 397end 398 399 if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_SINGLE_WAVE)) 400 //calculate wd_addr using absolute thread id 401 v_readlane_b32 s_save_tmp, v9, 0 402 s_lshr_b32 s_save_tmp, s_save_tmp, 6 403 s_mul_i32 s_save_tmp, s_save_tmp, WAVE_SPACE 404 s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO 405 s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI 406 s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL 407 else 408 end 409 if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_SINGLE_WAVE)) 410 s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO 411 s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI 412 s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL 413 else 414 end 415 416 // Save trap temporaries 4-11, 13 initialized by SPI debug dispatch logic 417 // ttmp SR memory offset : size(VGPR)+size(SGPR)+0x40 418 get_vgpr_size_bytes(s_save_ttmps_lo) 419 get_sgpr_size_bytes(s_save_ttmps_hi) 420 s_add_u32 s_save_ttmps_lo, s_save_ttmps_lo, s_save_ttmps_hi 421 s_add_u32 s_save_ttmps_lo, s_save_ttmps_lo, s_save_spi_init_lo 422 s_addc_u32 s_save_ttmps_hi, s_save_spi_init_hi, 0x0 423 s_and_b32 s_save_ttmps_hi, s_save_ttmps_hi, 0xFFFF 424 s_store_dwordx4 [ttmp4, ttmp5, ttmp6, ttmp7], [s_save_ttmps_lo, s_save_ttmps_hi], 0x50 glc:1 425 ack_sqc_store_workaround() 426 s_store_dwordx4 [ttmp8, ttmp9, ttmp10, ttmp11], [s_save_ttmps_lo, s_save_ttmps_hi], 0x60 glc:1 427 ack_sqc_store_workaround() 428 s_store_dword ttmp13, [s_save_ttmps_lo, s_save_ttmps_hi], 0x74 glc:1 429 ack_sqc_store_workaround() 430 431 /* setup Resource Contants */ 432 s_mov_b32 s_save_buf_rsrc0, s_save_spi_init_lo //base_addr_lo 433 s_and_b32 s_save_buf_rsrc1, s_save_spi_init_hi, 0x0000FFFF //base_addr_hi 434 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE 435 s_mov_b32 s_save_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) although not neccessarily inited 436 s_mov_b32 s_save_buf_rsrc3, S_SAVE_BUF_RSRC_WORD3_MISC 437 s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_ATC_MASK 438 s_lshr_b32 s_save_tmp, s_save_tmp, (S_SAVE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT) //get ATC bit into position 439 s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, s_save_tmp //or ATC 440 s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_MTYPE_MASK 441 s_lshr_b32 s_save_tmp, s_save_tmp, (S_SAVE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT) //get MTYPE bits into position 442 s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, s_save_tmp //or MTYPE 443 444 //FIXME right now s_save_m0/s_save_mem_offset use tma_lo/tma_hi (might need to save them before using them?) 445 s_mov_b32 s_save_m0, m0 //save M0 446 447 /* global mem offset */ 448 s_mov_b32 s_save_mem_offset, 0x0 //mem offset initial value = 0 449 450 451 452 453 /* save HW registers */ 454 ////////////////////////////// 455 456 L_SAVE_HWREG: 457 // HWREG SR memory offset : size(VGPR)+size(SGPR) 458 get_vgpr_size_bytes(s_save_mem_offset) 459 get_sgpr_size_bytes(s_save_tmp) 460 s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp 461 462 463 s_mov_b32 s_save_buf_rsrc2, 0x4 //NUM_RECORDS in bytes 464 if (SWIZZLE_EN) 465 s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 466 else 467 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 468 end 469 470 471 write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) //M0 472 473 if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_FIRST_TIME)) 474 s_add_u32 s_save_pc_lo, s_save_pc_lo, 4 //pc[31:0]+4 475 s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0 //carry bit over 476 end 477 478 write_hwreg_to_mem(s_save_pc_lo, s_save_buf_rsrc0, s_save_mem_offset) //PC 479 write_hwreg_to_mem(s_save_pc_hi, s_save_buf_rsrc0, s_save_mem_offset) 480 write_hwreg_to_mem(s_save_exec_lo, s_save_buf_rsrc0, s_save_mem_offset) //EXEC 481 write_hwreg_to_mem(s_save_exec_hi, s_save_buf_rsrc0, s_save_mem_offset) 482 write_hwreg_to_mem(s_save_status, s_save_buf_rsrc0, s_save_mem_offset) //STATUS 483 484 //s_save_trapsts conflicts with s_save_alloc_size 485 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 486 write_hwreg_to_mem(s_save_trapsts, s_save_buf_rsrc0, s_save_mem_offset) //TRAPSTS 487 488 write_hwreg_to_mem(xnack_mask_lo, s_save_buf_rsrc0, s_save_mem_offset) //XNACK_MASK_LO 489 write_hwreg_to_mem(xnack_mask_hi, s_save_buf_rsrc0, s_save_mem_offset) //XNACK_MASK_HI 490 491 //use s_save_tmp would introduce conflict here between s_save_tmp and s_save_buf_rsrc2 492 s_getreg_b32 s_save_m0, hwreg(HW_REG_MODE) //MODE 493 write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) 494 495 496 497 /* the first wave in the threadgroup */ 498 s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK // extract fisrt wave bit 499 s_mov_b32 s_save_exec_hi, 0x0 500 s_or_b32 s_save_exec_hi, s_save_tmp, s_save_exec_hi // save first wave bit to s_save_exec_hi.bits[26] 501 502 503 /* save SGPRs */ 504 // Save SGPR before LDS save, then the s0 to s4 can be used during LDS save... 505 ////////////////////////////// 506 507 // SGPR SR memory offset : size(VGPR) 508 get_vgpr_size_bytes(s_save_mem_offset) 509 // TODO, change RSRC word to rearrange memory layout for SGPRS 510 511 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size 512 s_add_u32 s_save_alloc_size, s_save_alloc_size, 1 513 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 4 //Number of SGPRs = (sgpr_size + 1) * 16 (non-zero value) 514 515 if (SGPR_SAVE_USE_SQC) 516 s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 2 //NUM_RECORDS in bytes 517 else 518 s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 8 //NUM_RECORDS in bytes (64 threads) 519 end 520 521 if (SWIZZLE_EN) 522 s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 523 else 524 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 525 end 526 527 528 // backup s_save_buf_rsrc0,1 to s_save_pc_lo/hi, since write_16sgpr_to_mem function will change the rsrc0 529 //s_mov_b64 s_save_pc_lo, s_save_buf_rsrc0 530 s_mov_b64 s_save_xnack_mask_lo, s_save_buf_rsrc0 531 s_add_u32 s_save_buf_rsrc0, s_save_buf_rsrc0, s_save_mem_offset 532 s_addc_u32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0 533 534 s_mov_b32 m0, 0x0 //SGPR initial index value =0 535 s_nop 0x0 //Manually inserted wait states 536 L_SAVE_SGPR_LOOP: 537 // SGPR is allocated in 16 SGPR granularity 538 s_movrels_b64 s0, s0 //s0 = s[0+m0], s1 = s[1+m0] 539 s_movrels_b64 s2, s2 //s2 = s[2+m0], s3 = s[3+m0] 540 s_movrels_b64 s4, s4 //s4 = s[4+m0], s5 = s[5+m0] 541 s_movrels_b64 s6, s6 //s6 = s[6+m0], s7 = s[7+m0] 542 s_movrels_b64 s8, s8 //s8 = s[8+m0], s9 = s[9+m0] 543 s_movrels_b64 s10, s10 //s10 = s[10+m0], s11 = s[11+m0] 544 s_movrels_b64 s12, s12 //s12 = s[12+m0], s13 = s[13+m0] 545 s_movrels_b64 s14, s14 //s14 = s[14+m0], s15 = s[15+m0] 546 547 write_16sgpr_to_mem(s0, s_save_buf_rsrc0, s_save_mem_offset) //PV: the best performance should be using s_buffer_store_dwordx4 548 s_add_u32 m0, m0, 16 //next sgpr index 549 s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 550 s_cbranch_scc1 L_SAVE_SGPR_LOOP //SGPR save is complete? 551 // restore s_save_buf_rsrc0,1 552 //s_mov_b64 s_save_buf_rsrc0, s_save_pc_lo 553 s_mov_b64 s_save_buf_rsrc0, s_save_xnack_mask_lo 554 555 556 557 558 /* save first 4 VGPR, then LDS save could use */ 559 // each wave will alloc 4 vgprs at least... 560 ///////////////////////////////////////////////////////////////////////////////////// 561 562 s_mov_b32 s_save_mem_offset, 0 563 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 564 s_mov_b32 exec_hi, 0xFFFFFFFF 565 s_mov_b32 xnack_mask_lo, 0x0 566 s_mov_b32 xnack_mask_hi, 0x0 567 568 if (SWIZZLE_EN) 569 s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 570 else 571 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 572 end 573 574 575 // VGPR Allocated in 4-GPR granularity 576 577if G8SR_VGPR_SR_IN_DWX4 578 // the const stride for DWx4 is 4*4 bytes 579 s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 580 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 // const stride to 4*4 bytes 581 582 buffer_store_dwordx4 v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 583 584 s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 585 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE // reset const stride to 4 bytes 586else 587 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 588 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256 589 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2 590 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3 591end 592 593 594 595 /* save LDS */ 596 ////////////////////////////// 597 598 L_SAVE_LDS: 599 600 // Change EXEC to all threads... 601 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 602 s_mov_b32 exec_hi, 0xFFFFFFFF 603 604 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) //lds_size 605 s_and_b32 s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF //lds_size is zero? 606 s_cbranch_scc0 L_SAVE_LDS_DONE //no lds used? jump to L_SAVE_DONE 607 608 s_barrier //LDS is used? wait for other waves in the same TG 609 s_and_b32 s_save_tmp, s_save_exec_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK //exec is still used here 610 s_cbranch_scc0 L_SAVE_LDS_DONE 611 612 // first wave do LDS save; 613 614 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 6 //LDS size in dwords = lds_size * 64dw 615 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 2 //LDS size in bytes 616 s_mov_b32 s_save_buf_rsrc2, s_save_alloc_size //NUM_RECORDS in bytes 617 618 // LDS at offset: size(VGPR)+SIZE(SGPR)+SIZE(HWREG) 619 // 620 get_vgpr_size_bytes(s_save_mem_offset) 621 get_sgpr_size_bytes(s_save_tmp) 622 s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp 623 s_add_u32 s_save_mem_offset, s_save_mem_offset, get_hwreg_size_bytes() 624 625 626 if (SWIZZLE_EN) 627 s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 628 else 629 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 630 end 631 632 s_mov_b32 m0, 0x0 //lds_offset initial value = 0 633 634 635var LDS_DMA_ENABLE = 0 636var UNROLL = 0 637if UNROLL==0 && LDS_DMA_ENABLE==1 638 s_mov_b32 s3, 256*2 639 s_nop 0 640 s_nop 0 641 s_nop 0 642 L_SAVE_LDS_LOOP: 643 //TODO: looks the 2 buffer_store/load clause for s/r will hurt performance.??? 644 if (SAVE_LDS) //SPI always alloc LDS space in 128DW granularity 645 buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 // first 64DW 646 buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:256 // second 64DW 647 end 648 649 s_add_u32 m0, m0, s3 //every buffer_store_lds does 256 bytes 650 s_add_u32 s_save_mem_offset, s_save_mem_offset, s3 //mem offset increased by 256 bytes 651 s_cmp_lt_u32 m0, s_save_alloc_size //scc=(m0 < s_save_alloc_size) ? 1 : 0 652 s_cbranch_scc1 L_SAVE_LDS_LOOP //LDS save is complete? 653 654elsif LDS_DMA_ENABLE==1 && UNROLL==1 // UNROOL , has ichace miss 655 // store from higest LDS address to lowest 656 s_mov_b32 s3, 256*2 657 s_sub_u32 m0, s_save_alloc_size, s3 658 s_add_u32 s_save_mem_offset, s_save_mem_offset, m0 659 s_lshr_b32 s_save_alloc_size, s_save_alloc_size, 9 // how many 128 trunks... 660 s_sub_u32 s_save_alloc_size, 128, s_save_alloc_size // store from higheset addr to lowest 661 s_mul_i32 s_save_alloc_size, s_save_alloc_size, 6*4 // PC offset increment, each LDS save block cost 6*4 Bytes instruction 662 s_add_u32 s_save_alloc_size, s_save_alloc_size, 3*4 //2is the below 2 inst...//s_addc and s_setpc 663 s_nop 0 664 s_nop 0 665 s_nop 0 //pad 3 dw to let LDS_DMA align with 64Bytes 666 s_getpc_b64 s[0:1] // reuse s[0:1], since s[0:1] already saved 667 s_add_u32 s0, s0,s_save_alloc_size 668 s_addc_u32 s1, s1, 0 669 s_setpc_b64 s[0:1] 670 671 672 for var i =0; i< 128; i++ 673 // be careful to make here a 64Byte aligned address, which could improve performance... 674 buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:0 // first 64DW 675 buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:256 // second 64DW 676 677 if i!=127 678 s_sub_u32 m0, m0, s3 // use a sgpr to shrink 2DW-inst to 1DW inst to improve performance , i.e. pack more LDS_DMA inst to one Cacheline 679 s_sub_u32 s_save_mem_offset, s_save_mem_offset, s3 680 end 681 end 682 683else // BUFFER_STORE 684 v_mbcnt_lo_u32_b32 v2, 0xffffffff, 0x0 685 v_mbcnt_hi_u32_b32 v3, 0xffffffff, v2 // tid 686 v_mul_i32_i24 v2, v3, 8 // tid*8 687 v_mov_b32 v3, 256*2 688 s_mov_b32 m0, 0x10000 689 s_mov_b32 s0, s_save_buf_rsrc3 690 s_and_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, 0xFF7FFFFF // disable add_tid 691 s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, 0x58000 //DFMT 692 693L_SAVE_LDS_LOOP_VECTOR: 694 ds_read_b64 v[0:1], v2 //x =LDS[a], byte address 695 s_waitcnt lgkmcnt(0) 696 buffer_store_dwordx2 v[0:1], v2, s_save_buf_rsrc0, s_save_mem_offset offen:1 glc:1 slc:1 697// s_waitcnt vmcnt(0) 698// v_add_u32 v2, vcc[0:1], v2, v3 699 v_add_u32 v2, v2, v3 700 v_cmp_lt_u32 vcc[0:1], v2, s_save_alloc_size 701 s_cbranch_vccnz L_SAVE_LDS_LOOP_VECTOR 702 703 // restore rsrc3 704 s_mov_b32 s_save_buf_rsrc3, s0 705 706end 707 708L_SAVE_LDS_DONE: 709 710 711 /* save VGPRs - set the Rest VGPRs */ 712 ////////////////////////////////////////////////////////////////////////////////////// 713 L_SAVE_VGPR: 714 // VGPR SR memory offset: 0 715 // TODO rearrange the RSRC words to use swizzle for VGPR save... 716 717 s_mov_b32 s_save_mem_offset, (0+256*4) // for the rest VGPRs 718 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 719 s_mov_b32 exec_hi, 0xFFFFFFFF 720 721 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) //vpgr_size 722 s_add_u32 s_save_alloc_size, s_save_alloc_size, 1 723 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value) //FIXME for GFX, zero is possible 724 s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 8 //NUM_RECORDS in bytes (64 threads*4) 725 if (SWIZZLE_EN) 726 s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 727 else 728 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 729 end 730 731 732 // VGPR Allocated in 4-GPR granularity 733 734if G8SR_VGPR_SR_IN_DWX4 735 // the const stride for DWx4 is 4*4 bytes 736 s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 737 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 // const stride to 4*4 bytes 738 739 s_mov_b32 m0, 4 // skip first 4 VGPRs 740 s_cmp_lt_u32 m0, s_save_alloc_size 741 s_cbranch_scc0 L_SAVE_VGPR_LOOP_END // no more vgprs 742 743 s_set_gpr_idx_on m0, 0x1 // This will change M0 744 s_add_u32 s_save_alloc_size, s_save_alloc_size, 0x1000 // because above inst change m0 745L_SAVE_VGPR_LOOP: 746 v_mov_b32 v0, v0 // v0 = v[0+m0] 747 v_mov_b32 v1, v1 748 v_mov_b32 v2, v2 749 v_mov_b32 v3, v3 750 751 752 buffer_store_dwordx4 v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 753 s_add_u32 m0, m0, 4 754 s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 755 s_cmp_lt_u32 m0, s_save_alloc_size 756 s_cbranch_scc1 L_SAVE_VGPR_LOOP //VGPR save is complete? 757 s_set_gpr_idx_off 758L_SAVE_VGPR_LOOP_END: 759 760 s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 761 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE // reset const stride to 4 bytes 762else 763 // VGPR store using dw burst 764 s_mov_b32 m0, 0x4 //VGPR initial index value =0 765 s_cmp_lt_u32 m0, s_save_alloc_size 766 s_cbranch_scc0 L_SAVE_VGPR_END 767 768 769 s_set_gpr_idx_on m0, 0x1 //M0[7:0] = M0[7:0] and M0[15:12] = 0x1 770 s_add_u32 s_save_alloc_size, s_save_alloc_size, 0x1000 //add 0x1000 since we compare m0 against it later 771 772 L_SAVE_VGPR_LOOP: 773 v_mov_b32 v0, v0 //v0 = v[0+m0] 774 v_mov_b32 v1, v1 //v0 = v[0+m0] 775 v_mov_b32 v2, v2 //v0 = v[0+m0] 776 v_mov_b32 v3, v3 //v0 = v[0+m0] 777 778 if(USE_MTBUF_INSTEAD_OF_MUBUF) 779 tbuffer_store_format_x v0, v0, s_save_buf_rsrc0, s_save_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1 780 else 781 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 782 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256 783 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2 784 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3 785 end 786 787 s_add_u32 m0, m0, 4 //next vgpr index 788 s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 //every buffer_store_dword does 256 bytes 789 s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 790 s_cbranch_scc1 L_SAVE_VGPR_LOOP //VGPR save is complete? 791 s_set_gpr_idx_off 792end 793 794L_SAVE_VGPR_END: 795 796if ASIC_TARGET_ARCTURUS 797 // Save ACC VGPRs 798 s_mov_b32 m0, 0x0 //VGPR initial index value =0 799 s_set_gpr_idx_on m0, 0x1 //M0[7:0] = M0[7:0] and M0[15:12] = 0x1 800 801if SAVE_AFTER_XNACK_ERROR 802 check_if_tcp_store_ok() 803 s_cbranch_scc1 L_SAVE_ACCVGPR_LOOP 804 805L_SAVE_ACCVGPR_LOOP_SQC: 806 for var vgpr = 0; vgpr < 4; ++ vgpr 807 v_accvgpr_read v[vgpr], acc[vgpr] // v[N] = acc[N+m0] 808 end 809 810 write_vgprs_to_mem_with_sqc(v0, 4, s_save_buf_rsrc0, s_save_mem_offset) 811 812 s_add_u32 m0, m0, 4 813 s_cmp_lt_u32 m0, s_save_alloc_size 814 s_cbranch_scc1 L_SAVE_ACCVGPR_LOOP_SQC 815 816 s_set_gpr_idx_off 817 s_branch L_SAVE_ACCVGPR_END 818end 819 820L_SAVE_ACCVGPR_LOOP: 821 for var vgpr = 0; vgpr < 4; ++ vgpr 822 v_accvgpr_read v[vgpr], acc[vgpr] // v[N] = acc[N+m0] 823 end 824 825 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 826 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256 827 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2 828 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3 829 830 s_add_u32 m0, m0, 4 831 s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 832 s_cmp_lt_u32 m0, s_save_alloc_size 833 s_cbranch_scc1 L_SAVE_ACCVGPR_LOOP 834 s_set_gpr_idx_off 835 836L_SAVE_ACCVGPR_END: 837end 838 839 /* S_PGM_END_SAVED */ //FIXME graphics ONLY 840 if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_NORMAL_EXIT)) 841 s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff //pc[47:32] 842 s_add_u32 s_save_pc_lo, s_save_pc_lo, 4 //pc[31:0]+4 843 s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0 //carry bit over 844 s_rfe_b64 s_save_pc_lo //Return to the main shader program 845 else 846 end 847 848// Save Done timestamp 849if G8SR_DEBUG_TIMESTAMP 850 s_memrealtime s_g8sr_ts_save_d 851 // SGPR SR memory offset : size(VGPR) 852 get_vgpr_size_bytes(s_save_mem_offset) 853 s_add_u32 s_save_mem_offset, s_save_mem_offset, G8SR_DEBUG_TS_SAVE_D_OFFSET 854 s_waitcnt lgkmcnt(0) //FIXME, will cause xnack?? 855 // Need reset rsrc2?? 856 s_mov_b32 m0, s_save_mem_offset 857 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 858 s_buffer_store_dwordx2 s_g8sr_ts_save_d, s_save_buf_rsrc0, m0 glc:1 859end 860 861 862 s_branch L_END_PGM 863 864 865 866/**************************************************************************/ 867/* restore routine */ 868/**************************************************************************/ 869 870L_RESTORE: 871 /* Setup Resource Contants */ 872 if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL)) 873 //calculate wd_addr using absolute thread id 874 v_readlane_b32 s_restore_tmp, v9, 0 875 s_lshr_b32 s_restore_tmp, s_restore_tmp, 6 876 s_mul_i32 s_restore_tmp, s_restore_tmp, WAVE_SPACE 877 s_add_i32 s_restore_spi_init_lo, s_restore_tmp, WG_BASE_ADDR_LO 878 s_mov_b32 s_restore_spi_init_hi, WG_BASE_ADDR_HI 879 s_and_b32 s_restore_spi_init_hi, s_restore_spi_init_hi, CTX_RESTORE_CONTROL 880 else 881 end 882 883if G8SR_DEBUG_TIMESTAMP 884 s_memrealtime s_g8sr_ts_restore_s 885 s_waitcnt lgkmcnt(0) //FIXME, will cause xnack?? 886 // tma_lo/hi are sgpr 110, 111, which will not used for 112 SGPR allocated case... 887 s_mov_b32 s_restore_pc_lo, s_g8sr_ts_restore_s[0] 888 s_mov_b32 s_restore_pc_hi, s_g8sr_ts_restore_s[1] //backup ts to ttmp0/1, sicne exec will be finally restored.. 889end 890 891 892 893 s_mov_b32 s_restore_buf_rsrc0, s_restore_spi_init_lo //base_addr_lo 894 s_and_b32 s_restore_buf_rsrc1, s_restore_spi_init_hi, 0x0000FFFF //base_addr_hi 895 s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE 896 s_mov_b32 s_restore_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) 897 s_mov_b32 s_restore_buf_rsrc3, S_RESTORE_BUF_RSRC_WORD3_MISC 898 s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_ATC_MASK 899 s_lshr_b32 s_restore_tmp, s_restore_tmp, (S_RESTORE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT) //get ATC bit into position 900 s_or_b32 s_restore_buf_rsrc3, s_restore_buf_rsrc3, s_restore_tmp //or ATC 901 s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_MTYPE_MASK 902 s_lshr_b32 s_restore_tmp, s_restore_tmp, (S_RESTORE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT) //get MTYPE bits into position 903 s_or_b32 s_restore_buf_rsrc3, s_restore_buf_rsrc3, s_restore_tmp //or MTYPE 904 905 /* global mem offset */ 906// s_mov_b32 s_restore_mem_offset, 0x0 //mem offset initial value = 0 907 908 /* the first wave in the threadgroup */ 909 s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_FIRST_WAVE_MASK 910 s_cbranch_scc0 L_RESTORE_VGPR 911 912 /* restore LDS */ 913 ////////////////////////////// 914 L_RESTORE_LDS: 915 916 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on //be consistent with SAVE although can be moved ahead 917 s_mov_b32 exec_hi, 0xFFFFFFFF 918 919 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) //lds_size 920 s_and_b32 s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF //lds_size is zero? 921 s_cbranch_scc0 L_RESTORE_VGPR //no lds used? jump to L_RESTORE_VGPR 922 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 6 //LDS size in dwords = lds_size * 64dw 923 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 2 //LDS size in bytes 924 s_mov_b32 s_restore_buf_rsrc2, s_restore_alloc_size //NUM_RECORDS in bytes 925 926 // LDS at offset: size(VGPR)+SIZE(SGPR)+SIZE(HWREG) 927 // 928 get_vgpr_size_bytes(s_restore_mem_offset) 929 get_sgpr_size_bytes(s_restore_tmp) 930 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 931 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_hwreg_size_bytes() //FIXME, Check if offset overflow??? 932 933 934 if (SWIZZLE_EN) 935 s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 936 else 937 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 938 end 939 s_mov_b32 m0, 0x0 //lds_offset initial value = 0 940 941 L_RESTORE_LDS_LOOP: 942 if (SAVE_LDS) 943 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 // first 64DW 944 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 offset:256 // second 64DW 945 end 946 s_add_u32 m0, m0, 256*2 // 128 DW 947 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*2 //mem offset increased by 128DW 948 s_cmp_lt_u32 m0, s_restore_alloc_size //scc=(m0 < s_restore_alloc_size) ? 1 : 0 949 s_cbranch_scc1 L_RESTORE_LDS_LOOP //LDS restore is complete? 950 951 952 /* restore VGPRs */ 953 ////////////////////////////// 954 L_RESTORE_VGPR: 955 // VGPR SR memory offset : 0 956 s_mov_b32 s_restore_mem_offset, 0x0 957 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on //be consistent with SAVE although can be moved ahead 958 s_mov_b32 exec_hi, 0xFFFFFFFF 959 960 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) //vpgr_size 961 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 1 962 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value) 963 s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 8 //NUM_RECORDS in bytes (64 threads*4) 964 965if ASIC_TARGET_ARCTURUS 966 s_mov_b32 s_restore_accvgpr_offset, s_restore_buf_rsrc2 //ACC VGPRs at end of VGPRs 967end 968 969 if (SWIZZLE_EN) 970 s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 971 else 972 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 973 end 974 975if G8SR_VGPR_SR_IN_DWX4 976 get_vgpr_size_bytes(s_restore_mem_offset) 977 s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 978 979 // the const stride for DWx4 is 4*4 bytes 980 s_and_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, 0x0000FFFF // reset const stride to 0 981 s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, G8SR_RESTORE_BUF_RSRC_WORD1_STRIDE_DWx4 // const stride to 4*4 bytes 982 983 s_mov_b32 m0, s_restore_alloc_size 984 s_set_gpr_idx_on m0, 0x8 // Note.. This will change m0 985 986L_RESTORE_VGPR_LOOP: 987 buffer_load_dwordx4 v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 988 s_waitcnt vmcnt(0) 989 s_sub_u32 m0, m0, 4 990 v_mov_b32 v0, v0 // v[0+m0] = v0 991 v_mov_b32 v1, v1 992 v_mov_b32 v2, v2 993 v_mov_b32 v3, v3 994 s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 995 s_cmp_eq_u32 m0, 0x8000 996 s_cbranch_scc0 L_RESTORE_VGPR_LOOP 997 s_set_gpr_idx_off 998 999 s_and_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, 0x0000FFFF // reset const stride to 0 1000 s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE // const stride to 4*4 bytes 1001 1002else 1003 // VGPR load using dw burst 1004 s_mov_b32 s_restore_mem_offset_save, s_restore_mem_offset // restore start with v1, v0 will be the last 1005 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 1006if ASIC_TARGET_ARCTURUS 1007 s_mov_b32 s_restore_accvgpr_offset_save, s_restore_accvgpr_offset 1008 s_add_u32 s_restore_accvgpr_offset, s_restore_accvgpr_offset, 256*4 1009end 1010 s_mov_b32 m0, 4 //VGPR initial index value = 1 1011 s_set_gpr_idx_on m0, 0x8 //M0[7:0] = M0[7:0] and M0[15:12] = 0x8 1012 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 0x8000 //add 0x8000 since we compare m0 against it later 1013 1014 L_RESTORE_VGPR_LOOP: 1015 if(USE_MTBUF_INSTEAD_OF_MUBUF) 1016 tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1 1017 else 1018 1019if ASIC_TARGET_ARCTURUS 1020 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset slc:1 glc:1 1021 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset slc:1 glc:1 offset:256 1022 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset slc:1 glc:1 offset:256*2 1023 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset slc:1 glc:1 offset:256*3 1024 s_add_u32 s_restore_accvgpr_offset, s_restore_accvgpr_offset, 256*4 1025 s_waitcnt vmcnt(0) 1026 1027 for var vgpr = 0; vgpr < 4; ++ vgpr 1028 v_accvgpr_write acc[vgpr], v[vgpr] 1029 end 1030end 1031 1032 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 1033 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256 1034 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*2 1035 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*3 1036 end 1037 s_waitcnt vmcnt(0) //ensure data ready 1038 v_mov_b32 v0, v0 //v[0+m0] = v0 1039 v_mov_b32 v1, v1 1040 v_mov_b32 v2, v2 1041 v_mov_b32 v3, v3 1042 s_add_u32 m0, m0, 4 //next vgpr index 1043 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 //every buffer_load_dword does 256 bytes 1044 s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0 1045 s_cbranch_scc1 L_RESTORE_VGPR_LOOP //VGPR restore (except v0) is complete? 1046 s_set_gpr_idx_off 1047 /* VGPR restore on v0 */ 1048if ASIC_TARGET_ARCTURUS 1049 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset_save slc:1 glc:1 1050 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset_save slc:1 glc:1 offset:256 1051 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset_save slc:1 glc:1 offset:256*2 1052 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset_save slc:1 glc:1 offset:256*3 1053 s_waitcnt vmcnt(0) 1054 1055 for var vgpr = 0; vgpr < 4; ++ vgpr 1056 v_accvgpr_write acc[vgpr], v[vgpr] 1057 end 1058end 1059 1060 if(USE_MTBUF_INSTEAD_OF_MUBUF) 1061 tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1 1062 else 1063 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 1064 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256 1065 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*2 1066 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*3 1067 end 1068 1069end 1070 1071 /* restore SGPRs */ 1072 ////////////////////////////// 1073 1074 // SGPR SR memory offset : size(VGPR) 1075 get_vgpr_size_bytes(s_restore_mem_offset) 1076 get_sgpr_size_bytes(s_restore_tmp) 1077 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 1078 s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 16*4 // restore SGPR from S[n] to S[0], by 16 sgprs group 1079 // TODO, change RSRC word to rearrange memory layout for SGPRS 1080 1081 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size 1082 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 1 1083 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 4 //Number of SGPRs = (sgpr_size + 1) * 16 (non-zero value) 1084 1085 if (SGPR_SAVE_USE_SQC) 1086 s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 2 //NUM_RECORDS in bytes 1087 else 1088 s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 8 //NUM_RECORDS in bytes (64 threads) 1089 end 1090 if (SWIZZLE_EN) 1091 s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 1092 else 1093 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 1094 end 1095 1096 s_mov_b32 m0, s_restore_alloc_size 1097 1098 L_RESTORE_SGPR_LOOP: 1099 read_16sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset) //PV: further performance improvement can be made 1100 s_waitcnt lgkmcnt(0) //ensure data ready 1101 1102 s_sub_u32 m0, m0, 16 // Restore from S[n] to S[0] 1103 s_nop 0 // hazard SALU M0=> S_MOVREL 1104 1105 s_movreld_b64 s0, s0 //s[0+m0] = s0 1106 s_movreld_b64 s2, s2 1107 s_movreld_b64 s4, s4 1108 s_movreld_b64 s6, s6 1109 s_movreld_b64 s8, s8 1110 s_movreld_b64 s10, s10 1111 s_movreld_b64 s12, s12 1112 s_movreld_b64 s14, s14 1113 1114 s_cmp_eq_u32 m0, 0 //scc = (m0 < s_restore_alloc_size) ? 1 : 0 1115 s_cbranch_scc0 L_RESTORE_SGPR_LOOP //SGPR restore (except s0) is complete? 1116 1117 /* restore HW registers */ 1118 ////////////////////////////// 1119 L_RESTORE_HWREG: 1120 1121 1122if G8SR_DEBUG_TIMESTAMP 1123 s_mov_b32 s_g8sr_ts_restore_s[0], s_restore_pc_lo 1124 s_mov_b32 s_g8sr_ts_restore_s[1], s_restore_pc_hi 1125end 1126 1127 // HWREG SR memory offset : size(VGPR)+size(SGPR) 1128 get_vgpr_size_bytes(s_restore_mem_offset) 1129 get_sgpr_size_bytes(s_restore_tmp) 1130 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 1131 1132 1133 s_mov_b32 s_restore_buf_rsrc2, 0x4 //NUM_RECORDS in bytes 1134 if (SWIZZLE_EN) 1135 s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 1136 else 1137 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 1138 end 1139 1140 read_hwreg_from_mem(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset) //M0 1141 read_hwreg_from_mem(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //PC 1142 read_hwreg_from_mem(s_restore_pc_hi, s_restore_buf_rsrc0, s_restore_mem_offset) 1143 read_hwreg_from_mem(s_restore_exec_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //EXEC 1144 read_hwreg_from_mem(s_restore_exec_hi, s_restore_buf_rsrc0, s_restore_mem_offset) 1145 read_hwreg_from_mem(s_restore_status, s_restore_buf_rsrc0, s_restore_mem_offset) //STATUS 1146 read_hwreg_from_mem(s_restore_trapsts, s_restore_buf_rsrc0, s_restore_mem_offset) //TRAPSTS 1147 read_hwreg_from_mem(xnack_mask_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //XNACK_MASK_LO 1148 read_hwreg_from_mem(xnack_mask_hi, s_restore_buf_rsrc0, s_restore_mem_offset) //XNACK_MASK_HI 1149 read_hwreg_from_mem(s_restore_mode, s_restore_buf_rsrc0, s_restore_mem_offset) //MODE 1150 1151 s_waitcnt lgkmcnt(0) //from now on, it is safe to restore STATUS and IB_STS 1152 1153 //for normal save & restore, the saved PC points to the next inst to execute, no adjustment needs to be made, otherwise: 1154 if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL)) 1155 s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 8 //pc[31:0]+8 //two back-to-back s_trap are used (first for save and second for restore) 1156 s_addc_u32 s_restore_pc_hi, s_restore_pc_hi, 0x0 //carry bit over 1157 end 1158 if ((EMU_RUN_HACK) && (EMU_RUN_HACK_RESTORE_NORMAL)) 1159 s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 4 //pc[31:0]+4 // save is hack through s_trap but restore is normal 1160 s_addc_u32 s_restore_pc_hi, s_restore_pc_hi, 0x0 //carry bit over 1161 end 1162 1163 s_mov_b32 m0, s_restore_m0 1164 s_mov_b32 exec_lo, s_restore_exec_lo 1165 s_mov_b32 exec_hi, s_restore_exec_hi 1166 1167 s_and_b32 s_restore_m0, SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK, s_restore_trapsts 1168 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE), s_restore_m0 1169 s_and_b32 s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK, s_restore_trapsts 1170 s_lshr_b32 s_restore_m0, s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT 1171 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE), s_restore_m0 1172 //s_setreg_b32 hwreg(HW_REG_TRAPSTS), s_restore_trapsts //don't overwrite SAVECTX bit as it may be set through external SAVECTX during restore 1173 s_setreg_b32 hwreg(HW_REG_MODE), s_restore_mode 1174 1175 // Restore trap temporaries 4-11, 13 initialized by SPI debug dispatch logic 1176 // ttmp SR memory offset : size(VGPR)+size(SGPR)+0x40 1177 get_vgpr_size_bytes(s_restore_ttmps_lo) 1178 get_sgpr_size_bytes(s_restore_ttmps_hi) 1179 s_add_u32 s_restore_ttmps_lo, s_restore_ttmps_lo, s_restore_ttmps_hi 1180 s_add_u32 s_restore_ttmps_lo, s_restore_ttmps_lo, s_restore_buf_rsrc0 1181 s_addc_u32 s_restore_ttmps_hi, s_restore_buf_rsrc1, 0x0 1182 s_and_b32 s_restore_ttmps_hi, s_restore_ttmps_hi, 0xFFFF 1183 s_load_dwordx4 [ttmp4, ttmp5, ttmp6, ttmp7], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x50 glc:1 1184 s_load_dwordx4 [ttmp8, ttmp9, ttmp10, ttmp11], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x60 glc:1 1185 s_load_dword ttmp13, [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x74 glc:1 1186 s_waitcnt lgkmcnt(0) 1187 1188 //reuse s_restore_m0 as a temp register 1189 s_and_b32 s_restore_m0, s_restore_pc_hi, S_SAVE_PC_HI_RCNT_MASK 1190 s_lshr_b32 s_restore_m0, s_restore_m0, S_SAVE_PC_HI_RCNT_SHIFT 1191 s_lshl_b32 s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_RCNT_SHIFT 1192 s_mov_b32 s_restore_tmp, 0x0 //IB_STS is zero 1193 s_or_b32 s_restore_tmp, s_restore_tmp, s_restore_m0 1194 s_and_b32 s_restore_m0, s_restore_pc_hi, S_SAVE_PC_HI_FIRST_REPLAY_MASK 1195 s_lshr_b32 s_restore_m0, s_restore_m0, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT 1196 s_lshl_b32 s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT 1197 s_or_b32 s_restore_tmp, s_restore_tmp, s_restore_m0 1198 s_and_b32 s_restore_m0, s_restore_status, SQ_WAVE_STATUS_INST_ATC_MASK 1199 s_lshr_b32 s_restore_m0, s_restore_m0, SQ_WAVE_STATUS_INST_ATC_SHIFT 1200 s_setreg_b32 hwreg(HW_REG_IB_STS), s_restore_tmp 1201 1202 s_and_b32 s_restore_pc_hi, s_restore_pc_hi, 0x0000ffff //pc[47:32] //Do it here in order not to affect STATUS 1203 s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32 1204 s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32 1205 set_status_without_spi_prio(s_restore_status, s_restore_tmp) // SCC is included, which is changed by previous salu 1206 1207 s_barrier //barrier to ensure the readiness of LDS before access attempts from any other wave in the same TG //FIXME not performance-optimal at this time 1208 1209if G8SR_DEBUG_TIMESTAMP 1210 s_memrealtime s_g8sr_ts_restore_d 1211 s_waitcnt lgkmcnt(0) 1212end 1213 1214// s_rfe_b64 s_restore_pc_lo //Return to the main shader program and resume execution 1215 s_rfe_restore_b64 s_restore_pc_lo, s_restore_m0 // s_restore_m0[0] is used to set STATUS.inst_atc 1216 1217 1218/**************************************************************************/ 1219/* the END */ 1220/**************************************************************************/ 1221L_END_PGM: 1222 s_endpgm 1223 1224end 1225 1226 1227/**************************************************************************/ 1228/* the helper functions */ 1229/**************************************************************************/ 1230 1231//Only for save hwreg to mem 1232function write_hwreg_to_mem(s, s_rsrc, s_mem_offset) 1233 s_mov_b32 exec_lo, m0 //assuming exec_lo is not needed anymore from this point on 1234 s_mov_b32 m0, s_mem_offset 1235 s_buffer_store_dword s, s_rsrc, m0 glc:1 1236 ack_sqc_store_workaround() 1237 s_add_u32 s_mem_offset, s_mem_offset, 4 1238 s_mov_b32 m0, exec_lo 1239end 1240 1241 1242// HWREG are saved before SGPRs, so all HWREG could be use. 1243function write_16sgpr_to_mem(s, s_rsrc, s_mem_offset) 1244 1245 s_buffer_store_dwordx4 s[0], s_rsrc, 0 glc:1 1246 ack_sqc_store_workaround() 1247 s_buffer_store_dwordx4 s[4], s_rsrc, 16 glc:1 1248 ack_sqc_store_workaround() 1249 s_buffer_store_dwordx4 s[8], s_rsrc, 32 glc:1 1250 ack_sqc_store_workaround() 1251 s_buffer_store_dwordx4 s[12], s_rsrc, 48 glc:1 1252 ack_sqc_store_workaround() 1253 s_add_u32 s_rsrc[0], s_rsrc[0], 4*16 1254 s_addc_u32 s_rsrc[1], s_rsrc[1], 0x0 // +scc 1255end 1256 1257 1258function read_hwreg_from_mem(s, s_rsrc, s_mem_offset) 1259 s_buffer_load_dword s, s_rsrc, s_mem_offset glc:1 1260 s_add_u32 s_mem_offset, s_mem_offset, 4 1261end 1262 1263function read_16sgpr_from_mem(s, s_rsrc, s_mem_offset) 1264 s_buffer_load_dwordx16 s, s_rsrc, s_mem_offset glc:1 1265 s_sub_u32 s_mem_offset, s_mem_offset, 4*16 1266end 1267 1268 1269 1270function get_lds_size_bytes(s_lds_size_byte) 1271 // SQ LDS granularity is 64DW, while PGM_RSRC2.lds_size is in granularity 128DW 1272 s_getreg_b32 s_lds_size_byte, hwreg(HW_REG_LDS_ALLOC, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) // lds_size 1273 s_lshl_b32 s_lds_size_byte, s_lds_size_byte, 8 //LDS size in dwords = lds_size * 64 *4Bytes // granularity 64DW 1274end 1275 1276function get_vgpr_size_bytes(s_vgpr_size_byte) 1277 s_getreg_b32 s_vgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) //vpgr_size 1278 s_add_u32 s_vgpr_size_byte, s_vgpr_size_byte, 1 1279 s_lshl_b32 s_vgpr_size_byte, s_vgpr_size_byte, (2+8) //Number of VGPRs = (vgpr_size + 1) * 4 * 64 * 4 (non-zero value) //FIXME for GFX, zero is possible 1280 1281if ASIC_TARGET_ARCTURUS 1282 s_lshl_b32 s_vgpr_size_byte, s_vgpr_size_byte, 1 // Double size for ACC VGPRs 1283end 1284end 1285 1286function get_sgpr_size_bytes(s_sgpr_size_byte) 1287 s_getreg_b32 s_sgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size 1288 s_add_u32 s_sgpr_size_byte, s_sgpr_size_byte, 1 1289 s_lshl_b32 s_sgpr_size_byte, s_sgpr_size_byte, 6 //Number of SGPRs = (sgpr_size + 1) * 16 *4 (non-zero value) 1290end 1291 1292function get_hwreg_size_bytes 1293 return 128 //HWREG size 128 bytes 1294end 1295 1296function ack_sqc_store_workaround 1297 if ACK_SQC_STORE 1298 s_waitcnt lgkmcnt(0) 1299 end 1300end 1301 1302function set_status_without_spi_prio(status, tmp) 1303 // Do not restore STATUS.SPI_PRIO since scheduler may have raised it. 1304 s_lshr_b32 tmp, status, SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT 1305 s_setreg_b32 hwreg(HW_REG_STATUS, SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT, SQ_WAVE_STATUS_POST_SPI_PRIO_SIZE), tmp 1306 s_nop 0x2 // avoid S_SETREG => S_SETREG hazard 1307 s_setreg_b32 hwreg(HW_REG_STATUS, SQ_WAVE_STATUS_PRE_SPI_PRIO_SHIFT, SQ_WAVE_STATUS_PRE_SPI_PRIO_SIZE), status 1308end 1309