1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23/* To compile this assembly code:
24 *
25 * gfx9:
26 *   cpp -DASIC_FAMILY=CHIP_VEGAM cwsr_trap_handler_gfx9.asm -P -o gfx9.sp3
27 *   sp3 gfx9.sp3 -hex gfx9.hex
28 *
29 * arcturus:
30 *   cpp -DASIC_FAMILY=CHIP_ARCTURUS cwsr_trap_handler_gfx9.asm -P -o arcturus.sp3
31 *   sp3 arcturus.sp3 -hex arcturus.hex
32 *
33 * aldebaran:
34 *   cpp -DASIC_FAMILY=CHIP_ALDEBARAN cwsr_trap_handler_gfx9.asm -P -o aldebaran.sp3
35 *   sp3 aldebaran.sp3 -hex aldebaran.hex
36 *
37 * gc_9_4_3:
38 *   cpp -DASIC_FAMILY=GC_9_4_3 cwsr_trap_handler_gfx9.asm -P -o gc_9_4_3.sp3
39 *   sp3 gc_9_4_3.sp3 -hex gc_9_4_3.hex
40 */
41
42#define CHIP_VEGAM 18
43#define CHIP_ARCTURUS 23
44#define CHIP_ALDEBARAN 25
45#define CHIP_GC_9_4_3 26
46
47var ACK_SQC_STORE		    =	1		    //workaround for suspected SQC store bug causing incorrect stores under concurrency
48var SAVE_AFTER_XNACK_ERROR	    =	1		    //workaround for TCP store failure after XNACK error when ALLOW_REPLAY=0, for debugger
49var SINGLE_STEP_MISSED_WORKAROUND   =	(ASIC_FAMILY <= CHIP_ALDEBARAN)	//workaround for lost MODE.DEBUG_EN exception when SAVECTX raised
50
51/**************************************************************************/
52/*			variables					  */
53/**************************************************************************/
54var SQ_WAVE_STATUS_SPI_PRIO_SHIFT  = 1
55var SQ_WAVE_STATUS_SPI_PRIO_MASK   = 0x00000006
56var SQ_WAVE_STATUS_HALT_MASK       = 0x2000
57var SQ_WAVE_STATUS_PRE_SPI_PRIO_SHIFT   = 0
58var SQ_WAVE_STATUS_PRE_SPI_PRIO_SIZE    = 1
59var SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT  = 3
60var SQ_WAVE_STATUS_POST_SPI_PRIO_SIZE   = 29
61var SQ_WAVE_STATUS_ALLOW_REPLAY_MASK    = 0x400000
62var SQ_WAVE_STATUS_ECC_ERR_MASK         = 0x20000
63
64var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT	= 12
65var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE	= 9
66var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE	= 6
67var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE	= 3			//FIXME	 sq.blk still has 4 bits at this time while SQ programming guide has 3 bits
68var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT	= 24
69
70#if ASIC_FAMILY >= CHIP_ALDEBARAN
71var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT	= 6
72var SQ_WAVE_GPR_ALLOC_ACCV_OFFSET_SHIFT	= 12
73var SQ_WAVE_GPR_ALLOC_ACCV_OFFSET_SIZE	= 6
74#else
75var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT	= 8
76#endif
77
78var SQ_WAVE_TRAPSTS_SAVECTX_MASK    =	0x400
79var SQ_WAVE_TRAPSTS_EXCP_MASK	    =	0x1FF
80var SQ_WAVE_TRAPSTS_SAVECTX_SHIFT   =	10
81var SQ_WAVE_TRAPSTS_ADDR_WATCH_MASK =	0x80
82var SQ_WAVE_TRAPSTS_ADDR_WATCH_SHIFT =	7
83var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK   =	0x100
84var SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT  =	8
85var SQ_WAVE_TRAPSTS_HOST_TRAP_MASK  =	0x400000
86var SQ_WAVE_TRAPSTS_WAVE_BEGIN_MASK =	0x800000
87var SQ_WAVE_TRAPSTS_WAVE_END_MASK   =	0x1000000
88var SQ_WAVE_TRAPSTS_TRAP_AFTER_INST_MASK =  0x2000000
89var SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK	=   0x3FF
90var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT	=   0x0
91var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE	=   10
92var SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK	=   0xFFFFF800
93var SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT	=   11
94var SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE	=   21
95var SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK	=   0x800
96var SQ_WAVE_TRAPSTS_EXCP_HI_MASK	=   0x7000
97var SQ_WAVE_TRAPSTS_XNACK_ERROR_MASK	=   0x10000000
98
99var SQ_WAVE_MODE_EXCP_EN_SHIFT		=   12
100var SQ_WAVE_MODE_EXCP_EN_ADDR_WATCH_SHIFT	= 19
101
102var SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT	=   15			//FIXME
103var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK	= 0x1F8000
104
105var SQ_WAVE_MODE_DEBUG_EN_MASK		=   0x800
106
107var TTMP_SAVE_RCNT_FIRST_REPLAY_SHIFT	=   26			// bits [31:26] unused by SPI debug data
108var TTMP_SAVE_RCNT_FIRST_REPLAY_MASK	=   0xFC000000
109var TTMP_DEBUG_TRAP_ENABLED_SHIFT	=   23
110var TTMP_DEBUG_TRAP_ENABLED_MASK	=   0x800000
111
112/*	Save	    */
113var S_SAVE_BUF_RSRC_WORD1_STRIDE	=   0x00040000		//stride is 4 bytes
114var S_SAVE_BUF_RSRC_WORD3_MISC		=   0x00807FAC		//SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14] when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE
115var S_SAVE_PC_HI_TRAP_ID_MASK		=   0x00FF0000
116var S_SAVE_PC_HI_HT_MASK		=   0x01000000
117var S_SAVE_SPI_INIT_FIRST_WAVE_MASK	=   0x04000000		//bit[26]: FirstWaveInTG
118var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT	=   26
119
120var s_save_spi_init_lo		    =	exec_lo
121var s_save_spi_init_hi		    =	exec_hi
122
123var s_save_pc_lo	    =	ttmp0		//{TTMP1, TTMP0} = {3'h0,pc_rewind[3:0], HT[0],trapID[7:0], PC[47:0]}
124var s_save_pc_hi	    =	ttmp1
125var s_save_exec_lo	    =	ttmp2
126var s_save_exec_hi	    =	ttmp3
127var s_save_tmp		    =	ttmp14
128var s_save_trapsts	    =	ttmp15		//not really used until the end of the SAVE routine
129var s_save_xnack_mask_lo    =	ttmp6
130var s_save_xnack_mask_hi    =	ttmp7
131var s_save_buf_rsrc0	    =	ttmp8
132var s_save_buf_rsrc1	    =	ttmp9
133var s_save_buf_rsrc2	    =	ttmp10
134var s_save_buf_rsrc3	    =	ttmp11
135var s_save_status	    =	ttmp12
136var s_save_mem_offset	    =	ttmp4
137var s_save_alloc_size	    =	s_save_trapsts		//conflict
138var s_save_m0		    =	ttmp5
139var s_save_ttmps_lo	    =	s_save_tmp		//no conflict
140var s_save_ttmps_hi	    =	s_save_trapsts		//no conflict
141#if ASIC_FAMILY >= CHIP_GC_9_4_3
142var s_save_ib_sts       =	ttmp13
143#else
144var s_save_ib_sts       =	ttmp11
145#endif
146
147/*	Restore	    */
148var S_RESTORE_BUF_RSRC_WORD1_STRIDE	    =	S_SAVE_BUF_RSRC_WORD1_STRIDE
149var S_RESTORE_BUF_RSRC_WORD3_MISC	    =	S_SAVE_BUF_RSRC_WORD3_MISC
150
151var S_RESTORE_SPI_INIT_FIRST_WAVE_MASK	    =	0x04000000	    //bit[26]: FirstWaveInTG
152var S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT	    =	26
153
154var s_restore_spi_init_lo		    =	exec_lo
155var s_restore_spi_init_hi		    =	exec_hi
156
157var s_restore_mem_offset	=   ttmp12
158var s_restore_tmp2		=   ttmp13
159var s_restore_alloc_size	=   ttmp3
160var s_restore_tmp		=   ttmp2
161var s_restore_mem_offset_save	=   s_restore_tmp	//no conflict
162var s_restore_accvgpr_offset_save = ttmp7
163
164var s_restore_m0	    =	s_restore_alloc_size	//no conflict
165
166var s_restore_mode	    =	s_restore_accvgpr_offset_save
167
168var s_restore_pc_lo	    =	ttmp0
169var s_restore_pc_hi	    =	ttmp1
170var s_restore_exec_lo	    =	ttmp4
171var s_restore_exec_hi	    = 	ttmp5
172var s_restore_status	    =	ttmp14
173var s_restore_trapsts	    =	ttmp15
174var s_restore_xnack_mask_lo =	xnack_mask_lo
175var s_restore_xnack_mask_hi =	xnack_mask_hi
176var s_restore_buf_rsrc0	    =	ttmp8
177var s_restore_buf_rsrc1	    =	ttmp9
178var s_restore_buf_rsrc2	    =	ttmp10
179var s_restore_buf_rsrc3	    =	ttmp11
180var s_restore_ttmps_lo	    =	s_restore_tmp		//no conflict
181var s_restore_ttmps_hi	    =	s_restore_alloc_size	//no conflict
182
183/**************************************************************************/
184/*			trap handler entry points			  */
185/**************************************************************************/
186/* Shader Main*/
187
188shader main
189  asic(DEFAULT)
190  type(CS)
191
192
193	s_branch L_SKIP_RESTORE					    //NOT restore. might be a regular trap or save
194
195L_JUMP_TO_RESTORE:
196    s_branch L_RESTORE						    //restore
197
198L_SKIP_RESTORE:
199
200    s_getreg_b32    s_save_status, hwreg(HW_REG_STATUS)				    //save STATUS since we will change SCC
201
202    // Clear SPI_PRIO: do not save with elevated priority.
203    // Clear ECC_ERR: prevents SQC store and triggers FATAL_HALT if setreg'd.
204    s_andn2_b32     s_save_status, s_save_status, SQ_WAVE_STATUS_SPI_PRIO_MASK|SQ_WAVE_STATUS_ECC_ERR_MASK
205
206    s_getreg_b32    s_save_trapsts, hwreg(HW_REG_TRAPSTS)
207
208    s_and_b32       ttmp2, s_save_status, SQ_WAVE_STATUS_HALT_MASK
209    s_cbranch_scc0  L_NOT_HALTED
210
211L_HALTED:
212    // Host trap may occur while wave is halted.
213    s_and_b32       ttmp2, s_save_pc_hi, S_SAVE_PC_HI_TRAP_ID_MASK
214    s_cbranch_scc1  L_FETCH_2ND_TRAP
215
216L_CHECK_SAVE:
217    s_and_b32       ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK    //check whether this is for save
218    s_cbranch_scc1  L_SAVE					//this is the operation for save
219
220    // Wave is halted but neither host trap nor SAVECTX is raised.
221    // Caused by instruction fetch memory violation.
222    // Spin wait until context saved to prevent interrupt storm.
223    s_sleep         0x10
224    s_getreg_b32    s_save_trapsts, hwreg(HW_REG_TRAPSTS)
225    s_branch        L_CHECK_SAVE
226
227L_NOT_HALTED:
228    // Let second-level handle non-SAVECTX exception or trap.
229    // Any concurrent SAVECTX will be handled upon re-entry once halted.
230
231    // Check non-maskable exceptions. memory_violation, illegal_instruction
232    // and debugger (host trap, wave start/end, trap after instruction)
233    // exceptions always cause the wave to enter the trap handler.
234    s_and_b32       ttmp2, s_save_trapsts,      \
235        SQ_WAVE_TRAPSTS_MEM_VIOL_MASK         | \
236        SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK     | \
237        SQ_WAVE_TRAPSTS_HOST_TRAP_MASK        | \
238        SQ_WAVE_TRAPSTS_WAVE_BEGIN_MASK       | \
239        SQ_WAVE_TRAPSTS_WAVE_END_MASK         | \
240        SQ_WAVE_TRAPSTS_TRAP_AFTER_INST_MASK
241    s_cbranch_scc1  L_FETCH_2ND_TRAP
242
243    // Check for maskable exceptions in trapsts.excp and trapsts.excp_hi.
244    // Maskable exceptions only cause the wave to enter the trap handler if
245    // their respective bit in mode.excp_en is set.
246    s_and_b32       ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_EXCP_MASK|SQ_WAVE_TRAPSTS_EXCP_HI_MASK
247    s_cbranch_scc0  L_CHECK_TRAP_ID
248
249    s_and_b32       ttmp3, s_save_trapsts, SQ_WAVE_TRAPSTS_ADDR_WATCH_MASK|SQ_WAVE_TRAPSTS_EXCP_HI_MASK
250    s_cbranch_scc0  L_NOT_ADDR_WATCH
251    s_bitset1_b32   ttmp2, SQ_WAVE_TRAPSTS_ADDR_WATCH_SHIFT // Check all addr_watch[123] exceptions against excp_en.addr_watch
252
253L_NOT_ADDR_WATCH:
254    s_getreg_b32    ttmp3, hwreg(HW_REG_MODE)
255    s_lshl_b32      ttmp2, ttmp2, SQ_WAVE_MODE_EXCP_EN_SHIFT
256    s_and_b32       ttmp2, ttmp2, ttmp3
257    s_cbranch_scc1  L_FETCH_2ND_TRAP
258
259L_CHECK_TRAP_ID:
260    // Check trap_id != 0
261    s_and_b32       ttmp2, s_save_pc_hi, S_SAVE_PC_HI_TRAP_ID_MASK
262    s_cbranch_scc1  L_FETCH_2ND_TRAP
263
264if SINGLE_STEP_MISSED_WORKAROUND
265    // Prioritize single step exception over context save.
266    // Second-level trap will halt wave and RFE, re-entering for SAVECTX.
267    s_getreg_b32    ttmp2, hwreg(HW_REG_MODE)
268    s_and_b32       ttmp2, ttmp2, SQ_WAVE_MODE_DEBUG_EN_MASK
269    s_cbranch_scc1  L_FETCH_2ND_TRAP
270end
271
272    s_and_b32       ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK
273    s_cbranch_scc1  L_SAVE
274
275L_FETCH_2ND_TRAP:
276    // Preserve and clear scalar XNACK state before issuing scalar reads.
277    save_and_clear_ib_sts(ttmp14)
278
279    // Read second-level TBA/TMA from first-level TMA and jump if available.
280    // ttmp[2:5] and ttmp12 can be used (others hold SPI-initialized debug data)
281    // ttmp12 holds SQ_WAVE_STATUS
282    s_getreg_b32    ttmp14, hwreg(HW_REG_SQ_SHADER_TMA_LO)
283    s_getreg_b32    ttmp15, hwreg(HW_REG_SQ_SHADER_TMA_HI)
284    s_lshl_b64      [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8
285
286    s_bitcmp1_b32   ttmp15, 0xF
287    s_cbranch_scc0  L_NO_SIGN_EXTEND_TMA
288    s_or_b32        ttmp15, ttmp15, 0xFFFF0000
289L_NO_SIGN_EXTEND_TMA:
290
291    s_load_dword    ttmp2, [ttmp14, ttmp15], 0x10 glc:1 // debug trap enabled flag
292    s_waitcnt       lgkmcnt(0)
293    s_lshl_b32      ttmp2, ttmp2, TTMP_DEBUG_TRAP_ENABLED_SHIFT
294    s_andn2_b32     s_save_ib_sts, s_save_ib_sts, TTMP_DEBUG_TRAP_ENABLED_MASK
295    s_or_b32        s_save_ib_sts, s_save_ib_sts, ttmp2
296
297    s_load_dwordx2  [ttmp2, ttmp3], [ttmp14, ttmp15], 0x0 glc:1 // second-level TBA
298    s_waitcnt       lgkmcnt(0)
299    s_load_dwordx2  [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 glc:1 // second-level TMA
300    s_waitcnt       lgkmcnt(0)
301
302    s_and_b64       [ttmp2, ttmp3], [ttmp2, ttmp3], [ttmp2, ttmp3]
303    s_cbranch_scc0  L_NO_NEXT_TRAP // second-level trap handler not been set
304    s_setpc_b64     [ttmp2, ttmp3] // jump to second-level trap handler
305
306L_NO_NEXT_TRAP:
307    // If not caused by trap then halt wave to prevent re-entry.
308    s_and_b32       ttmp2, s_save_pc_hi, (S_SAVE_PC_HI_TRAP_ID_MASK|S_SAVE_PC_HI_HT_MASK)
309    s_cbranch_scc1  L_TRAP_CASE
310    s_or_b32        s_save_status, s_save_status, SQ_WAVE_STATUS_HALT_MASK
311
312    // If the PC points to S_ENDPGM then context save will fail if STATUS.HALT is set.
313    // Rewind the PC to prevent this from occurring.
314    s_sub_u32       ttmp0, ttmp0, 0x8
315    s_subb_u32      ttmp1, ttmp1, 0x0
316
317    s_branch        L_EXIT_TRAP
318
319L_TRAP_CASE:
320    // Host trap will not cause trap re-entry.
321    s_and_b32       ttmp2, s_save_pc_hi, S_SAVE_PC_HI_HT_MASK
322    s_cbranch_scc1  L_EXIT_TRAP
323
324    // Advance past trap instruction to prevent re-entry.
325    s_add_u32       ttmp0, ttmp0, 0x4
326    s_addc_u32      ttmp1, ttmp1, 0x0
327
328L_EXIT_TRAP:
329    s_and_b32	ttmp1, ttmp1, 0xFFFF
330
331    restore_ib_sts(ttmp14)
332
333    // Restore SQ_WAVE_STATUS.
334    s_and_b64       exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32
335    s_and_b64       vcc, vcc, vcc    // Restore STATUS.VCCZ, not writable by s_setreg_b32
336    set_status_without_spi_prio(s_save_status, ttmp2)
337
338    s_rfe_b64       [ttmp0, ttmp1]
339
340    // *********	End handling of non-CWSR traps	 *******************
341
342/**************************************************************************/
343/*			save routine					  */
344/**************************************************************************/
345
346L_SAVE:
347    s_and_b32	    s_save_pc_hi, s_save_pc_hi, 0x0000ffff    //pc[47:32]
348
349    s_mov_b32	    s_save_tmp, 0							    //clear saveCtx bit
350    s_setreg_b32    hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_SAVECTX_SHIFT, 1), s_save_tmp	    //clear saveCtx bit
351
352    save_and_clear_ib_sts(s_save_tmp)
353
354    /*	    inform SPI the readiness and wait for SPI's go signal */
355    s_mov_b32	    s_save_exec_lo, exec_lo						    //save EXEC and use EXEC for the go signal from SPI
356    s_mov_b32	    s_save_exec_hi, exec_hi
357    s_mov_b64	    exec,   0x0								    //clear EXEC to get ready to receive
358
359	s_sendmsg   sendmsg(MSG_SAVEWAVE)  //send SPI a message and wait for SPI's write to EXEC
360
361    // Set SPI_PRIO=2 to avoid starving instruction fetch in the waves we're waiting for.
362    s_or_b32 s_save_tmp, s_save_status, (2 << SQ_WAVE_STATUS_SPI_PRIO_SHIFT)
363    s_setreg_b32 hwreg(HW_REG_STATUS), s_save_tmp
364
365  L_SLEEP:
366    s_sleep 0x2		       // sleep 1 (64clk) is not enough for 8 waves per SIMD, which will cause SQ hang, since the 7,8th wave could not get arbit to exec inst, while other waves are stuck into the sleep-loop and waiting for wrexec!=0
367
368	s_cbranch_execz L_SLEEP
369
370    // Save trap temporaries 4-11, 13 initialized by SPI debug dispatch logic
371    // ttmp SR memory offset : size(VGPR)+size(SGPR)+0x40
372    get_vgpr_size_bytes(s_save_ttmps_lo)
373    get_sgpr_size_bytes(s_save_ttmps_hi)
374    s_add_u32	    s_save_ttmps_lo, s_save_ttmps_lo, s_save_ttmps_hi
375    s_add_u32	    s_save_ttmps_lo, s_save_ttmps_lo, s_save_spi_init_lo
376    s_addc_u32	    s_save_ttmps_hi, s_save_spi_init_hi, 0x0
377    s_and_b32	    s_save_ttmps_hi, s_save_ttmps_hi, 0xFFFF
378    s_store_dwordx4 [ttmp4, ttmp5, ttmp6, ttmp7], [s_save_ttmps_lo, s_save_ttmps_hi], 0x50 glc:1
379    ack_sqc_store_workaround()
380    s_store_dwordx4 [ttmp8, ttmp9, ttmp10, ttmp11], [s_save_ttmps_lo, s_save_ttmps_hi], 0x60 glc:1
381    ack_sqc_store_workaround()
382    s_store_dword   ttmp13, [s_save_ttmps_lo, s_save_ttmps_hi], 0x74 glc:1
383    ack_sqc_store_workaround()
384
385    /*	    setup Resource Contants    */
386    s_mov_b32	    s_save_buf_rsrc0,	s_save_spi_init_lo							//base_addr_lo
387    s_and_b32	    s_save_buf_rsrc1,	s_save_spi_init_hi, 0x0000FFFF						//base_addr_hi
388    s_or_b32	    s_save_buf_rsrc1,	s_save_buf_rsrc1,  S_SAVE_BUF_RSRC_WORD1_STRIDE
389    s_mov_b32	    s_save_buf_rsrc2,	0									//NUM_RECORDS initial value = 0 (in bytes) although not neccessarily inited
390    s_mov_b32	    s_save_buf_rsrc3,	S_SAVE_BUF_RSRC_WORD3_MISC
391
392    //FIXME  right now s_save_m0/s_save_mem_offset use tma_lo/tma_hi  (might need to save them before using them?)
393    s_mov_b32	    s_save_m0,		m0								    //save M0
394
395    /*	    global mem offset		*/
396    s_mov_b32	    s_save_mem_offset,	0x0									//mem offset initial value = 0
397
398
399
400
401    /*	    save HW registers	*/
402    //////////////////////////////
403
404  L_SAVE_HWREG:
405	// HWREG SR memory offset : size(VGPR)+size(SGPR)
406       get_vgpr_size_bytes(s_save_mem_offset)
407       get_sgpr_size_bytes(s_save_tmp)
408       s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp
409
410
411    s_mov_b32	    s_save_buf_rsrc2, 0x4				//NUM_RECORDS	in bytes
412	s_mov_b32	s_save_buf_rsrc2,  0x1000000				    //NUM_RECORDS in bytes
413
414
415    write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset)			//M0
416    write_hwreg_to_mem(s_save_pc_lo, s_save_buf_rsrc0, s_save_mem_offset)		    //PC
417    write_hwreg_to_mem(s_save_pc_hi, s_save_buf_rsrc0, s_save_mem_offset)
418    write_hwreg_to_mem(s_save_exec_lo, s_save_buf_rsrc0, s_save_mem_offset)		//EXEC
419    write_hwreg_to_mem(s_save_exec_hi, s_save_buf_rsrc0, s_save_mem_offset)
420    write_hwreg_to_mem(s_save_status, s_save_buf_rsrc0, s_save_mem_offset)		//STATUS
421
422    //s_save_trapsts conflicts with s_save_alloc_size
423    s_getreg_b32    s_save_trapsts, hwreg(HW_REG_TRAPSTS)
424    write_hwreg_to_mem(s_save_trapsts, s_save_buf_rsrc0, s_save_mem_offset)		//TRAPSTS
425
426    write_hwreg_to_mem(xnack_mask_lo, s_save_buf_rsrc0, s_save_mem_offset)	    //XNACK_MASK_LO
427    write_hwreg_to_mem(xnack_mask_hi, s_save_buf_rsrc0, s_save_mem_offset)	    //XNACK_MASK_HI
428
429    //use s_save_tmp would introduce conflict here between s_save_tmp and s_save_buf_rsrc2
430    s_getreg_b32    s_save_m0, hwreg(HW_REG_MODE)						    //MODE
431    write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset)
432
433
434
435    /*	    the first wave in the threadgroup	 */
436    s_and_b32	    s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK	// extract fisrt wave bit
437    s_mov_b32	     s_save_exec_hi, 0x0
438    s_or_b32	     s_save_exec_hi, s_save_tmp, s_save_exec_hi				 // save first wave bit to s_save_exec_hi.bits[26]
439
440
441    /*		save SGPRs	*/
442	// Save SGPR before LDS save, then the s0 to s4 can be used during LDS save...
443    //////////////////////////////
444
445    // SGPR SR memory offset : size(VGPR)
446    get_vgpr_size_bytes(s_save_mem_offset)
447    // TODO, change RSRC word to rearrange memory layout for SGPRS
448
449    s_getreg_b32    s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE)		//spgr_size
450    s_add_u32	    s_save_alloc_size, s_save_alloc_size, 1
451    s_lshl_b32	    s_save_alloc_size, s_save_alloc_size, 4			    //Number of SGPRs = (sgpr_size + 1) * 16   (non-zero value)
452
453	s_lshl_b32	s_save_buf_rsrc2,   s_save_alloc_size, 2		    //NUM_RECORDS in bytes
454
455	s_mov_b32	s_save_buf_rsrc2,  0x1000000				    //NUM_RECORDS in bytes
456
457
458    // backup s_save_buf_rsrc0,1 to s_save_pc_lo/hi, since write_16sgpr_to_mem function will change the rsrc0
459    //s_mov_b64 s_save_pc_lo, s_save_buf_rsrc0
460    s_mov_b64 s_save_xnack_mask_lo, s_save_buf_rsrc0
461    s_add_u32 s_save_buf_rsrc0, s_save_buf_rsrc0, s_save_mem_offset
462    s_addc_u32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0
463
464    s_mov_b32	    m0, 0x0			    //SGPR initial index value =0
465    s_nop	    0x0				    //Manually inserted wait states
466  L_SAVE_SGPR_LOOP:
467    // SGPR is allocated in 16 SGPR granularity
468    s_movrels_b64   s0, s0     //s0 = s[0+m0], s1 = s[1+m0]
469    s_movrels_b64   s2, s2     //s2 = s[2+m0], s3 = s[3+m0]
470    s_movrels_b64   s4, s4     //s4 = s[4+m0], s5 = s[5+m0]
471    s_movrels_b64   s6, s6     //s6 = s[6+m0], s7 = s[7+m0]
472    s_movrels_b64   s8, s8     //s8 = s[8+m0], s9 = s[9+m0]
473    s_movrels_b64   s10, s10   //s10 = s[10+m0], s11 = s[11+m0]
474    s_movrels_b64   s12, s12   //s12 = s[12+m0], s13 = s[13+m0]
475    s_movrels_b64   s14, s14   //s14 = s[14+m0], s15 = s[15+m0]
476
477    write_16sgpr_to_mem(s0, s_save_buf_rsrc0, s_save_mem_offset) //PV: the best performance should be using s_buffer_store_dwordx4
478    s_add_u32	    m0, m0, 16							    //next sgpr index
479    s_cmp_lt_u32    m0, s_save_alloc_size					    //scc = (m0 < s_save_alloc_size) ? 1 : 0
480    s_cbranch_scc1  L_SAVE_SGPR_LOOP					//SGPR save is complete?
481    // restore s_save_buf_rsrc0,1
482    //s_mov_b64 s_save_buf_rsrc0, s_save_pc_lo
483    s_mov_b64 s_save_buf_rsrc0, s_save_xnack_mask_lo
484
485
486
487
488    /*		save first 4 VGPR, then LDS save could use   */
489	// each wave will alloc 4 vgprs at least...
490    /////////////////////////////////////////////////////////////////////////////////////
491
492    s_mov_b32	    s_save_mem_offset, 0
493    s_mov_b32	    exec_lo, 0xFFFFFFFF						    //need every thread from now on
494    s_mov_b32	    exec_hi, 0xFFFFFFFF
495    s_mov_b32	    xnack_mask_lo, 0x0
496    s_mov_b32	    xnack_mask_hi, 0x0
497
498	s_mov_b32	s_save_buf_rsrc2,  0x1000000				    //NUM_RECORDS in bytes
499
500
501    // VGPR Allocated in 4-GPR granularity
502
503if SAVE_AFTER_XNACK_ERROR
504	check_if_tcp_store_ok()
505	s_cbranch_scc1 L_SAVE_FIRST_VGPRS_WITH_TCP
506
507	write_vgprs_to_mem_with_sqc(v0, 4, s_save_buf_rsrc0, s_save_mem_offset)
508	s_branch L_SAVE_LDS
509
510L_SAVE_FIRST_VGPRS_WITH_TCP:
511end
512
513    write_4vgprs_to_mem(s_save_buf_rsrc0, s_save_mem_offset)
514
515    /*		save LDS	*/
516    //////////////////////////////
517
518  L_SAVE_LDS:
519
520	// Change EXEC to all threads...
521    s_mov_b32	    exec_lo, 0xFFFFFFFF	  //need every thread from now on
522    s_mov_b32	    exec_hi, 0xFFFFFFFF
523
524    s_getreg_b32    s_save_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE)		    //lds_size
525    s_and_b32	    s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF		    //lds_size is zero?
526    s_cbranch_scc0  L_SAVE_LDS_DONE									       //no lds used? jump to L_SAVE_DONE
527
528    s_barrier		    //LDS is used? wait for other waves in the same TG
529    s_and_b32	    s_save_tmp, s_save_exec_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK		       //exec is still used here
530    s_cbranch_scc0  L_SAVE_LDS_DONE
531
532	// first wave do LDS save;
533
534    s_lshl_b32	    s_save_alloc_size, s_save_alloc_size, 6			    //LDS size in dwords = lds_size * 64dw
535    s_lshl_b32	    s_save_alloc_size, s_save_alloc_size, 2			    //LDS size in bytes
536    s_mov_b32	    s_save_buf_rsrc2,  s_save_alloc_size			    //NUM_RECORDS in bytes
537
538    // LDS at offset: size(VGPR)+SIZE(SGPR)+SIZE(HWREG)
539    //
540    get_vgpr_size_bytes(s_save_mem_offset)
541    get_sgpr_size_bytes(s_save_tmp)
542    s_add_u32  s_save_mem_offset, s_save_mem_offset, s_save_tmp
543    s_add_u32 s_save_mem_offset, s_save_mem_offset, get_hwreg_size_bytes()
544
545
546	s_mov_b32	s_save_buf_rsrc2,  0x1000000		      //NUM_RECORDS in bytes
547
548    s_mov_b32	    m0, 0x0						  //lds_offset initial value = 0
549
550
551      v_mbcnt_lo_u32_b32 v2, 0xffffffff, 0x0
552      v_mbcnt_hi_u32_b32 v3, 0xffffffff, v2	// tid
553
554if SAVE_AFTER_XNACK_ERROR
555	check_if_tcp_store_ok()
556	s_cbranch_scc1 L_SAVE_LDS_WITH_TCP
557
558	v_lshlrev_b32 v2, 2, v3
559L_SAVE_LDS_LOOP_SQC:
560	ds_read2_b32 v[0:1], v2 offset0:0 offset1:0x40
561	s_waitcnt lgkmcnt(0)
562
563	write_vgprs_to_mem_with_sqc(v0, 2, s_save_buf_rsrc0, s_save_mem_offset)
564
565	v_add_u32 v2, 0x200, v2
566	v_cmp_lt_u32 vcc[0:1], v2, s_save_alloc_size
567	s_cbranch_vccnz L_SAVE_LDS_LOOP_SQC
568
569	s_branch L_SAVE_LDS_DONE
570
571L_SAVE_LDS_WITH_TCP:
572end
573
574      v_mul_i32_i24 v2, v3, 8	// tid*8
575      v_mov_b32 v3, 256*2
576      s_mov_b32 m0, 0x10000
577      s_mov_b32 s0, s_save_buf_rsrc3
578      s_and_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, 0xFF7FFFFF	  // disable add_tid
579      s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, 0x58000   //DFMT
580
581L_SAVE_LDS_LOOP_VECTOR:
582      ds_read_b64 v[0:1], v2	//x =LDS[a], byte address
583      s_waitcnt lgkmcnt(0)
584      buffer_store_dwordx2  v[0:1], v2, s_save_buf_rsrc0, s_save_mem_offset offen:1  glc:1  slc:1
585//	s_waitcnt vmcnt(0)
586//	v_add_u32 v2, vcc[0:1], v2, v3
587      v_add_u32 v2, v2, v3
588      v_cmp_lt_u32 vcc[0:1], v2, s_save_alloc_size
589      s_cbranch_vccnz L_SAVE_LDS_LOOP_VECTOR
590
591      // restore rsrc3
592      s_mov_b32 s_save_buf_rsrc3, s0
593
594L_SAVE_LDS_DONE:
595
596
597    /*		save VGPRs  - set the Rest VGPRs	*/
598    //////////////////////////////////////////////////////////////////////////////////////
599  L_SAVE_VGPR:
600    // VGPR SR memory offset: 0
601    // TODO rearrange the RSRC words to use swizzle for VGPR save...
602
603    s_mov_b32	    s_save_mem_offset, (0+256*4)				    // for the rest VGPRs
604    s_mov_b32	    exec_lo, 0xFFFFFFFF						    //need every thread from now on
605    s_mov_b32	    exec_hi, 0xFFFFFFFF
606
607    get_num_arch_vgprs(s_save_alloc_size)
608    s_mov_b32	    s_save_buf_rsrc2,  0x1000000				    //NUM_RECORDS in bytes
609
610
611    // VGPR store using dw burst
612    s_mov_b32	      m0, 0x4	//VGPR initial index value =0
613    s_cmp_lt_u32      m0, s_save_alloc_size
614    s_cbranch_scc0    L_SAVE_VGPR_END
615
616
617    s_set_gpr_idx_on	m0, 0x1 //M0[7:0] = M0[7:0] and M0[15:12] = 0x1
618    s_add_u32	    s_save_alloc_size, s_save_alloc_size, 0x1000		    //add 0x1000 since we compare m0 against it later
619
620if SAVE_AFTER_XNACK_ERROR
621	check_if_tcp_store_ok()
622	s_cbranch_scc1 L_SAVE_VGPR_LOOP
623
624L_SAVE_VGPR_LOOP_SQC:
625	write_vgprs_to_mem_with_sqc(v0, 4, s_save_buf_rsrc0, s_save_mem_offset)
626
627	s_add_u32 m0, m0, 4
628	s_cmp_lt_u32 m0, s_save_alloc_size
629	s_cbranch_scc1 L_SAVE_VGPR_LOOP_SQC
630
631	s_set_gpr_idx_off
632	s_branch L_SAVE_VGPR_END
633end
634
635  L_SAVE_VGPR_LOOP:
636    v_mov_b32	    v0, v0		//v0 = v[0+m0]
637    v_mov_b32	    v1, v1		//v0 = v[0+m0]
638    v_mov_b32	    v2, v2		//v0 = v[0+m0]
639    v_mov_b32	    v3, v3		//v0 = v[0+m0]
640
641    write_4vgprs_to_mem(s_save_buf_rsrc0, s_save_mem_offset)
642
643    s_add_u32	    m0, m0, 4							    //next vgpr index
644    s_add_u32	    s_save_mem_offset, s_save_mem_offset, 256*4			    //every buffer_store_dword does 256 bytes
645    s_cmp_lt_u32    m0, s_save_alloc_size					    //scc = (m0 < s_save_alloc_size) ? 1 : 0
646    s_cbranch_scc1  L_SAVE_VGPR_LOOP						    //VGPR save is complete?
647    s_set_gpr_idx_off
648
649L_SAVE_VGPR_END:
650
651#if ASIC_FAMILY >= CHIP_ARCTURUS
652    // Save ACC VGPRs
653
654#if ASIC_FAMILY >= CHIP_ALDEBARAN
655    // ACC VGPR count may differ from ARCH VGPR count.
656    get_num_acc_vgprs(s_save_alloc_size, s_save_tmp)
657    s_and_b32       s_save_alloc_size, s_save_alloc_size, s_save_alloc_size
658    s_cbranch_scc0  L_SAVE_ACCVGPR_END
659    s_add_u32	    s_save_alloc_size, s_save_alloc_size, 0x1000		    //add 0x1000 since we compare m0 against it later
660#endif
661
662    s_mov_b32 m0, 0x0 //VGPR initial index value =0
663    s_set_gpr_idx_on m0, 0x1 //M0[7:0] = M0[7:0] and M0[15:12] = 0x1
664
665if SAVE_AFTER_XNACK_ERROR
666    check_if_tcp_store_ok()
667    s_cbranch_scc1 L_SAVE_ACCVGPR_LOOP
668
669L_SAVE_ACCVGPR_LOOP_SQC:
670    for var vgpr = 0; vgpr < 4; ++ vgpr
671        v_accvgpr_read v[vgpr], acc[vgpr]  // v[N] = acc[N+m0]
672    end
673
674    write_vgprs_to_mem_with_sqc(v0, 4, s_save_buf_rsrc0, s_save_mem_offset)
675
676    s_add_u32 m0, m0, 4
677    s_cmp_lt_u32 m0, s_save_alloc_size
678    s_cbranch_scc1 L_SAVE_ACCVGPR_LOOP_SQC
679
680    s_set_gpr_idx_off
681    s_branch L_SAVE_ACCVGPR_END
682end
683
684L_SAVE_ACCVGPR_LOOP:
685    for var vgpr = 0; vgpr < 4; ++ vgpr
686        v_accvgpr_read v[vgpr], acc[vgpr]  // v[N] = acc[N+m0]
687    end
688
689    write_4vgprs_to_mem(s_save_buf_rsrc0, s_save_mem_offset)
690
691    s_add_u32 m0, m0, 4
692    s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4
693    s_cmp_lt_u32 m0, s_save_alloc_size
694    s_cbranch_scc1 L_SAVE_ACCVGPR_LOOP
695    s_set_gpr_idx_off
696
697L_SAVE_ACCVGPR_END:
698#endif
699
700    s_branch	L_END_PGM
701
702
703
704/**************************************************************************/
705/*			restore routine					  */
706/**************************************************************************/
707
708L_RESTORE:
709    /*	    Setup Resource Contants    */
710    s_mov_b32	    s_restore_buf_rsrc0,    s_restore_spi_init_lo							    //base_addr_lo
711    s_and_b32	    s_restore_buf_rsrc1,    s_restore_spi_init_hi, 0x0000FFFF						    //base_addr_hi
712    s_or_b32	    s_restore_buf_rsrc1,    s_restore_buf_rsrc1,  S_RESTORE_BUF_RSRC_WORD1_STRIDE
713    s_mov_b32	    s_restore_buf_rsrc2,    0										    //NUM_RECORDS initial value = 0 (in bytes)
714    s_mov_b32	    s_restore_buf_rsrc3,    S_RESTORE_BUF_RSRC_WORD3_MISC
715
716    /*	    global mem offset		*/
717//  s_mov_b32	    s_restore_mem_offset, 0x0				    //mem offset initial value = 0
718
719    /*	    the first wave in the threadgroup	 */
720    s_and_b32	    s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_FIRST_WAVE_MASK
721    s_cbranch_scc0  L_RESTORE_VGPR
722
723    /*		restore LDS	*/
724    //////////////////////////////
725  L_RESTORE_LDS:
726
727    s_mov_b32	    exec_lo, 0xFFFFFFFF							    //need every thread from now on   //be consistent with SAVE although can be moved ahead
728    s_mov_b32	    exec_hi, 0xFFFFFFFF
729
730    s_getreg_b32    s_restore_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE)		//lds_size
731    s_and_b32	    s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF		    //lds_size is zero?
732    s_cbranch_scc0  L_RESTORE_VGPR							    //no lds used? jump to L_RESTORE_VGPR
733    s_lshl_b32	    s_restore_alloc_size, s_restore_alloc_size, 6			    //LDS size in dwords = lds_size * 64dw
734    s_lshl_b32	    s_restore_alloc_size, s_restore_alloc_size, 2			    //LDS size in bytes
735    s_mov_b32	    s_restore_buf_rsrc2,    s_restore_alloc_size			    //NUM_RECORDS in bytes
736
737    // LDS at offset: size(VGPR)+SIZE(SGPR)+SIZE(HWREG)
738    //
739    get_vgpr_size_bytes(s_restore_mem_offset)
740    get_sgpr_size_bytes(s_restore_tmp)
741    s_add_u32  s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp
742    s_add_u32  s_restore_mem_offset, s_restore_mem_offset, get_hwreg_size_bytes()	     //FIXME, Check if offset overflow???
743
744
745	s_mov_b32	s_restore_buf_rsrc2,  0x1000000					    //NUM_RECORDS in bytes
746    s_mov_b32	    m0, 0x0								    //lds_offset initial value = 0
747
748  L_RESTORE_LDS_LOOP:
749	buffer_load_dword   v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1		       // first 64DW
750	buffer_load_dword   v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 offset:256	       // second 64DW
751    s_add_u32	    m0, m0, 256*2						// 128 DW
752    s_add_u32	    s_restore_mem_offset, s_restore_mem_offset, 256*2		//mem offset increased by 128DW
753    s_cmp_lt_u32    m0, s_restore_alloc_size					//scc=(m0 < s_restore_alloc_size) ? 1 : 0
754    s_cbranch_scc1  L_RESTORE_LDS_LOOP							    //LDS restore is complete?
755
756
757    /*		restore VGPRs	    */
758    //////////////////////////////
759  L_RESTORE_VGPR:
760    s_mov_b32	    exec_lo, 0xFFFFFFFF							    //need every thread from now on   //be consistent with SAVE although can be moved ahead
761    s_mov_b32	    exec_hi, 0xFFFFFFFF
762    s_mov_b32	    s_restore_buf_rsrc2,  0x1000000					    //NUM_RECORDS in bytes
763
764    // Save ARCH VGPRs 4-N, then all ACC VGPRs, then ARCH VGPRs 0-3.
765    get_num_arch_vgprs(s_restore_alloc_size)
766    s_add_u32	    s_restore_alloc_size, s_restore_alloc_size, 0x8000			    //add 0x8000 since we compare m0 against it later
767
768    // ARCH VGPRs at offset: 0
769    s_mov_b32	    s_restore_mem_offset, 0x0
770    s_mov_b32	    s_restore_mem_offset_save, s_restore_mem_offset	// restore start with v1, v0 will be the last
771    s_add_u32	    s_restore_mem_offset, s_restore_mem_offset, 256*4
772    s_mov_b32	    m0, 4				//VGPR initial index value = 1
773    s_set_gpr_idx_on	m0, 0x8								    //M0[7:0] = M0[7:0] and M0[15:12] = 0x8
774
775  L_RESTORE_VGPR_LOOP:
776    read_4vgprs_from_mem(s_restore_buf_rsrc0, s_restore_mem_offset)
777    v_mov_b32	    v0, v0								    //v[0+m0] = v0
778    v_mov_b32	    v1, v1
779    v_mov_b32	    v2, v2
780    v_mov_b32	    v3, v3
781    s_add_u32	    m0, m0, 4								    //next vgpr index
782    s_add_u32	    s_restore_mem_offset, s_restore_mem_offset, 256*4				//every buffer_load_dword does 256 bytes
783    s_cmp_lt_u32    m0, s_restore_alloc_size						    //scc = (m0 < s_restore_alloc_size) ? 1 : 0
784    s_cbranch_scc1  L_RESTORE_VGPR_LOOP							    //VGPR restore (except v0) is complete?
785
786#if ASIC_FAMILY >= CHIP_ALDEBARAN
787    // ACC VGPR count may differ from ARCH VGPR count.
788    get_num_acc_vgprs(s_restore_alloc_size, s_restore_tmp2)
789    s_and_b32       s_restore_alloc_size, s_restore_alloc_size, s_restore_alloc_size
790    s_cbranch_scc0  L_RESTORE_ACCVGPR_END
791    s_add_u32	    s_restore_alloc_size, s_restore_alloc_size, 0x8000			    //add 0x8000 since we compare m0 against it later
792#endif
793
794#if ASIC_FAMILY >= CHIP_ARCTURUS
795    // ACC VGPRs at offset: size(ARCH VGPRs)
796    s_mov_b32	    m0, 0
797    s_set_gpr_idx_on	m0, 0x8								    //M0[7:0] = M0[7:0] and M0[15:12] = 0x8
798
799  L_RESTORE_ACCVGPR_LOOP:
800    read_4vgprs_from_mem(s_restore_buf_rsrc0, s_restore_mem_offset)
801
802    for var vgpr = 0; vgpr < 4; ++ vgpr
803        v_accvgpr_write acc[vgpr], v[vgpr]
804    end
805
806    s_add_u32	    m0, m0, 4								    //next vgpr index
807    s_add_u32	    s_restore_mem_offset, s_restore_mem_offset, 256*4			    //every buffer_load_dword does 256 bytes
808    s_cmp_lt_u32    m0, s_restore_alloc_size						    //scc = (m0 < s_restore_alloc_size) ? 1 : 0
809    s_cbranch_scc1  L_RESTORE_ACCVGPR_LOOP						    //VGPR restore (except v0) is complete?
810  L_RESTORE_ACCVGPR_END:
811#endif
812
813    s_set_gpr_idx_off
814
815    // Restore VGPRs 0-3 last, no longer needed.
816    read_4vgprs_from_mem(s_restore_buf_rsrc0, s_restore_mem_offset_save)
817
818    /*		restore SGPRs	    */
819    //////////////////////////////
820
821    // SGPR SR memory offset : size(VGPR)
822    get_vgpr_size_bytes(s_restore_mem_offset)
823    get_sgpr_size_bytes(s_restore_tmp)
824    s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp
825    s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 16*4	   // restore SGPR from S[n] to S[0], by 16 sgprs group
826    // TODO, change RSRC word to rearrange memory layout for SGPRS
827
828    s_getreg_b32    s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE)		    //spgr_size
829    s_add_u32	    s_restore_alloc_size, s_restore_alloc_size, 1
830    s_lshl_b32	    s_restore_alloc_size, s_restore_alloc_size, 4			    //Number of SGPRs = (sgpr_size + 1) * 16   (non-zero value)
831
832	s_lshl_b32	s_restore_buf_rsrc2,	s_restore_alloc_size, 2			    //NUM_RECORDS in bytes
833	s_mov_b32	s_restore_buf_rsrc2,  0x1000000					    //NUM_RECORDS in bytes
834
835    s_mov_b32 m0, s_restore_alloc_size
836
837 L_RESTORE_SGPR_LOOP:
838    read_16sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset)	 //PV: further performance improvement can be made
839    s_waitcnt	    lgkmcnt(0)								    //ensure data ready
840
841    s_sub_u32 m0, m0, 16    // Restore from S[n] to S[0]
842    s_nop 0 // hazard SALU M0=> S_MOVREL
843
844    s_movreld_b64   s0, s0	//s[0+m0] = s0
845    s_movreld_b64   s2, s2
846    s_movreld_b64   s4, s4
847    s_movreld_b64   s6, s6
848    s_movreld_b64   s8, s8
849    s_movreld_b64   s10, s10
850    s_movreld_b64   s12, s12
851    s_movreld_b64   s14, s14
852
853    s_cmp_eq_u32    m0, 0		//scc = (m0 < s_restore_alloc_size) ? 1 : 0
854    s_cbranch_scc0  L_RESTORE_SGPR_LOOP		    //SGPR restore (except s0) is complete?
855
856    /*	    restore HW registers    */
857    //////////////////////////////
858  L_RESTORE_HWREG:
859
860
861    // HWREG SR memory offset : size(VGPR)+size(SGPR)
862    get_vgpr_size_bytes(s_restore_mem_offset)
863    get_sgpr_size_bytes(s_restore_tmp)
864    s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp
865
866
867    s_mov_b32	    s_restore_buf_rsrc2, 0x4						    //NUM_RECORDS   in bytes
868	s_mov_b32	s_restore_buf_rsrc2,  0x1000000					    //NUM_RECORDS in bytes
869
870    read_hwreg_from_mem(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset)		    //M0
871    read_hwreg_from_mem(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset)		//PC
872    read_hwreg_from_mem(s_restore_pc_hi, s_restore_buf_rsrc0, s_restore_mem_offset)
873    read_hwreg_from_mem(s_restore_exec_lo, s_restore_buf_rsrc0, s_restore_mem_offset)		    //EXEC
874    read_hwreg_from_mem(s_restore_exec_hi, s_restore_buf_rsrc0, s_restore_mem_offset)
875    read_hwreg_from_mem(s_restore_status, s_restore_buf_rsrc0, s_restore_mem_offset)		    //STATUS
876    read_hwreg_from_mem(s_restore_trapsts, s_restore_buf_rsrc0, s_restore_mem_offset)		    //TRAPSTS
877    read_hwreg_from_mem(xnack_mask_lo, s_restore_buf_rsrc0, s_restore_mem_offset)		    //XNACK_MASK_LO
878    read_hwreg_from_mem(xnack_mask_hi, s_restore_buf_rsrc0, s_restore_mem_offset)		    //XNACK_MASK_HI
879    read_hwreg_from_mem(s_restore_mode, s_restore_buf_rsrc0, s_restore_mem_offset)		//MODE
880
881    s_waitcnt	    lgkmcnt(0)											    //from now on, it is safe to restore STATUS and IB_STS
882
883    s_mov_b32	    m0,		s_restore_m0
884    s_mov_b32	    exec_lo,	s_restore_exec_lo
885    s_mov_b32	    exec_hi,	s_restore_exec_hi
886
887    s_and_b32	    s_restore_m0, SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK, s_restore_trapsts
888    s_setreg_b32    hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE), s_restore_m0
889    s_and_b32	    s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK, s_restore_trapsts
890    s_lshr_b32	    s_restore_m0, s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT
891    s_setreg_b32    hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE), s_restore_m0
892    //s_setreg_b32  hwreg(HW_REG_TRAPSTS),  s_restore_trapsts	   //don't overwrite SAVECTX bit as it may be set through external SAVECTX during restore
893    s_setreg_b32    hwreg(HW_REG_MODE),	    s_restore_mode
894
895    // Restore trap temporaries 4-11, 13 initialized by SPI debug dispatch logic
896    // ttmp SR memory offset : size(VGPR)+size(SGPR)+0x40
897    get_vgpr_size_bytes(s_restore_ttmps_lo)
898    get_sgpr_size_bytes(s_restore_ttmps_hi)
899    s_add_u32	    s_restore_ttmps_lo, s_restore_ttmps_lo, s_restore_ttmps_hi
900    s_add_u32	    s_restore_ttmps_lo, s_restore_ttmps_lo, s_restore_buf_rsrc0
901    s_addc_u32	    s_restore_ttmps_hi, s_restore_buf_rsrc1, 0x0
902    s_and_b32	    s_restore_ttmps_hi, s_restore_ttmps_hi, 0xFFFF
903    s_load_dwordx4  [ttmp4, ttmp5, ttmp6, ttmp7], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x50 glc:1
904    s_load_dwordx4  [ttmp8, ttmp9, ttmp10, ttmp11], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x60 glc:1
905    s_load_dword    ttmp13, [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x74 glc:1
906    s_waitcnt	    lgkmcnt(0)
907
908    restore_ib_sts(s_restore_tmp)
909
910    s_and_b32 s_restore_pc_hi, s_restore_pc_hi, 0x0000ffff	//pc[47:32]	   //Do it here in order not to affect STATUS
911    s_and_b64	 exec, exec, exec  // Restore STATUS.EXECZ, not writable by s_setreg_b32
912    s_and_b64	 vcc, vcc, vcc	// Restore STATUS.VCCZ, not writable by s_setreg_b32
913    set_status_without_spi_prio(s_restore_status, s_restore_tmp) // SCC is included, which is changed by previous salu
914
915    s_barrier							//barrier to ensure the readiness of LDS before access attempts from any other wave in the same TG //FIXME not performance-optimal at this time
916
917    s_rfe_b64 s_restore_pc_lo					//Return to the main shader program and resume execution
918
919
920/**************************************************************************/
921/*			the END						  */
922/**************************************************************************/
923L_END_PGM:
924    s_endpgm
925
926end
927
928
929/**************************************************************************/
930/*			the helper functions				  */
931/**************************************************************************/
932
933//Only for save hwreg to mem
934function write_hwreg_to_mem(s, s_rsrc, s_mem_offset)
935	s_mov_b32 exec_lo, m0			//assuming exec_lo is not needed anymore from this point on
936	s_mov_b32 m0, s_mem_offset
937	s_buffer_store_dword s, s_rsrc, m0	glc:1
938	ack_sqc_store_workaround()
939	s_add_u32	s_mem_offset, s_mem_offset, 4
940	s_mov_b32   m0, exec_lo
941end
942
943
944// HWREG are saved before SGPRs, so all HWREG could be use.
945function write_16sgpr_to_mem(s, s_rsrc, s_mem_offset)
946
947	s_buffer_store_dwordx4 s[0], s_rsrc, 0	glc:1
948	ack_sqc_store_workaround()
949	s_buffer_store_dwordx4 s[4], s_rsrc, 16	 glc:1
950	ack_sqc_store_workaround()
951	s_buffer_store_dwordx4 s[8], s_rsrc, 32	 glc:1
952	ack_sqc_store_workaround()
953	s_buffer_store_dwordx4 s[12], s_rsrc, 48 glc:1
954	ack_sqc_store_workaround()
955	s_add_u32	s_rsrc[0], s_rsrc[0], 4*16
956	s_addc_u32	s_rsrc[1], s_rsrc[1], 0x0	      // +scc
957end
958
959
960function read_hwreg_from_mem(s, s_rsrc, s_mem_offset)
961    s_buffer_load_dword s, s_rsrc, s_mem_offset	    glc:1
962    s_add_u32	    s_mem_offset, s_mem_offset, 4
963end
964
965function read_16sgpr_from_mem(s, s_rsrc, s_mem_offset)
966    s_buffer_load_dwordx16 s, s_rsrc, s_mem_offset	glc:1
967    s_sub_u32	    s_mem_offset, s_mem_offset, 4*16
968end
969
970function check_if_tcp_store_ok
971	// If STATUS.ALLOW_REPLAY=0 and TRAPSTS.XNACK_ERROR=1 then TCP stores will fail.
972	s_and_b32 s_save_tmp, s_save_status, SQ_WAVE_STATUS_ALLOW_REPLAY_MASK
973	s_cbranch_scc1 L_TCP_STORE_CHECK_DONE
974
975	s_getreg_b32 s_save_tmp, hwreg(HW_REG_TRAPSTS)
976	s_andn2_b32 s_save_tmp, SQ_WAVE_TRAPSTS_XNACK_ERROR_MASK, s_save_tmp
977
978L_TCP_STORE_CHECK_DONE:
979end
980
981function write_4vgprs_to_mem(s_rsrc, s_mem_offset)
982	buffer_store_dword v0, v0, s_rsrc, s_mem_offset slc:1 glc:1
983	buffer_store_dword v1, v0, s_rsrc, s_mem_offset slc:1 glc:1  offset:256
984	buffer_store_dword v2, v0, s_rsrc, s_mem_offset slc:1 glc:1  offset:256*2
985	buffer_store_dword v3, v0, s_rsrc, s_mem_offset slc:1 glc:1  offset:256*3
986end
987
988function read_4vgprs_from_mem(s_rsrc, s_mem_offset)
989	buffer_load_dword v0, v0, s_rsrc, s_mem_offset slc:1 glc:1
990	buffer_load_dword v1, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256
991	buffer_load_dword v2, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*2
992	buffer_load_dword v3, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*3
993	s_waitcnt vmcnt(0)
994end
995
996function write_vgpr_to_mem_with_sqc(v, s_rsrc, s_mem_offset)
997	s_mov_b32 s4, 0
998
999L_WRITE_VGPR_LANE_LOOP:
1000	for var lane = 0; lane < 4; ++ lane
1001		v_readlane_b32 s[lane], v, s4
1002		s_add_u32 s4, s4, 1
1003	end
1004
1005	s_buffer_store_dwordx4 s[0:3], s_rsrc, s_mem_offset glc:1
1006	ack_sqc_store_workaround()
1007
1008	s_add_u32 s_mem_offset, s_mem_offset, 0x10
1009	s_cmp_eq_u32 s4, 0x40
1010	s_cbranch_scc0 L_WRITE_VGPR_LANE_LOOP
1011end
1012
1013function write_vgprs_to_mem_with_sqc(v, n_vgprs, s_rsrc, s_mem_offset)
1014	for var vgpr = 0; vgpr < n_vgprs; ++ vgpr
1015		write_vgpr_to_mem_with_sqc(v[vgpr], s_rsrc, s_mem_offset)
1016	end
1017end
1018
1019function get_lds_size_bytes(s_lds_size_byte)
1020    // SQ LDS granularity is 64DW, while PGM_RSRC2.lds_size is in granularity 128DW
1021    s_getreg_b32   s_lds_size_byte, hwreg(HW_REG_LDS_ALLOC, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE)		// lds_size
1022    s_lshl_b32	   s_lds_size_byte, s_lds_size_byte, 8			    //LDS size in dwords = lds_size * 64 *4Bytes    // granularity 64DW
1023end
1024
1025function get_vgpr_size_bytes(s_vgpr_size_byte)
1026    s_getreg_b32   s_vgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE)	 //vpgr_size
1027    s_add_u32	   s_vgpr_size_byte, s_vgpr_size_byte, 1
1028    s_lshl_b32	   s_vgpr_size_byte, s_vgpr_size_byte, (2+8) //Number of VGPRs = (vgpr_size + 1) * 4 * 64 * 4	(non-zero value)   //FIXME for GFX, zero is possible
1029
1030#if ASIC_FAMILY >= CHIP_ARCTURUS
1031    s_lshl_b32     s_vgpr_size_byte, s_vgpr_size_byte, 1  // Double size for ACC VGPRs
1032#endif
1033end
1034
1035function get_sgpr_size_bytes(s_sgpr_size_byte)
1036    s_getreg_b32   s_sgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE)	 //spgr_size
1037    s_add_u32	   s_sgpr_size_byte, s_sgpr_size_byte, 1
1038    s_lshl_b32	   s_sgpr_size_byte, s_sgpr_size_byte, 6 //Number of SGPRs = (sgpr_size + 1) * 16 *4   (non-zero value)
1039end
1040
1041function get_hwreg_size_bytes
1042    return 128 //HWREG size 128 bytes
1043end
1044
1045function get_num_arch_vgprs(s_num_arch_vgprs)
1046#if ASIC_FAMILY >= CHIP_ALDEBARAN
1047    // VGPR count includes ACC VGPRs, use ACC VGPR offset for ARCH VGPR count.
1048    s_getreg_b32    s_num_arch_vgprs, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_ACCV_OFFSET_SHIFT,SQ_WAVE_GPR_ALLOC_ACCV_OFFSET_SIZE)
1049#else
1050    s_getreg_b32    s_num_arch_vgprs, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE)
1051#endif
1052
1053    // Number of VGPRs = (vgpr_size + 1) * 4
1054    s_add_u32	    s_num_arch_vgprs, s_num_arch_vgprs, 1
1055    s_lshl_b32	    s_num_arch_vgprs, s_num_arch_vgprs, 2
1056end
1057
1058#if ASIC_FAMILY >= CHIP_ALDEBARAN
1059function get_num_acc_vgprs(s_num_acc_vgprs, s_tmp)
1060    // VGPR count = (GPR_ALLOC.VGPR_SIZE + 1) * 8
1061    s_getreg_b32    s_num_acc_vgprs, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE)
1062    s_add_u32	    s_num_acc_vgprs, s_num_acc_vgprs, 1
1063    s_lshl_b32	    s_num_acc_vgprs, s_num_acc_vgprs, 3
1064
1065    // ACC VGPR count = VGPR count - ARCH VGPR count.
1066    get_num_arch_vgprs(s_tmp)
1067    s_sub_u32	    s_num_acc_vgprs, s_num_acc_vgprs, s_tmp
1068end
1069#endif
1070
1071function ack_sqc_store_workaround
1072    if ACK_SQC_STORE
1073        s_waitcnt lgkmcnt(0)
1074    end
1075end
1076
1077function set_status_without_spi_prio(status, tmp)
1078    // Do not restore STATUS.SPI_PRIO since scheduler may have raised it.
1079    s_lshr_b32      tmp, status, SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT
1080    s_setreg_b32    hwreg(HW_REG_STATUS, SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT, SQ_WAVE_STATUS_POST_SPI_PRIO_SIZE), tmp
1081    s_nop           0x2 // avoid S_SETREG => S_SETREG hazard
1082    s_setreg_b32    hwreg(HW_REG_STATUS, SQ_WAVE_STATUS_PRE_SPI_PRIO_SHIFT, SQ_WAVE_STATUS_PRE_SPI_PRIO_SIZE), status
1083end
1084
1085function save_and_clear_ib_sts(tmp)
1086    // Save IB_STS.FIRST_REPLAY[15] and IB_STS.RCNT[20:16] into unused space s_save_ib_sts[31:26].
1087    s_getreg_b32    tmp, hwreg(HW_REG_IB_STS)
1088    s_and_b32       tmp, tmp, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK
1089    s_lshl_b32      tmp, tmp, (TTMP_SAVE_RCNT_FIRST_REPLAY_SHIFT - SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT)
1090    s_andn2_b32     s_save_ib_sts, s_save_ib_sts, TTMP_SAVE_RCNT_FIRST_REPLAY_MASK
1091    s_or_b32        s_save_ib_sts, s_save_ib_sts, tmp
1092    s_setreg_imm32_b32 hwreg(HW_REG_IB_STS), 0x0
1093end
1094
1095function restore_ib_sts(tmp)
1096    s_lshr_b32      tmp, s_save_ib_sts, (TTMP_SAVE_RCNT_FIRST_REPLAY_SHIFT - SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT)
1097    s_and_b32       tmp, tmp, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK
1098    s_setreg_b32    hwreg(HW_REG_IB_STS), tmp
1099end
1100