1/* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23/* To compile this assembly code: 24 * PROJECT=greenland ./sp3 cwsr_trap_handler_gfx9.asm -hex tmp.hex 25 */ 26 27/* HW (GFX9) source code for CWSR trap handler */ 28/* Version 18 + multiple trap handler */ 29 30// this performance-optimal version was originally from Seven Xu at SRDC 31 32// Revison #18 --... 33/* Rev History 34** #1. Branch from gc dv. //gfxip/gfx9/main/src/test/suites/block/cs/sr/cs_trap_handler.sp3#1,#50, #51, #52-53(Skip, Already Fixed by PV), #54-56(merged),#57-58(mergerd, skiped-already fixed by PV) 35** #4. SR Memory Layout: 36** 1. VGPR-SGPR-HWREG-{LDS} 37** 2. tba_hi.bits.26 - reconfigured as the first wave in tg bits, for defer Save LDS for a threadgroup.. performance concern.. 38** #5. Update: 1. Accurate g8sr_ts_save_d timestamp 39** #6. Update: 1. Fix s_barrier usage; 2. VGPR s/r using swizzle buffer?(NoNeed, already matched the swizzle pattern, more investigation) 40** #7. Update: 1. don't barrier if noLDS 41** #8. Branch: 1. Branch to ver#0, which is very similar to gc dv version 42** 2. Fix SQ issue by s_sleep 2 43** #9. Update: 1. Fix scc restore failed issue, restore wave_status at last 44** 2. optimize s_buffer save by burst 16sgprs... 45** #10. Update 1. Optimize restore sgpr by busrt 16 sgprs. 46** #11. Update 1. Add 2 more timestamp for debug version 47** #12. Update 1. Add VGPR SR using DWx4, some case improve and some case drop performance 48** #13. Integ 1. Always use MUBUF for PV trap shader... 49** #14. Update 1. s_buffer_store soft clause... 50** #15. Update 1. PERF - sclar write with glc:0/mtype0 to allow L2 combine. perf improvement a lot. 51** #16. Update 1. PRRF - UNROLL LDS_DMA got 2500cycle save in IP tree 52** #17. Update 1. FUNC - LDS_DMA has issues while ATC, replace with ds_read/buffer_store for save part[TODO restore part] 53** 2. PERF - Save LDS before save VGPR to cover LDS save long latency... 54** #18. Update 1. FUNC - Implicitly estore STATUS.VCCZ, which is not writable by s_setreg_b32 55** 2. FUNC - Handle non-CWSR traps 56*/ 57 58var G8SR_WDMEM_HWREG_OFFSET = 0 59var G8SR_WDMEM_SGPR_OFFSET = 128 // in bytes 60 61// Keep definition same as the app shader, These 2 time stamps are part of the app shader... Should before any Save and after restore. 62 63var G8SR_DEBUG_TIMESTAMP = 0 64var G8SR_DEBUG_TS_SAVE_D_OFFSET = 40*4 // ts_save_d timestamp offset relative to SGPR_SR_memory_offset 65var s_g8sr_ts_save_s = s[34:35] // save start 66var s_g8sr_ts_sq_save_msg = s[36:37] // The save shader send SAVEWAVE msg to spi 67var s_g8sr_ts_spi_wrexec = s[38:39] // the SPI write the sr address to SQ 68var s_g8sr_ts_save_d = s[40:41] // save end 69var s_g8sr_ts_restore_s = s[42:43] // restore start 70var s_g8sr_ts_restore_d = s[44:45] // restore end 71 72var G8SR_VGPR_SR_IN_DWX4 = 0 73var G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 = 0x00100000 // DWx4 stride is 4*4Bytes 74var G8SR_RESTORE_BUF_RSRC_WORD1_STRIDE_DWx4 = G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 75 76 77/*************************************************************************/ 78/* control on how to run the shader */ 79/*************************************************************************/ 80//any hack that needs to be made to run this code in EMU (either because various EMU code are not ready or no compute save & restore in EMU run) 81var EMU_RUN_HACK = 0 82var EMU_RUN_HACK_RESTORE_NORMAL = 0 83var EMU_RUN_HACK_SAVE_NORMAL_EXIT = 0 84var EMU_RUN_HACK_SAVE_SINGLE_WAVE = 0 85var EMU_RUN_HACK_SAVE_FIRST_TIME = 0 //for interrupted restore in which the first save is through EMU_RUN_HACK 86var SAVE_LDS = 1 87var WG_BASE_ADDR_LO = 0x9000a000 88var WG_BASE_ADDR_HI = 0x0 89var WAVE_SPACE = 0x5000 //memory size that each wave occupies in workgroup state mem 90var CTX_SAVE_CONTROL = 0x0 91var CTX_RESTORE_CONTROL = CTX_SAVE_CONTROL 92var SIM_RUN_HACK = 0 //any hack that needs to be made to run this code in SIM (either because various RTL code are not ready or no compute save & restore in RTL run) 93var SGPR_SAVE_USE_SQC = 1 //use SQC D$ to do the write 94var USE_MTBUF_INSTEAD_OF_MUBUF = 0 //because TC EMU currently asserts on 0 of // overload DFMT field to carry 4 more bits of stride for MUBUF opcodes 95var SWIZZLE_EN = 0 //whether we use swizzled buffer addressing 96var ACK_SQC_STORE = 1 //workaround for suspected SQC store bug causing incorrect stores under concurrency 97 98/**************************************************************************/ 99/* variables */ 100/**************************************************************************/ 101var SQ_WAVE_STATUS_INST_ATC_SHIFT = 23 102var SQ_WAVE_STATUS_INST_ATC_MASK = 0x00800000 103var SQ_WAVE_STATUS_SPI_PRIO_SHIFT = 1 104var SQ_WAVE_STATUS_SPI_PRIO_MASK = 0x00000006 105var SQ_WAVE_STATUS_HALT_MASK = 0x2000 106var SQ_WAVE_STATUS_PRE_SPI_PRIO_SHIFT = 0 107var SQ_WAVE_STATUS_PRE_SPI_PRIO_SIZE = 1 108var SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT = 3 109var SQ_WAVE_STATUS_POST_SPI_PRIO_SIZE = 29 110 111var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT = 12 112var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE = 9 113var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 8 114var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE = 6 115var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT = 24 116var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE = 3 //FIXME sq.blk still has 4 bits at this time while SQ programming guide has 3 bits 117 118var SQ_WAVE_TRAPSTS_SAVECTX_MASK = 0x400 119var SQ_WAVE_TRAPSTS_EXCE_MASK = 0x1FF // Exception mask 120var SQ_WAVE_TRAPSTS_SAVECTX_SHIFT = 10 121var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK = 0x100 122var SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT = 8 123var SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK = 0x3FF 124var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT = 0x0 125var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE = 10 126var SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK = 0xFFFFF800 127var SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT = 11 128var SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE = 21 129var SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK = 0x800 130 131var SQ_WAVE_IB_STS_RCNT_SHIFT = 16 //FIXME 132var SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT = 15 //FIXME 133var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK = 0x1F8000 134var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG = 0x00007FFF //FIXME 135 136var SQ_BUF_RSRC_WORD1_ATC_SHIFT = 24 137var SQ_BUF_RSRC_WORD3_MTYPE_SHIFT = 27 138 139var TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT = 26 // bits [31:26] unused by SPI debug data 140var TTMP11_SAVE_RCNT_FIRST_REPLAY_MASK = 0xFC000000 141 142/* Save */ 143var S_SAVE_BUF_RSRC_WORD1_STRIDE = 0x00040000 //stride is 4 bytes 144var S_SAVE_BUF_RSRC_WORD3_MISC = 0x00807FAC //SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14] when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE 145 146var S_SAVE_SPI_INIT_ATC_MASK = 0x08000000 //bit[27]: ATC bit 147var S_SAVE_SPI_INIT_ATC_SHIFT = 27 148var S_SAVE_SPI_INIT_MTYPE_MASK = 0x70000000 //bit[30:28]: Mtype 149var S_SAVE_SPI_INIT_MTYPE_SHIFT = 28 150var S_SAVE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG 151var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT = 26 152 153var S_SAVE_PC_HI_RCNT_SHIFT = 27 //FIXME check with Brian to ensure all fields other than PC[47:0] can be used 154var S_SAVE_PC_HI_RCNT_MASK = 0xF8000000 //FIXME 155var S_SAVE_PC_HI_FIRST_REPLAY_SHIFT = 26 //FIXME 156var S_SAVE_PC_HI_FIRST_REPLAY_MASK = 0x04000000 //FIXME 157 158var s_save_spi_init_lo = exec_lo 159var s_save_spi_init_hi = exec_hi 160 161var s_save_pc_lo = ttmp0 //{TTMP1, TTMP0} = {3'h0,pc_rewind[3:0], HT[0],trapID[7:0], PC[47:0]} 162var s_save_pc_hi = ttmp1 163var s_save_exec_lo = ttmp2 164var s_save_exec_hi = ttmp3 165var s_save_tmp = ttmp14 166var s_save_trapsts = ttmp15 //not really used until the end of the SAVE routine 167var s_save_xnack_mask_lo = ttmp6 168var s_save_xnack_mask_hi = ttmp7 169var s_save_buf_rsrc0 = ttmp8 170var s_save_buf_rsrc1 = ttmp9 171var s_save_buf_rsrc2 = ttmp10 172var s_save_buf_rsrc3 = ttmp11 173var s_save_status = ttmp12 174var s_save_mem_offset = ttmp4 175var s_save_alloc_size = s_save_trapsts //conflict 176var s_save_m0 = ttmp5 177var s_save_ttmps_lo = s_save_tmp //no conflict 178var s_save_ttmps_hi = s_save_trapsts //no conflict 179 180/* Restore */ 181var S_RESTORE_BUF_RSRC_WORD1_STRIDE = S_SAVE_BUF_RSRC_WORD1_STRIDE 182var S_RESTORE_BUF_RSRC_WORD3_MISC = S_SAVE_BUF_RSRC_WORD3_MISC 183 184var S_RESTORE_SPI_INIT_ATC_MASK = 0x08000000 //bit[27]: ATC bit 185var S_RESTORE_SPI_INIT_ATC_SHIFT = 27 186var S_RESTORE_SPI_INIT_MTYPE_MASK = 0x70000000 //bit[30:28]: Mtype 187var S_RESTORE_SPI_INIT_MTYPE_SHIFT = 28 188var S_RESTORE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG 189var S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT = 26 190 191var S_RESTORE_PC_HI_RCNT_SHIFT = S_SAVE_PC_HI_RCNT_SHIFT 192var S_RESTORE_PC_HI_RCNT_MASK = S_SAVE_PC_HI_RCNT_MASK 193var S_RESTORE_PC_HI_FIRST_REPLAY_SHIFT = S_SAVE_PC_HI_FIRST_REPLAY_SHIFT 194var S_RESTORE_PC_HI_FIRST_REPLAY_MASK = S_SAVE_PC_HI_FIRST_REPLAY_MASK 195 196var s_restore_spi_init_lo = exec_lo 197var s_restore_spi_init_hi = exec_hi 198 199var s_restore_mem_offset = ttmp12 200var s_restore_alloc_size = ttmp3 201var s_restore_tmp = ttmp2 202var s_restore_mem_offset_save = s_restore_tmp //no conflict 203 204var s_restore_m0 = s_restore_alloc_size //no conflict 205 206var s_restore_mode = ttmp7 207 208var s_restore_pc_lo = ttmp0 209var s_restore_pc_hi = ttmp1 210var s_restore_exec_lo = ttmp4 211var s_restore_exec_hi = ttmp5 212var s_restore_status = ttmp14 213var s_restore_trapsts = ttmp15 214var s_restore_xnack_mask_lo = xnack_mask_lo 215var s_restore_xnack_mask_hi = xnack_mask_hi 216var s_restore_buf_rsrc0 = ttmp8 217var s_restore_buf_rsrc1 = ttmp9 218var s_restore_buf_rsrc2 = ttmp10 219var s_restore_buf_rsrc3 = ttmp11 220var s_restore_ttmps_lo = s_restore_tmp //no conflict 221var s_restore_ttmps_hi = s_restore_alloc_size //no conflict 222 223/**************************************************************************/ 224/* trap handler entry points */ 225/**************************************************************************/ 226/* Shader Main*/ 227 228shader main 229 asic(GFX9) 230 type(CS) 231 232 233 if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL)) //hack to use trap_id for determining save/restore 234 //FIXME VCCZ un-init assertion s_getreg_b32 s_save_status, hwreg(HW_REG_STATUS) //save STATUS since we will change SCC 235 s_and_b32 s_save_tmp, s_save_pc_hi, 0xffff0000 //change SCC 236 s_cmp_eq_u32 s_save_tmp, 0x007e0000 //Save: trap_id = 0x7e. Restore: trap_id = 0x7f. 237 s_cbranch_scc0 L_JUMP_TO_RESTORE //do not need to recover STATUS here since we are going to RESTORE 238 //FIXME s_setreg_b32 hwreg(HW_REG_STATUS), s_save_status //need to recover STATUS since we are going to SAVE 239 s_branch L_SKIP_RESTORE //NOT restore, SAVE actually 240 else 241 s_branch L_SKIP_RESTORE //NOT restore. might be a regular trap or save 242 end 243 244L_JUMP_TO_RESTORE: 245 s_branch L_RESTORE //restore 246 247L_SKIP_RESTORE: 248 249 s_getreg_b32 s_save_status, hwreg(HW_REG_STATUS) //save STATUS since we will change SCC 250 s_andn2_b32 s_save_status, s_save_status, SQ_WAVE_STATUS_SPI_PRIO_MASK //check whether this is for save 251 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 252 s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK //check whether this is for save 253 s_cbranch_scc1 L_SAVE //this is the operation for save 254 255 // ********* Handle non-CWSR traps ******************* 256if (!EMU_RUN_HACK) 257 // Illegal instruction is a non-maskable exception which blocks context save. 258 // Halt the wavefront and return from the trap. 259 s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK 260 s_cbranch_scc1 L_HALT_WAVE 261 262 // If STATUS.MEM_VIOL is asserted then we cannot fetch from the TMA. 263 // Instead, halt the wavefront and return from the trap. 264 s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_MEM_VIOL_MASK 265 s_cbranch_scc0 L_FETCH_2ND_TRAP 266 267L_HALT_WAVE: 268 // If STATUS.HALT is set then this fault must come from SQC instruction fetch. 269 // We cannot prevent further faults. Spin wait until context saved. 270 s_and_b32 ttmp2, s_save_status, SQ_WAVE_STATUS_HALT_MASK 271 s_cbranch_scc0 L_NOT_ALREADY_HALTED 272 273L_WAIT_CTX_SAVE: 274 s_sleep 0x10 275 s_getreg_b32 ttmp2, hwreg(HW_REG_TRAPSTS) 276 s_and_b32 ttmp2, ttmp2, SQ_WAVE_TRAPSTS_SAVECTX_MASK 277 s_cbranch_scc0 L_WAIT_CTX_SAVE 278 279L_NOT_ALREADY_HALTED: 280 s_or_b32 s_save_status, s_save_status, SQ_WAVE_STATUS_HALT_MASK 281 282 // If the PC points to S_ENDPGM then context save will fail if STATUS.HALT is set. 283 // Rewind the PC to prevent this from occurring. The debugger compensates for this. 284 s_sub_u32 ttmp0, ttmp0, 0x8 285 s_subb_u32 ttmp1, ttmp1, 0x0 286 287L_FETCH_2ND_TRAP: 288 // Preserve and clear scalar XNACK state before issuing scalar reads. 289 // Save IB_STS.FIRST_REPLAY[15] and IB_STS.RCNT[20:16] into unused space ttmp11[31:26]. 290 s_getreg_b32 ttmp2, hwreg(HW_REG_IB_STS) 291 s_and_b32 ttmp3, ttmp2, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK 292 s_lshl_b32 ttmp3, ttmp3, (TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT - SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT) 293 s_andn2_b32 ttmp11, ttmp11, TTMP11_SAVE_RCNT_FIRST_REPLAY_MASK 294 s_or_b32 ttmp11, ttmp11, ttmp3 295 296 s_andn2_b32 ttmp2, ttmp2, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK 297 s_setreg_b32 hwreg(HW_REG_IB_STS), ttmp2 298 299 // Read second-level TBA/TMA from first-level TMA and jump if available. 300 // ttmp[2:5] and ttmp12 can be used (others hold SPI-initialized debug data) 301 // ttmp12 holds SQ_WAVE_STATUS 302 s_getreg_b32 ttmp14, hwreg(HW_REG_SQ_SHADER_TMA_LO) 303 s_getreg_b32 ttmp15, hwreg(HW_REG_SQ_SHADER_TMA_HI) 304 s_lshl_b64 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 305 s_load_dwordx2 [ttmp2, ttmp3], [ttmp14, ttmp15], 0x0 glc:1 // second-level TBA 306 s_waitcnt lgkmcnt(0) 307 s_load_dwordx2 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 glc:1 // second-level TMA 308 s_waitcnt lgkmcnt(0) 309 s_and_b64 [ttmp2, ttmp3], [ttmp2, ttmp3], [ttmp2, ttmp3] 310 s_cbranch_scc0 L_NO_NEXT_TRAP // second-level trap handler not been set 311 s_setpc_b64 [ttmp2, ttmp3] // jump to second-level trap handler 312 313L_NO_NEXT_TRAP: 314 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 315 s_and_b32 s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_EXCE_MASK // Check whether it is an exception 316 s_cbranch_scc1 L_EXCP_CASE // Exception, jump back to the shader program directly. 317 s_add_u32 ttmp0, ttmp0, 4 // S_TRAP case, add 4 to ttmp0 318 s_addc_u32 ttmp1, ttmp1, 0 319L_EXCP_CASE: 320 s_and_b32 ttmp1, ttmp1, 0xFFFF 321 322 // Restore SQ_WAVE_IB_STS. 323 s_lshr_b32 ttmp2, ttmp11, (TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT - SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT) 324 s_and_b32 ttmp2, ttmp2, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK 325 s_setreg_b32 hwreg(HW_REG_IB_STS), ttmp2 326 327 // Restore SQ_WAVE_STATUS. 328 s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32 329 s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32 330 set_status_without_spi_prio(s_save_status, ttmp2) 331 332 s_rfe_b64 [ttmp0, ttmp1] 333end 334 // ********* End handling of non-CWSR traps ******************* 335 336/**************************************************************************/ 337/* save routine */ 338/**************************************************************************/ 339 340L_SAVE: 341 342if G8SR_DEBUG_TIMESTAMP 343 s_memrealtime s_g8sr_ts_save_s 344 s_waitcnt lgkmcnt(0) //FIXME, will cause xnack?? 345end 346 347 s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff //pc[47:32] 348 349 s_mov_b32 s_save_tmp, 0 //clear saveCtx bit 350 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_SAVECTX_SHIFT, 1), s_save_tmp //clear saveCtx bit 351 352 s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_RCNT_SHIFT, SQ_WAVE_IB_STS_RCNT_SIZE) //save RCNT 353 s_lshl_b32 s_save_tmp, s_save_tmp, S_SAVE_PC_HI_RCNT_SHIFT 354 s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp 355 s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT, SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE) //save FIRST_REPLAY 356 s_lshl_b32 s_save_tmp, s_save_tmp, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT 357 s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp 358 s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS) //clear RCNT and FIRST_REPLAY in IB_STS 359 s_and_b32 s_save_tmp, s_save_tmp, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG 360 361 s_setreg_b32 hwreg(HW_REG_IB_STS), s_save_tmp 362 363 /* inform SPI the readiness and wait for SPI's go signal */ 364 s_mov_b32 s_save_exec_lo, exec_lo //save EXEC and use EXEC for the go signal from SPI 365 s_mov_b32 s_save_exec_hi, exec_hi 366 s_mov_b64 exec, 0x0 //clear EXEC to get ready to receive 367 368if G8SR_DEBUG_TIMESTAMP 369 s_memrealtime s_g8sr_ts_sq_save_msg 370 s_waitcnt lgkmcnt(0) 371end 372 373 if (EMU_RUN_HACK) 374 375 else 376 s_sendmsg sendmsg(MSG_SAVEWAVE) //send SPI a message and wait for SPI's write to EXEC 377 end 378 379 // Set SPI_PRIO=2 to avoid starving instruction fetch in the waves we're waiting for. 380 s_or_b32 s_save_tmp, s_save_status, (2 << SQ_WAVE_STATUS_SPI_PRIO_SHIFT) 381 s_setreg_b32 hwreg(HW_REG_STATUS), s_save_tmp 382 383 L_SLEEP: 384 s_sleep 0x2 // sleep 1 (64clk) is not enough for 8 waves per SIMD, which will cause SQ hang, since the 7,8th wave could not get arbit to exec inst, while other waves are stuck into the sleep-loop and waiting for wrexec!=0 385 386 if (EMU_RUN_HACK) 387 388 else 389 s_cbranch_execz L_SLEEP 390 end 391 392if G8SR_DEBUG_TIMESTAMP 393 s_memrealtime s_g8sr_ts_spi_wrexec 394 s_waitcnt lgkmcnt(0) 395end 396 397 if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_SINGLE_WAVE)) 398 //calculate wd_addr using absolute thread id 399 v_readlane_b32 s_save_tmp, v9, 0 400 s_lshr_b32 s_save_tmp, s_save_tmp, 6 401 s_mul_i32 s_save_tmp, s_save_tmp, WAVE_SPACE 402 s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO 403 s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI 404 s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL 405 else 406 end 407 if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_SINGLE_WAVE)) 408 s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO 409 s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI 410 s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL 411 else 412 end 413 414 // Save trap temporaries 4-11, 13 initialized by SPI debug dispatch logic 415 // ttmp SR memory offset : size(VGPR)+size(SGPR)+0x40 416 get_vgpr_size_bytes(s_save_ttmps_lo) 417 get_sgpr_size_bytes(s_save_ttmps_hi) 418 s_add_u32 s_save_ttmps_lo, s_save_ttmps_lo, s_save_ttmps_hi 419 s_add_u32 s_save_ttmps_lo, s_save_ttmps_lo, s_save_spi_init_lo 420 s_addc_u32 s_save_ttmps_hi, s_save_spi_init_hi, 0x0 421 s_and_b32 s_save_ttmps_hi, s_save_ttmps_hi, 0xFFFF 422 s_store_dwordx4 [ttmp4, ttmp5, ttmp6, ttmp7], [s_save_ttmps_lo, s_save_ttmps_hi], 0x50 glc:1 423 ack_sqc_store_workaround() 424 s_store_dwordx4 [ttmp8, ttmp9, ttmp10, ttmp11], [s_save_ttmps_lo, s_save_ttmps_hi], 0x60 glc:1 425 ack_sqc_store_workaround() 426 s_store_dword ttmp13, [s_save_ttmps_lo, s_save_ttmps_hi], 0x74 glc:1 427 ack_sqc_store_workaround() 428 429 /* setup Resource Contants */ 430 s_mov_b32 s_save_buf_rsrc0, s_save_spi_init_lo //base_addr_lo 431 s_and_b32 s_save_buf_rsrc1, s_save_spi_init_hi, 0x0000FFFF //base_addr_hi 432 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE 433 s_mov_b32 s_save_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) although not neccessarily inited 434 s_mov_b32 s_save_buf_rsrc3, S_SAVE_BUF_RSRC_WORD3_MISC 435 s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_ATC_MASK 436 s_lshr_b32 s_save_tmp, s_save_tmp, (S_SAVE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT) //get ATC bit into position 437 s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, s_save_tmp //or ATC 438 s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_MTYPE_MASK 439 s_lshr_b32 s_save_tmp, s_save_tmp, (S_SAVE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT) //get MTYPE bits into position 440 s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, s_save_tmp //or MTYPE 441 442 //FIXME right now s_save_m0/s_save_mem_offset use tma_lo/tma_hi (might need to save them before using them?) 443 s_mov_b32 s_save_m0, m0 //save M0 444 445 /* global mem offset */ 446 s_mov_b32 s_save_mem_offset, 0x0 //mem offset initial value = 0 447 448 449 450 451 /* save HW registers */ 452 ////////////////////////////// 453 454 L_SAVE_HWREG: 455 // HWREG SR memory offset : size(VGPR)+size(SGPR) 456 get_vgpr_size_bytes(s_save_mem_offset) 457 get_sgpr_size_bytes(s_save_tmp) 458 s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp 459 460 461 s_mov_b32 s_save_buf_rsrc2, 0x4 //NUM_RECORDS in bytes 462 if (SWIZZLE_EN) 463 s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 464 else 465 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 466 end 467 468 469 write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) //M0 470 471 if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_FIRST_TIME)) 472 s_add_u32 s_save_pc_lo, s_save_pc_lo, 4 //pc[31:0]+4 473 s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0 //carry bit over 474 end 475 476 write_hwreg_to_mem(s_save_pc_lo, s_save_buf_rsrc0, s_save_mem_offset) //PC 477 write_hwreg_to_mem(s_save_pc_hi, s_save_buf_rsrc0, s_save_mem_offset) 478 write_hwreg_to_mem(s_save_exec_lo, s_save_buf_rsrc0, s_save_mem_offset) //EXEC 479 write_hwreg_to_mem(s_save_exec_hi, s_save_buf_rsrc0, s_save_mem_offset) 480 write_hwreg_to_mem(s_save_status, s_save_buf_rsrc0, s_save_mem_offset) //STATUS 481 482 //s_save_trapsts conflicts with s_save_alloc_size 483 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 484 write_hwreg_to_mem(s_save_trapsts, s_save_buf_rsrc0, s_save_mem_offset) //TRAPSTS 485 486 write_hwreg_to_mem(xnack_mask_lo, s_save_buf_rsrc0, s_save_mem_offset) //XNACK_MASK_LO 487 write_hwreg_to_mem(xnack_mask_hi, s_save_buf_rsrc0, s_save_mem_offset) //XNACK_MASK_HI 488 489 //use s_save_tmp would introduce conflict here between s_save_tmp and s_save_buf_rsrc2 490 s_getreg_b32 s_save_m0, hwreg(HW_REG_MODE) //MODE 491 write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) 492 493 494 495 /* the first wave in the threadgroup */ 496 s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK // extract fisrt wave bit 497 s_mov_b32 s_save_exec_hi, 0x0 498 s_or_b32 s_save_exec_hi, s_save_tmp, s_save_exec_hi // save first wave bit to s_save_exec_hi.bits[26] 499 500 501 /* save SGPRs */ 502 // Save SGPR before LDS save, then the s0 to s4 can be used during LDS save... 503 ////////////////////////////// 504 505 // SGPR SR memory offset : size(VGPR) 506 get_vgpr_size_bytes(s_save_mem_offset) 507 // TODO, change RSRC word to rearrange memory layout for SGPRS 508 509 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size 510 s_add_u32 s_save_alloc_size, s_save_alloc_size, 1 511 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 4 //Number of SGPRs = (sgpr_size + 1) * 16 (non-zero value) 512 513 if (SGPR_SAVE_USE_SQC) 514 s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 2 //NUM_RECORDS in bytes 515 else 516 s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 8 //NUM_RECORDS in bytes (64 threads) 517 end 518 519 if (SWIZZLE_EN) 520 s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 521 else 522 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 523 end 524 525 526 // backup s_save_buf_rsrc0,1 to s_save_pc_lo/hi, since write_16sgpr_to_mem function will change the rsrc0 527 //s_mov_b64 s_save_pc_lo, s_save_buf_rsrc0 528 s_mov_b64 s_save_xnack_mask_lo, s_save_buf_rsrc0 529 s_add_u32 s_save_buf_rsrc0, s_save_buf_rsrc0, s_save_mem_offset 530 s_addc_u32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0 531 532 s_mov_b32 m0, 0x0 //SGPR initial index value =0 533 s_nop 0x0 //Manually inserted wait states 534 L_SAVE_SGPR_LOOP: 535 // SGPR is allocated in 16 SGPR granularity 536 s_movrels_b64 s0, s0 //s0 = s[0+m0], s1 = s[1+m0] 537 s_movrels_b64 s2, s2 //s2 = s[2+m0], s3 = s[3+m0] 538 s_movrels_b64 s4, s4 //s4 = s[4+m0], s5 = s[5+m0] 539 s_movrels_b64 s6, s6 //s6 = s[6+m0], s7 = s[7+m0] 540 s_movrels_b64 s8, s8 //s8 = s[8+m0], s9 = s[9+m0] 541 s_movrels_b64 s10, s10 //s10 = s[10+m0], s11 = s[11+m0] 542 s_movrels_b64 s12, s12 //s12 = s[12+m0], s13 = s[13+m0] 543 s_movrels_b64 s14, s14 //s14 = s[14+m0], s15 = s[15+m0] 544 545 write_16sgpr_to_mem(s0, s_save_buf_rsrc0, s_save_mem_offset) //PV: the best performance should be using s_buffer_store_dwordx4 546 s_add_u32 m0, m0, 16 //next sgpr index 547 s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 548 s_cbranch_scc1 L_SAVE_SGPR_LOOP //SGPR save is complete? 549 // restore s_save_buf_rsrc0,1 550 //s_mov_b64 s_save_buf_rsrc0, s_save_pc_lo 551 s_mov_b64 s_save_buf_rsrc0, s_save_xnack_mask_lo 552 553 554 555 556 /* save first 4 VGPR, then LDS save could use */ 557 // each wave will alloc 4 vgprs at least... 558 ///////////////////////////////////////////////////////////////////////////////////// 559 560 s_mov_b32 s_save_mem_offset, 0 561 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 562 s_mov_b32 exec_hi, 0xFFFFFFFF 563 s_mov_b32 xnack_mask_lo, 0x0 564 s_mov_b32 xnack_mask_hi, 0x0 565 566 if (SWIZZLE_EN) 567 s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 568 else 569 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 570 end 571 572 573 // VGPR Allocated in 4-GPR granularity 574 575if G8SR_VGPR_SR_IN_DWX4 576 // the const stride for DWx4 is 4*4 bytes 577 s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 578 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 // const stride to 4*4 bytes 579 580 buffer_store_dwordx4 v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 581 582 s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 583 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE // reset const stride to 4 bytes 584else 585 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 586 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256 587 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2 588 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3 589end 590 591 592 593 /* save LDS */ 594 ////////////////////////////// 595 596 L_SAVE_LDS: 597 598 // Change EXEC to all threads... 599 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 600 s_mov_b32 exec_hi, 0xFFFFFFFF 601 602 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) //lds_size 603 s_and_b32 s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF //lds_size is zero? 604 s_cbranch_scc0 L_SAVE_LDS_DONE //no lds used? jump to L_SAVE_DONE 605 606 s_barrier //LDS is used? wait for other waves in the same TG 607 s_and_b32 s_save_tmp, s_save_exec_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK //exec is still used here 608 s_cbranch_scc0 L_SAVE_LDS_DONE 609 610 // first wave do LDS save; 611 612 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 6 //LDS size in dwords = lds_size * 64dw 613 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 2 //LDS size in bytes 614 s_mov_b32 s_save_buf_rsrc2, s_save_alloc_size //NUM_RECORDS in bytes 615 616 // LDS at offset: size(VGPR)+SIZE(SGPR)+SIZE(HWREG) 617 // 618 get_vgpr_size_bytes(s_save_mem_offset) 619 get_sgpr_size_bytes(s_save_tmp) 620 s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp 621 s_add_u32 s_save_mem_offset, s_save_mem_offset, get_hwreg_size_bytes() 622 623 624 if (SWIZZLE_EN) 625 s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 626 else 627 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 628 end 629 630 s_mov_b32 m0, 0x0 //lds_offset initial value = 0 631 632 633var LDS_DMA_ENABLE = 0 634var UNROLL = 0 635if UNROLL==0 && LDS_DMA_ENABLE==1 636 s_mov_b32 s3, 256*2 637 s_nop 0 638 s_nop 0 639 s_nop 0 640 L_SAVE_LDS_LOOP: 641 //TODO: looks the 2 buffer_store/load clause for s/r will hurt performance.??? 642 if (SAVE_LDS) //SPI always alloc LDS space in 128DW granularity 643 buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 // first 64DW 644 buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:256 // second 64DW 645 end 646 647 s_add_u32 m0, m0, s3 //every buffer_store_lds does 256 bytes 648 s_add_u32 s_save_mem_offset, s_save_mem_offset, s3 //mem offset increased by 256 bytes 649 s_cmp_lt_u32 m0, s_save_alloc_size //scc=(m0 < s_save_alloc_size) ? 1 : 0 650 s_cbranch_scc1 L_SAVE_LDS_LOOP //LDS save is complete? 651 652elsif LDS_DMA_ENABLE==1 && UNROLL==1 // UNROOL , has ichace miss 653 // store from higest LDS address to lowest 654 s_mov_b32 s3, 256*2 655 s_sub_u32 m0, s_save_alloc_size, s3 656 s_add_u32 s_save_mem_offset, s_save_mem_offset, m0 657 s_lshr_b32 s_save_alloc_size, s_save_alloc_size, 9 // how many 128 trunks... 658 s_sub_u32 s_save_alloc_size, 128, s_save_alloc_size // store from higheset addr to lowest 659 s_mul_i32 s_save_alloc_size, s_save_alloc_size, 6*4 // PC offset increment, each LDS save block cost 6*4 Bytes instruction 660 s_add_u32 s_save_alloc_size, s_save_alloc_size, 3*4 //2is the below 2 inst...//s_addc and s_setpc 661 s_nop 0 662 s_nop 0 663 s_nop 0 //pad 3 dw to let LDS_DMA align with 64Bytes 664 s_getpc_b64 s[0:1] // reuse s[0:1], since s[0:1] already saved 665 s_add_u32 s0, s0,s_save_alloc_size 666 s_addc_u32 s1, s1, 0 667 s_setpc_b64 s[0:1] 668 669 670 for var i =0; i< 128; i++ 671 // be careful to make here a 64Byte aligned address, which could improve performance... 672 buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:0 // first 64DW 673 buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:256 // second 64DW 674 675 if i!=127 676 s_sub_u32 m0, m0, s3 // use a sgpr to shrink 2DW-inst to 1DW inst to improve performance , i.e. pack more LDS_DMA inst to one Cacheline 677 s_sub_u32 s_save_mem_offset, s_save_mem_offset, s3 678 end 679 end 680 681else // BUFFER_STORE 682 v_mbcnt_lo_u32_b32 v2, 0xffffffff, 0x0 683 v_mbcnt_hi_u32_b32 v3, 0xffffffff, v2 // tid 684 v_mul_i32_i24 v2, v3, 8 // tid*8 685 v_mov_b32 v3, 256*2 686 s_mov_b32 m0, 0x10000 687 s_mov_b32 s0, s_save_buf_rsrc3 688 s_and_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, 0xFF7FFFFF // disable add_tid 689 s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, 0x58000 //DFMT 690 691L_SAVE_LDS_LOOP_VECTOR: 692 ds_read_b64 v[0:1], v2 //x =LDS[a], byte address 693 s_waitcnt lgkmcnt(0) 694 buffer_store_dwordx2 v[0:1], v2, s_save_buf_rsrc0, s_save_mem_offset offen:1 glc:1 slc:1 695// s_waitcnt vmcnt(0) 696// v_add_u32 v2, vcc[0:1], v2, v3 697 v_add_u32 v2, v2, v3 698 v_cmp_lt_u32 vcc[0:1], v2, s_save_alloc_size 699 s_cbranch_vccnz L_SAVE_LDS_LOOP_VECTOR 700 701 // restore rsrc3 702 s_mov_b32 s_save_buf_rsrc3, s0 703 704end 705 706L_SAVE_LDS_DONE: 707 708 709 /* save VGPRs - set the Rest VGPRs */ 710 ////////////////////////////////////////////////////////////////////////////////////// 711 L_SAVE_VGPR: 712 // VGPR SR memory offset: 0 713 // TODO rearrange the RSRC words to use swizzle for VGPR save... 714 715 s_mov_b32 s_save_mem_offset, (0+256*4) // for the rest VGPRs 716 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 717 s_mov_b32 exec_hi, 0xFFFFFFFF 718 719 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) //vpgr_size 720 s_add_u32 s_save_alloc_size, s_save_alloc_size, 1 721 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value) //FIXME for GFX, zero is possible 722 s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 8 //NUM_RECORDS in bytes (64 threads*4) 723 if (SWIZZLE_EN) 724 s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 725 else 726 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 727 end 728 729 730 // VGPR Allocated in 4-GPR granularity 731 732if G8SR_VGPR_SR_IN_DWX4 733 // the const stride for DWx4 is 4*4 bytes 734 s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 735 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 // const stride to 4*4 bytes 736 737 s_mov_b32 m0, 4 // skip first 4 VGPRs 738 s_cmp_lt_u32 m0, s_save_alloc_size 739 s_cbranch_scc0 L_SAVE_VGPR_LOOP_END // no more vgprs 740 741 s_set_gpr_idx_on m0, 0x1 // This will change M0 742 s_add_u32 s_save_alloc_size, s_save_alloc_size, 0x1000 // because above inst change m0 743L_SAVE_VGPR_LOOP: 744 v_mov_b32 v0, v0 // v0 = v[0+m0] 745 v_mov_b32 v1, v1 746 v_mov_b32 v2, v2 747 v_mov_b32 v3, v3 748 749 750 buffer_store_dwordx4 v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 751 s_add_u32 m0, m0, 4 752 s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 753 s_cmp_lt_u32 m0, s_save_alloc_size 754 s_cbranch_scc1 L_SAVE_VGPR_LOOP //VGPR save is complete? 755 s_set_gpr_idx_off 756L_SAVE_VGPR_LOOP_END: 757 758 s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 759 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE // reset const stride to 4 bytes 760else 761 // VGPR store using dw burst 762 s_mov_b32 m0, 0x4 //VGPR initial index value =0 763 s_cmp_lt_u32 m0, s_save_alloc_size 764 s_cbranch_scc0 L_SAVE_VGPR_END 765 766 767 s_set_gpr_idx_on m0, 0x1 //M0[7:0] = M0[7:0] and M0[15:12] = 0x1 768 s_add_u32 s_save_alloc_size, s_save_alloc_size, 0x1000 //add 0x1000 since we compare m0 against it later 769 770 L_SAVE_VGPR_LOOP: 771 v_mov_b32 v0, v0 //v0 = v[0+m0] 772 v_mov_b32 v1, v1 //v0 = v[0+m0] 773 v_mov_b32 v2, v2 //v0 = v[0+m0] 774 v_mov_b32 v3, v3 //v0 = v[0+m0] 775 776 if(USE_MTBUF_INSTEAD_OF_MUBUF) 777 tbuffer_store_format_x v0, v0, s_save_buf_rsrc0, s_save_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1 778 else 779 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 780 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256 781 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2 782 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3 783 end 784 785 s_add_u32 m0, m0, 4 //next vgpr index 786 s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 //every buffer_store_dword does 256 bytes 787 s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 788 s_cbranch_scc1 L_SAVE_VGPR_LOOP //VGPR save is complete? 789 s_set_gpr_idx_off 790end 791 792L_SAVE_VGPR_END: 793 794 795 796 797 798 799 /* S_PGM_END_SAVED */ //FIXME graphics ONLY 800 if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_NORMAL_EXIT)) 801 s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff //pc[47:32] 802 s_add_u32 s_save_pc_lo, s_save_pc_lo, 4 //pc[31:0]+4 803 s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0 //carry bit over 804 s_rfe_b64 s_save_pc_lo //Return to the main shader program 805 else 806 end 807 808// Save Done timestamp 809if G8SR_DEBUG_TIMESTAMP 810 s_memrealtime s_g8sr_ts_save_d 811 // SGPR SR memory offset : size(VGPR) 812 get_vgpr_size_bytes(s_save_mem_offset) 813 s_add_u32 s_save_mem_offset, s_save_mem_offset, G8SR_DEBUG_TS_SAVE_D_OFFSET 814 s_waitcnt lgkmcnt(0) //FIXME, will cause xnack?? 815 // Need reset rsrc2?? 816 s_mov_b32 m0, s_save_mem_offset 817 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 818 s_buffer_store_dwordx2 s_g8sr_ts_save_d, s_save_buf_rsrc0, m0 glc:1 819end 820 821 822 s_branch L_END_PGM 823 824 825 826/**************************************************************************/ 827/* restore routine */ 828/**************************************************************************/ 829 830L_RESTORE: 831 /* Setup Resource Contants */ 832 if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL)) 833 //calculate wd_addr using absolute thread id 834 v_readlane_b32 s_restore_tmp, v9, 0 835 s_lshr_b32 s_restore_tmp, s_restore_tmp, 6 836 s_mul_i32 s_restore_tmp, s_restore_tmp, WAVE_SPACE 837 s_add_i32 s_restore_spi_init_lo, s_restore_tmp, WG_BASE_ADDR_LO 838 s_mov_b32 s_restore_spi_init_hi, WG_BASE_ADDR_HI 839 s_and_b32 s_restore_spi_init_hi, s_restore_spi_init_hi, CTX_RESTORE_CONTROL 840 else 841 end 842 843if G8SR_DEBUG_TIMESTAMP 844 s_memrealtime s_g8sr_ts_restore_s 845 s_waitcnt lgkmcnt(0) //FIXME, will cause xnack?? 846 // tma_lo/hi are sgpr 110, 111, which will not used for 112 SGPR allocated case... 847 s_mov_b32 s_restore_pc_lo, s_g8sr_ts_restore_s[0] 848 s_mov_b32 s_restore_pc_hi, s_g8sr_ts_restore_s[1] //backup ts to ttmp0/1, sicne exec will be finally restored.. 849end 850 851 852 853 s_mov_b32 s_restore_buf_rsrc0, s_restore_spi_init_lo //base_addr_lo 854 s_and_b32 s_restore_buf_rsrc1, s_restore_spi_init_hi, 0x0000FFFF //base_addr_hi 855 s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE 856 s_mov_b32 s_restore_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) 857 s_mov_b32 s_restore_buf_rsrc3, S_RESTORE_BUF_RSRC_WORD3_MISC 858 s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_ATC_MASK 859 s_lshr_b32 s_restore_tmp, s_restore_tmp, (S_RESTORE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT) //get ATC bit into position 860 s_or_b32 s_restore_buf_rsrc3, s_restore_buf_rsrc3, s_restore_tmp //or ATC 861 s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_MTYPE_MASK 862 s_lshr_b32 s_restore_tmp, s_restore_tmp, (S_RESTORE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT) //get MTYPE bits into position 863 s_or_b32 s_restore_buf_rsrc3, s_restore_buf_rsrc3, s_restore_tmp //or MTYPE 864 865 /* global mem offset */ 866// s_mov_b32 s_restore_mem_offset, 0x0 //mem offset initial value = 0 867 868 /* the first wave in the threadgroup */ 869 s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_FIRST_WAVE_MASK 870 s_cbranch_scc0 L_RESTORE_VGPR 871 872 /* restore LDS */ 873 ////////////////////////////// 874 L_RESTORE_LDS: 875 876 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on //be consistent with SAVE although can be moved ahead 877 s_mov_b32 exec_hi, 0xFFFFFFFF 878 879 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) //lds_size 880 s_and_b32 s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF //lds_size is zero? 881 s_cbranch_scc0 L_RESTORE_VGPR //no lds used? jump to L_RESTORE_VGPR 882 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 6 //LDS size in dwords = lds_size * 64dw 883 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 2 //LDS size in bytes 884 s_mov_b32 s_restore_buf_rsrc2, s_restore_alloc_size //NUM_RECORDS in bytes 885 886 // LDS at offset: size(VGPR)+SIZE(SGPR)+SIZE(HWREG) 887 // 888 get_vgpr_size_bytes(s_restore_mem_offset) 889 get_sgpr_size_bytes(s_restore_tmp) 890 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 891 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_hwreg_size_bytes() //FIXME, Check if offset overflow??? 892 893 894 if (SWIZZLE_EN) 895 s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 896 else 897 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 898 end 899 s_mov_b32 m0, 0x0 //lds_offset initial value = 0 900 901 L_RESTORE_LDS_LOOP: 902 if (SAVE_LDS) 903 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 // first 64DW 904 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 offset:256 // second 64DW 905 end 906 s_add_u32 m0, m0, 256*2 // 128 DW 907 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*2 //mem offset increased by 128DW 908 s_cmp_lt_u32 m0, s_restore_alloc_size //scc=(m0 < s_restore_alloc_size) ? 1 : 0 909 s_cbranch_scc1 L_RESTORE_LDS_LOOP //LDS restore is complete? 910 911 912 /* restore VGPRs */ 913 ////////////////////////////// 914 L_RESTORE_VGPR: 915 // VGPR SR memory offset : 0 916 s_mov_b32 s_restore_mem_offset, 0x0 917 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on //be consistent with SAVE although can be moved ahead 918 s_mov_b32 exec_hi, 0xFFFFFFFF 919 920 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) //vpgr_size 921 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 1 922 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value) 923 s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 8 //NUM_RECORDS in bytes (64 threads*4) 924 if (SWIZZLE_EN) 925 s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 926 else 927 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 928 end 929 930if G8SR_VGPR_SR_IN_DWX4 931 get_vgpr_size_bytes(s_restore_mem_offset) 932 s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 933 934 // the const stride for DWx4 is 4*4 bytes 935 s_and_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, 0x0000FFFF // reset const stride to 0 936 s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, G8SR_RESTORE_BUF_RSRC_WORD1_STRIDE_DWx4 // const stride to 4*4 bytes 937 938 s_mov_b32 m0, s_restore_alloc_size 939 s_set_gpr_idx_on m0, 0x8 // Note.. This will change m0 940 941L_RESTORE_VGPR_LOOP: 942 buffer_load_dwordx4 v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 943 s_waitcnt vmcnt(0) 944 s_sub_u32 m0, m0, 4 945 v_mov_b32 v0, v0 // v[0+m0] = v0 946 v_mov_b32 v1, v1 947 v_mov_b32 v2, v2 948 v_mov_b32 v3, v3 949 s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 950 s_cmp_eq_u32 m0, 0x8000 951 s_cbranch_scc0 L_RESTORE_VGPR_LOOP 952 s_set_gpr_idx_off 953 954 s_and_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, 0x0000FFFF // reset const stride to 0 955 s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE // const stride to 4*4 bytes 956 957else 958 // VGPR load using dw burst 959 s_mov_b32 s_restore_mem_offset_save, s_restore_mem_offset // restore start with v1, v0 will be the last 960 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 961 s_mov_b32 m0, 4 //VGPR initial index value = 1 962 s_set_gpr_idx_on m0, 0x8 //M0[7:0] = M0[7:0] and M0[15:12] = 0x8 963 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 0x8000 //add 0x8000 since we compare m0 against it later 964 965 L_RESTORE_VGPR_LOOP: 966 if(USE_MTBUF_INSTEAD_OF_MUBUF) 967 tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1 968 else 969 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 970 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256 971 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*2 972 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*3 973 end 974 s_waitcnt vmcnt(0) //ensure data ready 975 v_mov_b32 v0, v0 //v[0+m0] = v0 976 v_mov_b32 v1, v1 977 v_mov_b32 v2, v2 978 v_mov_b32 v3, v3 979 s_add_u32 m0, m0, 4 //next vgpr index 980 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 //every buffer_load_dword does 256 bytes 981 s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0 982 s_cbranch_scc1 L_RESTORE_VGPR_LOOP //VGPR restore (except v0) is complete? 983 s_set_gpr_idx_off 984 /* VGPR restore on v0 */ 985 if(USE_MTBUF_INSTEAD_OF_MUBUF) 986 tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1 987 else 988 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 989 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256 990 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*2 991 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*3 992 end 993 994end 995 996 /* restore SGPRs */ 997 ////////////////////////////// 998 999 // SGPR SR memory offset : size(VGPR) 1000 get_vgpr_size_bytes(s_restore_mem_offset) 1001 get_sgpr_size_bytes(s_restore_tmp) 1002 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 1003 s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 16*4 // restore SGPR from S[n] to S[0], by 16 sgprs group 1004 // TODO, change RSRC word to rearrange memory layout for SGPRS 1005 1006 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size 1007 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 1 1008 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 4 //Number of SGPRs = (sgpr_size + 1) * 16 (non-zero value) 1009 1010 if (SGPR_SAVE_USE_SQC) 1011 s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 2 //NUM_RECORDS in bytes 1012 else 1013 s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 8 //NUM_RECORDS in bytes (64 threads) 1014 end 1015 if (SWIZZLE_EN) 1016 s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 1017 else 1018 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 1019 end 1020 1021 s_mov_b32 m0, s_restore_alloc_size 1022 1023 L_RESTORE_SGPR_LOOP: 1024 read_16sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset) //PV: further performance improvement can be made 1025 s_waitcnt lgkmcnt(0) //ensure data ready 1026 1027 s_sub_u32 m0, m0, 16 // Restore from S[n] to S[0] 1028 s_nop 0 // hazard SALU M0=> S_MOVREL 1029 1030 s_movreld_b64 s0, s0 //s[0+m0] = s0 1031 s_movreld_b64 s2, s2 1032 s_movreld_b64 s4, s4 1033 s_movreld_b64 s6, s6 1034 s_movreld_b64 s8, s8 1035 s_movreld_b64 s10, s10 1036 s_movreld_b64 s12, s12 1037 s_movreld_b64 s14, s14 1038 1039 s_cmp_eq_u32 m0, 0 //scc = (m0 < s_restore_alloc_size) ? 1 : 0 1040 s_cbranch_scc0 L_RESTORE_SGPR_LOOP //SGPR restore (except s0) is complete? 1041 1042 /* restore HW registers */ 1043 ////////////////////////////// 1044 L_RESTORE_HWREG: 1045 1046 1047if G8SR_DEBUG_TIMESTAMP 1048 s_mov_b32 s_g8sr_ts_restore_s[0], s_restore_pc_lo 1049 s_mov_b32 s_g8sr_ts_restore_s[1], s_restore_pc_hi 1050end 1051 1052 // HWREG SR memory offset : size(VGPR)+size(SGPR) 1053 get_vgpr_size_bytes(s_restore_mem_offset) 1054 get_sgpr_size_bytes(s_restore_tmp) 1055 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 1056 1057 1058 s_mov_b32 s_restore_buf_rsrc2, 0x4 //NUM_RECORDS in bytes 1059 if (SWIZZLE_EN) 1060 s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 1061 else 1062 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 1063 end 1064 1065 read_hwreg_from_mem(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset) //M0 1066 read_hwreg_from_mem(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //PC 1067 read_hwreg_from_mem(s_restore_pc_hi, s_restore_buf_rsrc0, s_restore_mem_offset) 1068 read_hwreg_from_mem(s_restore_exec_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //EXEC 1069 read_hwreg_from_mem(s_restore_exec_hi, s_restore_buf_rsrc0, s_restore_mem_offset) 1070 read_hwreg_from_mem(s_restore_status, s_restore_buf_rsrc0, s_restore_mem_offset) //STATUS 1071 read_hwreg_from_mem(s_restore_trapsts, s_restore_buf_rsrc0, s_restore_mem_offset) //TRAPSTS 1072 read_hwreg_from_mem(xnack_mask_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //XNACK_MASK_LO 1073 read_hwreg_from_mem(xnack_mask_hi, s_restore_buf_rsrc0, s_restore_mem_offset) //XNACK_MASK_HI 1074 read_hwreg_from_mem(s_restore_mode, s_restore_buf_rsrc0, s_restore_mem_offset) //MODE 1075 1076 s_waitcnt lgkmcnt(0) //from now on, it is safe to restore STATUS and IB_STS 1077 1078 //for normal save & restore, the saved PC points to the next inst to execute, no adjustment needs to be made, otherwise: 1079 if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL)) 1080 s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 8 //pc[31:0]+8 //two back-to-back s_trap are used (first for save and second for restore) 1081 s_addc_u32 s_restore_pc_hi, s_restore_pc_hi, 0x0 //carry bit over 1082 end 1083 if ((EMU_RUN_HACK) && (EMU_RUN_HACK_RESTORE_NORMAL)) 1084 s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 4 //pc[31:0]+4 // save is hack through s_trap but restore is normal 1085 s_addc_u32 s_restore_pc_hi, s_restore_pc_hi, 0x0 //carry bit over 1086 end 1087 1088 s_mov_b32 m0, s_restore_m0 1089 s_mov_b32 exec_lo, s_restore_exec_lo 1090 s_mov_b32 exec_hi, s_restore_exec_hi 1091 1092 s_and_b32 s_restore_m0, SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK, s_restore_trapsts 1093 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE), s_restore_m0 1094 s_and_b32 s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK, s_restore_trapsts 1095 s_lshr_b32 s_restore_m0, s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT 1096 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE), s_restore_m0 1097 //s_setreg_b32 hwreg(HW_REG_TRAPSTS), s_restore_trapsts //don't overwrite SAVECTX bit as it may be set through external SAVECTX during restore 1098 s_setreg_b32 hwreg(HW_REG_MODE), s_restore_mode 1099 1100 // Restore trap temporaries 4-11, 13 initialized by SPI debug dispatch logic 1101 // ttmp SR memory offset : size(VGPR)+size(SGPR)+0x40 1102 get_vgpr_size_bytes(s_restore_ttmps_lo) 1103 get_sgpr_size_bytes(s_restore_ttmps_hi) 1104 s_add_u32 s_restore_ttmps_lo, s_restore_ttmps_lo, s_restore_ttmps_hi 1105 s_add_u32 s_restore_ttmps_lo, s_restore_ttmps_lo, s_restore_buf_rsrc0 1106 s_addc_u32 s_restore_ttmps_hi, s_restore_buf_rsrc1, 0x0 1107 s_and_b32 s_restore_ttmps_hi, s_restore_ttmps_hi, 0xFFFF 1108 s_load_dwordx4 [ttmp4, ttmp5, ttmp6, ttmp7], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x50 glc:1 1109 s_load_dwordx4 [ttmp8, ttmp9, ttmp10, ttmp11], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x60 glc:1 1110 s_load_dword ttmp13, [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x74 glc:1 1111 s_waitcnt lgkmcnt(0) 1112 1113 //reuse s_restore_m0 as a temp register 1114 s_and_b32 s_restore_m0, s_restore_pc_hi, S_SAVE_PC_HI_RCNT_MASK 1115 s_lshr_b32 s_restore_m0, s_restore_m0, S_SAVE_PC_HI_RCNT_SHIFT 1116 s_lshl_b32 s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_RCNT_SHIFT 1117 s_mov_b32 s_restore_tmp, 0x0 //IB_STS is zero 1118 s_or_b32 s_restore_tmp, s_restore_tmp, s_restore_m0 1119 s_and_b32 s_restore_m0, s_restore_pc_hi, S_SAVE_PC_HI_FIRST_REPLAY_MASK 1120 s_lshr_b32 s_restore_m0, s_restore_m0, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT 1121 s_lshl_b32 s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT 1122 s_or_b32 s_restore_tmp, s_restore_tmp, s_restore_m0 1123 s_and_b32 s_restore_m0, s_restore_status, SQ_WAVE_STATUS_INST_ATC_MASK 1124 s_lshr_b32 s_restore_m0, s_restore_m0, SQ_WAVE_STATUS_INST_ATC_SHIFT 1125 s_setreg_b32 hwreg(HW_REG_IB_STS), s_restore_tmp 1126 1127 s_and_b32 s_restore_pc_hi, s_restore_pc_hi, 0x0000ffff //pc[47:32] //Do it here in order not to affect STATUS 1128 s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32 1129 s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32 1130 set_status_without_spi_prio(s_restore_status, s_restore_tmp) // SCC is included, which is changed by previous salu 1131 1132 s_barrier //barrier to ensure the readiness of LDS before access attempts from any other wave in the same TG //FIXME not performance-optimal at this time 1133 1134if G8SR_DEBUG_TIMESTAMP 1135 s_memrealtime s_g8sr_ts_restore_d 1136 s_waitcnt lgkmcnt(0) 1137end 1138 1139// s_rfe_b64 s_restore_pc_lo //Return to the main shader program and resume execution 1140 s_rfe_restore_b64 s_restore_pc_lo, s_restore_m0 // s_restore_m0[0] is used to set STATUS.inst_atc 1141 1142 1143/**************************************************************************/ 1144/* the END */ 1145/**************************************************************************/ 1146L_END_PGM: 1147 s_endpgm 1148 1149end 1150 1151 1152/**************************************************************************/ 1153/* the helper functions */ 1154/**************************************************************************/ 1155 1156//Only for save hwreg to mem 1157function write_hwreg_to_mem(s, s_rsrc, s_mem_offset) 1158 s_mov_b32 exec_lo, m0 //assuming exec_lo is not needed anymore from this point on 1159 s_mov_b32 m0, s_mem_offset 1160 s_buffer_store_dword s, s_rsrc, m0 glc:1 1161 ack_sqc_store_workaround() 1162 s_add_u32 s_mem_offset, s_mem_offset, 4 1163 s_mov_b32 m0, exec_lo 1164end 1165 1166 1167// HWREG are saved before SGPRs, so all HWREG could be use. 1168function write_16sgpr_to_mem(s, s_rsrc, s_mem_offset) 1169 1170 s_buffer_store_dwordx4 s[0], s_rsrc, 0 glc:1 1171 ack_sqc_store_workaround() 1172 s_buffer_store_dwordx4 s[4], s_rsrc, 16 glc:1 1173 ack_sqc_store_workaround() 1174 s_buffer_store_dwordx4 s[8], s_rsrc, 32 glc:1 1175 ack_sqc_store_workaround() 1176 s_buffer_store_dwordx4 s[12], s_rsrc, 48 glc:1 1177 ack_sqc_store_workaround() 1178 s_add_u32 s_rsrc[0], s_rsrc[0], 4*16 1179 s_addc_u32 s_rsrc[1], s_rsrc[1], 0x0 // +scc 1180end 1181 1182 1183function read_hwreg_from_mem(s, s_rsrc, s_mem_offset) 1184 s_buffer_load_dword s, s_rsrc, s_mem_offset glc:1 1185 s_add_u32 s_mem_offset, s_mem_offset, 4 1186end 1187 1188function read_16sgpr_from_mem(s, s_rsrc, s_mem_offset) 1189 s_buffer_load_dwordx16 s, s_rsrc, s_mem_offset glc:1 1190 s_sub_u32 s_mem_offset, s_mem_offset, 4*16 1191end 1192 1193 1194 1195function get_lds_size_bytes(s_lds_size_byte) 1196 // SQ LDS granularity is 64DW, while PGM_RSRC2.lds_size is in granularity 128DW 1197 s_getreg_b32 s_lds_size_byte, hwreg(HW_REG_LDS_ALLOC, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) // lds_size 1198 s_lshl_b32 s_lds_size_byte, s_lds_size_byte, 8 //LDS size in dwords = lds_size * 64 *4Bytes // granularity 64DW 1199end 1200 1201function get_vgpr_size_bytes(s_vgpr_size_byte) 1202 s_getreg_b32 s_vgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) //vpgr_size 1203 s_add_u32 s_vgpr_size_byte, s_vgpr_size_byte, 1 1204 s_lshl_b32 s_vgpr_size_byte, s_vgpr_size_byte, (2+8) //Number of VGPRs = (vgpr_size + 1) * 4 * 64 * 4 (non-zero value) //FIXME for GFX, zero is possible 1205end 1206 1207function get_sgpr_size_bytes(s_sgpr_size_byte) 1208 s_getreg_b32 s_sgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size 1209 s_add_u32 s_sgpr_size_byte, s_sgpr_size_byte, 1 1210 s_lshl_b32 s_sgpr_size_byte, s_sgpr_size_byte, 6 //Number of SGPRs = (sgpr_size + 1) * 16 *4 (non-zero value) 1211end 1212 1213function get_hwreg_size_bytes 1214 return 128 //HWREG size 128 bytes 1215end 1216 1217function ack_sqc_store_workaround 1218 if ACK_SQC_STORE 1219 s_waitcnt lgkmcnt(0) 1220 end 1221end 1222 1223function set_status_without_spi_prio(status, tmp) 1224 // Do not restore STATUS.SPI_PRIO since scheduler may have raised it. 1225 s_lshr_b32 tmp, status, SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT 1226 s_setreg_b32 hwreg(HW_REG_STATUS, SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT, SQ_WAVE_STATUS_POST_SPI_PRIO_SIZE), tmp 1227 s_nop 0x2 // avoid S_SETREG => S_SETREG hazard 1228 s_setreg_b32 hwreg(HW_REG_STATUS, SQ_WAVE_STATUS_PRE_SPI_PRIO_SHIFT, SQ_WAVE_STATUS_PRE_SPI_PRIO_SIZE), status 1229end 1230