1/* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23/* To compile this assembly code: 24 * PROJECT=greenland ./sp3 cwsr_trap_handler_gfx9.asm -hex tmp.hex 25 */ 26 27/* HW (GFX9) source code for CWSR trap handler */ 28/* Version 18 + multiple trap handler */ 29 30// this performance-optimal version was originally from Seven Xu at SRDC 31 32// Revison #18 --... 33/* Rev History 34** #1. Branch from gc dv. //gfxip/gfx9/main/src/test/suites/block/cs/sr/cs_trap_handler.sp3#1,#50, #51, #52-53(Skip, Already Fixed by PV), #54-56(merged),#57-58(mergerd, skiped-already fixed by PV) 35** #4. SR Memory Layout: 36** 1. VGPR-SGPR-HWREG-{LDS} 37** 2. tba_hi.bits.26 - reconfigured as the first wave in tg bits, for defer Save LDS for a threadgroup.. performance concern.. 38** #5. Update: 1. Accurate g8sr_ts_save_d timestamp 39** #6. Update: 1. Fix s_barrier usage; 2. VGPR s/r using swizzle buffer?(NoNeed, already matched the swizzle pattern, more investigation) 40** #7. Update: 1. don't barrier if noLDS 41** #8. Branch: 1. Branch to ver#0, which is very similar to gc dv version 42** 2. Fix SQ issue by s_sleep 2 43** #9. Update: 1. Fix scc restore failed issue, restore wave_status at last 44** 2. optimize s_buffer save by burst 16sgprs... 45** #10. Update 1. Optimize restore sgpr by busrt 16 sgprs. 46** #11. Update 1. Add 2 more timestamp for debug version 47** #12. Update 1. Add VGPR SR using DWx4, some case improve and some case drop performance 48** #13. Integ 1. Always use MUBUF for PV trap shader... 49** #14. Update 1. s_buffer_store soft clause... 50** #15. Update 1. PERF - sclar write with glc:0/mtype0 to allow L2 combine. perf improvement a lot. 51** #16. Update 1. PRRF - UNROLL LDS_DMA got 2500cycle save in IP tree 52** #17. Update 1. FUNC - LDS_DMA has issues while ATC, replace with ds_read/buffer_store for save part[TODO restore part] 53** 2. PERF - Save LDS before save VGPR to cover LDS save long latency... 54** #18. Update 1. FUNC - Implicitly estore STATUS.VCCZ, which is not writable by s_setreg_b32 55** 2. FUNC - Handle non-CWSR traps 56*/ 57 58var G8SR_WDMEM_HWREG_OFFSET = 0 59var G8SR_WDMEM_SGPR_OFFSET = 128 // in bytes 60 61// Keep definition same as the app shader, These 2 time stamps are part of the app shader... Should before any Save and after restore. 62 63var G8SR_DEBUG_TIMESTAMP = 0 64var G8SR_DEBUG_TS_SAVE_D_OFFSET = 40*4 // ts_save_d timestamp offset relative to SGPR_SR_memory_offset 65var s_g8sr_ts_save_s = s[34:35] // save start 66var s_g8sr_ts_sq_save_msg = s[36:37] // The save shader send SAVEWAVE msg to spi 67var s_g8sr_ts_spi_wrexec = s[38:39] // the SPI write the sr address to SQ 68var s_g8sr_ts_save_d = s[40:41] // save end 69var s_g8sr_ts_restore_s = s[42:43] // restore start 70var s_g8sr_ts_restore_d = s[44:45] // restore end 71 72var G8SR_VGPR_SR_IN_DWX4 = 0 73var G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 = 0x00100000 // DWx4 stride is 4*4Bytes 74var G8SR_RESTORE_BUF_RSRC_WORD1_STRIDE_DWx4 = G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 75 76 77/*************************************************************************/ 78/* control on how to run the shader */ 79/*************************************************************************/ 80//any hack that needs to be made to run this code in EMU (either because various EMU code are not ready or no compute save & restore in EMU run) 81var EMU_RUN_HACK = 0 82var EMU_RUN_HACK_RESTORE_NORMAL = 0 83var EMU_RUN_HACK_SAVE_NORMAL_EXIT = 0 84var EMU_RUN_HACK_SAVE_SINGLE_WAVE = 0 85var EMU_RUN_HACK_SAVE_FIRST_TIME = 0 //for interrupted restore in which the first save is through EMU_RUN_HACK 86var SAVE_LDS = 1 87var WG_BASE_ADDR_LO = 0x9000a000 88var WG_BASE_ADDR_HI = 0x0 89var WAVE_SPACE = 0x5000 //memory size that each wave occupies in workgroup state mem 90var CTX_SAVE_CONTROL = 0x0 91var CTX_RESTORE_CONTROL = CTX_SAVE_CONTROL 92var SIM_RUN_HACK = 0 //any hack that needs to be made to run this code in SIM (either because various RTL code are not ready or no compute save & restore in RTL run) 93var SGPR_SAVE_USE_SQC = 1 //use SQC D$ to do the write 94var USE_MTBUF_INSTEAD_OF_MUBUF = 0 //because TC EMU currently asserts on 0 of // overload DFMT field to carry 4 more bits of stride for MUBUF opcodes 95var SWIZZLE_EN = 0 //whether we use swizzled buffer addressing 96var ACK_SQC_STORE = 1 //workaround for suspected SQC store bug causing incorrect stores under concurrency 97 98/**************************************************************************/ 99/* variables */ 100/**************************************************************************/ 101var SQ_WAVE_STATUS_INST_ATC_SHIFT = 23 102var SQ_WAVE_STATUS_INST_ATC_MASK = 0x00800000 103var SQ_WAVE_STATUS_SPI_PRIO_SHIFT = 1 104var SQ_WAVE_STATUS_SPI_PRIO_MASK = 0x00000006 105var SQ_WAVE_STATUS_HALT_MASK = 0x2000 106var SQ_WAVE_STATUS_PRE_SPI_PRIO_SHIFT = 0 107var SQ_WAVE_STATUS_PRE_SPI_PRIO_SIZE = 1 108var SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT = 3 109var SQ_WAVE_STATUS_POST_SPI_PRIO_SIZE = 29 110 111var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT = 12 112var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE = 9 113var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 8 114var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE = 6 115var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT = 24 116var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE = 3 //FIXME sq.blk still has 4 bits at this time while SQ programming guide has 3 bits 117 118var SQ_WAVE_TRAPSTS_SAVECTX_MASK = 0x400 119var SQ_WAVE_TRAPSTS_EXCE_MASK = 0x1FF // Exception mask 120var SQ_WAVE_TRAPSTS_SAVECTX_SHIFT = 10 121var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK = 0x100 122var SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT = 8 123var SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK = 0x3FF 124var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT = 0x0 125var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE = 10 126var SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK = 0xFFFFF800 127var SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT = 11 128var SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE = 21 129var SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK = 0x800 130 131var SQ_WAVE_IB_STS_RCNT_SHIFT = 16 //FIXME 132var SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT = 15 //FIXME 133var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK = 0x1F8000 134var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG = 0x00007FFF //FIXME 135 136var SQ_BUF_RSRC_WORD1_ATC_SHIFT = 24 137var SQ_BUF_RSRC_WORD3_MTYPE_SHIFT = 27 138 139var TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT = 26 // bits [31:26] unused by SPI debug data 140var TTMP11_SAVE_RCNT_FIRST_REPLAY_MASK = 0xFC000000 141 142/* Save */ 143var S_SAVE_BUF_RSRC_WORD1_STRIDE = 0x00040000 //stride is 4 bytes 144var S_SAVE_BUF_RSRC_WORD3_MISC = 0x00807FAC //SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14] when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE 145 146var S_SAVE_SPI_INIT_ATC_MASK = 0x08000000 //bit[27]: ATC bit 147var S_SAVE_SPI_INIT_ATC_SHIFT = 27 148var S_SAVE_SPI_INIT_MTYPE_MASK = 0x70000000 //bit[30:28]: Mtype 149var S_SAVE_SPI_INIT_MTYPE_SHIFT = 28 150var S_SAVE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG 151var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT = 26 152 153var S_SAVE_PC_HI_RCNT_SHIFT = 28 //FIXME check with Brian to ensure all fields other than PC[47:0] can be used 154var S_SAVE_PC_HI_RCNT_MASK = 0xF0000000 //FIXME 155var S_SAVE_PC_HI_FIRST_REPLAY_SHIFT = 27 //FIXME 156var S_SAVE_PC_HI_FIRST_REPLAY_MASK = 0x08000000 //FIXME 157 158var s_save_spi_init_lo = exec_lo 159var s_save_spi_init_hi = exec_hi 160 161var s_save_pc_lo = ttmp0 //{TTMP1, TTMP0} = {3'h0,pc_rewind[3:0], HT[0],trapID[7:0], PC[47:0]} 162var s_save_pc_hi = ttmp1 163var s_save_exec_lo = ttmp2 164var s_save_exec_hi = ttmp3 165var s_save_tmp = ttmp4 166var s_save_trapsts = ttmp5 //not really used until the end of the SAVE routine 167var s_save_xnack_mask_lo = ttmp6 168var s_save_xnack_mask_hi = ttmp7 169var s_save_buf_rsrc0 = ttmp8 170var s_save_buf_rsrc1 = ttmp9 171var s_save_buf_rsrc2 = ttmp10 172var s_save_buf_rsrc3 = ttmp11 173var s_save_status = ttmp12 174var s_save_mem_offset = ttmp14 175var s_save_alloc_size = s_save_trapsts //conflict 176var s_save_m0 = ttmp15 177var s_save_ttmps_lo = s_save_tmp //no conflict 178var s_save_ttmps_hi = s_save_trapsts //no conflict 179 180/* Restore */ 181var S_RESTORE_BUF_RSRC_WORD1_STRIDE = S_SAVE_BUF_RSRC_WORD1_STRIDE 182var S_RESTORE_BUF_RSRC_WORD3_MISC = S_SAVE_BUF_RSRC_WORD3_MISC 183 184var S_RESTORE_SPI_INIT_ATC_MASK = 0x08000000 //bit[27]: ATC bit 185var S_RESTORE_SPI_INIT_ATC_SHIFT = 27 186var S_RESTORE_SPI_INIT_MTYPE_MASK = 0x70000000 //bit[30:28]: Mtype 187var S_RESTORE_SPI_INIT_MTYPE_SHIFT = 28 188var S_RESTORE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG 189var S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT = 26 190 191var S_RESTORE_PC_HI_RCNT_SHIFT = S_SAVE_PC_HI_RCNT_SHIFT 192var S_RESTORE_PC_HI_RCNT_MASK = S_SAVE_PC_HI_RCNT_MASK 193var S_RESTORE_PC_HI_FIRST_REPLAY_SHIFT = S_SAVE_PC_HI_FIRST_REPLAY_SHIFT 194var S_RESTORE_PC_HI_FIRST_REPLAY_MASK = S_SAVE_PC_HI_FIRST_REPLAY_MASK 195 196var s_restore_spi_init_lo = exec_lo 197var s_restore_spi_init_hi = exec_hi 198 199var s_restore_mem_offset = ttmp12 200var s_restore_alloc_size = ttmp3 201var s_restore_tmp = ttmp2 202var s_restore_mem_offset_save = s_restore_tmp //no conflict 203 204var s_restore_m0 = s_restore_alloc_size //no conflict 205 206var s_restore_mode = ttmp7 207 208var s_restore_pc_lo = ttmp0 209var s_restore_pc_hi = ttmp1 210var s_restore_exec_lo = ttmp14 211var s_restore_exec_hi = ttmp15 212var s_restore_status = ttmp4 213var s_restore_trapsts = ttmp5 214var s_restore_xnack_mask_lo = xnack_mask_lo 215var s_restore_xnack_mask_hi = xnack_mask_hi 216var s_restore_buf_rsrc0 = ttmp8 217var s_restore_buf_rsrc1 = ttmp9 218var s_restore_buf_rsrc2 = ttmp10 219var s_restore_buf_rsrc3 = ttmp11 220var s_restore_ttmps_lo = s_restore_tmp //no conflict 221var s_restore_ttmps_hi = s_restore_alloc_size //no conflict 222 223/**************************************************************************/ 224/* trap handler entry points */ 225/**************************************************************************/ 226/* Shader Main*/ 227 228shader main 229 asic(GFX9) 230 type(CS) 231 232 233 if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL)) //hack to use trap_id for determining save/restore 234 //FIXME VCCZ un-init assertion s_getreg_b32 s_save_status, hwreg(HW_REG_STATUS) //save STATUS since we will change SCC 235 s_and_b32 s_save_tmp, s_save_pc_hi, 0xffff0000 //change SCC 236 s_cmp_eq_u32 s_save_tmp, 0x007e0000 //Save: trap_id = 0x7e. Restore: trap_id = 0x7f. 237 s_cbranch_scc0 L_JUMP_TO_RESTORE //do not need to recover STATUS here since we are going to RESTORE 238 //FIXME s_setreg_b32 hwreg(HW_REG_STATUS), s_save_status //need to recover STATUS since we are going to SAVE 239 s_branch L_SKIP_RESTORE //NOT restore, SAVE actually 240 else 241 s_branch L_SKIP_RESTORE //NOT restore. might be a regular trap or save 242 end 243 244L_JUMP_TO_RESTORE: 245 s_branch L_RESTORE //restore 246 247L_SKIP_RESTORE: 248 249 s_getreg_b32 s_save_status, hwreg(HW_REG_STATUS) //save STATUS since we will change SCC 250 s_andn2_b32 s_save_status, s_save_status, SQ_WAVE_STATUS_SPI_PRIO_MASK //check whether this is for save 251 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 252 s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK //check whether this is for save 253 s_cbranch_scc1 L_SAVE //this is the operation for save 254 255 // ********* Handle non-CWSR traps ******************* 256if (!EMU_RUN_HACK) 257 // Illegal instruction is a non-maskable exception which blocks context save. 258 // Halt the wavefront and return from the trap. 259 s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK 260 s_cbranch_scc1 L_HALT_WAVE 261 262 // If STATUS.MEM_VIOL is asserted then we cannot fetch from the TMA. 263 // Instead, halt the wavefront and return from the trap. 264 s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_MEM_VIOL_MASK 265 s_cbranch_scc0 L_FETCH_2ND_TRAP 266 267L_HALT_WAVE: 268 // If STATUS.HALT is set then this fault must come from SQC instruction fetch. 269 // We cannot prevent further faults so just terminate the wavefront. 270 s_and_b32 ttmp2, s_save_status, SQ_WAVE_STATUS_HALT_MASK 271 s_cbranch_scc0 L_NOT_ALREADY_HALTED 272 s_endpgm 273L_NOT_ALREADY_HALTED: 274 s_or_b32 s_save_status, s_save_status, SQ_WAVE_STATUS_HALT_MASK 275 276 // If the PC points to S_ENDPGM then context save will fail if STATUS.HALT is set. 277 // Rewind the PC to prevent this from occurring. The debugger compensates for this. 278 s_sub_u32 ttmp0, ttmp0, 0x8 279 s_subb_u32 ttmp1, ttmp1, 0x0 280 281L_FETCH_2ND_TRAP: 282 // Preserve and clear scalar XNACK state before issuing scalar reads. 283 // Save IB_STS.FIRST_REPLAY[15] and IB_STS.RCNT[20:16] into unused space ttmp11[31:26]. 284 s_getreg_b32 ttmp2, hwreg(HW_REG_IB_STS) 285 s_and_b32 ttmp3, ttmp2, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK 286 s_lshl_b32 ttmp3, ttmp3, (TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT - SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT) 287 s_andn2_b32 ttmp11, ttmp11, TTMP11_SAVE_RCNT_FIRST_REPLAY_MASK 288 s_or_b32 ttmp11, ttmp11, ttmp3 289 290 s_andn2_b32 ttmp2, ttmp2, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK 291 s_setreg_b32 hwreg(HW_REG_IB_STS), ttmp2 292 293 // Read second-level TBA/TMA from first-level TMA and jump if available. 294 // ttmp[2:5] and ttmp12 can be used (others hold SPI-initialized debug data) 295 // ttmp12 holds SQ_WAVE_STATUS 296 s_getreg_b32 ttmp4, hwreg(HW_REG_SQ_SHADER_TMA_LO) 297 s_getreg_b32 ttmp5, hwreg(HW_REG_SQ_SHADER_TMA_HI) 298 s_lshl_b64 [ttmp4, ttmp5], [ttmp4, ttmp5], 0x8 299 s_load_dwordx2 [ttmp2, ttmp3], [ttmp4, ttmp5], 0x0 glc:1 // second-level TBA 300 s_waitcnt lgkmcnt(0) 301 s_load_dwordx2 [ttmp4, ttmp5], [ttmp4, ttmp5], 0x8 glc:1 // second-level TMA 302 s_waitcnt lgkmcnt(0) 303 s_and_b64 [ttmp2, ttmp3], [ttmp2, ttmp3], [ttmp2, ttmp3] 304 s_cbranch_scc0 L_NO_NEXT_TRAP // second-level trap handler not been set 305 s_setpc_b64 [ttmp2, ttmp3] // jump to second-level trap handler 306 307L_NO_NEXT_TRAP: 308 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 309 s_and_b32 s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_EXCE_MASK // Check whether it is an exception 310 s_cbranch_scc1 L_EXCP_CASE // Exception, jump back to the shader program directly. 311 s_add_u32 ttmp0, ttmp0, 4 // S_TRAP case, add 4 to ttmp0 312 s_addc_u32 ttmp1, ttmp1, 0 313L_EXCP_CASE: 314 s_and_b32 ttmp1, ttmp1, 0xFFFF 315 316 // Restore SQ_WAVE_IB_STS. 317 s_lshr_b32 ttmp2, ttmp11, (TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT - SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT) 318 s_and_b32 ttmp2, ttmp2, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK 319 s_setreg_b32 hwreg(HW_REG_IB_STS), ttmp2 320 321 // Restore SQ_WAVE_STATUS. 322 s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32 323 s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32 324 set_status_without_spi_prio(s_save_status, ttmp2) 325 326 s_rfe_b64 [ttmp0, ttmp1] 327end 328 // ********* End handling of non-CWSR traps ******************* 329 330/**************************************************************************/ 331/* save routine */ 332/**************************************************************************/ 333 334L_SAVE: 335 336if G8SR_DEBUG_TIMESTAMP 337 s_memrealtime s_g8sr_ts_save_s 338 s_waitcnt lgkmcnt(0) //FIXME, will cause xnack?? 339end 340 341 s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff //pc[47:32] 342 343 s_mov_b32 s_save_tmp, 0 //clear saveCtx bit 344 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_SAVECTX_SHIFT, 1), s_save_tmp //clear saveCtx bit 345 346 s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_RCNT_SHIFT, SQ_WAVE_IB_STS_RCNT_SIZE) //save RCNT 347 s_lshl_b32 s_save_tmp, s_save_tmp, S_SAVE_PC_HI_RCNT_SHIFT 348 s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp 349 s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT, SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE) //save FIRST_REPLAY 350 s_lshl_b32 s_save_tmp, s_save_tmp, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT 351 s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp 352 s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS) //clear RCNT and FIRST_REPLAY in IB_STS 353 s_and_b32 s_save_tmp, s_save_tmp, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG 354 355 s_setreg_b32 hwreg(HW_REG_IB_STS), s_save_tmp 356 357 /* inform SPI the readiness and wait for SPI's go signal */ 358 s_mov_b32 s_save_exec_lo, exec_lo //save EXEC and use EXEC for the go signal from SPI 359 s_mov_b32 s_save_exec_hi, exec_hi 360 s_mov_b64 exec, 0x0 //clear EXEC to get ready to receive 361 362if G8SR_DEBUG_TIMESTAMP 363 s_memrealtime s_g8sr_ts_sq_save_msg 364 s_waitcnt lgkmcnt(0) 365end 366 367 if (EMU_RUN_HACK) 368 369 else 370 s_sendmsg sendmsg(MSG_SAVEWAVE) //send SPI a message and wait for SPI's write to EXEC 371 end 372 373 // Set SPI_PRIO=2 to avoid starving instruction fetch in the waves we're waiting for. 374 s_or_b32 s_save_tmp, s_save_status, (2 << SQ_WAVE_STATUS_SPI_PRIO_SHIFT) 375 s_setreg_b32 hwreg(HW_REG_STATUS), s_save_tmp 376 377 L_SLEEP: 378 s_sleep 0x2 // sleep 1 (64clk) is not enough for 8 waves per SIMD, which will cause SQ hang, since the 7,8th wave could not get arbit to exec inst, while other waves are stuck into the sleep-loop and waiting for wrexec!=0 379 380 if (EMU_RUN_HACK) 381 382 else 383 s_cbranch_execz L_SLEEP 384 end 385 386if G8SR_DEBUG_TIMESTAMP 387 s_memrealtime s_g8sr_ts_spi_wrexec 388 s_waitcnt lgkmcnt(0) 389end 390 391 if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_SINGLE_WAVE)) 392 //calculate wd_addr using absolute thread id 393 v_readlane_b32 s_save_tmp, v9, 0 394 s_lshr_b32 s_save_tmp, s_save_tmp, 6 395 s_mul_i32 s_save_tmp, s_save_tmp, WAVE_SPACE 396 s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO 397 s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI 398 s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL 399 else 400 end 401 if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_SINGLE_WAVE)) 402 s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO 403 s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI 404 s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL 405 else 406 end 407 408 // Save trap temporaries 6-11, 13-15 initialized by SPI debug dispatch logic 409 // ttmp SR memory offset : size(VGPR)+size(SGPR)+0x40 410 get_vgpr_size_bytes(s_save_ttmps_lo) 411 get_sgpr_size_bytes(s_save_ttmps_hi) 412 s_add_u32 s_save_ttmps_lo, s_save_ttmps_lo, s_save_ttmps_hi 413 s_add_u32 s_save_ttmps_lo, s_save_ttmps_lo, s_save_spi_init_lo 414 s_addc_u32 s_save_ttmps_hi, s_save_spi_init_hi, 0x0 415 s_and_b32 s_save_ttmps_hi, s_save_ttmps_hi, 0xFFFF 416 s_store_dwordx2 [ttmp6, ttmp7], [s_save_ttmps_lo, s_save_ttmps_hi], 0x40 glc:1 417 ack_sqc_store_workaround() 418 s_store_dwordx4 [ttmp8, ttmp9, ttmp10, ttmp11], [s_save_ttmps_lo, s_save_ttmps_hi], 0x48 glc:1 419 ack_sqc_store_workaround() 420 s_store_dword ttmp13, [s_save_ttmps_lo, s_save_ttmps_hi], 0x58 glc:1 421 ack_sqc_store_workaround() 422 s_store_dwordx2 [ttmp14, ttmp15], [s_save_ttmps_lo, s_save_ttmps_hi], 0x5C glc:1 423 ack_sqc_store_workaround() 424 425 /* setup Resource Contants */ 426 s_mov_b32 s_save_buf_rsrc0, s_save_spi_init_lo //base_addr_lo 427 s_and_b32 s_save_buf_rsrc1, s_save_spi_init_hi, 0x0000FFFF //base_addr_hi 428 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE 429 s_mov_b32 s_save_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) although not neccessarily inited 430 s_mov_b32 s_save_buf_rsrc3, S_SAVE_BUF_RSRC_WORD3_MISC 431 s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_ATC_MASK 432 s_lshr_b32 s_save_tmp, s_save_tmp, (S_SAVE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT) //get ATC bit into position 433 s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, s_save_tmp //or ATC 434 s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_MTYPE_MASK 435 s_lshr_b32 s_save_tmp, s_save_tmp, (S_SAVE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT) //get MTYPE bits into position 436 s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, s_save_tmp //or MTYPE 437 438 //FIXME right now s_save_m0/s_save_mem_offset use tma_lo/tma_hi (might need to save them before using them?) 439 s_mov_b32 s_save_m0, m0 //save M0 440 441 /* global mem offset */ 442 s_mov_b32 s_save_mem_offset, 0x0 //mem offset initial value = 0 443 444 445 446 447 /* save HW registers */ 448 ////////////////////////////// 449 450 L_SAVE_HWREG: 451 // HWREG SR memory offset : size(VGPR)+size(SGPR) 452 get_vgpr_size_bytes(s_save_mem_offset) 453 get_sgpr_size_bytes(s_save_tmp) 454 s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp 455 456 457 s_mov_b32 s_save_buf_rsrc2, 0x4 //NUM_RECORDS in bytes 458 if (SWIZZLE_EN) 459 s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 460 else 461 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 462 end 463 464 465 write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) //M0 466 467 if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_FIRST_TIME)) 468 s_add_u32 s_save_pc_lo, s_save_pc_lo, 4 //pc[31:0]+4 469 s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0 //carry bit over 470 end 471 472 write_hwreg_to_mem(s_save_pc_lo, s_save_buf_rsrc0, s_save_mem_offset) //PC 473 write_hwreg_to_mem(s_save_pc_hi, s_save_buf_rsrc0, s_save_mem_offset) 474 write_hwreg_to_mem(s_save_exec_lo, s_save_buf_rsrc0, s_save_mem_offset) //EXEC 475 write_hwreg_to_mem(s_save_exec_hi, s_save_buf_rsrc0, s_save_mem_offset) 476 write_hwreg_to_mem(s_save_status, s_save_buf_rsrc0, s_save_mem_offset) //STATUS 477 478 //s_save_trapsts conflicts with s_save_alloc_size 479 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 480 write_hwreg_to_mem(s_save_trapsts, s_save_buf_rsrc0, s_save_mem_offset) //TRAPSTS 481 482 write_hwreg_to_mem(xnack_mask_lo, s_save_buf_rsrc0, s_save_mem_offset) //XNACK_MASK_LO 483 write_hwreg_to_mem(xnack_mask_hi, s_save_buf_rsrc0, s_save_mem_offset) //XNACK_MASK_HI 484 485 //use s_save_tmp would introduce conflict here between s_save_tmp and s_save_buf_rsrc2 486 s_getreg_b32 s_save_m0, hwreg(HW_REG_MODE) //MODE 487 write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) 488 489 490 491 /* the first wave in the threadgroup */ 492 s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK // extract fisrt wave bit 493 s_mov_b32 s_save_exec_hi, 0x0 494 s_or_b32 s_save_exec_hi, s_save_tmp, s_save_exec_hi // save first wave bit to s_save_exec_hi.bits[26] 495 496 497 /* save SGPRs */ 498 // Save SGPR before LDS save, then the s0 to s4 can be used during LDS save... 499 ////////////////////////////// 500 501 // SGPR SR memory offset : size(VGPR) 502 get_vgpr_size_bytes(s_save_mem_offset) 503 // TODO, change RSRC word to rearrange memory layout for SGPRS 504 505 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size 506 s_add_u32 s_save_alloc_size, s_save_alloc_size, 1 507 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 4 //Number of SGPRs = (sgpr_size + 1) * 16 (non-zero value) 508 509 if (SGPR_SAVE_USE_SQC) 510 s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 2 //NUM_RECORDS in bytes 511 else 512 s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 8 //NUM_RECORDS in bytes (64 threads) 513 end 514 515 if (SWIZZLE_EN) 516 s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 517 else 518 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 519 end 520 521 522 // backup s_save_buf_rsrc0,1 to s_save_pc_lo/hi, since write_16sgpr_to_mem function will change the rsrc0 523 //s_mov_b64 s_save_pc_lo, s_save_buf_rsrc0 524 s_mov_b64 s_save_xnack_mask_lo, s_save_buf_rsrc0 525 s_add_u32 s_save_buf_rsrc0, s_save_buf_rsrc0, s_save_mem_offset 526 s_addc_u32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0 527 528 s_mov_b32 m0, 0x0 //SGPR initial index value =0 529 s_nop 0x0 //Manually inserted wait states 530 L_SAVE_SGPR_LOOP: 531 // SGPR is allocated in 16 SGPR granularity 532 s_movrels_b64 s0, s0 //s0 = s[0+m0], s1 = s[1+m0] 533 s_movrels_b64 s2, s2 //s2 = s[2+m0], s3 = s[3+m0] 534 s_movrels_b64 s4, s4 //s4 = s[4+m0], s5 = s[5+m0] 535 s_movrels_b64 s6, s6 //s6 = s[6+m0], s7 = s[7+m0] 536 s_movrels_b64 s8, s8 //s8 = s[8+m0], s9 = s[9+m0] 537 s_movrels_b64 s10, s10 //s10 = s[10+m0], s11 = s[11+m0] 538 s_movrels_b64 s12, s12 //s12 = s[12+m0], s13 = s[13+m0] 539 s_movrels_b64 s14, s14 //s14 = s[14+m0], s15 = s[15+m0] 540 541 write_16sgpr_to_mem(s0, s_save_buf_rsrc0, s_save_mem_offset) //PV: the best performance should be using s_buffer_store_dwordx4 542 s_add_u32 m0, m0, 16 //next sgpr index 543 s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 544 s_cbranch_scc1 L_SAVE_SGPR_LOOP //SGPR save is complete? 545 // restore s_save_buf_rsrc0,1 546 //s_mov_b64 s_save_buf_rsrc0, s_save_pc_lo 547 s_mov_b64 s_save_buf_rsrc0, s_save_xnack_mask_lo 548 549 550 551 552 /* save first 4 VGPR, then LDS save could use */ 553 // each wave will alloc 4 vgprs at least... 554 ///////////////////////////////////////////////////////////////////////////////////// 555 556 s_mov_b32 s_save_mem_offset, 0 557 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 558 s_mov_b32 exec_hi, 0xFFFFFFFF 559 s_mov_b32 xnack_mask_lo, 0x0 560 s_mov_b32 xnack_mask_hi, 0x0 561 562 if (SWIZZLE_EN) 563 s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 564 else 565 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 566 end 567 568 569 // VGPR Allocated in 4-GPR granularity 570 571if G8SR_VGPR_SR_IN_DWX4 572 // the const stride for DWx4 is 4*4 bytes 573 s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 574 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 // const stride to 4*4 bytes 575 576 buffer_store_dwordx4 v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 577 578 s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 579 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE // reset const stride to 4 bytes 580else 581 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 582 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256 583 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2 584 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3 585end 586 587 588 589 /* save LDS */ 590 ////////////////////////////// 591 592 L_SAVE_LDS: 593 594 // Change EXEC to all threads... 595 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 596 s_mov_b32 exec_hi, 0xFFFFFFFF 597 598 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) //lds_size 599 s_and_b32 s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF //lds_size is zero? 600 s_cbranch_scc0 L_SAVE_LDS_DONE //no lds used? jump to L_SAVE_DONE 601 602 s_barrier //LDS is used? wait for other waves in the same TG 603 s_and_b32 s_save_tmp, s_save_exec_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK //exec is still used here 604 s_cbranch_scc0 L_SAVE_LDS_DONE 605 606 // first wave do LDS save; 607 608 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 6 //LDS size in dwords = lds_size * 64dw 609 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 2 //LDS size in bytes 610 s_mov_b32 s_save_buf_rsrc2, s_save_alloc_size //NUM_RECORDS in bytes 611 612 // LDS at offset: size(VGPR)+SIZE(SGPR)+SIZE(HWREG) 613 // 614 get_vgpr_size_bytes(s_save_mem_offset) 615 get_sgpr_size_bytes(s_save_tmp) 616 s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp 617 s_add_u32 s_save_mem_offset, s_save_mem_offset, get_hwreg_size_bytes() 618 619 620 if (SWIZZLE_EN) 621 s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 622 else 623 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 624 end 625 626 s_mov_b32 m0, 0x0 //lds_offset initial value = 0 627 628 629var LDS_DMA_ENABLE = 0 630var UNROLL = 0 631if UNROLL==0 && LDS_DMA_ENABLE==1 632 s_mov_b32 s3, 256*2 633 s_nop 0 634 s_nop 0 635 s_nop 0 636 L_SAVE_LDS_LOOP: 637 //TODO: looks the 2 buffer_store/load clause for s/r will hurt performance.??? 638 if (SAVE_LDS) //SPI always alloc LDS space in 128DW granularity 639 buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 // first 64DW 640 buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:256 // second 64DW 641 end 642 643 s_add_u32 m0, m0, s3 //every buffer_store_lds does 256 bytes 644 s_add_u32 s_save_mem_offset, s_save_mem_offset, s3 //mem offset increased by 256 bytes 645 s_cmp_lt_u32 m0, s_save_alloc_size //scc=(m0 < s_save_alloc_size) ? 1 : 0 646 s_cbranch_scc1 L_SAVE_LDS_LOOP //LDS save is complete? 647 648elsif LDS_DMA_ENABLE==1 && UNROLL==1 // UNROOL , has ichace miss 649 // store from higest LDS address to lowest 650 s_mov_b32 s3, 256*2 651 s_sub_u32 m0, s_save_alloc_size, s3 652 s_add_u32 s_save_mem_offset, s_save_mem_offset, m0 653 s_lshr_b32 s_save_alloc_size, s_save_alloc_size, 9 // how many 128 trunks... 654 s_sub_u32 s_save_alloc_size, 128, s_save_alloc_size // store from higheset addr to lowest 655 s_mul_i32 s_save_alloc_size, s_save_alloc_size, 6*4 // PC offset increment, each LDS save block cost 6*4 Bytes instruction 656 s_add_u32 s_save_alloc_size, s_save_alloc_size, 3*4 //2is the below 2 inst...//s_addc and s_setpc 657 s_nop 0 658 s_nop 0 659 s_nop 0 //pad 3 dw to let LDS_DMA align with 64Bytes 660 s_getpc_b64 s[0:1] // reuse s[0:1], since s[0:1] already saved 661 s_add_u32 s0, s0,s_save_alloc_size 662 s_addc_u32 s1, s1, 0 663 s_setpc_b64 s[0:1] 664 665 666 for var i =0; i< 128; i++ 667 // be careful to make here a 64Byte aligned address, which could improve performance... 668 buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:0 // first 64DW 669 buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:256 // second 64DW 670 671 if i!=127 672 s_sub_u32 m0, m0, s3 // use a sgpr to shrink 2DW-inst to 1DW inst to improve performance , i.e. pack more LDS_DMA inst to one Cacheline 673 s_sub_u32 s_save_mem_offset, s_save_mem_offset, s3 674 end 675 end 676 677else // BUFFER_STORE 678 v_mbcnt_lo_u32_b32 v2, 0xffffffff, 0x0 679 v_mbcnt_hi_u32_b32 v3, 0xffffffff, v2 // tid 680 v_mul_i32_i24 v2, v3, 8 // tid*8 681 v_mov_b32 v3, 256*2 682 s_mov_b32 m0, 0x10000 683 s_mov_b32 s0, s_save_buf_rsrc3 684 s_and_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, 0xFF7FFFFF // disable add_tid 685 s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, 0x58000 //DFMT 686 687L_SAVE_LDS_LOOP_VECTOR: 688 ds_read_b64 v[0:1], v2 //x =LDS[a], byte address 689 s_waitcnt lgkmcnt(0) 690 buffer_store_dwordx2 v[0:1], v2, s_save_buf_rsrc0, s_save_mem_offset offen:1 glc:1 slc:1 691// s_waitcnt vmcnt(0) 692// v_add_u32 v2, vcc[0:1], v2, v3 693 v_add_u32 v2, v2, v3 694 v_cmp_lt_u32 vcc[0:1], v2, s_save_alloc_size 695 s_cbranch_vccnz L_SAVE_LDS_LOOP_VECTOR 696 697 // restore rsrc3 698 s_mov_b32 s_save_buf_rsrc3, s0 699 700end 701 702L_SAVE_LDS_DONE: 703 704 705 /* save VGPRs - set the Rest VGPRs */ 706 ////////////////////////////////////////////////////////////////////////////////////// 707 L_SAVE_VGPR: 708 // VGPR SR memory offset: 0 709 // TODO rearrange the RSRC words to use swizzle for VGPR save... 710 711 s_mov_b32 s_save_mem_offset, (0+256*4) // for the rest VGPRs 712 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 713 s_mov_b32 exec_hi, 0xFFFFFFFF 714 715 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) //vpgr_size 716 s_add_u32 s_save_alloc_size, s_save_alloc_size, 1 717 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value) //FIXME for GFX, zero is possible 718 s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 8 //NUM_RECORDS in bytes (64 threads*4) 719 if (SWIZZLE_EN) 720 s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 721 else 722 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 723 end 724 725 726 // VGPR Allocated in 4-GPR granularity 727 728if G8SR_VGPR_SR_IN_DWX4 729 // the const stride for DWx4 is 4*4 bytes 730 s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 731 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 // const stride to 4*4 bytes 732 733 s_mov_b32 m0, 4 // skip first 4 VGPRs 734 s_cmp_lt_u32 m0, s_save_alloc_size 735 s_cbranch_scc0 L_SAVE_VGPR_LOOP_END // no more vgprs 736 737 s_set_gpr_idx_on m0, 0x1 // This will change M0 738 s_add_u32 s_save_alloc_size, s_save_alloc_size, 0x1000 // because above inst change m0 739L_SAVE_VGPR_LOOP: 740 v_mov_b32 v0, v0 // v0 = v[0+m0] 741 v_mov_b32 v1, v1 742 v_mov_b32 v2, v2 743 v_mov_b32 v3, v3 744 745 746 buffer_store_dwordx4 v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 747 s_add_u32 m0, m0, 4 748 s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 749 s_cmp_lt_u32 m0, s_save_alloc_size 750 s_cbranch_scc1 L_SAVE_VGPR_LOOP //VGPR save is complete? 751 s_set_gpr_idx_off 752L_SAVE_VGPR_LOOP_END: 753 754 s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 755 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE // reset const stride to 4 bytes 756else 757 // VGPR store using dw burst 758 s_mov_b32 m0, 0x4 //VGPR initial index value =0 759 s_cmp_lt_u32 m0, s_save_alloc_size 760 s_cbranch_scc0 L_SAVE_VGPR_END 761 762 763 s_set_gpr_idx_on m0, 0x1 //M0[7:0] = M0[7:0] and M0[15:12] = 0x1 764 s_add_u32 s_save_alloc_size, s_save_alloc_size, 0x1000 //add 0x1000 since we compare m0 against it later 765 766 L_SAVE_VGPR_LOOP: 767 v_mov_b32 v0, v0 //v0 = v[0+m0] 768 v_mov_b32 v1, v1 //v0 = v[0+m0] 769 v_mov_b32 v2, v2 //v0 = v[0+m0] 770 v_mov_b32 v3, v3 //v0 = v[0+m0] 771 772 if(USE_MTBUF_INSTEAD_OF_MUBUF) 773 tbuffer_store_format_x v0, v0, s_save_buf_rsrc0, s_save_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1 774 else 775 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 776 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256 777 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2 778 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3 779 end 780 781 s_add_u32 m0, m0, 4 //next vgpr index 782 s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 //every buffer_store_dword does 256 bytes 783 s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 784 s_cbranch_scc1 L_SAVE_VGPR_LOOP //VGPR save is complete? 785 s_set_gpr_idx_off 786end 787 788L_SAVE_VGPR_END: 789 790 791 792 793 794 795 /* S_PGM_END_SAVED */ //FIXME graphics ONLY 796 if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_NORMAL_EXIT)) 797 s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff //pc[47:32] 798 s_add_u32 s_save_pc_lo, s_save_pc_lo, 4 //pc[31:0]+4 799 s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0 //carry bit over 800 s_rfe_b64 s_save_pc_lo //Return to the main shader program 801 else 802 end 803 804// Save Done timestamp 805if G8SR_DEBUG_TIMESTAMP 806 s_memrealtime s_g8sr_ts_save_d 807 // SGPR SR memory offset : size(VGPR) 808 get_vgpr_size_bytes(s_save_mem_offset) 809 s_add_u32 s_save_mem_offset, s_save_mem_offset, G8SR_DEBUG_TS_SAVE_D_OFFSET 810 s_waitcnt lgkmcnt(0) //FIXME, will cause xnack?? 811 // Need reset rsrc2?? 812 s_mov_b32 m0, s_save_mem_offset 813 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 814 s_buffer_store_dwordx2 s_g8sr_ts_save_d, s_save_buf_rsrc0, m0 glc:1 815end 816 817 818 s_branch L_END_PGM 819 820 821 822/**************************************************************************/ 823/* restore routine */ 824/**************************************************************************/ 825 826L_RESTORE: 827 /* Setup Resource Contants */ 828 if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL)) 829 //calculate wd_addr using absolute thread id 830 v_readlane_b32 s_restore_tmp, v9, 0 831 s_lshr_b32 s_restore_tmp, s_restore_tmp, 6 832 s_mul_i32 s_restore_tmp, s_restore_tmp, WAVE_SPACE 833 s_add_i32 s_restore_spi_init_lo, s_restore_tmp, WG_BASE_ADDR_LO 834 s_mov_b32 s_restore_spi_init_hi, WG_BASE_ADDR_HI 835 s_and_b32 s_restore_spi_init_hi, s_restore_spi_init_hi, CTX_RESTORE_CONTROL 836 else 837 end 838 839if G8SR_DEBUG_TIMESTAMP 840 s_memrealtime s_g8sr_ts_restore_s 841 s_waitcnt lgkmcnt(0) //FIXME, will cause xnack?? 842 // tma_lo/hi are sgpr 110, 111, which will not used for 112 SGPR allocated case... 843 s_mov_b32 s_restore_pc_lo, s_g8sr_ts_restore_s[0] 844 s_mov_b32 s_restore_pc_hi, s_g8sr_ts_restore_s[1] //backup ts to ttmp0/1, sicne exec will be finally restored.. 845end 846 847 848 849 s_mov_b32 s_restore_buf_rsrc0, s_restore_spi_init_lo //base_addr_lo 850 s_and_b32 s_restore_buf_rsrc1, s_restore_spi_init_hi, 0x0000FFFF //base_addr_hi 851 s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE 852 s_mov_b32 s_restore_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) 853 s_mov_b32 s_restore_buf_rsrc3, S_RESTORE_BUF_RSRC_WORD3_MISC 854 s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_ATC_MASK 855 s_lshr_b32 s_restore_tmp, s_restore_tmp, (S_RESTORE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT) //get ATC bit into position 856 s_or_b32 s_restore_buf_rsrc3, s_restore_buf_rsrc3, s_restore_tmp //or ATC 857 s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_MTYPE_MASK 858 s_lshr_b32 s_restore_tmp, s_restore_tmp, (S_RESTORE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT) //get MTYPE bits into position 859 s_or_b32 s_restore_buf_rsrc3, s_restore_buf_rsrc3, s_restore_tmp //or MTYPE 860 861 /* global mem offset */ 862// s_mov_b32 s_restore_mem_offset, 0x0 //mem offset initial value = 0 863 864 /* the first wave in the threadgroup */ 865 s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_FIRST_WAVE_MASK 866 s_cbranch_scc0 L_RESTORE_VGPR 867 868 /* restore LDS */ 869 ////////////////////////////// 870 L_RESTORE_LDS: 871 872 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on //be consistent with SAVE although can be moved ahead 873 s_mov_b32 exec_hi, 0xFFFFFFFF 874 875 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) //lds_size 876 s_and_b32 s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF //lds_size is zero? 877 s_cbranch_scc0 L_RESTORE_VGPR //no lds used? jump to L_RESTORE_VGPR 878 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 6 //LDS size in dwords = lds_size * 64dw 879 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 2 //LDS size in bytes 880 s_mov_b32 s_restore_buf_rsrc2, s_restore_alloc_size //NUM_RECORDS in bytes 881 882 // LDS at offset: size(VGPR)+SIZE(SGPR)+SIZE(HWREG) 883 // 884 get_vgpr_size_bytes(s_restore_mem_offset) 885 get_sgpr_size_bytes(s_restore_tmp) 886 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 887 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_hwreg_size_bytes() //FIXME, Check if offset overflow??? 888 889 890 if (SWIZZLE_EN) 891 s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 892 else 893 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 894 end 895 s_mov_b32 m0, 0x0 //lds_offset initial value = 0 896 897 L_RESTORE_LDS_LOOP: 898 if (SAVE_LDS) 899 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 // first 64DW 900 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 offset:256 // second 64DW 901 end 902 s_add_u32 m0, m0, 256*2 // 128 DW 903 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*2 //mem offset increased by 128DW 904 s_cmp_lt_u32 m0, s_restore_alloc_size //scc=(m0 < s_restore_alloc_size) ? 1 : 0 905 s_cbranch_scc1 L_RESTORE_LDS_LOOP //LDS restore is complete? 906 907 908 /* restore VGPRs */ 909 ////////////////////////////// 910 L_RESTORE_VGPR: 911 // VGPR SR memory offset : 0 912 s_mov_b32 s_restore_mem_offset, 0x0 913 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on //be consistent with SAVE although can be moved ahead 914 s_mov_b32 exec_hi, 0xFFFFFFFF 915 916 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) //vpgr_size 917 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 1 918 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value) 919 s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 8 //NUM_RECORDS in bytes (64 threads*4) 920 if (SWIZZLE_EN) 921 s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 922 else 923 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 924 end 925 926if G8SR_VGPR_SR_IN_DWX4 927 get_vgpr_size_bytes(s_restore_mem_offset) 928 s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 929 930 // the const stride for DWx4 is 4*4 bytes 931 s_and_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, 0x0000FFFF // reset const stride to 0 932 s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, G8SR_RESTORE_BUF_RSRC_WORD1_STRIDE_DWx4 // const stride to 4*4 bytes 933 934 s_mov_b32 m0, s_restore_alloc_size 935 s_set_gpr_idx_on m0, 0x8 // Note.. This will change m0 936 937L_RESTORE_VGPR_LOOP: 938 buffer_load_dwordx4 v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 939 s_waitcnt vmcnt(0) 940 s_sub_u32 m0, m0, 4 941 v_mov_b32 v0, v0 // v[0+m0] = v0 942 v_mov_b32 v1, v1 943 v_mov_b32 v2, v2 944 v_mov_b32 v3, v3 945 s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 946 s_cmp_eq_u32 m0, 0x8000 947 s_cbranch_scc0 L_RESTORE_VGPR_LOOP 948 s_set_gpr_idx_off 949 950 s_and_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, 0x0000FFFF // reset const stride to 0 951 s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE // const stride to 4*4 bytes 952 953else 954 // VGPR load using dw burst 955 s_mov_b32 s_restore_mem_offset_save, s_restore_mem_offset // restore start with v1, v0 will be the last 956 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 957 s_mov_b32 m0, 4 //VGPR initial index value = 1 958 s_set_gpr_idx_on m0, 0x8 //M0[7:0] = M0[7:0] and M0[15:12] = 0x8 959 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 0x8000 //add 0x8000 since we compare m0 against it later 960 961 L_RESTORE_VGPR_LOOP: 962 if(USE_MTBUF_INSTEAD_OF_MUBUF) 963 tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1 964 else 965 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 966 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256 967 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*2 968 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*3 969 end 970 s_waitcnt vmcnt(0) //ensure data ready 971 v_mov_b32 v0, v0 //v[0+m0] = v0 972 v_mov_b32 v1, v1 973 v_mov_b32 v2, v2 974 v_mov_b32 v3, v3 975 s_add_u32 m0, m0, 4 //next vgpr index 976 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 //every buffer_load_dword does 256 bytes 977 s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0 978 s_cbranch_scc1 L_RESTORE_VGPR_LOOP //VGPR restore (except v0) is complete? 979 s_set_gpr_idx_off 980 /* VGPR restore on v0 */ 981 if(USE_MTBUF_INSTEAD_OF_MUBUF) 982 tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1 983 else 984 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 985 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256 986 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*2 987 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*3 988 end 989 990end 991 992 /* restore SGPRs */ 993 ////////////////////////////// 994 995 // SGPR SR memory offset : size(VGPR) 996 get_vgpr_size_bytes(s_restore_mem_offset) 997 get_sgpr_size_bytes(s_restore_tmp) 998 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 999 s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 16*4 // restore SGPR from S[n] to S[0], by 16 sgprs group 1000 // TODO, change RSRC word to rearrange memory layout for SGPRS 1001 1002 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size 1003 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 1 1004 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 4 //Number of SGPRs = (sgpr_size + 1) * 16 (non-zero value) 1005 1006 if (SGPR_SAVE_USE_SQC) 1007 s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 2 //NUM_RECORDS in bytes 1008 else 1009 s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 8 //NUM_RECORDS in bytes (64 threads) 1010 end 1011 if (SWIZZLE_EN) 1012 s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 1013 else 1014 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 1015 end 1016 1017 s_mov_b32 m0, s_restore_alloc_size 1018 1019 L_RESTORE_SGPR_LOOP: 1020 read_16sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset) //PV: further performance improvement can be made 1021 s_waitcnt lgkmcnt(0) //ensure data ready 1022 1023 s_sub_u32 m0, m0, 16 // Restore from S[n] to S[0] 1024 s_nop 0 // hazard SALU M0=> S_MOVREL 1025 1026 s_movreld_b64 s0, s0 //s[0+m0] = s0 1027 s_movreld_b64 s2, s2 1028 s_movreld_b64 s4, s4 1029 s_movreld_b64 s6, s6 1030 s_movreld_b64 s8, s8 1031 s_movreld_b64 s10, s10 1032 s_movreld_b64 s12, s12 1033 s_movreld_b64 s14, s14 1034 1035 s_cmp_eq_u32 m0, 0 //scc = (m0 < s_restore_alloc_size) ? 1 : 0 1036 s_cbranch_scc0 L_RESTORE_SGPR_LOOP //SGPR restore (except s0) is complete? 1037 1038 /* restore HW registers */ 1039 ////////////////////////////// 1040 L_RESTORE_HWREG: 1041 1042 1043if G8SR_DEBUG_TIMESTAMP 1044 s_mov_b32 s_g8sr_ts_restore_s[0], s_restore_pc_lo 1045 s_mov_b32 s_g8sr_ts_restore_s[1], s_restore_pc_hi 1046end 1047 1048 // HWREG SR memory offset : size(VGPR)+size(SGPR) 1049 get_vgpr_size_bytes(s_restore_mem_offset) 1050 get_sgpr_size_bytes(s_restore_tmp) 1051 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 1052 1053 1054 s_mov_b32 s_restore_buf_rsrc2, 0x4 //NUM_RECORDS in bytes 1055 if (SWIZZLE_EN) 1056 s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 1057 else 1058 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 1059 end 1060 1061 read_hwreg_from_mem(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset) //M0 1062 read_hwreg_from_mem(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //PC 1063 read_hwreg_from_mem(s_restore_pc_hi, s_restore_buf_rsrc0, s_restore_mem_offset) 1064 read_hwreg_from_mem(s_restore_exec_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //EXEC 1065 read_hwreg_from_mem(s_restore_exec_hi, s_restore_buf_rsrc0, s_restore_mem_offset) 1066 read_hwreg_from_mem(s_restore_status, s_restore_buf_rsrc0, s_restore_mem_offset) //STATUS 1067 read_hwreg_from_mem(s_restore_trapsts, s_restore_buf_rsrc0, s_restore_mem_offset) //TRAPSTS 1068 read_hwreg_from_mem(xnack_mask_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //XNACK_MASK_LO 1069 read_hwreg_from_mem(xnack_mask_hi, s_restore_buf_rsrc0, s_restore_mem_offset) //XNACK_MASK_HI 1070 read_hwreg_from_mem(s_restore_mode, s_restore_buf_rsrc0, s_restore_mem_offset) //MODE 1071 1072 s_waitcnt lgkmcnt(0) //from now on, it is safe to restore STATUS and IB_STS 1073 1074 //for normal save & restore, the saved PC points to the next inst to execute, no adjustment needs to be made, otherwise: 1075 if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL)) 1076 s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 8 //pc[31:0]+8 //two back-to-back s_trap are used (first for save and second for restore) 1077 s_addc_u32 s_restore_pc_hi, s_restore_pc_hi, 0x0 //carry bit over 1078 end 1079 if ((EMU_RUN_HACK) && (EMU_RUN_HACK_RESTORE_NORMAL)) 1080 s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 4 //pc[31:0]+4 // save is hack through s_trap but restore is normal 1081 s_addc_u32 s_restore_pc_hi, s_restore_pc_hi, 0x0 //carry bit over 1082 end 1083 1084 s_mov_b32 m0, s_restore_m0 1085 s_mov_b32 exec_lo, s_restore_exec_lo 1086 s_mov_b32 exec_hi, s_restore_exec_hi 1087 1088 s_and_b32 s_restore_m0, SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK, s_restore_trapsts 1089 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE), s_restore_m0 1090 s_and_b32 s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK, s_restore_trapsts 1091 s_lshr_b32 s_restore_m0, s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT 1092 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE), s_restore_m0 1093 //s_setreg_b32 hwreg(HW_REG_TRAPSTS), s_restore_trapsts //don't overwrite SAVECTX bit as it may be set through external SAVECTX during restore 1094 s_setreg_b32 hwreg(HW_REG_MODE), s_restore_mode 1095 1096 // Restore trap temporaries 6-11, 13-15 initialized by SPI debug dispatch logic 1097 // ttmp SR memory offset : size(VGPR)+size(SGPR)+0x40 1098 get_vgpr_size_bytes(s_restore_ttmps_lo) 1099 get_sgpr_size_bytes(s_restore_ttmps_hi) 1100 s_add_u32 s_restore_ttmps_lo, s_restore_ttmps_lo, s_restore_ttmps_hi 1101 s_add_u32 s_restore_ttmps_lo, s_restore_ttmps_lo, s_restore_buf_rsrc0 1102 s_addc_u32 s_restore_ttmps_hi, s_restore_buf_rsrc1, 0x0 1103 s_and_b32 s_restore_ttmps_hi, s_restore_ttmps_hi, 0xFFFF 1104 s_load_dwordx2 [ttmp6, ttmp7], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x40 glc:1 1105 s_load_dwordx4 [ttmp8, ttmp9, ttmp10, ttmp11], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x48 glc:1 1106 s_load_dword ttmp13, [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x58 glc:1 1107 s_load_dwordx2 [ttmp14, ttmp15], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x5C glc:1 1108 s_waitcnt lgkmcnt(0) 1109 1110 //reuse s_restore_m0 as a temp register 1111 s_and_b32 s_restore_m0, s_restore_pc_hi, S_SAVE_PC_HI_RCNT_MASK 1112 s_lshr_b32 s_restore_m0, s_restore_m0, S_SAVE_PC_HI_RCNT_SHIFT 1113 s_lshl_b32 s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_RCNT_SHIFT 1114 s_mov_b32 s_restore_tmp, 0x0 //IB_STS is zero 1115 s_or_b32 s_restore_tmp, s_restore_tmp, s_restore_m0 1116 s_and_b32 s_restore_m0, s_restore_pc_hi, S_SAVE_PC_HI_FIRST_REPLAY_MASK 1117 s_lshr_b32 s_restore_m0, s_restore_m0, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT 1118 s_lshl_b32 s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT 1119 s_or_b32 s_restore_tmp, s_restore_tmp, s_restore_m0 1120 s_and_b32 s_restore_m0, s_restore_status, SQ_WAVE_STATUS_INST_ATC_MASK 1121 s_lshr_b32 s_restore_m0, s_restore_m0, SQ_WAVE_STATUS_INST_ATC_SHIFT 1122 s_setreg_b32 hwreg(HW_REG_IB_STS), s_restore_tmp 1123 1124 s_and_b32 s_restore_pc_hi, s_restore_pc_hi, 0x0000ffff //pc[47:32] //Do it here in order not to affect STATUS 1125 s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32 1126 s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32 1127 set_status_without_spi_prio(s_restore_status, s_restore_tmp) // SCC is included, which is changed by previous salu 1128 1129 s_barrier //barrier to ensure the readiness of LDS before access attempts from any other wave in the same TG //FIXME not performance-optimal at this time 1130 1131if G8SR_DEBUG_TIMESTAMP 1132 s_memrealtime s_g8sr_ts_restore_d 1133 s_waitcnt lgkmcnt(0) 1134end 1135 1136// s_rfe_b64 s_restore_pc_lo //Return to the main shader program and resume execution 1137 s_rfe_restore_b64 s_restore_pc_lo, s_restore_m0 // s_restore_m0[0] is used to set STATUS.inst_atc 1138 1139 1140/**************************************************************************/ 1141/* the END */ 1142/**************************************************************************/ 1143L_END_PGM: 1144 s_endpgm 1145 1146end 1147 1148 1149/**************************************************************************/ 1150/* the helper functions */ 1151/**************************************************************************/ 1152 1153//Only for save hwreg to mem 1154function write_hwreg_to_mem(s, s_rsrc, s_mem_offset) 1155 s_mov_b32 exec_lo, m0 //assuming exec_lo is not needed anymore from this point on 1156 s_mov_b32 m0, s_mem_offset 1157 s_buffer_store_dword s, s_rsrc, m0 glc:1 1158 ack_sqc_store_workaround() 1159 s_add_u32 s_mem_offset, s_mem_offset, 4 1160 s_mov_b32 m0, exec_lo 1161end 1162 1163 1164// HWREG are saved before SGPRs, so all HWREG could be use. 1165function write_16sgpr_to_mem(s, s_rsrc, s_mem_offset) 1166 1167 s_buffer_store_dwordx4 s[0], s_rsrc, 0 glc:1 1168 ack_sqc_store_workaround() 1169 s_buffer_store_dwordx4 s[4], s_rsrc, 16 glc:1 1170 ack_sqc_store_workaround() 1171 s_buffer_store_dwordx4 s[8], s_rsrc, 32 glc:1 1172 ack_sqc_store_workaround() 1173 s_buffer_store_dwordx4 s[12], s_rsrc, 48 glc:1 1174 ack_sqc_store_workaround() 1175 s_add_u32 s_rsrc[0], s_rsrc[0], 4*16 1176 s_addc_u32 s_rsrc[1], s_rsrc[1], 0x0 // +scc 1177end 1178 1179 1180function read_hwreg_from_mem(s, s_rsrc, s_mem_offset) 1181 s_buffer_load_dword s, s_rsrc, s_mem_offset glc:1 1182 s_add_u32 s_mem_offset, s_mem_offset, 4 1183end 1184 1185function read_16sgpr_from_mem(s, s_rsrc, s_mem_offset) 1186 s_buffer_load_dwordx16 s, s_rsrc, s_mem_offset glc:1 1187 s_sub_u32 s_mem_offset, s_mem_offset, 4*16 1188end 1189 1190 1191 1192function get_lds_size_bytes(s_lds_size_byte) 1193 // SQ LDS granularity is 64DW, while PGM_RSRC2.lds_size is in granularity 128DW 1194 s_getreg_b32 s_lds_size_byte, hwreg(HW_REG_LDS_ALLOC, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) // lds_size 1195 s_lshl_b32 s_lds_size_byte, s_lds_size_byte, 8 //LDS size in dwords = lds_size * 64 *4Bytes // granularity 64DW 1196end 1197 1198function get_vgpr_size_bytes(s_vgpr_size_byte) 1199 s_getreg_b32 s_vgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) //vpgr_size 1200 s_add_u32 s_vgpr_size_byte, s_vgpr_size_byte, 1 1201 s_lshl_b32 s_vgpr_size_byte, s_vgpr_size_byte, (2+8) //Number of VGPRs = (vgpr_size + 1) * 4 * 64 * 4 (non-zero value) //FIXME for GFX, zero is possible 1202end 1203 1204function get_sgpr_size_bytes(s_sgpr_size_byte) 1205 s_getreg_b32 s_sgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size 1206 s_add_u32 s_sgpr_size_byte, s_sgpr_size_byte, 1 1207 s_lshl_b32 s_sgpr_size_byte, s_sgpr_size_byte, 6 //Number of SGPRs = (sgpr_size + 1) * 16 *4 (non-zero value) 1208end 1209 1210function get_hwreg_size_bytes 1211 return 128 //HWREG size 128 bytes 1212end 1213 1214function ack_sqc_store_workaround 1215 if ACK_SQC_STORE 1216 s_waitcnt lgkmcnt(0) 1217 end 1218end 1219 1220function set_status_without_spi_prio(status, tmp) 1221 // Do not restore STATUS.SPI_PRIO since scheduler may have raised it. 1222 s_lshr_b32 tmp, status, SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT 1223 s_setreg_b32 hwreg(HW_REG_STATUS, SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT, SQ_WAVE_STATUS_POST_SPI_PRIO_SIZE), tmp 1224 s_nop 0x2 // avoid S_SETREG => S_SETREG hazard 1225 s_setreg_b32 hwreg(HW_REG_STATUS, SQ_WAVE_STATUS_PRE_SPI_PRIO_SHIFT, SQ_WAVE_STATUS_PRE_SPI_PRIO_SIZE), status 1226end 1227