1/* 2 * Copyright 2015-2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23/* To compile this assembly code: 24 * PROJECT=vi ./sp3 cwsr_trap_handler_gfx8.asm -hex tmp.hex 25 */ 26 27/* HW (VI) source code for CWSR trap handler */ 28/* Version 18 + multiple trap handler */ 29 30// this performance-optimal version was originally from Seven Xu at SRDC 31 32// Revison #18 --... 33/* Rev History 34** #1. Branch from gc dv. //gfxip/gfx8/main/src/test/suites/block/cs/sr/cs_trap_handler.sp3#1,#50, #51, #52-53(Skip, Already Fixed by PV), #54-56(merged),#57-58(mergerd, skiped-already fixed by PV) 35** #4. SR Memory Layout: 36** 1. VGPR-SGPR-HWREG-{LDS} 37** 2. tba_hi.bits.26 - reconfigured as the first wave in tg bits, for defer Save LDS for a threadgroup.. performance concern.. 38** #5. Update: 1. Accurate g8sr_ts_save_d timestamp 39** #6. Update: 1. Fix s_barrier usage; 2. VGPR s/r using swizzle buffer?(NoNeed, already matched the swizzle pattern, more investigation) 40** #7. Update: 1. don't barrier if noLDS 41** #8. Branch: 1. Branch to ver#0, which is very similar to gc dv version 42** 2. Fix SQ issue by s_sleep 2 43** #9. Update: 1. Fix scc restore failed issue, restore wave_status at last 44** 2. optimize s_buffer save by burst 16sgprs... 45** #10. Update 1. Optimize restore sgpr by busrt 16 sgprs. 46** #11. Update 1. Add 2 more timestamp for debug version 47** #12. Update 1. Add VGPR SR using DWx4, some case improve and some case drop performance 48** #13. Integ 1. Always use MUBUF for PV trap shader... 49** #14. Update 1. s_buffer_store soft clause... 50** #15. Update 1. PERF - sclar write with glc:0/mtype0 to allow L2 combine. perf improvement a lot. 51** #16. Update 1. PRRF - UNROLL LDS_DMA got 2500cycle save in IP tree 52** #17. Update 1. FUNC - LDS_DMA has issues while ATC, replace with ds_read/buffer_store for save part[TODO restore part] 53** 2. PERF - Save LDS before save VGPR to cover LDS save long latency... 54** #18. Update 1. FUNC - Implicitly estore STATUS.VCCZ, which is not writable by s_setreg_b32 55** 2. FUNC - Handle non-CWSR traps 56*/ 57 58var G8SR_WDMEM_HWREG_OFFSET = 0 59var G8SR_WDMEM_SGPR_OFFSET = 128 // in bytes 60 61// Keep definition same as the app shader, These 2 time stamps are part of the app shader... Should before any Save and after restore. 62 63var G8SR_DEBUG_TIMESTAMP = 0 64var G8SR_DEBUG_TS_SAVE_D_OFFSET = 40*4 // ts_save_d timestamp offset relative to SGPR_SR_memory_offset 65var s_g8sr_ts_save_s = s[34:35] // save start 66var s_g8sr_ts_sq_save_msg = s[36:37] // The save shader send SAVEWAVE msg to spi 67var s_g8sr_ts_spi_wrexec = s[38:39] // the SPI write the sr address to SQ 68var s_g8sr_ts_save_d = s[40:41] // save end 69var s_g8sr_ts_restore_s = s[42:43] // restore start 70var s_g8sr_ts_restore_d = s[44:45] // restore end 71 72var G8SR_VGPR_SR_IN_DWX4 = 0 73var G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 = 0x00100000 // DWx4 stride is 4*4Bytes 74var G8SR_RESTORE_BUF_RSRC_WORD1_STRIDE_DWx4 = G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 75 76 77/*************************************************************************/ 78/* control on how to run the shader */ 79/*************************************************************************/ 80//any hack that needs to be made to run this code in EMU (either because various EMU code are not ready or no compute save & restore in EMU run) 81var EMU_RUN_HACK = 0 82var EMU_RUN_HACK_RESTORE_NORMAL = 0 83var EMU_RUN_HACK_SAVE_NORMAL_EXIT = 0 84var EMU_RUN_HACK_SAVE_SINGLE_WAVE = 0 85var EMU_RUN_HACK_SAVE_FIRST_TIME = 0 //for interrupted restore in which the first save is through EMU_RUN_HACK 86var EMU_RUN_HACK_SAVE_FIRST_TIME_TBA_LO = 0 //for interrupted restore in which the first save is through EMU_RUN_HACK 87var EMU_RUN_HACK_SAVE_FIRST_TIME_TBA_HI = 0 //for interrupted restore in which the first save is through EMU_RUN_HACK 88var SAVE_LDS = 1 89var WG_BASE_ADDR_LO = 0x9000a000 90var WG_BASE_ADDR_HI = 0x0 91var WAVE_SPACE = 0x5000 //memory size that each wave occupies in workgroup state mem 92var CTX_SAVE_CONTROL = 0x0 93var CTX_RESTORE_CONTROL = CTX_SAVE_CONTROL 94var SIM_RUN_HACK = 0 //any hack that needs to be made to run this code in SIM (either because various RTL code are not ready or no compute save & restore in RTL run) 95var SGPR_SAVE_USE_SQC = 1 //use SQC D$ to do the write 96var USE_MTBUF_INSTEAD_OF_MUBUF = 0 //because TC EMU currently asserts on 0 of // overload DFMT field to carry 4 more bits of stride for MUBUF opcodes 97var SWIZZLE_EN = 0 //whether we use swizzled buffer addressing 98 99/**************************************************************************/ 100/* variables */ 101/**************************************************************************/ 102var SQ_WAVE_STATUS_INST_ATC_SHIFT = 23 103var SQ_WAVE_STATUS_INST_ATC_MASK = 0x00800000 104var SQ_WAVE_STATUS_SPI_PRIO_SHIFT = 1 105var SQ_WAVE_STATUS_SPI_PRIO_MASK = 0x00000006 106 107var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT = 12 108var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE = 9 109var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 8 110var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE = 6 111var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT = 24 112var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE = 3 //FIXME sq.blk still has 4 bits at this time while SQ programming guide has 3 bits 113 114var SQ_WAVE_TRAPSTS_SAVECTX_MASK = 0x400 115var SQ_WAVE_TRAPSTS_EXCE_MASK = 0x1FF // Exception mask 116var SQ_WAVE_TRAPSTS_SAVECTX_SHIFT = 10 117var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK = 0x100 118var SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT = 8 119var SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK = 0x3FF 120var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT = 0x0 121var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE = 10 122var SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK = 0xFFFFF800 123var SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT = 11 124var SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE = 21 125 126var SQ_WAVE_IB_STS_RCNT_SHIFT = 16 //FIXME 127var SQ_WAVE_IB_STS_RCNT_SIZE = 4 //FIXME 128var SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT = 15 //FIXME 129var SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE = 1 //FIXME 130var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG = 0x00007FFF //FIXME 131 132var SQ_BUF_RSRC_WORD1_ATC_SHIFT = 24 133var SQ_BUF_RSRC_WORD3_MTYPE_SHIFT = 27 134 135 136/* Save */ 137var S_SAVE_BUF_RSRC_WORD1_STRIDE = 0x00040000 //stride is 4 bytes 138var S_SAVE_BUF_RSRC_WORD3_MISC = 0x00807FAC //SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14] when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE 139 140var S_SAVE_SPI_INIT_ATC_MASK = 0x08000000 //bit[27]: ATC bit 141var S_SAVE_SPI_INIT_ATC_SHIFT = 27 142var S_SAVE_SPI_INIT_MTYPE_MASK = 0x70000000 //bit[30:28]: Mtype 143var S_SAVE_SPI_INIT_MTYPE_SHIFT = 28 144var S_SAVE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG 145var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT = 26 146 147var S_SAVE_PC_HI_RCNT_SHIFT = 28 //FIXME check with Brian to ensure all fields other than PC[47:0] can be used 148var S_SAVE_PC_HI_RCNT_MASK = 0xF0000000 //FIXME 149var S_SAVE_PC_HI_FIRST_REPLAY_SHIFT = 27 //FIXME 150var S_SAVE_PC_HI_FIRST_REPLAY_MASK = 0x08000000 //FIXME 151 152var s_save_spi_init_lo = exec_lo 153var s_save_spi_init_hi = exec_hi 154 155 //tba_lo and tba_hi need to be saved/restored 156var s_save_pc_lo = ttmp0 //{TTMP1, TTMP0} = {3'h0,pc_rewind[3:0], HT[0],trapID[7:0], PC[47:0]} 157var s_save_pc_hi = ttmp1 158var s_save_exec_lo = ttmp2 159var s_save_exec_hi = ttmp3 160var s_save_status = ttmp4 161var s_save_trapsts = ttmp5 //not really used until the end of the SAVE routine 162var s_save_xnack_mask_lo = ttmp6 163var s_save_xnack_mask_hi = ttmp7 164var s_save_buf_rsrc0 = ttmp8 165var s_save_buf_rsrc1 = ttmp9 166var s_save_buf_rsrc2 = ttmp10 167var s_save_buf_rsrc3 = ttmp11 168 169var s_save_mem_offset = tma_lo 170var s_save_alloc_size = s_save_trapsts //conflict 171var s_save_tmp = s_save_buf_rsrc2 //shared with s_save_buf_rsrc2 (conflict: should not use mem access with s_save_tmp at the same time) 172var s_save_m0 = tma_hi 173 174/* Restore */ 175var S_RESTORE_BUF_RSRC_WORD1_STRIDE = S_SAVE_BUF_RSRC_WORD1_STRIDE 176var S_RESTORE_BUF_RSRC_WORD3_MISC = S_SAVE_BUF_RSRC_WORD3_MISC 177 178var S_RESTORE_SPI_INIT_ATC_MASK = 0x08000000 //bit[27]: ATC bit 179var S_RESTORE_SPI_INIT_ATC_SHIFT = 27 180var S_RESTORE_SPI_INIT_MTYPE_MASK = 0x70000000 //bit[30:28]: Mtype 181var S_RESTORE_SPI_INIT_MTYPE_SHIFT = 28 182var S_RESTORE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG 183var S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT = 26 184 185var S_RESTORE_PC_HI_RCNT_SHIFT = S_SAVE_PC_HI_RCNT_SHIFT 186var S_RESTORE_PC_HI_RCNT_MASK = S_SAVE_PC_HI_RCNT_MASK 187var S_RESTORE_PC_HI_FIRST_REPLAY_SHIFT = S_SAVE_PC_HI_FIRST_REPLAY_SHIFT 188var S_RESTORE_PC_HI_FIRST_REPLAY_MASK = S_SAVE_PC_HI_FIRST_REPLAY_MASK 189 190var s_restore_spi_init_lo = exec_lo 191var s_restore_spi_init_hi = exec_hi 192 193var s_restore_mem_offset = ttmp2 194var s_restore_alloc_size = ttmp3 195var s_restore_tmp = ttmp6 //tba_lo/hi need to be restored 196var s_restore_mem_offset_save = s_restore_tmp //no conflict 197 198var s_restore_m0 = s_restore_alloc_size //no conflict 199 200var s_restore_mode = ttmp7 201 202var s_restore_pc_lo = ttmp0 203var s_restore_pc_hi = ttmp1 204var s_restore_exec_lo = tma_lo //no conflict 205var s_restore_exec_hi = tma_hi //no conflict 206var s_restore_status = ttmp4 207var s_restore_trapsts = ttmp5 208var s_restore_xnack_mask_lo = xnack_mask_lo 209var s_restore_xnack_mask_hi = xnack_mask_hi 210var s_restore_buf_rsrc0 = ttmp8 211var s_restore_buf_rsrc1 = ttmp9 212var s_restore_buf_rsrc2 = ttmp10 213var s_restore_buf_rsrc3 = ttmp11 214 215/**************************************************************************/ 216/* trap handler entry points */ 217/**************************************************************************/ 218/* Shader Main*/ 219 220shader main 221 asic(VI) 222 type(CS) 223 224 225 if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL)) //hack to use trap_id for determining save/restore 226 //FIXME VCCZ un-init assertion s_getreg_b32 s_save_status, hwreg(HW_REG_STATUS) //save STATUS since we will change SCC 227 s_and_b32 s_save_tmp, s_save_pc_hi, 0xffff0000 //change SCC 228 s_cmp_eq_u32 s_save_tmp, 0x007e0000 //Save: trap_id = 0x7e. Restore: trap_id = 0x7f. 229 s_cbranch_scc0 L_JUMP_TO_RESTORE //do not need to recover STATUS here since we are going to RESTORE 230 //FIXME s_setreg_b32 hwreg(HW_REG_STATUS), s_save_status //need to recover STATUS since we are going to SAVE 231 s_branch L_SKIP_RESTORE //NOT restore, SAVE actually 232 else 233 s_branch L_SKIP_RESTORE //NOT restore. might be a regular trap or save 234 end 235 236L_JUMP_TO_RESTORE: 237 s_branch L_RESTORE //restore 238 239L_SKIP_RESTORE: 240 241 s_getreg_b32 s_save_status, hwreg(HW_REG_STATUS) //save STATUS since we will change SCC 242 s_andn2_b32 s_save_status, s_save_status, SQ_WAVE_STATUS_SPI_PRIO_MASK //check whether this is for save 243 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 244 s_and_b32 s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK //check whether this is for save 245 s_cbranch_scc1 L_SAVE //this is the operation for save 246 247 // ********* Handle non-CWSR traps ******************* 248if (!EMU_RUN_HACK) 249 /* read tba and tma for next level trap handler, ttmp4 is used as s_save_status */ 250 s_load_dwordx4 [ttmp8,ttmp9,ttmp10, ttmp11], [tma_lo,tma_hi], 0 251 s_waitcnt lgkmcnt(0) 252 s_or_b32 ttmp7, ttmp8, ttmp9 253 s_cbranch_scc0 L_NO_NEXT_TRAP //next level trap handler not been set 254 s_setreg_b32 hwreg(HW_REG_STATUS), s_save_status //restore HW status(SCC) 255 s_setpc_b64 [ttmp8,ttmp9] //jump to next level trap handler 256 257L_NO_NEXT_TRAP: 258 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 259 s_and_b32 s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_EXCE_MASK // Check whether it is an exception 260 s_cbranch_scc1 L_EXCP_CASE // Exception, jump back to the shader program directly. 261 s_add_u32 ttmp0, ttmp0, 4 // S_TRAP case, add 4 to ttmp0 262 s_addc_u32 ttmp1, ttmp1, 0 263L_EXCP_CASE: 264 s_and_b32 ttmp1, ttmp1, 0xFFFF 265 s_setreg_b32 hwreg(HW_REG_STATUS), s_save_status //restore HW status(SCC) 266 s_rfe_b64 [ttmp0, ttmp1] 267end 268 // ********* End handling of non-CWSR traps ******************* 269 270/**************************************************************************/ 271/* save routine */ 272/**************************************************************************/ 273 274L_SAVE: 275 276if G8SR_DEBUG_TIMESTAMP 277 s_memrealtime s_g8sr_ts_save_s 278 s_waitcnt lgkmcnt(0) //FIXME, will cause xnack?? 279end 280 281 //check whether there is mem_viol 282 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 283 s_and_b32 s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_MEM_VIOL_MASK 284 s_cbranch_scc0 L_NO_PC_REWIND 285 286 //if so, need rewind PC assuming GDS operation gets NACKed 287 s_mov_b32 s_save_tmp, 0 //clear mem_viol bit 288 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT, 1), s_save_tmp //clear mem_viol bit 289 s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff //pc[47:32] 290 s_sub_u32 s_save_pc_lo, s_save_pc_lo, 8 //pc[31:0]-8 291 s_subb_u32 s_save_pc_hi, s_save_pc_hi, 0x0 // -scc 292 293L_NO_PC_REWIND: 294 s_mov_b32 s_save_tmp, 0 //clear saveCtx bit 295 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_SAVECTX_SHIFT, 1), s_save_tmp //clear saveCtx bit 296 297 s_mov_b32 s_save_xnack_mask_lo, xnack_mask_lo //save XNACK_MASK 298 s_mov_b32 s_save_xnack_mask_hi, xnack_mask_hi //save XNACK must before any memory operation 299 s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_RCNT_SHIFT, SQ_WAVE_IB_STS_RCNT_SIZE) //save RCNT 300 s_lshl_b32 s_save_tmp, s_save_tmp, S_SAVE_PC_HI_RCNT_SHIFT 301 s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp 302 s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT, SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE) //save FIRST_REPLAY 303 s_lshl_b32 s_save_tmp, s_save_tmp, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT 304 s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp 305 s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS) //clear RCNT and FIRST_REPLAY in IB_STS 306 s_and_b32 s_save_tmp, s_save_tmp, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG 307 308 s_setreg_b32 hwreg(HW_REG_IB_STS), s_save_tmp 309 310 /* inform SPI the readiness and wait for SPI's go signal */ 311 s_mov_b32 s_save_exec_lo, exec_lo //save EXEC and use EXEC for the go signal from SPI 312 s_mov_b32 s_save_exec_hi, exec_hi 313 s_mov_b64 exec, 0x0 //clear EXEC to get ready to receive 314 315if G8SR_DEBUG_TIMESTAMP 316 s_memrealtime s_g8sr_ts_sq_save_msg 317 s_waitcnt lgkmcnt(0) 318end 319 320 if (EMU_RUN_HACK) 321 322 else 323 s_sendmsg sendmsg(MSG_SAVEWAVE) //send SPI a message and wait for SPI's write to EXEC 324 end 325 326 // Set SPI_PRIO=2 to avoid starving instruction fetch in the waves we're waiting for. 327 s_or_b32 s_save_tmp, s_save_status, (2 << SQ_WAVE_STATUS_SPI_PRIO_SHIFT) 328 s_setreg_b32 hwreg(HW_REG_STATUS), s_save_tmp 329 330 L_SLEEP: 331 s_sleep 0x2 // sleep 1 (64clk) is not enough for 8 waves per SIMD, which will cause SQ hang, since the 7,8th wave could not get arbit to exec inst, while other waves are stuck into the sleep-loop and waiting for wrexec!=0 332 333 if (EMU_RUN_HACK) 334 335 else 336 s_cbranch_execz L_SLEEP 337 end 338 339if G8SR_DEBUG_TIMESTAMP 340 s_memrealtime s_g8sr_ts_spi_wrexec 341 s_waitcnt lgkmcnt(0) 342end 343 344 /* setup Resource Contants */ 345 if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_SINGLE_WAVE)) 346 //calculate wd_addr using absolute thread id 347 v_readlane_b32 s_save_tmp, v9, 0 348 s_lshr_b32 s_save_tmp, s_save_tmp, 6 349 s_mul_i32 s_save_tmp, s_save_tmp, WAVE_SPACE 350 s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO 351 s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI 352 s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL 353 else 354 end 355 if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_SINGLE_WAVE)) 356 s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO 357 s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI 358 s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL 359 else 360 end 361 362 363 s_mov_b32 s_save_buf_rsrc0, s_save_spi_init_lo //base_addr_lo 364 s_and_b32 s_save_buf_rsrc1, s_save_spi_init_hi, 0x0000FFFF //base_addr_hi 365 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE 366 s_mov_b32 s_save_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) although not neccessarily inited 367 s_mov_b32 s_save_buf_rsrc3, S_SAVE_BUF_RSRC_WORD3_MISC 368 s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_ATC_MASK 369 s_lshr_b32 s_save_tmp, s_save_tmp, (S_SAVE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT) //get ATC bit into position 370 s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, s_save_tmp //or ATC 371 s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_MTYPE_MASK 372 s_lshr_b32 s_save_tmp, s_save_tmp, (S_SAVE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT) //get MTYPE bits into position 373 s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, s_save_tmp //or MTYPE 374 375 //FIXME right now s_save_m0/s_save_mem_offset use tma_lo/tma_hi (might need to save them before using them?) 376 s_mov_b32 s_save_m0, m0 //save M0 377 378 /* global mem offset */ 379 s_mov_b32 s_save_mem_offset, 0x0 //mem offset initial value = 0 380 381 382 383 384 /* save HW registers */ 385 ////////////////////////////// 386 387 L_SAVE_HWREG: 388 // HWREG SR memory offset : size(VGPR)+size(SGPR) 389 get_vgpr_size_bytes(s_save_mem_offset) 390 get_sgpr_size_bytes(s_save_tmp) 391 s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp 392 393 394 s_mov_b32 s_save_buf_rsrc2, 0x4 //NUM_RECORDS in bytes 395 if (SWIZZLE_EN) 396 s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 397 else 398 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 399 end 400 401 402 write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) //M0 403 404 if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_FIRST_TIME)) 405 s_add_u32 s_save_pc_lo, s_save_pc_lo, 4 //pc[31:0]+4 406 s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0 //carry bit over 407 s_mov_b32 tba_lo, EMU_RUN_HACK_SAVE_FIRST_TIME_TBA_LO 408 s_mov_b32 tba_hi, EMU_RUN_HACK_SAVE_FIRST_TIME_TBA_HI 409 end 410 411 write_hwreg_to_mem(s_save_pc_lo, s_save_buf_rsrc0, s_save_mem_offset) //PC 412 write_hwreg_to_mem(s_save_pc_hi, s_save_buf_rsrc0, s_save_mem_offset) 413 write_hwreg_to_mem(s_save_exec_lo, s_save_buf_rsrc0, s_save_mem_offset) //EXEC 414 write_hwreg_to_mem(s_save_exec_hi, s_save_buf_rsrc0, s_save_mem_offset) 415 write_hwreg_to_mem(s_save_status, s_save_buf_rsrc0, s_save_mem_offset) //STATUS 416 417 //s_save_trapsts conflicts with s_save_alloc_size 418 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 419 write_hwreg_to_mem(s_save_trapsts, s_save_buf_rsrc0, s_save_mem_offset) //TRAPSTS 420 421 write_hwreg_to_mem(s_save_xnack_mask_lo, s_save_buf_rsrc0, s_save_mem_offset) //XNACK_MASK_LO 422 write_hwreg_to_mem(s_save_xnack_mask_hi, s_save_buf_rsrc0, s_save_mem_offset) //XNACK_MASK_HI 423 424 //use s_save_tmp would introduce conflict here between s_save_tmp and s_save_buf_rsrc2 425 s_getreg_b32 s_save_m0, hwreg(HW_REG_MODE) //MODE 426 write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) 427 write_hwreg_to_mem(tba_lo, s_save_buf_rsrc0, s_save_mem_offset) //TBA_LO 428 write_hwreg_to_mem(tba_hi, s_save_buf_rsrc0, s_save_mem_offset) //TBA_HI 429 430 431 432 /* the first wave in the threadgroup */ 433 // save fist_wave bits in tba_hi unused bit.26 434 s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK // extract fisrt wave bit 435 //s_or_b32 tba_hi, s_save_tmp, tba_hi // save first wave bit to tba_hi.bits[26] 436 s_mov_b32 s_save_exec_hi, 0x0 437 s_or_b32 s_save_exec_hi, s_save_tmp, s_save_exec_hi // save first wave bit to s_save_exec_hi.bits[26] 438 439 440 /* save SGPRs */ 441 // Save SGPR before LDS save, then the s0 to s4 can be used during LDS save... 442 ////////////////////////////// 443 444 // SGPR SR memory offset : size(VGPR) 445 get_vgpr_size_bytes(s_save_mem_offset) 446 // TODO, change RSRC word to rearrange memory layout for SGPRS 447 448 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size 449 s_add_u32 s_save_alloc_size, s_save_alloc_size, 1 450 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 4 //Number of SGPRs = (sgpr_size + 1) * 16 (non-zero value) 451 452 if (SGPR_SAVE_USE_SQC) 453 s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 2 //NUM_RECORDS in bytes 454 else 455 s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 8 //NUM_RECORDS in bytes (64 threads) 456 end 457 458 if (SWIZZLE_EN) 459 s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 460 else 461 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 462 end 463 464 465 // backup s_save_buf_rsrc0,1 to s_save_pc_lo/hi, since write_16sgpr_to_mem function will change the rsrc0 466 //s_mov_b64 s_save_pc_lo, s_save_buf_rsrc0 467 s_mov_b64 s_save_xnack_mask_lo, s_save_buf_rsrc0 468 s_add_u32 s_save_buf_rsrc0, s_save_buf_rsrc0, s_save_mem_offset 469 s_addc_u32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0 470 471 s_mov_b32 m0, 0x0 //SGPR initial index value =0 472 L_SAVE_SGPR_LOOP: 473 // SGPR is allocated in 16 SGPR granularity 474 s_movrels_b64 s0, s0 //s0 = s[0+m0], s1 = s[1+m0] 475 s_movrels_b64 s2, s2 //s2 = s[2+m0], s3 = s[3+m0] 476 s_movrels_b64 s4, s4 //s4 = s[4+m0], s5 = s[5+m0] 477 s_movrels_b64 s6, s6 //s6 = s[6+m0], s7 = s[7+m0] 478 s_movrels_b64 s8, s8 //s8 = s[8+m0], s9 = s[9+m0] 479 s_movrels_b64 s10, s10 //s10 = s[10+m0], s11 = s[11+m0] 480 s_movrels_b64 s12, s12 //s12 = s[12+m0], s13 = s[13+m0] 481 s_movrels_b64 s14, s14 //s14 = s[14+m0], s15 = s[15+m0] 482 483 write_16sgpr_to_mem(s0, s_save_buf_rsrc0, s_save_mem_offset) //PV: the best performance should be using s_buffer_store_dwordx4 484 s_add_u32 m0, m0, 16 //next sgpr index 485 s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 486 s_cbranch_scc1 L_SAVE_SGPR_LOOP //SGPR save is complete? 487 // restore s_save_buf_rsrc0,1 488 //s_mov_b64 s_save_buf_rsrc0, s_save_pc_lo 489 s_mov_b64 s_save_buf_rsrc0, s_save_xnack_mask_lo 490 491 492 493 494 /* save first 4 VGPR, then LDS save could use */ 495 // each wave will alloc 4 vgprs at least... 496 ///////////////////////////////////////////////////////////////////////////////////// 497 498 s_mov_b32 s_save_mem_offset, 0 499 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 500 s_mov_b32 exec_hi, 0xFFFFFFFF 501 502 if (SWIZZLE_EN) 503 s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 504 else 505 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 506 end 507 508 509 // VGPR Allocated in 4-GPR granularity 510 511if G8SR_VGPR_SR_IN_DWX4 512 // the const stride for DWx4 is 4*4 bytes 513 s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 514 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 // const stride to 4*4 bytes 515 516 buffer_store_dwordx4 v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 517 518 s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 519 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE // reset const stride to 4 bytes 520else 521 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 522 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256 523 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2 524 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3 525end 526 527 528 529 /* save LDS */ 530 ////////////////////////////// 531 532 L_SAVE_LDS: 533 534 // Change EXEC to all threads... 535 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 536 s_mov_b32 exec_hi, 0xFFFFFFFF 537 538 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) //lds_size 539 s_and_b32 s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF //lds_size is zero? 540 s_cbranch_scc0 L_SAVE_LDS_DONE //no lds used? jump to L_SAVE_DONE 541 542 s_barrier //LDS is used? wait for other waves in the same TG 543 //s_and_b32 s_save_tmp, tba_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK //exec is still used here 544 s_and_b32 s_save_tmp, s_save_exec_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK //exec is still used here 545 s_cbranch_scc0 L_SAVE_LDS_DONE 546 547 // first wave do LDS save; 548 549 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 6 //LDS size in dwords = lds_size * 64dw 550 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 2 //LDS size in bytes 551 s_mov_b32 s_save_buf_rsrc2, s_save_alloc_size //NUM_RECORDS in bytes 552 553 // LDS at offset: size(VGPR)+SIZE(SGPR)+SIZE(HWREG) 554 // 555 get_vgpr_size_bytes(s_save_mem_offset) 556 get_sgpr_size_bytes(s_save_tmp) 557 s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp 558 s_add_u32 s_save_mem_offset, s_save_mem_offset, get_hwreg_size_bytes() 559 560 561 if (SWIZZLE_EN) 562 s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 563 else 564 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 565 end 566 567 s_mov_b32 m0, 0x0 //lds_offset initial value = 0 568 569 570var LDS_DMA_ENABLE = 0 571var UNROLL = 0 572if UNROLL==0 && LDS_DMA_ENABLE==1 573 s_mov_b32 s3, 256*2 574 s_nop 0 575 s_nop 0 576 s_nop 0 577 L_SAVE_LDS_LOOP: 578 //TODO: looks the 2 buffer_store/load clause for s/r will hurt performance.??? 579 if (SAVE_LDS) //SPI always alloc LDS space in 128DW granularity 580 buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 // first 64DW 581 buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:256 // second 64DW 582 end 583 584 s_add_u32 m0, m0, s3 //every buffer_store_lds does 256 bytes 585 s_add_u32 s_save_mem_offset, s_save_mem_offset, s3 //mem offset increased by 256 bytes 586 s_cmp_lt_u32 m0, s_save_alloc_size //scc=(m0 < s_save_alloc_size) ? 1 : 0 587 s_cbranch_scc1 L_SAVE_LDS_LOOP //LDS save is complete? 588 589elsif LDS_DMA_ENABLE==1 && UNROLL==1 // UNROOL , has ichace miss 590 // store from higest LDS address to lowest 591 s_mov_b32 s3, 256*2 592 s_sub_u32 m0, s_save_alloc_size, s3 593 s_add_u32 s_save_mem_offset, s_save_mem_offset, m0 594 s_lshr_b32 s_save_alloc_size, s_save_alloc_size, 9 // how many 128 trunks... 595 s_sub_u32 s_save_alloc_size, 128, s_save_alloc_size // store from higheset addr to lowest 596 s_mul_i32 s_save_alloc_size, s_save_alloc_size, 6*4 // PC offset increment, each LDS save block cost 6*4 Bytes instruction 597 s_add_u32 s_save_alloc_size, s_save_alloc_size, 3*4 //2is the below 2 inst...//s_addc and s_setpc 598 s_nop 0 599 s_nop 0 600 s_nop 0 //pad 3 dw to let LDS_DMA align with 64Bytes 601 s_getpc_b64 s[0:1] // reuse s[0:1], since s[0:1] already saved 602 s_add_u32 s0, s0,s_save_alloc_size 603 s_addc_u32 s1, s1, 0 604 s_setpc_b64 s[0:1] 605 606 607 for var i =0; i< 128; i++ 608 // be careful to make here a 64Byte aligned address, which could improve performance... 609 buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:0 // first 64DW 610 buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:256 // second 64DW 611 612 if i!=127 613 s_sub_u32 m0, m0, s3 // use a sgpr to shrink 2DW-inst to 1DW inst to improve performance , i.e. pack more LDS_DMA inst to one Cacheline 614 s_sub_u32 s_save_mem_offset, s_save_mem_offset, s3 615 end 616 end 617 618else // BUFFER_STORE 619 v_mbcnt_lo_u32_b32 v2, 0xffffffff, 0x0 620 v_mbcnt_hi_u32_b32 v3, 0xffffffff, v2 // tid 621 v_mul_i32_i24 v2, v3, 8 // tid*8 622 v_mov_b32 v3, 256*2 623 s_mov_b32 m0, 0x10000 624 s_mov_b32 s0, s_save_buf_rsrc3 625 s_and_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, 0xFF7FFFFF // disable add_tid 626 s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, 0x58000 //DFMT 627 628L_SAVE_LDS_LOOP_VECTOR: 629 ds_read_b64 v[0:1], v2 //x =LDS[a], byte address 630 s_waitcnt lgkmcnt(0) 631 buffer_store_dwordx2 v[0:1], v2, s_save_buf_rsrc0, s_save_mem_offset offen:1 glc:1 slc:1 632// s_waitcnt vmcnt(0) 633 v_add_u32 v2, vcc[0:1], v2, v3 634 v_cmp_lt_u32 vcc[0:1], v2, s_save_alloc_size 635 s_cbranch_vccnz L_SAVE_LDS_LOOP_VECTOR 636 637 // restore rsrc3 638 s_mov_b32 s_save_buf_rsrc3, s0 639 640end 641 642L_SAVE_LDS_DONE: 643 644 645 /* save VGPRs - set the Rest VGPRs */ 646 ////////////////////////////////////////////////////////////////////////////////////// 647 L_SAVE_VGPR: 648 // VGPR SR memory offset: 0 649 // TODO rearrange the RSRC words to use swizzle for VGPR save... 650 651 s_mov_b32 s_save_mem_offset, (0+256*4) // for the rest VGPRs 652 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 653 s_mov_b32 exec_hi, 0xFFFFFFFF 654 655 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) //vpgr_size 656 s_add_u32 s_save_alloc_size, s_save_alloc_size, 1 657 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value) //FIXME for GFX, zero is possible 658 s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 8 //NUM_RECORDS in bytes (64 threads*4) 659 if (SWIZZLE_EN) 660 s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 661 else 662 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 663 end 664 665 666 // VGPR Allocated in 4-GPR granularity 667 668if G8SR_VGPR_SR_IN_DWX4 669 // the const stride for DWx4 is 4*4 bytes 670 s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 671 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 // const stride to 4*4 bytes 672 673 s_mov_b32 m0, 4 // skip first 4 VGPRs 674 s_cmp_lt_u32 m0, s_save_alloc_size 675 s_cbranch_scc0 L_SAVE_VGPR_LOOP_END // no more vgprs 676 677 s_set_gpr_idx_on m0, 0x1 // This will change M0 678 s_add_u32 s_save_alloc_size, s_save_alloc_size, 0x1000 // because above inst change m0 679L_SAVE_VGPR_LOOP: 680 v_mov_b32 v0, v0 // v0 = v[0+m0] 681 v_mov_b32 v1, v1 682 v_mov_b32 v2, v2 683 v_mov_b32 v3, v3 684 685 686 buffer_store_dwordx4 v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 687 s_add_u32 m0, m0, 4 688 s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 689 s_cmp_lt_u32 m0, s_save_alloc_size 690 s_cbranch_scc1 L_SAVE_VGPR_LOOP //VGPR save is complete? 691 s_set_gpr_idx_off 692L_SAVE_VGPR_LOOP_END: 693 694 s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 695 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE // reset const stride to 4 bytes 696else 697 // VGPR store using dw burst 698 s_mov_b32 m0, 0x4 //VGPR initial index value =0 699 s_cmp_lt_u32 m0, s_save_alloc_size 700 s_cbranch_scc0 L_SAVE_VGPR_END 701 702 703 s_set_gpr_idx_on m0, 0x1 //M0[7:0] = M0[7:0] and M0[15:12] = 0x1 704 s_add_u32 s_save_alloc_size, s_save_alloc_size, 0x1000 //add 0x1000 since we compare m0 against it later 705 706 L_SAVE_VGPR_LOOP: 707 v_mov_b32 v0, v0 //v0 = v[0+m0] 708 v_mov_b32 v1, v1 //v0 = v[0+m0] 709 v_mov_b32 v2, v2 //v0 = v[0+m0] 710 v_mov_b32 v3, v3 //v0 = v[0+m0] 711 712 if(USE_MTBUF_INSTEAD_OF_MUBUF) 713 tbuffer_store_format_x v0, v0, s_save_buf_rsrc0, s_save_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1 714 else 715 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 716 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256 717 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2 718 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3 719 end 720 721 s_add_u32 m0, m0, 4 //next vgpr index 722 s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 //every buffer_store_dword does 256 bytes 723 s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 724 s_cbranch_scc1 L_SAVE_VGPR_LOOP //VGPR save is complete? 725 s_set_gpr_idx_off 726end 727 728L_SAVE_VGPR_END: 729 730 731 732 733 734 735 /* S_PGM_END_SAVED */ //FIXME graphics ONLY 736 if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_NORMAL_EXIT)) 737 s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff //pc[47:32] 738 s_add_u32 s_save_pc_lo, s_save_pc_lo, 4 //pc[31:0]+4 739 s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0 //carry bit over 740 s_rfe_b64 s_save_pc_lo //Return to the main shader program 741 else 742 end 743 744// Save Done timestamp 745if G8SR_DEBUG_TIMESTAMP 746 s_memrealtime s_g8sr_ts_save_d 747 // SGPR SR memory offset : size(VGPR) 748 get_vgpr_size_bytes(s_save_mem_offset) 749 s_add_u32 s_save_mem_offset, s_save_mem_offset, G8SR_DEBUG_TS_SAVE_D_OFFSET 750 s_waitcnt lgkmcnt(0) //FIXME, will cause xnack?? 751 // Need reset rsrc2?? 752 s_mov_b32 m0, s_save_mem_offset 753 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 754 s_buffer_store_dwordx2 s_g8sr_ts_save_d, s_save_buf_rsrc0, m0 glc:1 755end 756 757 758 s_branch L_END_PGM 759 760 761 762/**************************************************************************/ 763/* restore routine */ 764/**************************************************************************/ 765 766L_RESTORE: 767 /* Setup Resource Contants */ 768 if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL)) 769 //calculate wd_addr using absolute thread id 770 v_readlane_b32 s_restore_tmp, v9, 0 771 s_lshr_b32 s_restore_tmp, s_restore_tmp, 6 772 s_mul_i32 s_restore_tmp, s_restore_tmp, WAVE_SPACE 773 s_add_i32 s_restore_spi_init_lo, s_restore_tmp, WG_BASE_ADDR_LO 774 s_mov_b32 s_restore_spi_init_hi, WG_BASE_ADDR_HI 775 s_and_b32 s_restore_spi_init_hi, s_restore_spi_init_hi, CTX_RESTORE_CONTROL 776 else 777 end 778 779if G8SR_DEBUG_TIMESTAMP 780 s_memrealtime s_g8sr_ts_restore_s 781 s_waitcnt lgkmcnt(0) //FIXME, will cause xnack?? 782 // tma_lo/hi are sgpr 110, 111, which will not used for 112 SGPR allocated case... 783 s_mov_b32 s_restore_pc_lo, s_g8sr_ts_restore_s[0] 784 s_mov_b32 s_restore_pc_hi, s_g8sr_ts_restore_s[1] //backup ts to ttmp0/1, sicne exec will be finally restored.. 785end 786 787 788 789 s_mov_b32 s_restore_buf_rsrc0, s_restore_spi_init_lo //base_addr_lo 790 s_and_b32 s_restore_buf_rsrc1, s_restore_spi_init_hi, 0x0000FFFF //base_addr_hi 791 s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE 792 s_mov_b32 s_restore_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) 793 s_mov_b32 s_restore_buf_rsrc3, S_RESTORE_BUF_RSRC_WORD3_MISC 794 s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_ATC_MASK 795 s_lshr_b32 s_restore_tmp, s_restore_tmp, (S_RESTORE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT) //get ATC bit into position 796 s_or_b32 s_restore_buf_rsrc3, s_restore_buf_rsrc3, s_restore_tmp //or ATC 797 s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_MTYPE_MASK 798 s_lshr_b32 s_restore_tmp, s_restore_tmp, (S_RESTORE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT) //get MTYPE bits into position 799 s_or_b32 s_restore_buf_rsrc3, s_restore_buf_rsrc3, s_restore_tmp //or MTYPE 800 801 /* global mem offset */ 802// s_mov_b32 s_restore_mem_offset, 0x0 //mem offset initial value = 0 803 804 /* the first wave in the threadgroup */ 805 s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_FIRST_WAVE_MASK 806 s_cbranch_scc0 L_RESTORE_VGPR 807 808 /* restore LDS */ 809 ////////////////////////////// 810 L_RESTORE_LDS: 811 812 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on //be consistent with SAVE although can be moved ahead 813 s_mov_b32 exec_hi, 0xFFFFFFFF 814 815 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) //lds_size 816 s_and_b32 s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF //lds_size is zero? 817 s_cbranch_scc0 L_RESTORE_VGPR //no lds used? jump to L_RESTORE_VGPR 818 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 6 //LDS size in dwords = lds_size * 64dw 819 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 2 //LDS size in bytes 820 s_mov_b32 s_restore_buf_rsrc2, s_restore_alloc_size //NUM_RECORDS in bytes 821 822 // LDS at offset: size(VGPR)+SIZE(SGPR)+SIZE(HWREG) 823 // 824 get_vgpr_size_bytes(s_restore_mem_offset) 825 get_sgpr_size_bytes(s_restore_tmp) 826 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 827 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_hwreg_size_bytes() //FIXME, Check if offset overflow??? 828 829 830 if (SWIZZLE_EN) 831 s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 832 else 833 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 834 end 835 s_mov_b32 m0, 0x0 //lds_offset initial value = 0 836 837 L_RESTORE_LDS_LOOP: 838 if (SAVE_LDS) 839 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 // first 64DW 840 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 offset:256 // second 64DW 841 end 842 s_add_u32 m0, m0, 256*2 // 128 DW 843 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*2 //mem offset increased by 128DW 844 s_cmp_lt_u32 m0, s_restore_alloc_size //scc=(m0 < s_restore_alloc_size) ? 1 : 0 845 s_cbranch_scc1 L_RESTORE_LDS_LOOP //LDS restore is complete? 846 847 848 /* restore VGPRs */ 849 ////////////////////////////// 850 L_RESTORE_VGPR: 851 // VGPR SR memory offset : 0 852 s_mov_b32 s_restore_mem_offset, 0x0 853 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on //be consistent with SAVE although can be moved ahead 854 s_mov_b32 exec_hi, 0xFFFFFFFF 855 856 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) //vpgr_size 857 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 1 858 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value) 859 s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 8 //NUM_RECORDS in bytes (64 threads*4) 860 if (SWIZZLE_EN) 861 s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 862 else 863 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 864 end 865 866if G8SR_VGPR_SR_IN_DWX4 867 get_vgpr_size_bytes(s_restore_mem_offset) 868 s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 869 870 // the const stride for DWx4 is 4*4 bytes 871 s_and_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, 0x0000FFFF // reset const stride to 0 872 s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, G8SR_RESTORE_BUF_RSRC_WORD1_STRIDE_DWx4 // const stride to 4*4 bytes 873 874 s_mov_b32 m0, s_restore_alloc_size 875 s_set_gpr_idx_on m0, 0x8 // Note.. This will change m0 876 877L_RESTORE_VGPR_LOOP: 878 buffer_load_dwordx4 v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 879 s_waitcnt vmcnt(0) 880 s_sub_u32 m0, m0, 4 881 v_mov_b32 v0, v0 // v[0+m0] = v0 882 v_mov_b32 v1, v1 883 v_mov_b32 v2, v2 884 v_mov_b32 v3, v3 885 s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 886 s_cmp_eq_u32 m0, 0x8000 887 s_cbranch_scc0 L_RESTORE_VGPR_LOOP 888 s_set_gpr_idx_off 889 890 s_and_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, 0x0000FFFF // reset const stride to 0 891 s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE // const stride to 4*4 bytes 892 893else 894 // VGPR load using dw burst 895 s_mov_b32 s_restore_mem_offset_save, s_restore_mem_offset // restore start with v1, v0 will be the last 896 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 897 s_mov_b32 m0, 4 //VGPR initial index value = 1 898 s_set_gpr_idx_on m0, 0x8 //M0[7:0] = M0[7:0] and M0[15:12] = 0x8 899 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 0x8000 //add 0x8000 since we compare m0 against it later 900 901 L_RESTORE_VGPR_LOOP: 902 if(USE_MTBUF_INSTEAD_OF_MUBUF) 903 tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1 904 else 905 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 906 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256 907 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*2 908 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*3 909 end 910 s_waitcnt vmcnt(0) //ensure data ready 911 v_mov_b32 v0, v0 //v[0+m0] = v0 912 v_mov_b32 v1, v1 913 v_mov_b32 v2, v2 914 v_mov_b32 v3, v3 915 s_add_u32 m0, m0, 4 //next vgpr index 916 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 //every buffer_load_dword does 256 bytes 917 s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0 918 s_cbranch_scc1 L_RESTORE_VGPR_LOOP //VGPR restore (except v0) is complete? 919 s_set_gpr_idx_off 920 /* VGPR restore on v0 */ 921 if(USE_MTBUF_INSTEAD_OF_MUBUF) 922 tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1 923 else 924 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 925 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256 926 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*2 927 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*3 928 end 929 930end 931 932 /* restore SGPRs */ 933 ////////////////////////////// 934 935 // SGPR SR memory offset : size(VGPR) 936 get_vgpr_size_bytes(s_restore_mem_offset) 937 get_sgpr_size_bytes(s_restore_tmp) 938 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 939 s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 16*4 // restore SGPR from S[n] to S[0], by 16 sgprs group 940 // TODO, change RSRC word to rearrange memory layout for SGPRS 941 942 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size 943 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 1 944 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 4 //Number of SGPRs = (sgpr_size + 1) * 16 (non-zero value) 945 946 if (SGPR_SAVE_USE_SQC) 947 s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 2 //NUM_RECORDS in bytes 948 else 949 s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 8 //NUM_RECORDS in bytes (64 threads) 950 end 951 if (SWIZZLE_EN) 952 s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 953 else 954 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 955 end 956 957 /* If 112 SGPRs ar allocated, 4 sgprs are not used TBA(108,109),TMA(110,111), 958 However, we are safe to restore these 4 SGPRs anyway, since TBA,TMA will later be restored by HWREG 959 */ 960 s_mov_b32 m0, s_restore_alloc_size 961 962 L_RESTORE_SGPR_LOOP: 963 read_16sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset) //PV: further performance improvement can be made 964 s_waitcnt lgkmcnt(0) //ensure data ready 965 966 s_sub_u32 m0, m0, 16 // Restore from S[n] to S[0] 967 968 s_movreld_b64 s0, s0 //s[0+m0] = s0 969 s_movreld_b64 s2, s2 970 s_movreld_b64 s4, s4 971 s_movreld_b64 s6, s6 972 s_movreld_b64 s8, s8 973 s_movreld_b64 s10, s10 974 s_movreld_b64 s12, s12 975 s_movreld_b64 s14, s14 976 977 s_cmp_eq_u32 m0, 0 //scc = (m0 < s_restore_alloc_size) ? 1 : 0 978 s_cbranch_scc0 L_RESTORE_SGPR_LOOP //SGPR restore (except s0) is complete? 979 980 /* restore HW registers */ 981 ////////////////////////////// 982 L_RESTORE_HWREG: 983 984 985if G8SR_DEBUG_TIMESTAMP 986 s_mov_b32 s_g8sr_ts_restore_s[0], s_restore_pc_lo 987 s_mov_b32 s_g8sr_ts_restore_s[1], s_restore_pc_hi 988end 989 990 // HWREG SR memory offset : size(VGPR)+size(SGPR) 991 get_vgpr_size_bytes(s_restore_mem_offset) 992 get_sgpr_size_bytes(s_restore_tmp) 993 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 994 995 996 s_mov_b32 s_restore_buf_rsrc2, 0x4 //NUM_RECORDS in bytes 997 if (SWIZZLE_EN) 998 s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 999 else 1000 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 1001 end 1002 1003 read_hwreg_from_mem(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset) //M0 1004 read_hwreg_from_mem(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //PC 1005 read_hwreg_from_mem(s_restore_pc_hi, s_restore_buf_rsrc0, s_restore_mem_offset) 1006 read_hwreg_from_mem(s_restore_exec_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //EXEC 1007 read_hwreg_from_mem(s_restore_exec_hi, s_restore_buf_rsrc0, s_restore_mem_offset) 1008 read_hwreg_from_mem(s_restore_status, s_restore_buf_rsrc0, s_restore_mem_offset) //STATUS 1009 read_hwreg_from_mem(s_restore_trapsts, s_restore_buf_rsrc0, s_restore_mem_offset) //TRAPSTS 1010 read_hwreg_from_mem(xnack_mask_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //XNACK_MASK_LO 1011 read_hwreg_from_mem(xnack_mask_hi, s_restore_buf_rsrc0, s_restore_mem_offset) //XNACK_MASK_HI 1012 read_hwreg_from_mem(s_restore_mode, s_restore_buf_rsrc0, s_restore_mem_offset) //MODE 1013 read_hwreg_from_mem(tba_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //TBA_LO 1014 read_hwreg_from_mem(tba_hi, s_restore_buf_rsrc0, s_restore_mem_offset) //TBA_HI 1015 1016 s_waitcnt lgkmcnt(0) //from now on, it is safe to restore STATUS and IB_STS 1017 1018 //for normal save & restore, the saved PC points to the next inst to execute, no adjustment needs to be made, otherwise: 1019 if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL)) 1020 s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 8 //pc[31:0]+8 //two back-to-back s_trap are used (first for save and second for restore) 1021 s_addc_u32 s_restore_pc_hi, s_restore_pc_hi, 0x0 //carry bit over 1022 end 1023 if ((EMU_RUN_HACK) && (EMU_RUN_HACK_RESTORE_NORMAL)) 1024 s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 4 //pc[31:0]+4 // save is hack through s_trap but restore is normal 1025 s_addc_u32 s_restore_pc_hi, s_restore_pc_hi, 0x0 //carry bit over 1026 end 1027 1028 s_mov_b32 m0, s_restore_m0 1029 s_mov_b32 exec_lo, s_restore_exec_lo 1030 s_mov_b32 exec_hi, s_restore_exec_hi 1031 1032 s_and_b32 s_restore_m0, SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK, s_restore_trapsts 1033 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE), s_restore_m0 1034 s_and_b32 s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK, s_restore_trapsts 1035 s_lshr_b32 s_restore_m0, s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT 1036 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE), s_restore_m0 1037 //s_setreg_b32 hwreg(HW_REG_TRAPSTS), s_restore_trapsts //don't overwrite SAVECTX bit as it may be set through external SAVECTX during restore 1038 s_setreg_b32 hwreg(HW_REG_MODE), s_restore_mode 1039 //reuse s_restore_m0 as a temp register 1040 s_and_b32 s_restore_m0, s_restore_pc_hi, S_SAVE_PC_HI_RCNT_MASK 1041 s_lshr_b32 s_restore_m0, s_restore_m0, S_SAVE_PC_HI_RCNT_SHIFT 1042 s_lshl_b32 s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_RCNT_SHIFT 1043 s_mov_b32 s_restore_tmp, 0x0 //IB_STS is zero 1044 s_or_b32 s_restore_tmp, s_restore_tmp, s_restore_m0 1045 s_and_b32 s_restore_m0, s_restore_pc_hi, S_SAVE_PC_HI_FIRST_REPLAY_MASK 1046 s_lshr_b32 s_restore_m0, s_restore_m0, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT 1047 s_lshl_b32 s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT 1048 s_or_b32 s_restore_tmp, s_restore_tmp, s_restore_m0 1049 s_and_b32 s_restore_m0, s_restore_status, SQ_WAVE_STATUS_INST_ATC_MASK 1050 s_lshr_b32 s_restore_m0, s_restore_m0, SQ_WAVE_STATUS_INST_ATC_SHIFT 1051 s_setreg_b32 hwreg(HW_REG_IB_STS), s_restore_tmp 1052 1053 s_and_b32 s_restore_pc_hi, s_restore_pc_hi, 0x0000ffff //pc[47:32] //Do it here in order not to affect STATUS 1054 s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32 1055 s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32 1056 s_setreg_b32 hwreg(HW_REG_STATUS), s_restore_status // SCC is included, which is changed by previous salu 1057 1058 s_barrier //barrier to ensure the readiness of LDS before access attempts from any other wave in the same TG //FIXME not performance-optimal at this time 1059 1060if G8SR_DEBUG_TIMESTAMP 1061 s_memrealtime s_g8sr_ts_restore_d 1062 s_waitcnt lgkmcnt(0) 1063end 1064 1065// s_rfe_b64 s_restore_pc_lo //Return to the main shader program and resume execution 1066 s_rfe_restore_b64 s_restore_pc_lo, s_restore_m0 // s_restore_m0[0] is used to set STATUS.inst_atc 1067 1068 1069/**************************************************************************/ 1070/* the END */ 1071/**************************************************************************/ 1072L_END_PGM: 1073 s_endpgm 1074 1075end 1076 1077 1078/**************************************************************************/ 1079/* the helper functions */ 1080/**************************************************************************/ 1081 1082//Only for save hwreg to mem 1083function write_hwreg_to_mem(s, s_rsrc, s_mem_offset) 1084 s_mov_b32 exec_lo, m0 //assuming exec_lo is not needed anymore from this point on 1085 s_mov_b32 m0, s_mem_offset 1086 s_buffer_store_dword s, s_rsrc, m0 glc:1 1087 s_add_u32 s_mem_offset, s_mem_offset, 4 1088 s_mov_b32 m0, exec_lo 1089end 1090 1091 1092// HWREG are saved before SGPRs, so all HWREG could be use. 1093function write_16sgpr_to_mem(s, s_rsrc, s_mem_offset) 1094 1095 s_buffer_store_dwordx4 s[0], s_rsrc, 0 glc:1 1096 s_buffer_store_dwordx4 s[4], s_rsrc, 16 glc:1 1097 s_buffer_store_dwordx4 s[8], s_rsrc, 32 glc:1 1098 s_buffer_store_dwordx4 s[12], s_rsrc, 48 glc:1 1099 s_add_u32 s_rsrc[0], s_rsrc[0], 4*16 1100 s_addc_u32 s_rsrc[1], s_rsrc[1], 0x0 // +scc 1101end 1102 1103 1104function read_hwreg_from_mem(s, s_rsrc, s_mem_offset) 1105 s_buffer_load_dword s, s_rsrc, s_mem_offset glc:1 1106 s_add_u32 s_mem_offset, s_mem_offset, 4 1107end 1108 1109function read_16sgpr_from_mem(s, s_rsrc, s_mem_offset) 1110 s_buffer_load_dwordx16 s, s_rsrc, s_mem_offset glc:1 1111 s_sub_u32 s_mem_offset, s_mem_offset, 4*16 1112end 1113 1114 1115 1116function get_lds_size_bytes(s_lds_size_byte) 1117 // SQ LDS granularity is 64DW, while PGM_RSRC2.lds_size is in granularity 128DW 1118 s_getreg_b32 s_lds_size_byte, hwreg(HW_REG_LDS_ALLOC, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) // lds_size 1119 s_lshl_b32 s_lds_size_byte, s_lds_size_byte, 8 //LDS size in dwords = lds_size * 64 *4Bytes // granularity 64DW 1120end 1121 1122function get_vgpr_size_bytes(s_vgpr_size_byte) 1123 s_getreg_b32 s_vgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) //vpgr_size 1124 s_add_u32 s_vgpr_size_byte, s_vgpr_size_byte, 1 1125 s_lshl_b32 s_vgpr_size_byte, s_vgpr_size_byte, (2+8) //Number of VGPRs = (vgpr_size + 1) * 4 * 64 * 4 (non-zero value) //FIXME for GFX, zero is possible 1126end 1127 1128function get_sgpr_size_bytes(s_sgpr_size_byte) 1129 s_getreg_b32 s_sgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size 1130 s_add_u32 s_sgpr_size_byte, s_sgpr_size_byte, 1 1131 s_lshl_b32 s_sgpr_size_byte, s_sgpr_size_byte, 6 //Number of SGPRs = (sgpr_size + 1) * 16 *4 (non-zero value) 1132end 1133 1134function get_hwreg_size_bytes 1135 return 128 //HWREG size 128 bytes 1136end 1137