1/* 2 * Copyright 2015-2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23/* To compile this assembly code: 24 * PROJECT=vi ./sp3 cwsr_trap_handler_gfx8.asm -hex tmp.hex 25 */ 26 27/* HW (VI) source code for CWSR trap handler */ 28/* Version 18 + multiple trap handler */ 29 30// this performance-optimal version was originally from Seven Xu at SRDC 31 32// Revison #18 --... 33/* Rev History 34** #1. Branch from gc dv. //gfxip/gfx8/main/src/test/suites/block/cs/sr/cs_trap_handler.sp3#1,#50, #51, #52-53(Skip, Already Fixed by PV), #54-56(merged),#57-58(mergerd, skiped-already fixed by PV) 35** #4. SR Memory Layout: 36** 1. VGPR-SGPR-HWREG-{LDS} 37** 2. tba_hi.bits.26 - reconfigured as the first wave in tg bits, for defer Save LDS for a threadgroup.. performance concern.. 38** #5. Update: 1. Accurate g8sr_ts_save_d timestamp 39** #6. Update: 1. Fix s_barrier usage; 2. VGPR s/r using swizzle buffer?(NoNeed, already matched the swizzle pattern, more investigation) 40** #7. Update: 1. don't barrier if noLDS 41** #8. Branch: 1. Branch to ver#0, which is very similar to gc dv version 42** 2. Fix SQ issue by s_sleep 2 43** #9. Update: 1. Fix scc restore failed issue, restore wave_status at last 44** 2. optimize s_buffer save by burst 16sgprs... 45** #10. Update 1. Optimize restore sgpr by busrt 16 sgprs. 46** #11. Update 1. Add 2 more timestamp for debug version 47** #12. Update 1. Add VGPR SR using DWx4, some case improve and some case drop performance 48** #13. Integ 1. Always use MUBUF for PV trap shader... 49** #14. Update 1. s_buffer_store soft clause... 50** #15. Update 1. PERF - sclar write with glc:0/mtype0 to allow L2 combine. perf improvement a lot. 51** #16. Update 1. PRRF - UNROLL LDS_DMA got 2500cycle save in IP tree 52** #17. Update 1. FUNC - LDS_DMA has issues while ATC, replace with ds_read/buffer_store for save part[TODO restore part] 53** 2. PERF - Save LDS before save VGPR to cover LDS save long latency... 54** #18. Update 1. FUNC - Implicitly estore STATUS.VCCZ, which is not writable by s_setreg_b32 55** 2. FUNC - Handle non-CWSR traps 56*/ 57 58var G8SR_WDMEM_HWREG_OFFSET = 0 59var G8SR_WDMEM_SGPR_OFFSET = 128 // in bytes 60 61// Keep definition same as the app shader, These 2 time stamps are part of the app shader... Should before any Save and after restore. 62 63var G8SR_DEBUG_TIMESTAMP = 0 64var G8SR_DEBUG_TS_SAVE_D_OFFSET = 40*4 // ts_save_d timestamp offset relative to SGPR_SR_memory_offset 65var s_g8sr_ts_save_s = s[34:35] // save start 66var s_g8sr_ts_sq_save_msg = s[36:37] // The save shader send SAVEWAVE msg to spi 67var s_g8sr_ts_spi_wrexec = s[38:39] // the SPI write the sr address to SQ 68var s_g8sr_ts_save_d = s[40:41] // save end 69var s_g8sr_ts_restore_s = s[42:43] // restore start 70var s_g8sr_ts_restore_d = s[44:45] // restore end 71 72var G8SR_VGPR_SR_IN_DWX4 = 0 73var G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 = 0x00100000 // DWx4 stride is 4*4Bytes 74var G8SR_RESTORE_BUF_RSRC_WORD1_STRIDE_DWx4 = G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 75 76 77/*************************************************************************/ 78/* control on how to run the shader */ 79/*************************************************************************/ 80//any hack that needs to be made to run this code in EMU (either because various EMU code are not ready or no compute save & restore in EMU run) 81var EMU_RUN_HACK = 0 82var EMU_RUN_HACK_RESTORE_NORMAL = 0 83var EMU_RUN_HACK_SAVE_NORMAL_EXIT = 0 84var EMU_RUN_HACK_SAVE_SINGLE_WAVE = 0 85var EMU_RUN_HACK_SAVE_FIRST_TIME = 0 //for interrupted restore in which the first save is through EMU_RUN_HACK 86var EMU_RUN_HACK_SAVE_FIRST_TIME_TBA_LO = 0 //for interrupted restore in which the first save is through EMU_RUN_HACK 87var EMU_RUN_HACK_SAVE_FIRST_TIME_TBA_HI = 0 //for interrupted restore in which the first save is through EMU_RUN_HACK 88var SAVE_LDS = 1 89var WG_BASE_ADDR_LO = 0x9000a000 90var WG_BASE_ADDR_HI = 0x0 91var WAVE_SPACE = 0x5000 //memory size that each wave occupies in workgroup state mem 92var CTX_SAVE_CONTROL = 0x0 93var CTX_RESTORE_CONTROL = CTX_SAVE_CONTROL 94var SIM_RUN_HACK = 0 //any hack that needs to be made to run this code in SIM (either because various RTL code are not ready or no compute save & restore in RTL run) 95var SGPR_SAVE_USE_SQC = 1 //use SQC D$ to do the write 96var USE_MTBUF_INSTEAD_OF_MUBUF = 0 //because TC EMU currently asserts on 0 of // overload DFMT field to carry 4 more bits of stride for MUBUF opcodes 97var SWIZZLE_EN = 0 //whether we use swizzled buffer addressing 98 99/**************************************************************************/ 100/* variables */ 101/**************************************************************************/ 102var SQ_WAVE_STATUS_INST_ATC_SHIFT = 23 103var SQ_WAVE_STATUS_INST_ATC_MASK = 0x00800000 104var SQ_WAVE_STATUS_SPI_PRIO_SHIFT = 1 105var SQ_WAVE_STATUS_SPI_PRIO_MASK = 0x00000006 106var SQ_WAVE_STATUS_PRE_SPI_PRIO_SHIFT = 0 107var SQ_WAVE_STATUS_PRE_SPI_PRIO_SIZE = 1 108var SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT = 3 109var SQ_WAVE_STATUS_POST_SPI_PRIO_SIZE = 29 110 111var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT = 12 112var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE = 9 113var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 8 114var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE = 6 115var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT = 24 116var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE = 3 //FIXME sq.blk still has 4 bits at this time while SQ programming guide has 3 bits 117 118var SQ_WAVE_TRAPSTS_SAVECTX_MASK = 0x400 119var SQ_WAVE_TRAPSTS_EXCE_MASK = 0x1FF // Exception mask 120var SQ_WAVE_TRAPSTS_SAVECTX_SHIFT = 10 121var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK = 0x100 122var SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT = 8 123var SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK = 0x3FF 124var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT = 0x0 125var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE = 10 126var SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK = 0xFFFFF800 127var SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT = 11 128var SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE = 21 129 130var SQ_WAVE_IB_STS_RCNT_SHIFT = 16 //FIXME 131var SQ_WAVE_IB_STS_RCNT_SIZE = 4 //FIXME 132var SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT = 15 //FIXME 133var SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE = 1 //FIXME 134var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG = 0x00007FFF //FIXME 135 136var SQ_BUF_RSRC_WORD1_ATC_SHIFT = 24 137var SQ_BUF_RSRC_WORD3_MTYPE_SHIFT = 27 138 139 140/* Save */ 141var S_SAVE_BUF_RSRC_WORD1_STRIDE = 0x00040000 //stride is 4 bytes 142var S_SAVE_BUF_RSRC_WORD3_MISC = 0x00807FAC //SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14] when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE 143 144var S_SAVE_SPI_INIT_ATC_MASK = 0x08000000 //bit[27]: ATC bit 145var S_SAVE_SPI_INIT_ATC_SHIFT = 27 146var S_SAVE_SPI_INIT_MTYPE_MASK = 0x70000000 //bit[30:28]: Mtype 147var S_SAVE_SPI_INIT_MTYPE_SHIFT = 28 148var S_SAVE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG 149var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT = 26 150 151var S_SAVE_PC_HI_RCNT_SHIFT = 28 //FIXME check with Brian to ensure all fields other than PC[47:0] can be used 152var S_SAVE_PC_HI_RCNT_MASK = 0xF0000000 //FIXME 153var S_SAVE_PC_HI_FIRST_REPLAY_SHIFT = 27 //FIXME 154var S_SAVE_PC_HI_FIRST_REPLAY_MASK = 0x08000000 //FIXME 155 156var s_save_spi_init_lo = exec_lo 157var s_save_spi_init_hi = exec_hi 158 159 //tba_lo and tba_hi need to be saved/restored 160var s_save_pc_lo = ttmp0 //{TTMP1, TTMP0} = {3'h0,pc_rewind[3:0], HT[0],trapID[7:0], PC[47:0]} 161var s_save_pc_hi = ttmp1 162var s_save_exec_lo = ttmp2 163var s_save_exec_hi = ttmp3 164var s_save_status = ttmp4 165var s_save_trapsts = ttmp5 //not really used until the end of the SAVE routine 166var s_save_xnack_mask_lo = ttmp6 167var s_save_xnack_mask_hi = ttmp7 168var s_save_buf_rsrc0 = ttmp8 169var s_save_buf_rsrc1 = ttmp9 170var s_save_buf_rsrc2 = ttmp10 171var s_save_buf_rsrc3 = ttmp11 172 173var s_save_mem_offset = tma_lo 174var s_save_alloc_size = s_save_trapsts //conflict 175var s_save_tmp = s_save_buf_rsrc2 //shared with s_save_buf_rsrc2 (conflict: should not use mem access with s_save_tmp at the same time) 176var s_save_m0 = tma_hi 177 178/* Restore */ 179var S_RESTORE_BUF_RSRC_WORD1_STRIDE = S_SAVE_BUF_RSRC_WORD1_STRIDE 180var S_RESTORE_BUF_RSRC_WORD3_MISC = S_SAVE_BUF_RSRC_WORD3_MISC 181 182var S_RESTORE_SPI_INIT_ATC_MASK = 0x08000000 //bit[27]: ATC bit 183var S_RESTORE_SPI_INIT_ATC_SHIFT = 27 184var S_RESTORE_SPI_INIT_MTYPE_MASK = 0x70000000 //bit[30:28]: Mtype 185var S_RESTORE_SPI_INIT_MTYPE_SHIFT = 28 186var S_RESTORE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG 187var S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT = 26 188 189var S_RESTORE_PC_HI_RCNT_SHIFT = S_SAVE_PC_HI_RCNT_SHIFT 190var S_RESTORE_PC_HI_RCNT_MASK = S_SAVE_PC_HI_RCNT_MASK 191var S_RESTORE_PC_HI_FIRST_REPLAY_SHIFT = S_SAVE_PC_HI_FIRST_REPLAY_SHIFT 192var S_RESTORE_PC_HI_FIRST_REPLAY_MASK = S_SAVE_PC_HI_FIRST_REPLAY_MASK 193 194var s_restore_spi_init_lo = exec_lo 195var s_restore_spi_init_hi = exec_hi 196 197var s_restore_mem_offset = ttmp2 198var s_restore_alloc_size = ttmp3 199var s_restore_tmp = ttmp6 //tba_lo/hi need to be restored 200var s_restore_mem_offset_save = s_restore_tmp //no conflict 201 202var s_restore_m0 = s_restore_alloc_size //no conflict 203 204var s_restore_mode = ttmp7 205 206var s_restore_pc_lo = ttmp0 207var s_restore_pc_hi = ttmp1 208var s_restore_exec_lo = tma_lo //no conflict 209var s_restore_exec_hi = tma_hi //no conflict 210var s_restore_status = ttmp4 211var s_restore_trapsts = ttmp5 212var s_restore_xnack_mask_lo = xnack_mask_lo 213var s_restore_xnack_mask_hi = xnack_mask_hi 214var s_restore_buf_rsrc0 = ttmp8 215var s_restore_buf_rsrc1 = ttmp9 216var s_restore_buf_rsrc2 = ttmp10 217var s_restore_buf_rsrc3 = ttmp11 218 219/**************************************************************************/ 220/* trap handler entry points */ 221/**************************************************************************/ 222/* Shader Main*/ 223 224shader main 225 asic(VI) 226 type(CS) 227 228 229 if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL)) //hack to use trap_id for determining save/restore 230 //FIXME VCCZ un-init assertion s_getreg_b32 s_save_status, hwreg(HW_REG_STATUS) //save STATUS since we will change SCC 231 s_and_b32 s_save_tmp, s_save_pc_hi, 0xffff0000 //change SCC 232 s_cmp_eq_u32 s_save_tmp, 0x007e0000 //Save: trap_id = 0x7e. Restore: trap_id = 0x7f. 233 s_cbranch_scc0 L_JUMP_TO_RESTORE //do not need to recover STATUS here since we are going to RESTORE 234 //FIXME s_setreg_b32 hwreg(HW_REG_STATUS), s_save_status //need to recover STATUS since we are going to SAVE 235 s_branch L_SKIP_RESTORE //NOT restore, SAVE actually 236 else 237 s_branch L_SKIP_RESTORE //NOT restore. might be a regular trap or save 238 end 239 240L_JUMP_TO_RESTORE: 241 s_branch L_RESTORE //restore 242 243L_SKIP_RESTORE: 244 245 s_getreg_b32 s_save_status, hwreg(HW_REG_STATUS) //save STATUS since we will change SCC 246 s_andn2_b32 s_save_status, s_save_status, SQ_WAVE_STATUS_SPI_PRIO_MASK //check whether this is for save 247 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 248 s_and_b32 s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK //check whether this is for save 249 s_cbranch_scc1 L_SAVE //this is the operation for save 250 251 // ********* Handle non-CWSR traps ******************* 252if (!EMU_RUN_HACK) 253 /* read tba and tma for next level trap handler, ttmp4 is used as s_save_status */ 254 s_load_dwordx4 [ttmp8,ttmp9,ttmp10, ttmp11], [tma_lo,tma_hi], 0 255 s_waitcnt lgkmcnt(0) 256 s_or_b32 ttmp7, ttmp8, ttmp9 257 s_cbranch_scc0 L_NO_NEXT_TRAP //next level trap handler not been set 258 set_status_without_spi_prio(s_save_status, ttmp2) //restore HW status(SCC) 259 s_setpc_b64 [ttmp8,ttmp9] //jump to next level trap handler 260 261L_NO_NEXT_TRAP: 262 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 263 s_and_b32 s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_EXCE_MASK // Check whether it is an exception 264 s_cbranch_scc1 L_EXCP_CASE // Exception, jump back to the shader program directly. 265 s_add_u32 ttmp0, ttmp0, 4 // S_TRAP case, add 4 to ttmp0 266 s_addc_u32 ttmp1, ttmp1, 0 267L_EXCP_CASE: 268 s_and_b32 ttmp1, ttmp1, 0xFFFF 269 set_status_without_spi_prio(s_save_status, ttmp2) //restore HW status(SCC) 270 s_rfe_b64 [ttmp0, ttmp1] 271end 272 // ********* End handling of non-CWSR traps ******************* 273 274/**************************************************************************/ 275/* save routine */ 276/**************************************************************************/ 277 278L_SAVE: 279 280if G8SR_DEBUG_TIMESTAMP 281 s_memrealtime s_g8sr_ts_save_s 282 s_waitcnt lgkmcnt(0) //FIXME, will cause xnack?? 283end 284 285 //check whether there is mem_viol 286 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 287 s_and_b32 s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_MEM_VIOL_MASK 288 s_cbranch_scc0 L_NO_PC_REWIND 289 290 //if so, need rewind PC assuming GDS operation gets NACKed 291 s_mov_b32 s_save_tmp, 0 //clear mem_viol bit 292 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT, 1), s_save_tmp //clear mem_viol bit 293 s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff //pc[47:32] 294 s_sub_u32 s_save_pc_lo, s_save_pc_lo, 8 //pc[31:0]-8 295 s_subb_u32 s_save_pc_hi, s_save_pc_hi, 0x0 // -scc 296 297L_NO_PC_REWIND: 298 s_mov_b32 s_save_tmp, 0 //clear saveCtx bit 299 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_SAVECTX_SHIFT, 1), s_save_tmp //clear saveCtx bit 300 301 s_mov_b32 s_save_xnack_mask_lo, xnack_mask_lo //save XNACK_MASK 302 s_mov_b32 s_save_xnack_mask_hi, xnack_mask_hi //save XNACK must before any memory operation 303 s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_RCNT_SHIFT, SQ_WAVE_IB_STS_RCNT_SIZE) //save RCNT 304 s_lshl_b32 s_save_tmp, s_save_tmp, S_SAVE_PC_HI_RCNT_SHIFT 305 s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp 306 s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT, SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE) //save FIRST_REPLAY 307 s_lshl_b32 s_save_tmp, s_save_tmp, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT 308 s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp 309 s_getreg_b32 s_save_tmp, hwreg(HW_REG_IB_STS) //clear RCNT and FIRST_REPLAY in IB_STS 310 s_and_b32 s_save_tmp, s_save_tmp, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG 311 312 s_setreg_b32 hwreg(HW_REG_IB_STS), s_save_tmp 313 314 /* inform SPI the readiness and wait for SPI's go signal */ 315 s_mov_b32 s_save_exec_lo, exec_lo //save EXEC and use EXEC for the go signal from SPI 316 s_mov_b32 s_save_exec_hi, exec_hi 317 s_mov_b64 exec, 0x0 //clear EXEC to get ready to receive 318 319if G8SR_DEBUG_TIMESTAMP 320 s_memrealtime s_g8sr_ts_sq_save_msg 321 s_waitcnt lgkmcnt(0) 322end 323 324 if (EMU_RUN_HACK) 325 326 else 327 s_sendmsg sendmsg(MSG_SAVEWAVE) //send SPI a message and wait for SPI's write to EXEC 328 end 329 330 // Set SPI_PRIO=2 to avoid starving instruction fetch in the waves we're waiting for. 331 s_or_b32 s_save_tmp, s_save_status, (2 << SQ_WAVE_STATUS_SPI_PRIO_SHIFT) 332 s_setreg_b32 hwreg(HW_REG_STATUS), s_save_tmp 333 334 L_SLEEP: 335 s_sleep 0x2 // sleep 1 (64clk) is not enough for 8 waves per SIMD, which will cause SQ hang, since the 7,8th wave could not get arbit to exec inst, while other waves are stuck into the sleep-loop and waiting for wrexec!=0 336 337 if (EMU_RUN_HACK) 338 339 else 340 s_cbranch_execz L_SLEEP 341 end 342 343if G8SR_DEBUG_TIMESTAMP 344 s_memrealtime s_g8sr_ts_spi_wrexec 345 s_waitcnt lgkmcnt(0) 346end 347 348 /* setup Resource Contants */ 349 if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_SINGLE_WAVE)) 350 //calculate wd_addr using absolute thread id 351 v_readlane_b32 s_save_tmp, v9, 0 352 s_lshr_b32 s_save_tmp, s_save_tmp, 6 353 s_mul_i32 s_save_tmp, s_save_tmp, WAVE_SPACE 354 s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO 355 s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI 356 s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL 357 else 358 end 359 if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_SINGLE_WAVE)) 360 s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO 361 s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI 362 s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL 363 else 364 end 365 366 367 s_mov_b32 s_save_buf_rsrc0, s_save_spi_init_lo //base_addr_lo 368 s_and_b32 s_save_buf_rsrc1, s_save_spi_init_hi, 0x0000FFFF //base_addr_hi 369 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE 370 s_mov_b32 s_save_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) although not neccessarily inited 371 s_mov_b32 s_save_buf_rsrc3, S_SAVE_BUF_RSRC_WORD3_MISC 372 s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_ATC_MASK 373 s_lshr_b32 s_save_tmp, s_save_tmp, (S_SAVE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT) //get ATC bit into position 374 s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, s_save_tmp //or ATC 375 s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_MTYPE_MASK 376 s_lshr_b32 s_save_tmp, s_save_tmp, (S_SAVE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT) //get MTYPE bits into position 377 s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, s_save_tmp //or MTYPE 378 379 //FIXME right now s_save_m0/s_save_mem_offset use tma_lo/tma_hi (might need to save them before using them?) 380 s_mov_b32 s_save_m0, m0 //save M0 381 382 /* global mem offset */ 383 s_mov_b32 s_save_mem_offset, 0x0 //mem offset initial value = 0 384 385 386 387 388 /* save HW registers */ 389 ////////////////////////////// 390 391 L_SAVE_HWREG: 392 // HWREG SR memory offset : size(VGPR)+size(SGPR) 393 get_vgpr_size_bytes(s_save_mem_offset) 394 get_sgpr_size_bytes(s_save_tmp) 395 s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp 396 397 398 s_mov_b32 s_save_buf_rsrc2, 0x4 //NUM_RECORDS in bytes 399 if (SWIZZLE_EN) 400 s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 401 else 402 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 403 end 404 405 406 write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) //M0 407 408 if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_FIRST_TIME)) 409 s_add_u32 s_save_pc_lo, s_save_pc_lo, 4 //pc[31:0]+4 410 s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0 //carry bit over 411 s_mov_b32 tba_lo, EMU_RUN_HACK_SAVE_FIRST_TIME_TBA_LO 412 s_mov_b32 tba_hi, EMU_RUN_HACK_SAVE_FIRST_TIME_TBA_HI 413 end 414 415 write_hwreg_to_mem(s_save_pc_lo, s_save_buf_rsrc0, s_save_mem_offset) //PC 416 write_hwreg_to_mem(s_save_pc_hi, s_save_buf_rsrc0, s_save_mem_offset) 417 write_hwreg_to_mem(s_save_exec_lo, s_save_buf_rsrc0, s_save_mem_offset) //EXEC 418 write_hwreg_to_mem(s_save_exec_hi, s_save_buf_rsrc0, s_save_mem_offset) 419 write_hwreg_to_mem(s_save_status, s_save_buf_rsrc0, s_save_mem_offset) //STATUS 420 421 //s_save_trapsts conflicts with s_save_alloc_size 422 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 423 write_hwreg_to_mem(s_save_trapsts, s_save_buf_rsrc0, s_save_mem_offset) //TRAPSTS 424 425 write_hwreg_to_mem(s_save_xnack_mask_lo, s_save_buf_rsrc0, s_save_mem_offset) //XNACK_MASK_LO 426 write_hwreg_to_mem(s_save_xnack_mask_hi, s_save_buf_rsrc0, s_save_mem_offset) //XNACK_MASK_HI 427 428 //use s_save_tmp would introduce conflict here between s_save_tmp and s_save_buf_rsrc2 429 s_getreg_b32 s_save_m0, hwreg(HW_REG_MODE) //MODE 430 write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) 431 write_hwreg_to_mem(tba_lo, s_save_buf_rsrc0, s_save_mem_offset) //TBA_LO 432 write_hwreg_to_mem(tba_hi, s_save_buf_rsrc0, s_save_mem_offset) //TBA_HI 433 434 435 436 /* the first wave in the threadgroup */ 437 // save fist_wave bits in tba_hi unused bit.26 438 s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK // extract fisrt wave bit 439 //s_or_b32 tba_hi, s_save_tmp, tba_hi // save first wave bit to tba_hi.bits[26] 440 s_mov_b32 s_save_exec_hi, 0x0 441 s_or_b32 s_save_exec_hi, s_save_tmp, s_save_exec_hi // save first wave bit to s_save_exec_hi.bits[26] 442 443 444 /* save SGPRs */ 445 // Save SGPR before LDS save, then the s0 to s4 can be used during LDS save... 446 ////////////////////////////// 447 448 // SGPR SR memory offset : size(VGPR) 449 get_vgpr_size_bytes(s_save_mem_offset) 450 // TODO, change RSRC word to rearrange memory layout for SGPRS 451 452 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size 453 s_add_u32 s_save_alloc_size, s_save_alloc_size, 1 454 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 4 //Number of SGPRs = (sgpr_size + 1) * 16 (non-zero value) 455 456 if (SGPR_SAVE_USE_SQC) 457 s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 2 //NUM_RECORDS in bytes 458 else 459 s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 8 //NUM_RECORDS in bytes (64 threads) 460 end 461 462 if (SWIZZLE_EN) 463 s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 464 else 465 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 466 end 467 468 469 // backup s_save_buf_rsrc0,1 to s_save_pc_lo/hi, since write_16sgpr_to_mem function will change the rsrc0 470 //s_mov_b64 s_save_pc_lo, s_save_buf_rsrc0 471 s_mov_b64 s_save_xnack_mask_lo, s_save_buf_rsrc0 472 s_add_u32 s_save_buf_rsrc0, s_save_buf_rsrc0, s_save_mem_offset 473 s_addc_u32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0 474 475 s_mov_b32 m0, 0x0 //SGPR initial index value =0 476 L_SAVE_SGPR_LOOP: 477 // SGPR is allocated in 16 SGPR granularity 478 s_movrels_b64 s0, s0 //s0 = s[0+m0], s1 = s[1+m0] 479 s_movrels_b64 s2, s2 //s2 = s[2+m0], s3 = s[3+m0] 480 s_movrels_b64 s4, s4 //s4 = s[4+m0], s5 = s[5+m0] 481 s_movrels_b64 s6, s6 //s6 = s[6+m0], s7 = s[7+m0] 482 s_movrels_b64 s8, s8 //s8 = s[8+m0], s9 = s[9+m0] 483 s_movrels_b64 s10, s10 //s10 = s[10+m0], s11 = s[11+m0] 484 s_movrels_b64 s12, s12 //s12 = s[12+m0], s13 = s[13+m0] 485 s_movrels_b64 s14, s14 //s14 = s[14+m0], s15 = s[15+m0] 486 487 write_16sgpr_to_mem(s0, s_save_buf_rsrc0, s_save_mem_offset) //PV: the best performance should be using s_buffer_store_dwordx4 488 s_add_u32 m0, m0, 16 //next sgpr index 489 s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 490 s_cbranch_scc1 L_SAVE_SGPR_LOOP //SGPR save is complete? 491 // restore s_save_buf_rsrc0,1 492 //s_mov_b64 s_save_buf_rsrc0, s_save_pc_lo 493 s_mov_b64 s_save_buf_rsrc0, s_save_xnack_mask_lo 494 495 496 497 498 /* save first 4 VGPR, then LDS save could use */ 499 // each wave will alloc 4 vgprs at least... 500 ///////////////////////////////////////////////////////////////////////////////////// 501 502 s_mov_b32 s_save_mem_offset, 0 503 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 504 s_mov_b32 exec_hi, 0xFFFFFFFF 505 506 if (SWIZZLE_EN) 507 s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 508 else 509 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 510 end 511 512 513 // VGPR Allocated in 4-GPR granularity 514 515if G8SR_VGPR_SR_IN_DWX4 516 // the const stride for DWx4 is 4*4 bytes 517 s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 518 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 // const stride to 4*4 bytes 519 520 buffer_store_dwordx4 v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 521 522 s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 523 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE // reset const stride to 4 bytes 524else 525 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 526 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256 527 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2 528 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3 529end 530 531 532 533 /* save LDS */ 534 ////////////////////////////// 535 536 L_SAVE_LDS: 537 538 // Change EXEC to all threads... 539 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 540 s_mov_b32 exec_hi, 0xFFFFFFFF 541 542 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) //lds_size 543 s_and_b32 s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF //lds_size is zero? 544 s_cbranch_scc0 L_SAVE_LDS_DONE //no lds used? jump to L_SAVE_DONE 545 546 s_barrier //LDS is used? wait for other waves in the same TG 547 //s_and_b32 s_save_tmp, tba_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK //exec is still used here 548 s_and_b32 s_save_tmp, s_save_exec_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK //exec is still used here 549 s_cbranch_scc0 L_SAVE_LDS_DONE 550 551 // first wave do LDS save; 552 553 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 6 //LDS size in dwords = lds_size * 64dw 554 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 2 //LDS size in bytes 555 s_mov_b32 s_save_buf_rsrc2, s_save_alloc_size //NUM_RECORDS in bytes 556 557 // LDS at offset: size(VGPR)+SIZE(SGPR)+SIZE(HWREG) 558 // 559 get_vgpr_size_bytes(s_save_mem_offset) 560 get_sgpr_size_bytes(s_save_tmp) 561 s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp 562 s_add_u32 s_save_mem_offset, s_save_mem_offset, get_hwreg_size_bytes() 563 564 565 if (SWIZZLE_EN) 566 s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 567 else 568 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 569 end 570 571 s_mov_b32 m0, 0x0 //lds_offset initial value = 0 572 573 574var LDS_DMA_ENABLE = 0 575var UNROLL = 0 576if UNROLL==0 && LDS_DMA_ENABLE==1 577 s_mov_b32 s3, 256*2 578 s_nop 0 579 s_nop 0 580 s_nop 0 581 L_SAVE_LDS_LOOP: 582 //TODO: looks the 2 buffer_store/load clause for s/r will hurt performance.??? 583 if (SAVE_LDS) //SPI always alloc LDS space in 128DW granularity 584 buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 // first 64DW 585 buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:256 // second 64DW 586 end 587 588 s_add_u32 m0, m0, s3 //every buffer_store_lds does 256 bytes 589 s_add_u32 s_save_mem_offset, s_save_mem_offset, s3 //mem offset increased by 256 bytes 590 s_cmp_lt_u32 m0, s_save_alloc_size //scc=(m0 < s_save_alloc_size) ? 1 : 0 591 s_cbranch_scc1 L_SAVE_LDS_LOOP //LDS save is complete? 592 593elsif LDS_DMA_ENABLE==1 && UNROLL==1 // UNROOL , has ichace miss 594 // store from higest LDS address to lowest 595 s_mov_b32 s3, 256*2 596 s_sub_u32 m0, s_save_alloc_size, s3 597 s_add_u32 s_save_mem_offset, s_save_mem_offset, m0 598 s_lshr_b32 s_save_alloc_size, s_save_alloc_size, 9 // how many 128 trunks... 599 s_sub_u32 s_save_alloc_size, 128, s_save_alloc_size // store from higheset addr to lowest 600 s_mul_i32 s_save_alloc_size, s_save_alloc_size, 6*4 // PC offset increment, each LDS save block cost 6*4 Bytes instruction 601 s_add_u32 s_save_alloc_size, s_save_alloc_size, 3*4 //2is the below 2 inst...//s_addc and s_setpc 602 s_nop 0 603 s_nop 0 604 s_nop 0 //pad 3 dw to let LDS_DMA align with 64Bytes 605 s_getpc_b64 s[0:1] // reuse s[0:1], since s[0:1] already saved 606 s_add_u32 s0, s0,s_save_alloc_size 607 s_addc_u32 s1, s1, 0 608 s_setpc_b64 s[0:1] 609 610 611 for var i =0; i< 128; i++ 612 // be careful to make here a 64Byte aligned address, which could improve performance... 613 buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:0 // first 64DW 614 buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:256 // second 64DW 615 616 if i!=127 617 s_sub_u32 m0, m0, s3 // use a sgpr to shrink 2DW-inst to 1DW inst to improve performance , i.e. pack more LDS_DMA inst to one Cacheline 618 s_sub_u32 s_save_mem_offset, s_save_mem_offset, s3 619 end 620 end 621 622else // BUFFER_STORE 623 v_mbcnt_lo_u32_b32 v2, 0xffffffff, 0x0 624 v_mbcnt_hi_u32_b32 v3, 0xffffffff, v2 // tid 625 v_mul_i32_i24 v2, v3, 8 // tid*8 626 v_mov_b32 v3, 256*2 627 s_mov_b32 m0, 0x10000 628 s_mov_b32 s0, s_save_buf_rsrc3 629 s_and_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, 0xFF7FFFFF // disable add_tid 630 s_or_b32 s_save_buf_rsrc3, s_save_buf_rsrc3, 0x58000 //DFMT 631 632L_SAVE_LDS_LOOP_VECTOR: 633 ds_read_b64 v[0:1], v2 //x =LDS[a], byte address 634 s_waitcnt lgkmcnt(0) 635 buffer_store_dwordx2 v[0:1], v2, s_save_buf_rsrc0, s_save_mem_offset offen:1 glc:1 slc:1 636// s_waitcnt vmcnt(0) 637 v_add_u32 v2, vcc[0:1], v2, v3 638 v_cmp_lt_u32 vcc[0:1], v2, s_save_alloc_size 639 s_cbranch_vccnz L_SAVE_LDS_LOOP_VECTOR 640 641 // restore rsrc3 642 s_mov_b32 s_save_buf_rsrc3, s0 643 644end 645 646L_SAVE_LDS_DONE: 647 648 649 /* save VGPRs - set the Rest VGPRs */ 650 ////////////////////////////////////////////////////////////////////////////////////// 651 L_SAVE_VGPR: 652 // VGPR SR memory offset: 0 653 // TODO rearrange the RSRC words to use swizzle for VGPR save... 654 655 s_mov_b32 s_save_mem_offset, (0+256*4) // for the rest VGPRs 656 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 657 s_mov_b32 exec_hi, 0xFFFFFFFF 658 659 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) //vpgr_size 660 s_add_u32 s_save_alloc_size, s_save_alloc_size, 1 661 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value) //FIXME for GFX, zero is possible 662 s_lshl_b32 s_save_buf_rsrc2, s_save_alloc_size, 8 //NUM_RECORDS in bytes (64 threads*4) 663 if (SWIZZLE_EN) 664 s_add_u32 s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 665 else 666 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 667 end 668 669 670 // VGPR Allocated in 4-GPR granularity 671 672if G8SR_VGPR_SR_IN_DWX4 673 // the const stride for DWx4 is 4*4 bytes 674 s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 675 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 // const stride to 4*4 bytes 676 677 s_mov_b32 m0, 4 // skip first 4 VGPRs 678 s_cmp_lt_u32 m0, s_save_alloc_size 679 s_cbranch_scc0 L_SAVE_VGPR_LOOP_END // no more vgprs 680 681 s_set_gpr_idx_on m0, 0x1 // This will change M0 682 s_add_u32 s_save_alloc_size, s_save_alloc_size, 0x1000 // because above inst change m0 683L_SAVE_VGPR_LOOP: 684 v_mov_b32 v0, v0 // v0 = v[0+m0] 685 v_mov_b32 v1, v1 686 v_mov_b32 v2, v2 687 v_mov_b32 v3, v3 688 689 690 buffer_store_dwordx4 v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 691 s_add_u32 m0, m0, 4 692 s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 693 s_cmp_lt_u32 m0, s_save_alloc_size 694 s_cbranch_scc1 L_SAVE_VGPR_LOOP //VGPR save is complete? 695 s_set_gpr_idx_off 696L_SAVE_VGPR_LOOP_END: 697 698 s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF // reset const stride to 0 699 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE // reset const stride to 4 bytes 700else 701 // VGPR store using dw burst 702 s_mov_b32 m0, 0x4 //VGPR initial index value =0 703 s_cmp_lt_u32 m0, s_save_alloc_size 704 s_cbranch_scc0 L_SAVE_VGPR_END 705 706 707 s_set_gpr_idx_on m0, 0x1 //M0[7:0] = M0[7:0] and M0[15:12] = 0x1 708 s_add_u32 s_save_alloc_size, s_save_alloc_size, 0x1000 //add 0x1000 since we compare m0 against it later 709 710 L_SAVE_VGPR_LOOP: 711 v_mov_b32 v0, v0 //v0 = v[0+m0] 712 v_mov_b32 v1, v1 //v0 = v[0+m0] 713 v_mov_b32 v2, v2 //v0 = v[0+m0] 714 v_mov_b32 v3, v3 //v0 = v[0+m0] 715 716 if(USE_MTBUF_INSTEAD_OF_MUBUF) 717 tbuffer_store_format_x v0, v0, s_save_buf_rsrc0, s_save_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1 718 else 719 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 720 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256 721 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2 722 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3 723 end 724 725 s_add_u32 m0, m0, 4 //next vgpr index 726 s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 //every buffer_store_dword does 256 bytes 727 s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 728 s_cbranch_scc1 L_SAVE_VGPR_LOOP //VGPR save is complete? 729 s_set_gpr_idx_off 730end 731 732L_SAVE_VGPR_END: 733 734 735 736 737 738 739 /* S_PGM_END_SAVED */ //FIXME graphics ONLY 740 if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_NORMAL_EXIT)) 741 s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff //pc[47:32] 742 s_add_u32 s_save_pc_lo, s_save_pc_lo, 4 //pc[31:0]+4 743 s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0 //carry bit over 744 s_rfe_b64 s_save_pc_lo //Return to the main shader program 745 else 746 end 747 748// Save Done timestamp 749if G8SR_DEBUG_TIMESTAMP 750 s_memrealtime s_g8sr_ts_save_d 751 // SGPR SR memory offset : size(VGPR) 752 get_vgpr_size_bytes(s_save_mem_offset) 753 s_add_u32 s_save_mem_offset, s_save_mem_offset, G8SR_DEBUG_TS_SAVE_D_OFFSET 754 s_waitcnt lgkmcnt(0) //FIXME, will cause xnack?? 755 // Need reset rsrc2?? 756 s_mov_b32 m0, s_save_mem_offset 757 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 758 s_buffer_store_dwordx2 s_g8sr_ts_save_d, s_save_buf_rsrc0, m0 glc:1 759end 760 761 762 s_branch L_END_PGM 763 764 765 766/**************************************************************************/ 767/* restore routine */ 768/**************************************************************************/ 769 770L_RESTORE: 771 /* Setup Resource Contants */ 772 if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL)) 773 //calculate wd_addr using absolute thread id 774 v_readlane_b32 s_restore_tmp, v9, 0 775 s_lshr_b32 s_restore_tmp, s_restore_tmp, 6 776 s_mul_i32 s_restore_tmp, s_restore_tmp, WAVE_SPACE 777 s_add_i32 s_restore_spi_init_lo, s_restore_tmp, WG_BASE_ADDR_LO 778 s_mov_b32 s_restore_spi_init_hi, WG_BASE_ADDR_HI 779 s_and_b32 s_restore_spi_init_hi, s_restore_spi_init_hi, CTX_RESTORE_CONTROL 780 else 781 end 782 783if G8SR_DEBUG_TIMESTAMP 784 s_memrealtime s_g8sr_ts_restore_s 785 s_waitcnt lgkmcnt(0) //FIXME, will cause xnack?? 786 // tma_lo/hi are sgpr 110, 111, which will not used for 112 SGPR allocated case... 787 s_mov_b32 s_restore_pc_lo, s_g8sr_ts_restore_s[0] 788 s_mov_b32 s_restore_pc_hi, s_g8sr_ts_restore_s[1] //backup ts to ttmp0/1, sicne exec will be finally restored.. 789end 790 791 792 793 s_mov_b32 s_restore_buf_rsrc0, s_restore_spi_init_lo //base_addr_lo 794 s_and_b32 s_restore_buf_rsrc1, s_restore_spi_init_hi, 0x0000FFFF //base_addr_hi 795 s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE 796 s_mov_b32 s_restore_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) 797 s_mov_b32 s_restore_buf_rsrc3, S_RESTORE_BUF_RSRC_WORD3_MISC 798 s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_ATC_MASK 799 s_lshr_b32 s_restore_tmp, s_restore_tmp, (S_RESTORE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT) //get ATC bit into position 800 s_or_b32 s_restore_buf_rsrc3, s_restore_buf_rsrc3, s_restore_tmp //or ATC 801 s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_MTYPE_MASK 802 s_lshr_b32 s_restore_tmp, s_restore_tmp, (S_RESTORE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT) //get MTYPE bits into position 803 s_or_b32 s_restore_buf_rsrc3, s_restore_buf_rsrc3, s_restore_tmp //or MTYPE 804 805 /* global mem offset */ 806// s_mov_b32 s_restore_mem_offset, 0x0 //mem offset initial value = 0 807 808 /* the first wave in the threadgroup */ 809 s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_FIRST_WAVE_MASK 810 s_cbranch_scc0 L_RESTORE_VGPR 811 812 /* restore LDS */ 813 ////////////////////////////// 814 L_RESTORE_LDS: 815 816 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on //be consistent with SAVE although can be moved ahead 817 s_mov_b32 exec_hi, 0xFFFFFFFF 818 819 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) //lds_size 820 s_and_b32 s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF //lds_size is zero? 821 s_cbranch_scc0 L_RESTORE_VGPR //no lds used? jump to L_RESTORE_VGPR 822 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 6 //LDS size in dwords = lds_size * 64dw 823 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 2 //LDS size in bytes 824 s_mov_b32 s_restore_buf_rsrc2, s_restore_alloc_size //NUM_RECORDS in bytes 825 826 // LDS at offset: size(VGPR)+SIZE(SGPR)+SIZE(HWREG) 827 // 828 get_vgpr_size_bytes(s_restore_mem_offset) 829 get_sgpr_size_bytes(s_restore_tmp) 830 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 831 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_hwreg_size_bytes() //FIXME, Check if offset overflow??? 832 833 834 if (SWIZZLE_EN) 835 s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 836 else 837 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 838 end 839 s_mov_b32 m0, 0x0 //lds_offset initial value = 0 840 841 L_RESTORE_LDS_LOOP: 842 if (SAVE_LDS) 843 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 // first 64DW 844 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 offset:256 // second 64DW 845 end 846 s_add_u32 m0, m0, 256*2 // 128 DW 847 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*2 //mem offset increased by 128DW 848 s_cmp_lt_u32 m0, s_restore_alloc_size //scc=(m0 < s_restore_alloc_size) ? 1 : 0 849 s_cbranch_scc1 L_RESTORE_LDS_LOOP //LDS restore is complete? 850 851 852 /* restore VGPRs */ 853 ////////////////////////////// 854 L_RESTORE_VGPR: 855 // VGPR SR memory offset : 0 856 s_mov_b32 s_restore_mem_offset, 0x0 857 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on //be consistent with SAVE although can be moved ahead 858 s_mov_b32 exec_hi, 0xFFFFFFFF 859 860 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) //vpgr_size 861 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 1 862 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value) 863 s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 8 //NUM_RECORDS in bytes (64 threads*4) 864 if (SWIZZLE_EN) 865 s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 866 else 867 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 868 end 869 870if G8SR_VGPR_SR_IN_DWX4 871 get_vgpr_size_bytes(s_restore_mem_offset) 872 s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 873 874 // the const stride for DWx4 is 4*4 bytes 875 s_and_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, 0x0000FFFF // reset const stride to 0 876 s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, G8SR_RESTORE_BUF_RSRC_WORD1_STRIDE_DWx4 // const stride to 4*4 bytes 877 878 s_mov_b32 m0, s_restore_alloc_size 879 s_set_gpr_idx_on m0, 0x8 // Note.. This will change m0 880 881L_RESTORE_VGPR_LOOP: 882 buffer_load_dwordx4 v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 883 s_waitcnt vmcnt(0) 884 s_sub_u32 m0, m0, 4 885 v_mov_b32 v0, v0 // v[0+m0] = v0 886 v_mov_b32 v1, v1 887 v_mov_b32 v2, v2 888 v_mov_b32 v3, v3 889 s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 890 s_cmp_eq_u32 m0, 0x8000 891 s_cbranch_scc0 L_RESTORE_VGPR_LOOP 892 s_set_gpr_idx_off 893 894 s_and_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, 0x0000FFFF // reset const stride to 0 895 s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE // const stride to 4*4 bytes 896 897else 898 // VGPR load using dw burst 899 s_mov_b32 s_restore_mem_offset_save, s_restore_mem_offset // restore start with v1, v0 will be the last 900 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 901 s_mov_b32 m0, 4 //VGPR initial index value = 1 902 s_set_gpr_idx_on m0, 0x8 //M0[7:0] = M0[7:0] and M0[15:12] = 0x8 903 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 0x8000 //add 0x8000 since we compare m0 against it later 904 905 L_RESTORE_VGPR_LOOP: 906 if(USE_MTBUF_INSTEAD_OF_MUBUF) 907 tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1 908 else 909 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 910 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256 911 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*2 912 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*3 913 end 914 s_waitcnt vmcnt(0) //ensure data ready 915 v_mov_b32 v0, v0 //v[0+m0] = v0 916 v_mov_b32 v1, v1 917 v_mov_b32 v2, v2 918 v_mov_b32 v3, v3 919 s_add_u32 m0, m0, 4 //next vgpr index 920 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 //every buffer_load_dword does 256 bytes 921 s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0 922 s_cbranch_scc1 L_RESTORE_VGPR_LOOP //VGPR restore (except v0) is complete? 923 s_set_gpr_idx_off 924 /* VGPR restore on v0 */ 925 if(USE_MTBUF_INSTEAD_OF_MUBUF) 926 tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1 927 else 928 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 929 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256 930 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*2 931 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*3 932 end 933 934end 935 936 /* restore SGPRs */ 937 ////////////////////////////// 938 939 // SGPR SR memory offset : size(VGPR) 940 get_vgpr_size_bytes(s_restore_mem_offset) 941 get_sgpr_size_bytes(s_restore_tmp) 942 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 943 s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 16*4 // restore SGPR from S[n] to S[0], by 16 sgprs group 944 // TODO, change RSRC word to rearrange memory layout for SGPRS 945 946 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size 947 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 1 948 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 4 //Number of SGPRs = (sgpr_size + 1) * 16 (non-zero value) 949 950 if (SGPR_SAVE_USE_SQC) 951 s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 2 //NUM_RECORDS in bytes 952 else 953 s_lshl_b32 s_restore_buf_rsrc2, s_restore_alloc_size, 8 //NUM_RECORDS in bytes (64 threads) 954 end 955 if (SWIZZLE_EN) 956 s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 957 else 958 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 959 end 960 961 /* If 112 SGPRs ar allocated, 4 sgprs are not used TBA(108,109),TMA(110,111), 962 However, we are safe to restore these 4 SGPRs anyway, since TBA,TMA will later be restored by HWREG 963 */ 964 s_mov_b32 m0, s_restore_alloc_size 965 966 L_RESTORE_SGPR_LOOP: 967 read_16sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset) //PV: further performance improvement can be made 968 s_waitcnt lgkmcnt(0) //ensure data ready 969 970 s_sub_u32 m0, m0, 16 // Restore from S[n] to S[0] 971 972 s_movreld_b64 s0, s0 //s[0+m0] = s0 973 s_movreld_b64 s2, s2 974 s_movreld_b64 s4, s4 975 s_movreld_b64 s6, s6 976 s_movreld_b64 s8, s8 977 s_movreld_b64 s10, s10 978 s_movreld_b64 s12, s12 979 s_movreld_b64 s14, s14 980 981 s_cmp_eq_u32 m0, 0 //scc = (m0 < s_restore_alloc_size) ? 1 : 0 982 s_cbranch_scc0 L_RESTORE_SGPR_LOOP //SGPR restore (except s0) is complete? 983 984 /* restore HW registers */ 985 ////////////////////////////// 986 L_RESTORE_HWREG: 987 988 989if G8SR_DEBUG_TIMESTAMP 990 s_mov_b32 s_g8sr_ts_restore_s[0], s_restore_pc_lo 991 s_mov_b32 s_g8sr_ts_restore_s[1], s_restore_pc_hi 992end 993 994 // HWREG SR memory offset : size(VGPR)+size(SGPR) 995 get_vgpr_size_bytes(s_restore_mem_offset) 996 get_sgpr_size_bytes(s_restore_tmp) 997 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 998 999 1000 s_mov_b32 s_restore_buf_rsrc2, 0x4 //NUM_RECORDS in bytes 1001 if (SWIZZLE_EN) 1002 s_add_u32 s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0 //FIXME need to use swizzle to enable bounds checking? 1003 else 1004 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 1005 end 1006 1007 read_hwreg_from_mem(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset) //M0 1008 read_hwreg_from_mem(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //PC 1009 read_hwreg_from_mem(s_restore_pc_hi, s_restore_buf_rsrc0, s_restore_mem_offset) 1010 read_hwreg_from_mem(s_restore_exec_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //EXEC 1011 read_hwreg_from_mem(s_restore_exec_hi, s_restore_buf_rsrc0, s_restore_mem_offset) 1012 read_hwreg_from_mem(s_restore_status, s_restore_buf_rsrc0, s_restore_mem_offset) //STATUS 1013 read_hwreg_from_mem(s_restore_trapsts, s_restore_buf_rsrc0, s_restore_mem_offset) //TRAPSTS 1014 read_hwreg_from_mem(xnack_mask_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //XNACK_MASK_LO 1015 read_hwreg_from_mem(xnack_mask_hi, s_restore_buf_rsrc0, s_restore_mem_offset) //XNACK_MASK_HI 1016 read_hwreg_from_mem(s_restore_mode, s_restore_buf_rsrc0, s_restore_mem_offset) //MODE 1017 read_hwreg_from_mem(tba_lo, s_restore_buf_rsrc0, s_restore_mem_offset) //TBA_LO 1018 read_hwreg_from_mem(tba_hi, s_restore_buf_rsrc0, s_restore_mem_offset) //TBA_HI 1019 1020 s_waitcnt lgkmcnt(0) //from now on, it is safe to restore STATUS and IB_STS 1021 1022 //for normal save & restore, the saved PC points to the next inst to execute, no adjustment needs to be made, otherwise: 1023 if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL)) 1024 s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 8 //pc[31:0]+8 //two back-to-back s_trap are used (first for save and second for restore) 1025 s_addc_u32 s_restore_pc_hi, s_restore_pc_hi, 0x0 //carry bit over 1026 end 1027 if ((EMU_RUN_HACK) && (EMU_RUN_HACK_RESTORE_NORMAL)) 1028 s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 4 //pc[31:0]+4 // save is hack through s_trap but restore is normal 1029 s_addc_u32 s_restore_pc_hi, s_restore_pc_hi, 0x0 //carry bit over 1030 end 1031 1032 s_mov_b32 m0, s_restore_m0 1033 s_mov_b32 exec_lo, s_restore_exec_lo 1034 s_mov_b32 exec_hi, s_restore_exec_hi 1035 1036 s_and_b32 s_restore_m0, SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK, s_restore_trapsts 1037 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE), s_restore_m0 1038 s_and_b32 s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK, s_restore_trapsts 1039 s_lshr_b32 s_restore_m0, s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT 1040 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE), s_restore_m0 1041 //s_setreg_b32 hwreg(HW_REG_TRAPSTS), s_restore_trapsts //don't overwrite SAVECTX bit as it may be set through external SAVECTX during restore 1042 s_setreg_b32 hwreg(HW_REG_MODE), s_restore_mode 1043 //reuse s_restore_m0 as a temp register 1044 s_and_b32 s_restore_m0, s_restore_pc_hi, S_SAVE_PC_HI_RCNT_MASK 1045 s_lshr_b32 s_restore_m0, s_restore_m0, S_SAVE_PC_HI_RCNT_SHIFT 1046 s_lshl_b32 s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_RCNT_SHIFT 1047 s_mov_b32 s_restore_tmp, 0x0 //IB_STS is zero 1048 s_or_b32 s_restore_tmp, s_restore_tmp, s_restore_m0 1049 s_and_b32 s_restore_m0, s_restore_pc_hi, S_SAVE_PC_HI_FIRST_REPLAY_MASK 1050 s_lshr_b32 s_restore_m0, s_restore_m0, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT 1051 s_lshl_b32 s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT 1052 s_or_b32 s_restore_tmp, s_restore_tmp, s_restore_m0 1053 s_and_b32 s_restore_m0, s_restore_status, SQ_WAVE_STATUS_INST_ATC_MASK 1054 s_lshr_b32 s_restore_m0, s_restore_m0, SQ_WAVE_STATUS_INST_ATC_SHIFT 1055 s_setreg_b32 hwreg(HW_REG_IB_STS), s_restore_tmp 1056 1057 s_and_b32 s_restore_pc_hi, s_restore_pc_hi, 0x0000ffff //pc[47:32] //Do it here in order not to affect STATUS 1058 s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32 1059 s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32 1060 set_status_without_spi_prio(s_restore_status, s_restore_tmp) // SCC is included, which is changed by previous salu 1061 1062 s_barrier //barrier to ensure the readiness of LDS before access attempts from any other wave in the same TG //FIXME not performance-optimal at this time 1063 1064if G8SR_DEBUG_TIMESTAMP 1065 s_memrealtime s_g8sr_ts_restore_d 1066 s_waitcnt lgkmcnt(0) 1067end 1068 1069// s_rfe_b64 s_restore_pc_lo //Return to the main shader program and resume execution 1070 s_rfe_restore_b64 s_restore_pc_lo, s_restore_m0 // s_restore_m0[0] is used to set STATUS.inst_atc 1071 1072 1073/**************************************************************************/ 1074/* the END */ 1075/**************************************************************************/ 1076L_END_PGM: 1077 s_endpgm 1078 1079end 1080 1081 1082/**************************************************************************/ 1083/* the helper functions */ 1084/**************************************************************************/ 1085 1086//Only for save hwreg to mem 1087function write_hwreg_to_mem(s, s_rsrc, s_mem_offset) 1088 s_mov_b32 exec_lo, m0 //assuming exec_lo is not needed anymore from this point on 1089 s_mov_b32 m0, s_mem_offset 1090 s_buffer_store_dword s, s_rsrc, m0 glc:1 1091 s_add_u32 s_mem_offset, s_mem_offset, 4 1092 s_mov_b32 m0, exec_lo 1093end 1094 1095 1096// HWREG are saved before SGPRs, so all HWREG could be use. 1097function write_16sgpr_to_mem(s, s_rsrc, s_mem_offset) 1098 1099 s_buffer_store_dwordx4 s[0], s_rsrc, 0 glc:1 1100 s_buffer_store_dwordx4 s[4], s_rsrc, 16 glc:1 1101 s_buffer_store_dwordx4 s[8], s_rsrc, 32 glc:1 1102 s_buffer_store_dwordx4 s[12], s_rsrc, 48 glc:1 1103 s_add_u32 s_rsrc[0], s_rsrc[0], 4*16 1104 s_addc_u32 s_rsrc[1], s_rsrc[1], 0x0 // +scc 1105end 1106 1107 1108function read_hwreg_from_mem(s, s_rsrc, s_mem_offset) 1109 s_buffer_load_dword s, s_rsrc, s_mem_offset glc:1 1110 s_add_u32 s_mem_offset, s_mem_offset, 4 1111end 1112 1113function read_16sgpr_from_mem(s, s_rsrc, s_mem_offset) 1114 s_buffer_load_dwordx16 s, s_rsrc, s_mem_offset glc:1 1115 s_sub_u32 s_mem_offset, s_mem_offset, 4*16 1116end 1117 1118 1119 1120function get_lds_size_bytes(s_lds_size_byte) 1121 // SQ LDS granularity is 64DW, while PGM_RSRC2.lds_size is in granularity 128DW 1122 s_getreg_b32 s_lds_size_byte, hwreg(HW_REG_LDS_ALLOC, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) // lds_size 1123 s_lshl_b32 s_lds_size_byte, s_lds_size_byte, 8 //LDS size in dwords = lds_size * 64 *4Bytes // granularity 64DW 1124end 1125 1126function get_vgpr_size_bytes(s_vgpr_size_byte) 1127 s_getreg_b32 s_vgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) //vpgr_size 1128 s_add_u32 s_vgpr_size_byte, s_vgpr_size_byte, 1 1129 s_lshl_b32 s_vgpr_size_byte, s_vgpr_size_byte, (2+8) //Number of VGPRs = (vgpr_size + 1) * 4 * 64 * 4 (non-zero value) //FIXME for GFX, zero is possible 1130end 1131 1132function get_sgpr_size_bytes(s_sgpr_size_byte) 1133 s_getreg_b32 s_sgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) //spgr_size 1134 s_add_u32 s_sgpr_size_byte, s_sgpr_size_byte, 1 1135 s_lshl_b32 s_sgpr_size_byte, s_sgpr_size_byte, 6 //Number of SGPRs = (sgpr_size + 1) * 16 *4 (non-zero value) 1136end 1137 1138function get_hwreg_size_bytes 1139 return 128 //HWREG size 128 bytes 1140end 1141 1142function set_status_without_spi_prio(status, tmp) 1143 // Do not restore STATUS.SPI_PRIO since scheduler may have raised it. 1144 s_lshr_b32 tmp, status, SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT 1145 s_setreg_b32 hwreg(HW_REG_STATUS, SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT, SQ_WAVE_STATUS_POST_SPI_PRIO_SIZE), tmp 1146 s_nop 0x2 // avoid S_SETREG => S_SETREG hazard 1147 s_setreg_b32 hwreg(HW_REG_STATUS, SQ_WAVE_STATUS_PRE_SPI_PRIO_SHIFT, SQ_WAVE_STATUS_PRE_SPI_PRIO_SIZE), status 1148end 1149