1/* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23/* To compile this assembly code: 24 * 25 * Navi1x: 26 * cpp -DASIC_FAMILY=CHIP_NAVI10 cwsr_trap_handler_gfx10.asm -P -o nv1x.sp3 27 * sp3 nv1x.sp3 -hex nv1x.hex 28 * 29 * gfx10: 30 * cpp -DASIC_FAMILY=CHIP_SIENNA_CICHLID cwsr_trap_handler_gfx10.asm -P -o gfx10.sp3 31 * sp3 gfx10.sp3 -hex gfx10.hex 32 * 33 * gfx11: 34 * cpp -DASIC_FAMILY=CHIP_PLUM_BONITO cwsr_trap_handler_gfx10.asm -P -o gfx11.sp3 35 * sp3 gfx11.sp3 -hex gfx11.hex 36 */ 37 38#define CHIP_NAVI10 26 39#define CHIP_SIENNA_CICHLID 30 40#define CHIP_PLUM_BONITO 36 41 42#define NO_SQC_STORE (ASIC_FAMILY >= CHIP_SIENNA_CICHLID) 43#define HAVE_XNACK (ASIC_FAMILY < CHIP_SIENNA_CICHLID) 44#define HAVE_SENDMSG_RTN (ASIC_FAMILY >= CHIP_PLUM_BONITO) 45#define HAVE_BUFFER_LDS_LOAD (ASIC_FAMILY < CHIP_PLUM_BONITO) 46 47var SINGLE_STEP_MISSED_WORKAROUND = 1 //workaround for lost MODE.DEBUG_EN exception when SAVECTX raised 48 49var SQ_WAVE_STATUS_SPI_PRIO_MASK = 0x00000006 50var SQ_WAVE_STATUS_HALT_MASK = 0x2000 51var SQ_WAVE_STATUS_ECC_ERR_MASK = 0x20000 52 53var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT = 12 54var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE = 9 55var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE = 8 56var SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT = 24 57var SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE = 4 58var SQ_WAVE_IB_STS2_WAVE64_SHIFT = 11 59var SQ_WAVE_IB_STS2_WAVE64_SIZE = 1 60 61#if ASIC_FAMILY < CHIP_PLUM_BONITO 62var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 8 63#else 64var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 12 65#endif 66 67var SQ_WAVE_TRAPSTS_SAVECTX_MASK = 0x400 68var SQ_WAVE_TRAPSTS_EXCP_MASK = 0x1FF 69var SQ_WAVE_TRAPSTS_SAVECTX_SHIFT = 10 70var SQ_WAVE_TRAPSTS_ADDR_WATCH_MASK = 0x80 71var SQ_WAVE_TRAPSTS_ADDR_WATCH_SHIFT = 7 72var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK = 0x100 73var SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT = 8 74var SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK = 0x3FF 75var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT = 0x0 76var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE = 10 77var SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK = 0xFFFFF800 78var SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT = 11 79var SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE = 21 80var SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK = 0x800 81var SQ_WAVE_TRAPSTS_EXCP_HI_MASK = 0x7000 82 83var SQ_WAVE_MODE_EXCP_EN_SHIFT = 12 84var SQ_WAVE_MODE_EXCP_EN_ADDR_WATCH_SHIFT = 19 85 86var SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT = 15 87var SQ_WAVE_IB_STS_REPLAY_W64H_SHIFT = 25 88var SQ_WAVE_IB_STS_REPLAY_W64H_MASK = 0x02000000 89var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK = 0x003F8000 90 91var SQ_WAVE_MODE_DEBUG_EN_MASK = 0x800 92 93// bits [31:24] unused by SPI debug data 94var TTMP11_SAVE_REPLAY_W64H_SHIFT = 31 95var TTMP11_SAVE_REPLAY_W64H_MASK = 0x80000000 96var TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT = 24 97var TTMP11_SAVE_RCNT_FIRST_REPLAY_MASK = 0x7F000000 98var TTMP11_DEBUG_TRAP_ENABLED_SHIFT = 23 99var TTMP11_DEBUG_TRAP_ENABLED_MASK = 0x800000 100 101// SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14] 102// when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE 103var S_SAVE_BUF_RSRC_WORD1_STRIDE = 0x00040000 104var S_SAVE_BUF_RSRC_WORD3_MISC = 0x10807FAC 105var S_SAVE_PC_HI_TRAP_ID_MASK = 0x00FF0000 106var S_SAVE_PC_HI_HT_MASK = 0x01000000 107var S_SAVE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 108var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT = 26 109 110var S_SAVE_PC_HI_FIRST_WAVE_MASK = 0x80000000 111var S_SAVE_PC_HI_FIRST_WAVE_SHIFT = 31 112 113var s_sgpr_save_num = 108 114 115var s_save_spi_init_lo = exec_lo 116var s_save_spi_init_hi = exec_hi 117var s_save_pc_lo = ttmp0 118var s_save_pc_hi = ttmp1 119var s_save_exec_lo = ttmp2 120var s_save_exec_hi = ttmp3 121var s_save_status = ttmp12 122var s_save_trapsts = ttmp15 123var s_save_xnack_mask = s_save_trapsts 124var s_wave_size = ttmp7 125var s_save_buf_rsrc0 = ttmp8 126var s_save_buf_rsrc1 = ttmp9 127var s_save_buf_rsrc2 = ttmp10 128var s_save_buf_rsrc3 = ttmp11 129var s_save_mem_offset = ttmp4 130var s_save_alloc_size = s_save_trapsts 131var s_save_tmp = ttmp14 132var s_save_m0 = ttmp5 133var s_save_ttmps_lo = s_save_tmp 134var s_save_ttmps_hi = s_save_trapsts 135 136var S_RESTORE_BUF_RSRC_WORD1_STRIDE = S_SAVE_BUF_RSRC_WORD1_STRIDE 137var S_RESTORE_BUF_RSRC_WORD3_MISC = S_SAVE_BUF_RSRC_WORD3_MISC 138 139var S_RESTORE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 140var S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT = 26 141var S_WAVE_SIZE = 25 142 143var s_restore_spi_init_lo = exec_lo 144var s_restore_spi_init_hi = exec_hi 145var s_restore_mem_offset = ttmp12 146var s_restore_alloc_size = ttmp3 147var s_restore_tmp = ttmp2 148var s_restore_mem_offset_save = s_restore_tmp 149var s_restore_m0 = s_restore_alloc_size 150var s_restore_mode = ttmp7 151var s_restore_flat_scratch = s_restore_tmp 152var s_restore_pc_lo = ttmp0 153var s_restore_pc_hi = ttmp1 154var s_restore_exec_lo = ttmp4 155var s_restore_exec_hi = ttmp5 156var s_restore_status = ttmp14 157var s_restore_trapsts = ttmp15 158var s_restore_xnack_mask = ttmp13 159var s_restore_buf_rsrc0 = ttmp8 160var s_restore_buf_rsrc1 = ttmp9 161var s_restore_buf_rsrc2 = ttmp10 162var s_restore_buf_rsrc3 = ttmp11 163var s_restore_size = ttmp6 164var s_restore_ttmps_lo = s_restore_tmp 165var s_restore_ttmps_hi = s_restore_alloc_size 166 167shader main 168 asic(DEFAULT) 169 type(CS) 170 wave_size(32) 171 172 s_branch L_SKIP_RESTORE //NOT restore. might be a regular trap or save 173 174L_JUMP_TO_RESTORE: 175 s_branch L_RESTORE 176 177L_SKIP_RESTORE: 178 s_getreg_b32 s_save_status, hwreg(HW_REG_STATUS) //save STATUS since we will change SCC 179 180 // Clear SPI_PRIO: do not save with elevated priority. 181 // Clear ECC_ERR: prevents SQC store and triggers FATAL_HALT if setreg'd. 182 s_andn2_b32 s_save_status, s_save_status, SQ_WAVE_STATUS_SPI_PRIO_MASK|SQ_WAVE_STATUS_ECC_ERR_MASK 183 184 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 185 186 s_and_b32 ttmp2, s_save_status, SQ_WAVE_STATUS_HALT_MASK 187 s_cbranch_scc0 L_NOT_HALTED 188 189L_HALTED: 190 // Host trap may occur while wave is halted. 191 s_and_b32 ttmp2, s_save_pc_hi, S_SAVE_PC_HI_TRAP_ID_MASK 192 s_cbranch_scc1 L_FETCH_2ND_TRAP 193 194L_CHECK_SAVE: 195 s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK 196 s_cbranch_scc1 L_SAVE 197 198 // Wave is halted but neither host trap nor SAVECTX is raised. 199 // Caused by instruction fetch memory violation. 200 // Spin wait until context saved to prevent interrupt storm. 201 s_sleep 0x10 202 s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) 203 s_branch L_CHECK_SAVE 204 205L_NOT_HALTED: 206 // Let second-level handle non-SAVECTX exception or trap. 207 // Any concurrent SAVECTX will be handled upon re-entry once halted. 208 209 // Check non-maskable exceptions. memory_violation, illegal_instruction 210 // and xnack_error exceptions always cause the wave to enter the trap 211 // handler. 212 s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_MEM_VIOL_MASK|SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK 213 s_cbranch_scc1 L_FETCH_2ND_TRAP 214 215 // Check for maskable exceptions in trapsts.excp and trapsts.excp_hi. 216 // Maskable exceptions only cause the wave to enter the trap handler if 217 // their respective bit in mode.excp_en is set. 218 s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_EXCP_MASK|SQ_WAVE_TRAPSTS_EXCP_HI_MASK 219 s_cbranch_scc0 L_CHECK_TRAP_ID 220 221 s_and_b32 ttmp3, s_save_trapsts, SQ_WAVE_TRAPSTS_ADDR_WATCH_MASK|SQ_WAVE_TRAPSTS_EXCP_HI_MASK 222 s_cbranch_scc0 L_NOT_ADDR_WATCH 223 s_bitset1_b32 ttmp2, SQ_WAVE_TRAPSTS_ADDR_WATCH_SHIFT // Check all addr_watch[123] exceptions against excp_en.addr_watch 224 225L_NOT_ADDR_WATCH: 226 s_getreg_b32 ttmp3, hwreg(HW_REG_MODE) 227 s_lshl_b32 ttmp2, ttmp2, SQ_WAVE_MODE_EXCP_EN_SHIFT 228 s_and_b32 ttmp2, ttmp2, ttmp3 229 s_cbranch_scc1 L_FETCH_2ND_TRAP 230 231L_CHECK_TRAP_ID: 232 // Check trap_id != 0 233 s_and_b32 ttmp2, s_save_pc_hi, S_SAVE_PC_HI_TRAP_ID_MASK 234 s_cbranch_scc1 L_FETCH_2ND_TRAP 235 236if SINGLE_STEP_MISSED_WORKAROUND 237 // Prioritize single step exception over context save. 238 // Second-level trap will halt wave and RFE, re-entering for SAVECTX. 239 s_getreg_b32 ttmp2, hwreg(HW_REG_MODE) 240 s_and_b32 ttmp2, ttmp2, SQ_WAVE_MODE_DEBUG_EN_MASK 241 s_cbranch_scc1 L_FETCH_2ND_TRAP 242end 243 244 s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK 245 s_cbranch_scc1 L_SAVE 246 247L_FETCH_2ND_TRAP: 248#if HAVE_XNACK 249 save_and_clear_ib_sts(ttmp14, ttmp15) 250#endif 251 252 // Read second-level TBA/TMA from first-level TMA and jump if available. 253 // ttmp[2:5] and ttmp12 can be used (others hold SPI-initialized debug data) 254 // ttmp12 holds SQ_WAVE_STATUS 255#if HAVE_SENDMSG_RTN 256 s_sendmsg_rtn_b64 [ttmp14, ttmp15], sendmsg(MSG_RTN_GET_TMA) 257 s_waitcnt lgkmcnt(0) 258#else 259 s_getreg_b32 ttmp14, hwreg(HW_REG_SHADER_TMA_LO) 260 s_getreg_b32 ttmp15, hwreg(HW_REG_SHADER_TMA_HI) 261#endif 262 s_lshl_b64 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 263 264 s_load_dword ttmp2, [ttmp14, ttmp15], 0x10 glc:1 // debug trap enabled flag 265 s_waitcnt lgkmcnt(0) 266 s_lshl_b32 ttmp2, ttmp2, TTMP11_DEBUG_TRAP_ENABLED_SHIFT 267 s_andn2_b32 ttmp11, ttmp11, TTMP11_DEBUG_TRAP_ENABLED_MASK 268 s_or_b32 ttmp11, ttmp11, ttmp2 269 270 s_load_dwordx2 [ttmp2, ttmp3], [ttmp14, ttmp15], 0x0 glc:1 // second-level TBA 271 s_waitcnt lgkmcnt(0) 272 s_load_dwordx2 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 glc:1 // second-level TMA 273 s_waitcnt lgkmcnt(0) 274 275 s_and_b64 [ttmp2, ttmp3], [ttmp2, ttmp3], [ttmp2, ttmp3] 276 s_cbranch_scc0 L_NO_NEXT_TRAP // second-level trap handler not been set 277 s_setpc_b64 [ttmp2, ttmp3] // jump to second-level trap handler 278 279L_NO_NEXT_TRAP: 280 // If not caused by trap then halt wave to prevent re-entry. 281 s_and_b32 ttmp2, s_save_pc_hi, (S_SAVE_PC_HI_TRAP_ID_MASK|S_SAVE_PC_HI_HT_MASK) 282 s_cbranch_scc1 L_TRAP_CASE 283 s_or_b32 s_save_status, s_save_status, SQ_WAVE_STATUS_HALT_MASK 284 285 // If the PC points to S_ENDPGM then context save will fail if STATUS.HALT is set. 286 // Rewind the PC to prevent this from occurring. 287 s_sub_u32 ttmp0, ttmp0, 0x8 288 s_subb_u32 ttmp1, ttmp1, 0x0 289 290 s_branch L_EXIT_TRAP 291 292L_TRAP_CASE: 293 // Host trap will not cause trap re-entry. 294 s_and_b32 ttmp2, s_save_pc_hi, S_SAVE_PC_HI_HT_MASK 295 s_cbranch_scc1 L_EXIT_TRAP 296 297 // Advance past trap instruction to prevent re-entry. 298 s_add_u32 ttmp0, ttmp0, 0x4 299 s_addc_u32 ttmp1, ttmp1, 0x0 300 301L_EXIT_TRAP: 302 s_and_b32 ttmp1, ttmp1, 0xFFFF 303 304#if HAVE_XNACK 305 restore_ib_sts(ttmp14, ttmp15) 306#endif 307 308 // Restore SQ_WAVE_STATUS. 309 s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32 310 s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32 311 s_setreg_b32 hwreg(HW_REG_STATUS), s_save_status 312 313 s_rfe_b64 [ttmp0, ttmp1] 314 315L_SAVE: 316 s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff //pc[47:32] 317 s_mov_b32 s_save_tmp, 0 318 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_SAVECTX_SHIFT, 1), s_save_tmp //clear saveCtx bit 319 320#if HAVE_XNACK 321 save_and_clear_ib_sts(s_save_tmp, s_save_trapsts) 322#endif 323 324 /* inform SPI the readiness and wait for SPI's go signal */ 325 s_mov_b32 s_save_exec_lo, exec_lo //save EXEC and use EXEC for the go signal from SPI 326 s_mov_b32 s_save_exec_hi, exec_hi 327 s_mov_b64 exec, 0x0 //clear EXEC to get ready to receive 328 329#if HAVE_SENDMSG_RTN 330 s_sendmsg_rtn_b64 [exec_lo, exec_hi], sendmsg(MSG_RTN_SAVE_WAVE) 331#else 332 s_sendmsg sendmsg(MSG_SAVEWAVE) //send SPI a message and wait for SPI's write to EXEC 333#endif 334 335#if ASIC_FAMILY < CHIP_SIENNA_CICHLID 336L_SLEEP: 337 // sleep 1 (64clk) is not enough for 8 waves per SIMD, which will cause 338 // SQ hang, since the 7,8th wave could not get arbit to exec inst, while 339 // other waves are stuck into the sleep-loop and waiting for wrexec!=0 340 s_sleep 0x2 341 s_cbranch_execz L_SLEEP 342#else 343 s_waitcnt lgkmcnt(0) 344#endif 345 346 // Save first_wave flag so we can clear high bits of save address. 347 s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK 348 s_lshl_b32 s_save_tmp, s_save_tmp, (S_SAVE_PC_HI_FIRST_WAVE_SHIFT - S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT) 349 s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp 350 351#if NO_SQC_STORE 352 // Trap temporaries must be saved via VGPR but all VGPRs are in use. 353 // There is no ttmp space to hold the resource constant for VGPR save. 354 // Save v0 by itself since it requires only two SGPRs. 355 s_mov_b32 s_save_ttmps_lo, exec_lo 356 s_and_b32 s_save_ttmps_hi, exec_hi, 0xFFFF 357 s_mov_b32 exec_lo, 0xFFFFFFFF 358 s_mov_b32 exec_hi, 0xFFFFFFFF 359 global_store_dword_addtid v0, [s_save_ttmps_lo, s_save_ttmps_hi] slc:1 glc:1 360 v_mov_b32 v0, 0x0 361 s_mov_b32 exec_lo, s_save_ttmps_lo 362 s_mov_b32 exec_hi, s_save_ttmps_hi 363#endif 364 365 // Save trap temporaries 4-11, 13 initialized by SPI debug dispatch logic 366 // ttmp SR memory offset : size(VGPR)+size(SVGPR)+size(SGPR)+0x40 367 get_wave_size(s_save_ttmps_hi) 368 get_vgpr_size_bytes(s_save_ttmps_lo, s_save_ttmps_hi) 369 get_svgpr_size_bytes(s_save_ttmps_hi) 370 s_add_u32 s_save_ttmps_lo, s_save_ttmps_lo, s_save_ttmps_hi 371 s_and_b32 s_save_ttmps_hi, s_save_spi_init_hi, 0xFFFF 372 s_add_u32 s_save_ttmps_lo, s_save_ttmps_lo, get_sgpr_size_bytes() 373 s_add_u32 s_save_ttmps_lo, s_save_ttmps_lo, s_save_spi_init_lo 374 s_addc_u32 s_save_ttmps_hi, s_save_ttmps_hi, 0x0 375 376#if NO_SQC_STORE 377 v_writelane_b32 v0, ttmp4, 0x4 378 v_writelane_b32 v0, ttmp5, 0x5 379 v_writelane_b32 v0, ttmp6, 0x6 380 v_writelane_b32 v0, ttmp7, 0x7 381 v_writelane_b32 v0, ttmp8, 0x8 382 v_writelane_b32 v0, ttmp9, 0x9 383 v_writelane_b32 v0, ttmp10, 0xA 384 v_writelane_b32 v0, ttmp11, 0xB 385 v_writelane_b32 v0, ttmp13, 0xD 386 v_writelane_b32 v0, exec_lo, 0xE 387 v_writelane_b32 v0, exec_hi, 0xF 388 389 s_mov_b32 exec_lo, 0x3FFF 390 s_mov_b32 exec_hi, 0x0 391 global_store_dword_addtid v0, [s_save_ttmps_lo, s_save_ttmps_hi] inst_offset:0x40 slc:1 glc:1 392 v_readlane_b32 ttmp14, v0, 0xE 393 v_readlane_b32 ttmp15, v0, 0xF 394 s_mov_b32 exec_lo, ttmp14 395 s_mov_b32 exec_hi, ttmp15 396#else 397 s_store_dwordx4 [ttmp4, ttmp5, ttmp6, ttmp7], [s_save_ttmps_lo, s_save_ttmps_hi], 0x50 glc:1 398 s_store_dwordx4 [ttmp8, ttmp9, ttmp10, ttmp11], [s_save_ttmps_lo, s_save_ttmps_hi], 0x60 glc:1 399 s_store_dword ttmp13, [s_save_ttmps_lo, s_save_ttmps_hi], 0x74 glc:1 400#endif 401 402 /* setup Resource Contants */ 403 s_mov_b32 s_save_buf_rsrc0, s_save_spi_init_lo //base_addr_lo 404 s_and_b32 s_save_buf_rsrc1, s_save_spi_init_hi, 0x0000FFFF //base_addr_hi 405 s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE 406 s_mov_b32 s_save_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) although not neccessarily inited 407 s_mov_b32 s_save_buf_rsrc3, S_SAVE_BUF_RSRC_WORD3_MISC 408 409 s_mov_b32 s_save_m0, m0 410 411 /* global mem offset */ 412 s_mov_b32 s_save_mem_offset, 0x0 413 get_wave_size(s_wave_size) 414 415#if HAVE_XNACK 416 // Save and clear vector XNACK state late to free up SGPRs. 417 s_getreg_b32 s_save_xnack_mask, hwreg(HW_REG_SHADER_XNACK_MASK) 418 s_setreg_imm32_b32 hwreg(HW_REG_SHADER_XNACK_MASK), 0x0 419#endif 420 421 /* save first 4 VGPRs, needed for SGPR save */ 422 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 423 s_lshr_b32 m0, s_wave_size, S_WAVE_SIZE 424 s_and_b32 m0, m0, 1 425 s_cmp_eq_u32 m0, 1 426 s_cbranch_scc1 L_ENABLE_SAVE_4VGPR_EXEC_HI 427 s_mov_b32 exec_hi, 0x00000000 428 s_branch L_SAVE_4VGPR_WAVE32 429L_ENABLE_SAVE_4VGPR_EXEC_HI: 430 s_mov_b32 exec_hi, 0xFFFFFFFF 431 s_branch L_SAVE_4VGPR_WAVE64 432L_SAVE_4VGPR_WAVE32: 433 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 434 435 // VGPR Allocated in 4-GPR granularity 436 437#if !NO_SQC_STORE 438 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 439#endif 440 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128 441 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128*2 442 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128*3 443 s_branch L_SAVE_HWREG 444 445L_SAVE_4VGPR_WAVE64: 446 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 447 448 // VGPR Allocated in 4-GPR granularity 449 450#if !NO_SQC_STORE 451 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 452#endif 453 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256 454 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2 455 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3 456 457 /* save HW registers */ 458 459L_SAVE_HWREG: 460 // HWREG SR memory offset : size(VGPR)+size(SVGPR)+size(SGPR) 461 get_vgpr_size_bytes(s_save_mem_offset, s_wave_size) 462 get_svgpr_size_bytes(s_save_tmp) 463 s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp 464 s_add_u32 s_save_mem_offset, s_save_mem_offset, get_sgpr_size_bytes() 465 466 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 467 468#if NO_SQC_STORE 469 v_mov_b32 v0, 0x0 //Offset[31:0] from buffer resource 470 v_mov_b32 v1, 0x0 //Offset[63:32] from buffer resource 471 v_mov_b32 v2, 0x0 //Set of SGPRs for TCP store 472 s_mov_b32 m0, 0x0 //Next lane of v2 to write to 473#endif 474 475 write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) 476 write_hwreg_to_mem(s_save_pc_lo, s_save_buf_rsrc0, s_save_mem_offset) 477 s_andn2_b32 s_save_tmp, s_save_pc_hi, S_SAVE_PC_HI_FIRST_WAVE_MASK 478 write_hwreg_to_mem(s_save_tmp, s_save_buf_rsrc0, s_save_mem_offset) 479 write_hwreg_to_mem(s_save_exec_lo, s_save_buf_rsrc0, s_save_mem_offset) 480 write_hwreg_to_mem(s_save_exec_hi, s_save_buf_rsrc0, s_save_mem_offset) 481 write_hwreg_to_mem(s_save_status, s_save_buf_rsrc0, s_save_mem_offset) 482 483 s_getreg_b32 s_save_tmp, hwreg(HW_REG_TRAPSTS) 484 write_hwreg_to_mem(s_save_tmp, s_save_buf_rsrc0, s_save_mem_offset) 485 486 // Not used on Sienna_Cichlid but keep layout same for debugger. 487 write_hwreg_to_mem(s_save_xnack_mask, s_save_buf_rsrc0, s_save_mem_offset) 488 489 s_getreg_b32 s_save_m0, hwreg(HW_REG_MODE) 490 write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) 491 492 s_getreg_b32 s_save_m0, hwreg(HW_REG_SHADER_FLAT_SCRATCH_LO) 493 write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) 494 495 s_getreg_b32 s_save_m0, hwreg(HW_REG_SHADER_FLAT_SCRATCH_HI) 496 write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset) 497 498#if NO_SQC_STORE 499 // Write HWREGs with 16 VGPR lanes. TTMPs occupy space after this. 500 s_mov_b32 exec_lo, 0xFFFF 501 s_mov_b32 exec_hi, 0x0 502 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 503 504 // Write SGPRs with 32 VGPR lanes. This works in wave32 and wave64 mode. 505 s_mov_b32 exec_lo, 0xFFFFFFFF 506#endif 507 508 /* save SGPRs */ 509 // Save SGPR before LDS save, then the s0 to s4 can be used during LDS save... 510 511 // SGPR SR memory offset : size(VGPR)+size(SVGPR) 512 get_vgpr_size_bytes(s_save_mem_offset, s_wave_size) 513 get_svgpr_size_bytes(s_save_tmp) 514 s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp 515 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 516 517#if NO_SQC_STORE 518 s_mov_b32 ttmp13, 0x0 //next VGPR lane to copy SGPR into 519#else 520 // backup s_save_buf_rsrc0,1 to s_save_pc_lo/hi, since write_16sgpr_to_mem function will change the rsrc0 521 s_mov_b32 s_save_xnack_mask, s_save_buf_rsrc0 522 s_add_u32 s_save_buf_rsrc0, s_save_buf_rsrc0, s_save_mem_offset 523 s_addc_u32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0 524#endif 525 526 s_mov_b32 m0, 0x0 //SGPR initial index value =0 527 s_nop 0x0 //Manually inserted wait states 528L_SAVE_SGPR_LOOP: 529 // SGPR is allocated in 16 SGPR granularity 530 s_movrels_b64 s0, s0 //s0 = s[0+m0], s1 = s[1+m0] 531 s_movrels_b64 s2, s2 //s2 = s[2+m0], s3 = s[3+m0] 532 s_movrels_b64 s4, s4 //s4 = s[4+m0], s5 = s[5+m0] 533 s_movrels_b64 s6, s6 //s6 = s[6+m0], s7 = s[7+m0] 534 s_movrels_b64 s8, s8 //s8 = s[8+m0], s9 = s[9+m0] 535 s_movrels_b64 s10, s10 //s10 = s[10+m0], s11 = s[11+m0] 536 s_movrels_b64 s12, s12 //s12 = s[12+m0], s13 = s[13+m0] 537 s_movrels_b64 s14, s14 //s14 = s[14+m0], s15 = s[15+m0] 538 539 write_16sgpr_to_mem(s0, s_save_buf_rsrc0, s_save_mem_offset) 540 541#if NO_SQC_STORE 542 s_cmp_eq_u32 ttmp13, 0x20 //have 32 VGPR lanes filled? 543 s_cbranch_scc0 L_SAVE_SGPR_SKIP_TCP_STORE 544 545 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 546 s_add_u32 s_save_mem_offset, s_save_mem_offset, 0x80 547 s_mov_b32 ttmp13, 0x0 548 v_mov_b32 v2, 0x0 549L_SAVE_SGPR_SKIP_TCP_STORE: 550#endif 551 552 s_add_u32 m0, m0, 16 //next sgpr index 553 s_cmp_lt_u32 m0, 96 //scc = (m0 < first 96 SGPR) ? 1 : 0 554 s_cbranch_scc1 L_SAVE_SGPR_LOOP //first 96 SGPR save is complete? 555 556 //save the rest 12 SGPR 557 s_movrels_b64 s0, s0 //s0 = s[0+m0], s1 = s[1+m0] 558 s_movrels_b64 s2, s2 //s2 = s[2+m0], s3 = s[3+m0] 559 s_movrels_b64 s4, s4 //s4 = s[4+m0], s5 = s[5+m0] 560 s_movrels_b64 s6, s6 //s6 = s[6+m0], s7 = s[7+m0] 561 s_movrels_b64 s8, s8 //s8 = s[8+m0], s9 = s[9+m0] 562 s_movrels_b64 s10, s10 //s10 = s[10+m0], s11 = s[11+m0] 563 write_12sgpr_to_mem(s0, s_save_buf_rsrc0, s_save_mem_offset) 564 565#if NO_SQC_STORE 566 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 567#else 568 // restore s_save_buf_rsrc0,1 569 s_mov_b32 s_save_buf_rsrc0, s_save_xnack_mask 570#endif 571 572 /* save LDS */ 573 574L_SAVE_LDS: 575 // Change EXEC to all threads... 576 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 577 s_lshr_b32 m0, s_wave_size, S_WAVE_SIZE 578 s_and_b32 m0, m0, 1 579 s_cmp_eq_u32 m0, 1 580 s_cbranch_scc1 L_ENABLE_SAVE_LDS_EXEC_HI 581 s_mov_b32 exec_hi, 0x00000000 582 s_branch L_SAVE_LDS_NORMAL 583L_ENABLE_SAVE_LDS_EXEC_HI: 584 s_mov_b32 exec_hi, 0xFFFFFFFF 585L_SAVE_LDS_NORMAL: 586 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) 587 s_and_b32 s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF //lds_size is zero? 588 s_cbranch_scc0 L_SAVE_LDS_DONE //no lds used? jump to L_SAVE_DONE 589 590 s_barrier //LDS is used? wait for other waves in the same TG 591 s_and_b32 s_save_tmp, s_save_pc_hi, S_SAVE_PC_HI_FIRST_WAVE_MASK 592 s_cbranch_scc0 L_SAVE_LDS_DONE 593 594 // first wave do LDS save; 595 596 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 6 //LDS size in dwords = lds_size * 64dw 597 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 2 //LDS size in bytes 598 s_mov_b32 s_save_buf_rsrc2, s_save_alloc_size //NUM_RECORDS in bytes 599 600 // LDS at offset: size(VGPR)+size(SVGPR)+SIZE(SGPR)+SIZE(HWREG) 601 // 602 get_vgpr_size_bytes(s_save_mem_offset, s_wave_size) 603 get_svgpr_size_bytes(s_save_tmp) 604 s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp 605 s_add_u32 s_save_mem_offset, s_save_mem_offset, get_sgpr_size_bytes() 606 s_add_u32 s_save_mem_offset, s_save_mem_offset, get_hwreg_size_bytes() 607 608 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 609 610 //load 0~63*4(byte address) to vgpr v0 611 v_mbcnt_lo_u32_b32 v0, -1, 0 612 v_mbcnt_hi_u32_b32 v0, -1, v0 613 v_mul_u32_u24 v0, 4, v0 614 615 s_lshr_b32 m0, s_wave_size, S_WAVE_SIZE 616 s_and_b32 m0, m0, 1 617 s_cmp_eq_u32 m0, 1 618 s_mov_b32 m0, 0x0 619 s_cbranch_scc1 L_SAVE_LDS_W64 620 621L_SAVE_LDS_W32: 622 s_mov_b32 s3, 128 623 s_nop 0 624 s_nop 0 625 s_nop 0 626L_SAVE_LDS_LOOP_W32: 627 ds_read_b32 v1, v0 628 s_waitcnt 0 629 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 630 631 s_add_u32 m0, m0, s3 //every buffer_store_lds does 256 bytes 632 s_add_u32 s_save_mem_offset, s_save_mem_offset, s3 633 v_add_nc_u32 v0, v0, 128 //mem offset increased by 128 bytes 634 s_cmp_lt_u32 m0, s_save_alloc_size //scc=(m0 < s_save_alloc_size) ? 1 : 0 635 s_cbranch_scc1 L_SAVE_LDS_LOOP_W32 //LDS save is complete? 636 637 s_branch L_SAVE_LDS_DONE 638 639L_SAVE_LDS_W64: 640 s_mov_b32 s3, 256 641 s_nop 0 642 s_nop 0 643 s_nop 0 644L_SAVE_LDS_LOOP_W64: 645 ds_read_b32 v1, v0 646 s_waitcnt 0 647 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 648 649 s_add_u32 m0, m0, s3 //every buffer_store_lds does 256 bytes 650 s_add_u32 s_save_mem_offset, s_save_mem_offset, s3 651 v_add_nc_u32 v0, v0, 256 //mem offset increased by 256 bytes 652 s_cmp_lt_u32 m0, s_save_alloc_size //scc=(m0 < s_save_alloc_size) ? 1 : 0 653 s_cbranch_scc1 L_SAVE_LDS_LOOP_W64 //LDS save is complete? 654 655L_SAVE_LDS_DONE: 656 /* save VGPRs - set the Rest VGPRs */ 657L_SAVE_VGPR: 658 // VGPR SR memory offset: 0 659 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 660 s_lshr_b32 m0, s_wave_size, S_WAVE_SIZE 661 s_and_b32 m0, m0, 1 662 s_cmp_eq_u32 m0, 1 663 s_cbranch_scc1 L_ENABLE_SAVE_VGPR_EXEC_HI 664 s_mov_b32 s_save_mem_offset, (0+128*4) // for the rest VGPRs 665 s_mov_b32 exec_hi, 0x00000000 666 s_branch L_SAVE_VGPR_NORMAL 667L_ENABLE_SAVE_VGPR_EXEC_HI: 668 s_mov_b32 s_save_mem_offset, (0+256*4) // for the rest VGPRs 669 s_mov_b32 exec_hi, 0xFFFFFFFF 670L_SAVE_VGPR_NORMAL: 671 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) 672 s_add_u32 s_save_alloc_size, s_save_alloc_size, 1 673 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value) 674 //determine it is wave32 or wave64 675 s_lshr_b32 m0, s_wave_size, S_WAVE_SIZE 676 s_and_b32 m0, m0, 1 677 s_cmp_eq_u32 m0, 1 678 s_cbranch_scc1 L_SAVE_VGPR_WAVE64 679 680 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 681 682 // VGPR Allocated in 4-GPR granularity 683 684 // VGPR store using dw burst 685 s_mov_b32 m0, 0x4 //VGPR initial index value =4 686 s_cmp_lt_u32 m0, s_save_alloc_size 687 s_cbranch_scc0 L_SAVE_VGPR_END 688 689L_SAVE_VGPR_W32_LOOP: 690 v_movrels_b32 v0, v0 //v0 = v[0+m0] 691 v_movrels_b32 v1, v1 //v1 = v[1+m0] 692 v_movrels_b32 v2, v2 //v2 = v[2+m0] 693 v_movrels_b32 v3, v3 //v3 = v[3+m0] 694 695 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 696 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128 697 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128*2 698 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128*3 699 700 s_add_u32 m0, m0, 4 //next vgpr index 701 s_add_u32 s_save_mem_offset, s_save_mem_offset, 128*4 //every buffer_store_dword does 128 bytes 702 s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 703 s_cbranch_scc1 L_SAVE_VGPR_W32_LOOP //VGPR save is complete? 704 705 s_branch L_SAVE_VGPR_END 706 707L_SAVE_VGPR_WAVE64: 708 s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 709 710 // VGPR store using dw burst 711 s_mov_b32 m0, 0x4 //VGPR initial index value =4 712 s_cmp_lt_u32 m0, s_save_alloc_size 713 s_cbranch_scc0 L_SAVE_SHARED_VGPR 714 715L_SAVE_VGPR_W64_LOOP: 716 v_movrels_b32 v0, v0 //v0 = v[0+m0] 717 v_movrels_b32 v1, v1 //v1 = v[1+m0] 718 v_movrels_b32 v2, v2 //v2 = v[2+m0] 719 v_movrels_b32 v3, v3 //v3 = v[3+m0] 720 721 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 722 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256 723 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2 724 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3 725 726 s_add_u32 m0, m0, 4 //next vgpr index 727 s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 //every buffer_store_dword does 256 bytes 728 s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 729 s_cbranch_scc1 L_SAVE_VGPR_W64_LOOP //VGPR save is complete? 730 731L_SAVE_SHARED_VGPR: 732 //Below part will be the save shared vgpr part (new for gfx10) 733 s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE) 734 s_and_b32 s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF //shared_vgpr_size is zero? 735 s_cbranch_scc0 L_SAVE_VGPR_END //no shared_vgpr used? jump to L_SAVE_LDS 736 s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 3 //Number of SHARED_VGPRs = shared_vgpr_size * 8 (non-zero value) 737 //m0 now has the value of normal vgpr count, just add the m0 with shared_vgpr count to get the total count. 738 //save shared_vgpr will start from the index of m0 739 s_add_u32 s_save_alloc_size, s_save_alloc_size, m0 740 s_mov_b32 exec_lo, 0xFFFFFFFF 741 s_mov_b32 exec_hi, 0x00000000 742L_SAVE_SHARED_VGPR_WAVE64_LOOP: 743 v_movrels_b32 v0, v0 //v0 = v[0+m0] 744 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 745 s_add_u32 m0, m0, 1 //next vgpr index 746 s_add_u32 s_save_mem_offset, s_save_mem_offset, 128 747 s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 748 s_cbranch_scc1 L_SAVE_SHARED_VGPR_WAVE64_LOOP //SHARED_VGPR save is complete? 749 750L_SAVE_VGPR_END: 751 s_branch L_END_PGM 752 753L_RESTORE: 754 /* Setup Resource Contants */ 755 s_mov_b32 s_restore_buf_rsrc0, s_restore_spi_init_lo //base_addr_lo 756 s_and_b32 s_restore_buf_rsrc1, s_restore_spi_init_hi, 0x0000FFFF //base_addr_hi 757 s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE 758 s_mov_b32 s_restore_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) 759 s_mov_b32 s_restore_buf_rsrc3, S_RESTORE_BUF_RSRC_WORD3_MISC 760 761 //determine it is wave32 or wave64 762 get_wave_size(s_restore_size) 763 764 s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_FIRST_WAVE_MASK 765 s_cbranch_scc0 L_RESTORE_VGPR 766 767 /* restore LDS */ 768L_RESTORE_LDS: 769 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 770 s_lshr_b32 m0, s_restore_size, S_WAVE_SIZE 771 s_and_b32 m0, m0, 1 772 s_cmp_eq_u32 m0, 1 773 s_cbranch_scc1 L_ENABLE_RESTORE_LDS_EXEC_HI 774 s_mov_b32 exec_hi, 0x00000000 775 s_branch L_RESTORE_LDS_NORMAL 776L_ENABLE_RESTORE_LDS_EXEC_HI: 777 s_mov_b32 exec_hi, 0xFFFFFFFF 778L_RESTORE_LDS_NORMAL: 779 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) 780 s_and_b32 s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF //lds_size is zero? 781 s_cbranch_scc0 L_RESTORE_VGPR //no lds used? jump to L_RESTORE_VGPR 782 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 6 //LDS size in dwords = lds_size * 64dw 783 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 2 //LDS size in bytes 784 s_mov_b32 s_restore_buf_rsrc2, s_restore_alloc_size //NUM_RECORDS in bytes 785 786 // LDS at offset: size(VGPR)+size(SVGPR)+SIZE(SGPR)+SIZE(HWREG) 787 // 788 get_vgpr_size_bytes(s_restore_mem_offset, s_restore_size) 789 get_svgpr_size_bytes(s_restore_tmp) 790 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 791 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_sgpr_size_bytes() 792 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_hwreg_size_bytes() 793 794 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 795 796 s_lshr_b32 m0, s_restore_size, S_WAVE_SIZE 797 s_and_b32 m0, m0, 1 798 s_cmp_eq_u32 m0, 1 799 s_mov_b32 m0, 0x0 800 s_cbranch_scc1 L_RESTORE_LDS_LOOP_W64 801 802L_RESTORE_LDS_LOOP_W32: 803#if HAVE_BUFFER_LDS_LOAD 804 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 // first 64DW 805#else 806 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset 807 s_waitcnt vmcnt(0) 808 ds_store_addtid_b32 v0 809#endif 810 s_add_u32 m0, m0, 128 // 128 DW 811 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 128 //mem offset increased by 128DW 812 s_cmp_lt_u32 m0, s_restore_alloc_size //scc=(m0 < s_restore_alloc_size) ? 1 : 0 813 s_cbranch_scc1 L_RESTORE_LDS_LOOP_W32 //LDS restore is complete? 814 s_branch L_RESTORE_VGPR 815 816L_RESTORE_LDS_LOOP_W64: 817#if HAVE_BUFFER_LDS_LOAD 818 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 // first 64DW 819#else 820 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset 821 s_waitcnt vmcnt(0) 822 ds_store_addtid_b32 v0 823#endif 824 s_add_u32 m0, m0, 256 // 256 DW 825 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256 //mem offset increased by 256DW 826 s_cmp_lt_u32 m0, s_restore_alloc_size //scc=(m0 < s_restore_alloc_size) ? 1 : 0 827 s_cbranch_scc1 L_RESTORE_LDS_LOOP_W64 //LDS restore is complete? 828 829 /* restore VGPRs */ 830L_RESTORE_VGPR: 831 // VGPR SR memory offset : 0 832 s_mov_b32 s_restore_mem_offset, 0x0 833 s_mov_b32 exec_lo, 0xFFFFFFFF //need every thread from now on 834 s_lshr_b32 m0, s_restore_size, S_WAVE_SIZE 835 s_and_b32 m0, m0, 1 836 s_cmp_eq_u32 m0, 1 837 s_cbranch_scc1 L_ENABLE_RESTORE_VGPR_EXEC_HI 838 s_mov_b32 exec_hi, 0x00000000 839 s_branch L_RESTORE_VGPR_NORMAL 840L_ENABLE_RESTORE_VGPR_EXEC_HI: 841 s_mov_b32 exec_hi, 0xFFFFFFFF 842L_RESTORE_VGPR_NORMAL: 843 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) 844 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, 1 845 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 2 //Number of VGPRs = (vgpr_size + 1) * 4 (non-zero value) 846 //determine it is wave32 or wave64 847 s_lshr_b32 m0, s_restore_size, S_WAVE_SIZE 848 s_and_b32 m0, m0, 1 849 s_cmp_eq_u32 m0, 1 850 s_cbranch_scc1 L_RESTORE_VGPR_WAVE64 851 852 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 853 854 // VGPR load using dw burst 855 s_mov_b32 s_restore_mem_offset_save, s_restore_mem_offset // restore start with v1, v0 will be the last 856 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 128*4 857 s_mov_b32 m0, 4 //VGPR initial index value = 4 858 s_cmp_lt_u32 m0, s_restore_alloc_size 859 s_cbranch_scc0 L_RESTORE_SGPR 860 861L_RESTORE_VGPR_WAVE32_LOOP: 862 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 863 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:128 864 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:128*2 865 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:128*3 866 s_waitcnt vmcnt(0) 867 v_movreld_b32 v0, v0 //v[0+m0] = v0 868 v_movreld_b32 v1, v1 869 v_movreld_b32 v2, v2 870 v_movreld_b32 v3, v3 871 s_add_u32 m0, m0, 4 //next vgpr index 872 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 128*4 //every buffer_load_dword does 128 bytes 873 s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0 874 s_cbranch_scc1 L_RESTORE_VGPR_WAVE32_LOOP //VGPR restore (except v0) is complete? 875 876 /* VGPR restore on v0 */ 877 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 878 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:128 879 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:128*2 880 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:128*3 881 s_waitcnt vmcnt(0) 882 883 s_branch L_RESTORE_SGPR 884 885L_RESTORE_VGPR_WAVE64: 886 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 887 888 // VGPR load using dw burst 889 s_mov_b32 s_restore_mem_offset_save, s_restore_mem_offset // restore start with v4, v0 will be the last 890 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 891 s_mov_b32 m0, 4 //VGPR initial index value = 4 892 s_cmp_lt_u32 m0, s_restore_alloc_size 893 s_cbranch_scc0 L_RESTORE_SHARED_VGPR 894 895L_RESTORE_VGPR_WAVE64_LOOP: 896 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 897 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256 898 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*2 899 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*3 900 s_waitcnt vmcnt(0) 901 v_movreld_b32 v0, v0 //v[0+m0] = v0 902 v_movreld_b32 v1, v1 903 v_movreld_b32 v2, v2 904 v_movreld_b32 v3, v3 905 s_add_u32 m0, m0, 4 //next vgpr index 906 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 //every buffer_load_dword does 256 bytes 907 s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0 908 s_cbranch_scc1 L_RESTORE_VGPR_WAVE64_LOOP //VGPR restore (except v0) is complete? 909 910L_RESTORE_SHARED_VGPR: 911 //Below part will be the restore shared vgpr part (new for gfx10) 912 s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE) //shared_vgpr_size 913 s_and_b32 s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF //shared_vgpr_size is zero? 914 s_cbranch_scc0 L_RESTORE_V0 //no shared_vgpr used? 915 s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 3 //Number of SHARED_VGPRs = shared_vgpr_size * 8 (non-zero value) 916 //m0 now has the value of normal vgpr count, just add the m0 with shared_vgpr count to get the total count. 917 //restore shared_vgpr will start from the index of m0 918 s_add_u32 s_restore_alloc_size, s_restore_alloc_size, m0 919 s_mov_b32 exec_lo, 0xFFFFFFFF 920 s_mov_b32 exec_hi, 0x00000000 921L_RESTORE_SHARED_VGPR_WAVE64_LOOP: 922 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 923 s_waitcnt vmcnt(0) 924 v_movreld_b32 v0, v0 //v[0+m0] = v0 925 s_add_u32 m0, m0, 1 //next vgpr index 926 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 128 927 s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0 928 s_cbranch_scc1 L_RESTORE_SHARED_VGPR_WAVE64_LOOP //VGPR restore (except v0) is complete? 929 930 s_mov_b32 exec_hi, 0xFFFFFFFF //restore back exec_hi before restoring V0!! 931 932 /* VGPR restore on v0 */ 933L_RESTORE_V0: 934 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 935 buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256 936 buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*2 937 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*3 938 s_waitcnt vmcnt(0) 939 940 /* restore SGPRs */ 941 //will be 2+8+16*6 942 // SGPR SR memory offset : size(VGPR)+size(SVGPR) 943L_RESTORE_SGPR: 944 get_vgpr_size_bytes(s_restore_mem_offset, s_restore_size) 945 get_svgpr_size_bytes(s_restore_tmp) 946 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 947 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_sgpr_size_bytes() 948 s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 20*4 //s108~s127 is not saved 949 950 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 951 952 s_mov_b32 m0, s_sgpr_save_num 953 954 read_4sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset) 955 s_waitcnt lgkmcnt(0) 956 957 s_sub_u32 m0, m0, 4 // Restore from S[0] to S[104] 958 s_nop 0 // hazard SALU M0=> S_MOVREL 959 960 s_movreld_b64 s0, s0 //s[0+m0] = s0 961 s_movreld_b64 s2, s2 962 963 read_8sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset) 964 s_waitcnt lgkmcnt(0) 965 966 s_sub_u32 m0, m0, 8 // Restore from S[0] to S[96] 967 s_nop 0 // hazard SALU M0=> S_MOVREL 968 969 s_movreld_b64 s0, s0 //s[0+m0] = s0 970 s_movreld_b64 s2, s2 971 s_movreld_b64 s4, s4 972 s_movreld_b64 s6, s6 973 974 L_RESTORE_SGPR_LOOP: 975 read_16sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset) 976 s_waitcnt lgkmcnt(0) 977 978 s_sub_u32 m0, m0, 16 // Restore from S[n] to S[0] 979 s_nop 0 // hazard SALU M0=> S_MOVREL 980 981 s_movreld_b64 s0, s0 //s[0+m0] = s0 982 s_movreld_b64 s2, s2 983 s_movreld_b64 s4, s4 984 s_movreld_b64 s6, s6 985 s_movreld_b64 s8, s8 986 s_movreld_b64 s10, s10 987 s_movreld_b64 s12, s12 988 s_movreld_b64 s14, s14 989 990 s_cmp_eq_u32 m0, 0 //scc = (m0 < s_sgpr_save_num) ? 1 : 0 991 s_cbranch_scc0 L_RESTORE_SGPR_LOOP 992 993 // s_barrier with MODE.DEBUG_EN=1, STATUS.PRIV=1 incorrectly asserts debug exception. 994 // Clear DEBUG_EN before and restore MODE after the barrier. 995 s_setreg_imm32_b32 hwreg(HW_REG_MODE), 0 996 s_barrier //barrier to ensure the readiness of LDS before access attemps from any other wave in the same TG 997 998 /* restore HW registers */ 999L_RESTORE_HWREG: 1000 // HWREG SR memory offset : size(VGPR)+size(SVGPR)+size(SGPR) 1001 get_vgpr_size_bytes(s_restore_mem_offset, s_restore_size) 1002 get_svgpr_size_bytes(s_restore_tmp) 1003 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp 1004 s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_sgpr_size_bytes() 1005 1006 s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes 1007 1008 read_hwreg_from_mem(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset) 1009 read_hwreg_from_mem(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset) 1010 read_hwreg_from_mem(s_restore_pc_hi, s_restore_buf_rsrc0, s_restore_mem_offset) 1011 read_hwreg_from_mem(s_restore_exec_lo, s_restore_buf_rsrc0, s_restore_mem_offset) 1012 read_hwreg_from_mem(s_restore_exec_hi, s_restore_buf_rsrc0, s_restore_mem_offset) 1013 read_hwreg_from_mem(s_restore_status, s_restore_buf_rsrc0, s_restore_mem_offset) 1014 read_hwreg_from_mem(s_restore_trapsts, s_restore_buf_rsrc0, s_restore_mem_offset) 1015 read_hwreg_from_mem(s_restore_xnack_mask, s_restore_buf_rsrc0, s_restore_mem_offset) 1016 read_hwreg_from_mem(s_restore_mode, s_restore_buf_rsrc0, s_restore_mem_offset) 1017 read_hwreg_from_mem(s_restore_flat_scratch, s_restore_buf_rsrc0, s_restore_mem_offset) 1018 s_waitcnt lgkmcnt(0) 1019 1020 s_setreg_b32 hwreg(HW_REG_SHADER_FLAT_SCRATCH_LO), s_restore_flat_scratch 1021 1022 read_hwreg_from_mem(s_restore_flat_scratch, s_restore_buf_rsrc0, s_restore_mem_offset) 1023 s_waitcnt lgkmcnt(0) //from now on, it is safe to restore STATUS and IB_STS 1024 1025 s_setreg_b32 hwreg(HW_REG_SHADER_FLAT_SCRATCH_HI), s_restore_flat_scratch 1026 1027 s_mov_b32 m0, s_restore_m0 1028 s_mov_b32 exec_lo, s_restore_exec_lo 1029 s_mov_b32 exec_hi, s_restore_exec_hi 1030 1031 s_and_b32 s_restore_m0, SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK, s_restore_trapsts 1032 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE), s_restore_m0 1033 1034#if HAVE_XNACK 1035 s_setreg_b32 hwreg(HW_REG_SHADER_XNACK_MASK), s_restore_xnack_mask 1036#endif 1037 1038 s_and_b32 s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK, s_restore_trapsts 1039 s_lshr_b32 s_restore_m0, s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT 1040 s_setreg_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE), s_restore_m0 1041 s_setreg_b32 hwreg(HW_REG_MODE), s_restore_mode 1042 1043 // Restore trap temporaries 4-11, 13 initialized by SPI debug dispatch logic 1044 // ttmp SR memory offset : size(VGPR)+size(SVGPR)+size(SGPR)+0x40 1045 get_vgpr_size_bytes(s_restore_ttmps_lo, s_restore_size) 1046 get_svgpr_size_bytes(s_restore_ttmps_hi) 1047 s_add_u32 s_restore_ttmps_lo, s_restore_ttmps_lo, s_restore_ttmps_hi 1048 s_add_u32 s_restore_ttmps_lo, s_restore_ttmps_lo, get_sgpr_size_bytes() 1049 s_add_u32 s_restore_ttmps_lo, s_restore_ttmps_lo, s_restore_buf_rsrc0 1050 s_addc_u32 s_restore_ttmps_hi, s_restore_buf_rsrc1, 0x0 1051 s_and_b32 s_restore_ttmps_hi, s_restore_ttmps_hi, 0xFFFF 1052 s_load_dwordx4 [ttmp4, ttmp5, ttmp6, ttmp7], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x50 glc:1 1053 s_load_dwordx4 [ttmp8, ttmp9, ttmp10, ttmp11], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x60 glc:1 1054 s_load_dword ttmp13, [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x74 glc:1 1055 s_waitcnt lgkmcnt(0) 1056 1057#if HAVE_XNACK 1058 restore_ib_sts(s_restore_tmp, s_restore_m0) 1059#endif 1060 1061 s_and_b32 s_restore_pc_hi, s_restore_pc_hi, 0x0000ffff //pc[47:32] //Do it here in order not to affect STATUS 1062 s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32 1063 s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32 1064 s_setreg_b32 hwreg(HW_REG_STATUS), s_restore_status // SCC is included, which is changed by previous salu 1065 1066 s_rfe_b64 s_restore_pc_lo //Return to the main shader program and resume execution 1067 1068L_END_PGM: 1069 s_endpgm 1070end 1071 1072function write_hwreg_to_mem(s, s_rsrc, s_mem_offset) 1073#if NO_SQC_STORE 1074 // Copy into VGPR for later TCP store. 1075 v_writelane_b32 v2, s, m0 1076 s_add_u32 m0, m0, 0x1 1077#else 1078 s_mov_b32 exec_lo, m0 1079 s_mov_b32 m0, s_mem_offset 1080 s_buffer_store_dword s, s_rsrc, m0 glc:1 1081 s_add_u32 s_mem_offset, s_mem_offset, 4 1082 s_mov_b32 m0, exec_lo 1083#endif 1084end 1085 1086 1087function write_16sgpr_to_mem(s, s_rsrc, s_mem_offset) 1088#if NO_SQC_STORE 1089 // Copy into VGPR for later TCP store. 1090 for var sgpr_idx = 0; sgpr_idx < 16; sgpr_idx ++ 1091 v_writelane_b32 v2, s[sgpr_idx], ttmp13 1092 s_add_u32 ttmp13, ttmp13, 0x1 1093 end 1094#else 1095 s_buffer_store_dwordx4 s[0], s_rsrc, 0 glc:1 1096 s_buffer_store_dwordx4 s[4], s_rsrc, 16 glc:1 1097 s_buffer_store_dwordx4 s[8], s_rsrc, 32 glc:1 1098 s_buffer_store_dwordx4 s[12], s_rsrc, 48 glc:1 1099 s_add_u32 s_rsrc[0], s_rsrc[0], 4*16 1100 s_addc_u32 s_rsrc[1], s_rsrc[1], 0x0 1101#endif 1102end 1103 1104function write_12sgpr_to_mem(s, s_rsrc, s_mem_offset) 1105#if NO_SQC_STORE 1106 // Copy into VGPR for later TCP store. 1107 for var sgpr_idx = 0; sgpr_idx < 12; sgpr_idx ++ 1108 v_writelane_b32 v2, s[sgpr_idx], ttmp13 1109 s_add_u32 ttmp13, ttmp13, 0x1 1110 end 1111#else 1112 s_buffer_store_dwordx4 s[0], s_rsrc, 0 glc:1 1113 s_buffer_store_dwordx4 s[4], s_rsrc, 16 glc:1 1114 s_buffer_store_dwordx4 s[8], s_rsrc, 32 glc:1 1115 s_add_u32 s_rsrc[0], s_rsrc[0], 4*12 1116 s_addc_u32 s_rsrc[1], s_rsrc[1], 0x0 1117#endif 1118end 1119 1120function read_hwreg_from_mem(s, s_rsrc, s_mem_offset) 1121 s_buffer_load_dword s, s_rsrc, s_mem_offset glc:1 1122 s_add_u32 s_mem_offset, s_mem_offset, 4 1123end 1124 1125function read_16sgpr_from_mem(s, s_rsrc, s_mem_offset) 1126 s_sub_u32 s_mem_offset, s_mem_offset, 4*16 1127 s_buffer_load_dwordx16 s, s_rsrc, s_mem_offset glc:1 1128end 1129 1130function read_8sgpr_from_mem(s, s_rsrc, s_mem_offset) 1131 s_sub_u32 s_mem_offset, s_mem_offset, 4*8 1132 s_buffer_load_dwordx8 s, s_rsrc, s_mem_offset glc:1 1133end 1134 1135function read_4sgpr_from_mem(s, s_rsrc, s_mem_offset) 1136 s_sub_u32 s_mem_offset, s_mem_offset, 4*4 1137 s_buffer_load_dwordx4 s, s_rsrc, s_mem_offset glc:1 1138end 1139 1140 1141function get_lds_size_bytes(s_lds_size_byte) 1142 s_getreg_b32 s_lds_size_byte, hwreg(HW_REG_LDS_ALLOC, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) 1143 s_lshl_b32 s_lds_size_byte, s_lds_size_byte, 8 //LDS size in dwords = lds_size * 64 *4Bytes // granularity 64DW 1144end 1145 1146function get_vgpr_size_bytes(s_vgpr_size_byte, s_size) 1147 s_getreg_b32 s_vgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) 1148 s_add_u32 s_vgpr_size_byte, s_vgpr_size_byte, 1 1149 s_bitcmp1_b32 s_size, S_WAVE_SIZE 1150 s_cbranch_scc1 L_ENABLE_SHIFT_W64 1151 s_lshl_b32 s_vgpr_size_byte, s_vgpr_size_byte, (2+7) //Number of VGPRs = (vgpr_size + 1) * 4 * 32 * 4 (non-zero value) 1152 s_branch L_SHIFT_DONE 1153L_ENABLE_SHIFT_W64: 1154 s_lshl_b32 s_vgpr_size_byte, s_vgpr_size_byte, (2+8) //Number of VGPRs = (vgpr_size + 1) * 4 * 64 * 4 (non-zero value) 1155L_SHIFT_DONE: 1156end 1157 1158function get_svgpr_size_bytes(s_svgpr_size_byte) 1159 s_getreg_b32 s_svgpr_size_byte, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE) 1160 s_lshl_b32 s_svgpr_size_byte, s_svgpr_size_byte, (3+7) 1161end 1162 1163function get_sgpr_size_bytes 1164 return 512 1165end 1166 1167function get_hwreg_size_bytes 1168 return 128 1169end 1170 1171function get_wave_size(s_reg) 1172 s_getreg_b32 s_reg, hwreg(HW_REG_IB_STS2,SQ_WAVE_IB_STS2_WAVE64_SHIFT,SQ_WAVE_IB_STS2_WAVE64_SIZE) 1173 s_lshl_b32 s_reg, s_reg, S_WAVE_SIZE 1174end 1175 1176function save_and_clear_ib_sts(tmp1, tmp2) 1177 // Preserve and clear scalar XNACK state before issuing scalar loads. 1178 // Save IB_STS.REPLAY_W64H[25], RCNT[21:16], FIRST_REPLAY[15] into 1179 // unused space ttmp11[31:24]. 1180 s_andn2_b32 ttmp11, ttmp11, (TTMP11_SAVE_REPLAY_W64H_MASK | TTMP11_SAVE_RCNT_FIRST_REPLAY_MASK) 1181 s_getreg_b32 tmp1, hwreg(HW_REG_IB_STS) 1182 s_and_b32 tmp2, tmp1, SQ_WAVE_IB_STS_REPLAY_W64H_MASK 1183 s_lshl_b32 tmp2, tmp2, (TTMP11_SAVE_REPLAY_W64H_SHIFT - SQ_WAVE_IB_STS_REPLAY_W64H_SHIFT) 1184 s_or_b32 ttmp11, ttmp11, tmp2 1185 s_and_b32 tmp2, tmp1, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK 1186 s_lshl_b32 tmp2, tmp2, (TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT - SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT) 1187 s_or_b32 ttmp11, ttmp11, tmp2 1188 s_andn2_b32 tmp1, tmp1, (SQ_WAVE_IB_STS_REPLAY_W64H_MASK | SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK) 1189 s_setreg_b32 hwreg(HW_REG_IB_STS), tmp1 1190end 1191 1192function restore_ib_sts(tmp1, tmp2) 1193 s_lshr_b32 tmp1, ttmp11, (TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT - SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT) 1194 s_and_b32 tmp2, tmp1, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK 1195 s_lshr_b32 tmp1, ttmp11, (TTMP11_SAVE_REPLAY_W64H_SHIFT - SQ_WAVE_IB_STS_REPLAY_W64H_SHIFT) 1196 s_and_b32 tmp1, tmp1, SQ_WAVE_IB_STS_REPLAY_W64H_MASK 1197 s_or_b32 tmp1, tmp1, tmp2 1198 s_setreg_b32 hwreg(HW_REG_IB_STS), tmp1 1199end 1200