1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef VI_H 24 #define VI_H 25 26 #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ 27 #define SDMA1_REGISTER_OFFSET 0x200 /* not a register */ 28 #define SDMA_MAX_INSTANCE 2 29 30 #define KFD_VI_SDMA_QUEUE_OFFSET 0x80 /* not a register */ 31 32 /* crtc instance offsets */ 33 #define CRTC0_REGISTER_OFFSET (0x1b9c - 0x1b9c) 34 #define CRTC1_REGISTER_OFFSET (0x1d9c - 0x1b9c) 35 #define CRTC2_REGISTER_OFFSET (0x1f9c - 0x1b9c) 36 #define CRTC3_REGISTER_OFFSET (0x419c - 0x1b9c) 37 #define CRTC4_REGISTER_OFFSET (0x439c - 0x1b9c) 38 #define CRTC5_REGISTER_OFFSET (0x459c - 0x1b9c) 39 #define CRTC6_REGISTER_OFFSET (0x479c - 0x1b9c) 40 41 /* dig instance offsets */ 42 #define DIG0_REGISTER_OFFSET (0x4a00 - 0x4a00) 43 #define DIG1_REGISTER_OFFSET (0x4b00 - 0x4a00) 44 #define DIG2_REGISTER_OFFSET (0x4c00 - 0x4a00) 45 #define DIG3_REGISTER_OFFSET (0x4d00 - 0x4a00) 46 #define DIG4_REGISTER_OFFSET (0x4e00 - 0x4a00) 47 #define DIG5_REGISTER_OFFSET (0x4f00 - 0x4a00) 48 #define DIG6_REGISTER_OFFSET (0x5400 - 0x4a00) 49 #define DIG7_REGISTER_OFFSET (0x5600 - 0x4a00) 50 #define DIG8_REGISTER_OFFSET (0x5700 - 0x4a00) 51 52 /* audio endpt instance offsets */ 53 #define AUD0_REGISTER_OFFSET (0x17a8 - 0x17a8) 54 #define AUD1_REGISTER_OFFSET (0x17ac - 0x17a8) 55 #define AUD2_REGISTER_OFFSET (0x17b0 - 0x17a8) 56 #define AUD3_REGISTER_OFFSET (0x17b4 - 0x17a8) 57 #define AUD4_REGISTER_OFFSET (0x17b8 - 0x17a8) 58 #define AUD5_REGISTER_OFFSET (0x17bc - 0x17a8) 59 #define AUD6_REGISTER_OFFSET (0x17c0 - 0x17a8) 60 #define AUD7_REGISTER_OFFSET (0x17c4 - 0x17a8) 61 62 /* hpd instance offsets */ 63 #define HPD0_REGISTER_OFFSET (0x1898 - 0x1898) 64 #define HPD1_REGISTER_OFFSET (0x18a0 - 0x1898) 65 #define HPD2_REGISTER_OFFSET (0x18a8 - 0x1898) 66 #define HPD3_REGISTER_OFFSET (0x18b0 - 0x1898) 67 #define HPD4_REGISTER_OFFSET (0x18b8 - 0x1898) 68 #define HPD5_REGISTER_OFFSET (0x18c0 - 0x1898) 69 70 #define AMDGPU_NUM_OF_VMIDS 8 71 72 #define PIPEID(x) ((x) << 0) 73 #define MEID(x) ((x) << 2) 74 #define VMID(x) ((x) << 4) 75 #define QUEUEID(x) ((x) << 8) 76 77 #define MC_SEQ_MISC0__MT__MASK 0xf0000000 78 #define MC_SEQ_MISC0__MT__GDDR1 0x10000000 79 #define MC_SEQ_MISC0__MT__DDR2 0x20000000 80 #define MC_SEQ_MISC0__MT__GDDR3 0x30000000 81 #define MC_SEQ_MISC0__MT__GDDR4 0x40000000 82 #define MC_SEQ_MISC0__MT__GDDR5 0x50000000 83 #define MC_SEQ_MISC0__MT__HBM 0x60000000 84 #define MC_SEQ_MISC0__MT__DDR3 0xB0000000 85 86 /* 87 * PM4 88 */ 89 #define PACKET_TYPE0 0 90 #define PACKET_TYPE1 1 91 #define PACKET_TYPE2 2 92 #define PACKET_TYPE3 3 93 94 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 95 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 96 #define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF) 97 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 98 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 99 ((reg) & 0xFFFF) | \ 100 ((n) & 0x3FFF) << 16) 101 #define CP_PACKET2 0x80000000 102 #define PACKET2_PAD_SHIFT 0 103 #define PACKET2_PAD_MASK (0x3fffffff << 0) 104 105 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 106 107 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 108 (((op) & 0xFF) << 8) | \ 109 ((n) & 0x3FFF) << 16) 110 111 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 112 113 /* Packet 3 types */ 114 #define PACKET3_NOP 0x10 115 #define PACKET3_SET_BASE 0x11 116 #define PACKET3_BASE_INDEX(x) ((x) << 0) 117 #define CE_PARTITION_BASE 3 118 #define PACKET3_CLEAR_STATE 0x12 119 #define PACKET3_INDEX_BUFFER_SIZE 0x13 120 #define PACKET3_DISPATCH_DIRECT 0x15 121 #define PACKET3_DISPATCH_INDIRECT 0x16 122 #define PACKET3_ATOMIC_GDS 0x1D 123 #define PACKET3_ATOMIC_MEM 0x1E 124 #define PACKET3_OCCLUSION_QUERY 0x1F 125 #define PACKET3_SET_PREDICATION 0x20 126 #define PACKET3_REG_RMW 0x21 127 #define PACKET3_COND_EXEC 0x22 128 #define PACKET3_PRED_EXEC 0x23 129 #define PACKET3_DRAW_INDIRECT 0x24 130 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 131 #define PACKET3_INDEX_BASE 0x26 132 #define PACKET3_DRAW_INDEX_2 0x27 133 #define PACKET3_CONTEXT_CONTROL 0x28 134 #define PACKET3_INDEX_TYPE 0x2A 135 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 136 #define PACKET3_DRAW_INDEX_AUTO 0x2D 137 #define PACKET3_NUM_INSTANCES 0x2F 138 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 139 #define PACKET3_INDIRECT_BUFFER_CONST 0x33 140 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 141 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 142 #define PACKET3_DRAW_PREAMBLE 0x36 143 #define PACKET3_WRITE_DATA 0x37 144 #define WRITE_DATA_DST_SEL(x) ((x) << 8) 145 /* 0 - register 146 * 1 - memory (sync - via GRBM) 147 * 2 - gl2 148 * 3 - gds 149 * 4 - reserved 150 * 5 - memory (async - direct) 151 */ 152 #define WR_ONE_ADDR (1 << 16) 153 #define WR_CONFIRM (1 << 20) 154 #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) 155 /* 0 - LRU 156 * 1 - Stream 157 */ 158 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 159 /* 0 - me 160 * 1 - pfp 161 * 2 - ce 162 */ 163 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 164 #define PACKET3_MEM_SEMAPHORE 0x39 165 # define PACKET3_SEM_USE_MAILBOX (0x1 << 16) 166 # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ 167 # define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */ 168 # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 169 # define PACKET3_SEM_SEL_WAIT (0x7 << 29) 170 #define PACKET3_WAIT_REG_MEM 0x3C 171 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 172 /* 0 - always 173 * 1 - < 174 * 2 - <= 175 * 3 - == 176 * 4 - != 177 * 5 - >= 178 * 6 - > 179 */ 180 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 181 /* 0 - reg 182 * 1 - mem 183 */ 184 #define WAIT_REG_MEM_OPERATION(x) ((x) << 6) 185 /* 0 - wait_reg_mem 186 * 1 - wr_wait_wr_reg 187 */ 188 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 189 /* 0 - me 190 * 1 - pfp 191 */ 192 #define PACKET3_INDIRECT_BUFFER 0x3F 193 #define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22) 194 #define INDIRECT_BUFFER_VALID (1 << 23) 195 #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) 196 /* 0 - LRU 197 * 1 - Stream 198 * 2 - Bypass 199 */ 200 #define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21) 201 #define PACKET3_COPY_DATA 0x40 202 #define PACKET3_PFP_SYNC_ME 0x42 203 #define PACKET3_SURFACE_SYNC 0x43 204 # define PACKET3_DEST_BASE_0_ENA (1 << 0) 205 # define PACKET3_DEST_BASE_1_ENA (1 << 1) 206 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 207 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 208 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 209 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 210 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 211 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 212 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 213 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 214 # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 215 # define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15) 216 # define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */ 217 # define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */ 218 # define PACKET3_DEST_BASE_2_ENA (1 << 19) 219 # define PACKET3_DEST_BASE_3_ENA (1 << 21) 220 # define PACKET3_TCL1_ACTION_ENA (1 << 22) 221 # define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */ 222 # define PACKET3_CB_ACTION_ENA (1 << 25) 223 # define PACKET3_DB_ACTION_ENA (1 << 26) 224 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 225 # define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28) 226 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 227 #define PACKET3_COND_WRITE 0x45 228 #define PACKET3_EVENT_WRITE 0x46 229 #define EVENT_TYPE(x) ((x) << 0) 230 #define EVENT_INDEX(x) ((x) << 8) 231 /* 0 - any non-TS event 232 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* 233 * 2 - SAMPLE_PIPELINESTAT 234 * 3 - SAMPLE_STREAMOUTSTAT* 235 * 4 - *S_PARTIAL_FLUSH 236 * 5 - EOP events 237 * 6 - EOS events 238 */ 239 #define PACKET3_EVENT_WRITE_EOP 0x47 240 #define EOP_TCL1_VOL_ACTION_EN (1 << 12) 241 #define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */ 242 #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */ 243 #define EOP_TCL1_ACTION_EN (1 << 16) 244 #define EOP_TC_ACTION_EN (1 << 17) /* L2 */ 245 #define EOP_TCL2_VOLATILE (1 << 24) 246 #define EOP_CACHE_POLICY(x) ((x) << 25) 247 /* 0 - LRU 248 * 1 - Stream 249 * 2 - Bypass 250 */ 251 #define DATA_SEL(x) ((x) << 29) 252 /* 0 - discard 253 * 1 - send low 32bit data 254 * 2 - send 64bit data 255 * 3 - send 64bit GPU counter value 256 * 4 - send 64bit sys counter value 257 */ 258 #define INT_SEL(x) ((x) << 24) 259 /* 0 - none 260 * 1 - interrupt only (DATA_SEL = 0) 261 * 2 - interrupt when data write is confirmed 262 */ 263 #define DST_SEL(x) ((x) << 16) 264 /* 0 - MC 265 * 1 - TC/L2 266 */ 267 #define PACKET3_EVENT_WRITE_EOS 0x48 268 #define PACKET3_RELEASE_MEM 0x49 269 #define PACKET3_PREAMBLE_CNTL 0x4A 270 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 271 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 272 #define PACKET3_DMA_DATA 0x50 273 /* 1. header 274 * 2. CONTROL 275 * 3. SRC_ADDR_LO or DATA [31:0] 276 * 4. SRC_ADDR_HI [31:0] 277 * 5. DST_ADDR_LO [31:0] 278 * 6. DST_ADDR_HI [7:0] 279 * 7. COMMAND [30:21] | BYTE_COUNT [20:0] 280 */ 281 /* CONTROL */ 282 # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) 283 /* 0 - ME 284 * 1 - PFP 285 */ 286 # define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) 287 /* 0 - LRU 288 * 1 - Stream 289 * 2 - Bypass 290 */ 291 # define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15) 292 # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) 293 /* 0 - DST_ADDR using DAS 294 * 1 - GDS 295 * 3 - DST_ADDR using L2 296 */ 297 # define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) 298 /* 0 - LRU 299 * 1 - Stream 300 * 2 - Bypass 301 */ 302 # define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27) 303 # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) 304 /* 0 - SRC_ADDR using SAS 305 * 1 - GDS 306 * 2 - DATA 307 * 3 - SRC_ADDR using L2 308 */ 309 # define PACKET3_DMA_DATA_CP_SYNC (1 << 31) 310 /* COMMAND */ 311 # define PACKET3_DMA_DATA_DIS_WC (1 << 21) 312 # define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22) 313 /* 0 - none 314 * 1 - 8 in 16 315 * 2 - 8 in 32 316 * 3 - 8 in 64 317 */ 318 # define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24) 319 /* 0 - none 320 * 1 - 8 in 16 321 * 2 - 8 in 32 322 * 3 - 8 in 64 323 */ 324 # define PACKET3_DMA_DATA_CMD_SAS (1 << 26) 325 /* 0 - memory 326 * 1 - register 327 */ 328 # define PACKET3_DMA_DATA_CMD_DAS (1 << 27) 329 /* 0 - memory 330 * 1 - register 331 */ 332 # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) 333 # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) 334 # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) 335 #define PACKET3_AQUIRE_MEM 0x58 336 #define PACKET3_REWIND 0x59 337 #define PACKET3_LOAD_UCONFIG_REG 0x5E 338 #define PACKET3_LOAD_SH_REG 0x5F 339 #define PACKET3_LOAD_CONFIG_REG 0x60 340 #define PACKET3_LOAD_CONTEXT_REG 0x61 341 #define PACKET3_SET_CONFIG_REG 0x68 342 #define PACKET3_SET_CONFIG_REG_START 0x00002000 343 #define PACKET3_SET_CONFIG_REG_END 0x00002c00 344 #define PACKET3_SET_CONTEXT_REG 0x69 345 #define PACKET3_SET_CONTEXT_REG_START 0x0000a000 346 #define PACKET3_SET_CONTEXT_REG_END 0x0000a400 347 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 348 #define PACKET3_SET_SH_REG 0x76 349 #define PACKET3_SET_SH_REG_START 0x00002c00 350 #define PACKET3_SET_SH_REG_END 0x00003000 351 #define PACKET3_SET_SH_REG_OFFSET 0x77 352 #define PACKET3_SET_QUEUE_REG 0x78 353 #define PACKET3_SET_UCONFIG_REG 0x79 354 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 355 #define PACKET3_SET_UCONFIG_REG_END 0x0000c400 356 #define PACKET3_SCRATCH_RAM_WRITE 0x7D 357 #define PACKET3_SCRATCH_RAM_READ 0x7E 358 #define PACKET3_LOAD_CONST_RAM 0x80 359 #define PACKET3_WRITE_CONST_RAM 0x81 360 #define PACKET3_DUMP_CONST_RAM 0x83 361 #define PACKET3_INCREMENT_CE_COUNTER 0x84 362 #define PACKET3_INCREMENT_DE_COUNTER 0x85 363 #define PACKET3_WAIT_ON_CE_COUNTER 0x86 364 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 365 #define PACKET3_SWITCH_BUFFER 0x8B 366 #define PACKET3_FRAME_CONTROL 0x90 367 # define FRAME_CMD(x) ((x) << 28) 368 /* 369 * x=0: tmz_begin 370 * x=1: tmz_end 371 */ 372 #define PACKET3_SET_RESOURCES 0xA0 373 /* 1. header 374 * 2. CONTROL 375 * 3. QUEUE_MASK_LO [31:0] 376 * 4. QUEUE_MASK_HI [31:0] 377 * 5. GWS_MASK_LO [31:0] 378 * 6. GWS_MASK_HI [31:0] 379 * 7. OAC_MASK [15:0] 380 * 8. GDS_HEAP_SIZE [16:11] | GDS_HEAP_BASE [5:0] 381 */ 382 # define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0) 383 # define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16) 384 # define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) ((x) << 29) 385 #define PACKET3_MAP_QUEUES 0xA2 386 /* 1. header 387 * 2. CONTROL 388 * 3. CONTROL2 389 * 4. MQD_ADDR_LO [31:0] 390 * 5. MQD_ADDR_HI [31:0] 391 * 6. WPTR_ADDR_LO [31:0] 392 * 7. WPTR_ADDR_HI [31:0] 393 */ 394 /* CONTROL */ 395 # define PACKET3_MAP_QUEUES_QUEUE_SEL(x) ((x) << 4) 396 # define PACKET3_MAP_QUEUES_VMID(x) ((x) << 8) 397 # define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) ((x) << 21) 398 # define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x) ((x) << 24) 399 # define PACKET3_MAP_QUEUES_ENGINE_SEL(x) ((x) << 26) 400 # define PACKET3_MAP_QUEUES_NUM_QUEUES(x) ((x) << 29) 401 /* CONTROL2 */ 402 # define PACKET3_MAP_QUEUES_CHECK_DISABLE(x) ((x) << 1) 403 # define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2) 404 # define PACKET3_MAP_QUEUES_QUEUE(x) ((x) << 26) 405 # define PACKET3_MAP_QUEUES_PIPE(x) ((x) << 29) 406 # define PACKET3_MAP_QUEUES_ME(x) ((x) << 31) 407 #define PACKET3_UNMAP_QUEUES 0xA3 408 /* 1. header 409 * 2. CONTROL 410 * 3. CONTROL2 411 * 4. CONTROL3 412 * 5. CONTROL4 413 * 6. CONTROL5 414 */ 415 /* CONTROL */ 416 # define PACKET3_UNMAP_QUEUES_ACTION(x) ((x) << 0) 417 /* 0 - PREEMPT_QUEUES 418 * 1 - RESET_QUEUES 419 * 2 - DISABLE_PROCESS_QUEUES 420 * 3 - PREEMPT_QUEUES_NO_UNMAP 421 */ 422 # define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x) ((x) << 4) 423 # define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x) ((x) << 26) 424 # define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x) ((x) << 29) 425 /* CONTROL2a */ 426 # define PACKET3_UNMAP_QUEUES_PASID(x) ((x) << 0) 427 /* CONTROL2b */ 428 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2) 429 /* CONTROL3a */ 430 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2) 431 /* CONTROL3b */ 432 # define PACKET3_UNMAP_QUEUES_RB_WPTR(x) ((x) << 0) 433 /* CONTROL4 */ 434 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2) 435 /* CONTROL5 */ 436 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2) 437 #define PACKET3_QUERY_STATUS 0xA4 438 /* 1. header 439 * 2. CONTROL 440 * 3. CONTROL2 441 * 4. ADDR_LO [31:0] 442 * 5. ADDR_HI [31:0] 443 * 6. DATA_LO [31:0] 444 * 7. DATA_HI [31:0] 445 */ 446 /* CONTROL */ 447 # define PACKET3_QUERY_STATUS_CONTEXT_ID(x) ((x) << 0) 448 # define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x) ((x) << 28) 449 # define PACKET3_QUERY_STATUS_COMMAND(x) ((x) << 30) 450 /* CONTROL2a */ 451 # define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0) 452 /* CONTROL2b */ 453 # define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2) 454 # define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 25) 455 456 457 #define VCE_CMD_NO_OP 0x00000000 458 #define VCE_CMD_END 0x00000001 459 #define VCE_CMD_IB 0x00000002 460 #define VCE_CMD_FENCE 0x00000003 461 #define VCE_CMD_TRAP 0x00000004 462 #define VCE_CMD_IB_AUTO 0x00000005 463 #define VCE_CMD_SEMAPHORE 0x00000006 464 465 #define VCE_CMD_IB_VM 0x00000102 466 #define VCE_CMD_WAIT_GE 0x00000106 467 #define VCE_CMD_UPDATE_PTB 0x00000107 468 #define VCE_CMD_FLUSH_TLB 0x00000108 469 470 /* HEVC ENC */ 471 #define HEVC_ENC_CMD_NO_OP 0x00000000 472 #define HEVC_ENC_CMD_END 0x00000001 473 #define HEVC_ENC_CMD_FENCE 0x00000003 474 #define HEVC_ENC_CMD_TRAP 0x00000004 475 #define HEVC_ENC_CMD_IB_VM 0x00000102 476 #define HEVC_ENC_CMD_WAIT_GE 0x00000106 477 #define HEVC_ENC_CMD_UPDATE_PTB 0x00000107 478 #define HEVC_ENC_CMD_FLUSH_TLB 0x00000108 479 480 /* mmPA_SC_RASTER_CONFIG mask */ 481 #define RB_MAP_PKR0(x) ((x) << 0) 482 #define RB_MAP_PKR0_MASK (0x3 << 0) 483 #define RB_MAP_PKR1(x) ((x) << 2) 484 #define RB_MAP_PKR1_MASK (0x3 << 2) 485 #define RB_XSEL2(x) ((x) << 4) 486 #define RB_XSEL2_MASK (0x3 << 4) 487 #define RB_XSEL (1 << 6) 488 #define RB_YSEL (1 << 7) 489 #define PKR_MAP(x) ((x) << 8) 490 #define PKR_MAP_MASK (0x3 << 8) 491 #define PKR_XSEL(x) ((x) << 10) 492 #define PKR_XSEL_MASK (0x3 << 10) 493 #define PKR_YSEL(x) ((x) << 12) 494 #define PKR_YSEL_MASK (0x3 << 12) 495 #define SC_MAP(x) ((x) << 16) 496 #define SC_MAP_MASK (0x3 << 16) 497 #define SC_XSEL(x) ((x) << 18) 498 #define SC_XSEL_MASK (0x3 << 18) 499 #define SC_YSEL(x) ((x) << 20) 500 #define SC_YSEL_MASK (0x3 << 20) 501 #define SE_MAP(x) ((x) << 24) 502 #define SE_MAP_MASK (0x3 << 24) 503 #define SE_XSEL(x) ((x) << 26) 504 #define SE_XSEL_MASK (0x3 << 26) 505 #define SE_YSEL(x) ((x) << 28) 506 #define SE_YSEL_MASK (0x3 << 28) 507 508 /* mmPA_SC_RASTER_CONFIG_1 mask */ 509 #define SE_PAIR_MAP(x) ((x) << 0) 510 #define SE_PAIR_MAP_MASK (0x3 << 0) 511 #define SE_PAIR_XSEL(x) ((x) << 2) 512 #define SE_PAIR_XSEL_MASK (0x3 << 2) 513 #define SE_PAIR_YSEL(x) ((x) << 4) 514 #define SE_PAIR_YSEL_MASK (0x3 << 4) 515 516 #endif 517