1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __VI_H__ 25 #define __VI_H__ 26 27 void vi_srbm_select(struct amdgpu_device *adev, 28 u32 me, u32 pipe, u32 queue, u32 vmid); 29 int vi_set_ip_blocks(struct amdgpu_device *adev); 30 31 struct amdgpu_ce_ib_state 32 { 33 uint32_t ce_ib_completion_status; 34 uint32_t ce_constegnine_count; 35 uint32_t ce_ibOffset_ib1; 36 uint32_t ce_ibOffset_ib2; 37 }; /* Total of 4 DWORD */ 38 39 struct amdgpu_de_ib_state 40 { 41 uint32_t ib_completion_status; 42 uint32_t de_constEngine_count; 43 uint32_t ib_offset_ib1; 44 uint32_t ib_offset_ib2; 45 uint32_t preamble_begin_ib1; 46 uint32_t preamble_begin_ib2; 47 uint32_t preamble_end_ib1; 48 uint32_t preamble_end_ib2; 49 uint32_t draw_indirect_baseLo; 50 uint32_t draw_indirect_baseHi; 51 uint32_t disp_indirect_baseLo; 52 uint32_t disp_indirect_baseHi; 53 uint32_t gds_backup_addrlo; 54 uint32_t gds_backup_addrhi; 55 uint32_t index_base_addrlo; 56 uint32_t index_base_addrhi; 57 uint32_t sample_cntl; 58 }; /* Total of 17 DWORD */ 59 60 struct amdgpu_ce_ib_state_chained_ib 61 { 62 /* section of non chained ib part */ 63 uint32_t ce_ib_completion_status; 64 uint32_t ce_constegnine_count; 65 uint32_t ce_ibOffset_ib1; 66 uint32_t ce_ibOffset_ib2; 67 68 /* section of chained ib */ 69 uint32_t ce_chainib_addrlo_ib1; 70 uint32_t ce_chainib_addrlo_ib2; 71 uint32_t ce_chainib_addrhi_ib1; 72 uint32_t ce_chainib_addrhi_ib2; 73 uint32_t ce_chainib_size_ib1; 74 uint32_t ce_chainib_size_ib2; 75 }; /* total 10 DWORD */ 76 77 struct amdgpu_de_ib_state_chained_ib 78 { 79 /* section of non chained ib part */ 80 uint32_t ib_completion_status; 81 uint32_t de_constEngine_count; 82 uint32_t ib_offset_ib1; 83 uint32_t ib_offset_ib2; 84 85 /* section of chained ib */ 86 uint32_t chain_ib_addrlo_ib1; 87 uint32_t chain_ib_addrlo_ib2; 88 uint32_t chain_ib_addrhi_ib1; 89 uint32_t chain_ib_addrhi_ib2; 90 uint32_t chain_ib_size_ib1; 91 uint32_t chain_ib_size_ib2; 92 93 /* section of non chained ib part */ 94 uint32_t preamble_begin_ib1; 95 uint32_t preamble_begin_ib2; 96 uint32_t preamble_end_ib1; 97 uint32_t preamble_end_ib2; 98 99 /* section of chained ib */ 100 uint32_t chain_ib_pream_addrlo_ib1; 101 uint32_t chain_ib_pream_addrlo_ib2; 102 uint32_t chain_ib_pream_addrhi_ib1; 103 uint32_t chain_ib_pream_addrhi_ib2; 104 105 /* section of non chained ib part */ 106 uint32_t draw_indirect_baseLo; 107 uint32_t draw_indirect_baseHi; 108 uint32_t disp_indirect_baseLo; 109 uint32_t disp_indirect_baseHi; 110 uint32_t gds_backup_addrlo; 111 uint32_t gds_backup_addrhi; 112 uint32_t index_base_addrlo; 113 uint32_t index_base_addrhi; 114 uint32_t sample_cntl; 115 }; /* Total of 27 DWORD */ 116 117 struct amdgpu_gfx_meta_data 118 { 119 /* 4 DWORD, address must be 4KB aligned */ 120 struct amdgpu_ce_ib_state ce_payload; 121 uint32_t reserved1[60]; 122 /* 17 DWORD, address must be 64B aligned */ 123 struct amdgpu_de_ib_state de_payload; 124 /* PFP IB base address which get pre-empted */ 125 uint32_t DeIbBaseAddrLo; 126 uint32_t DeIbBaseAddrHi; 127 uint32_t reserved2[941]; 128 }; /* Total of 4K Bytes */ 129 130 struct amdgpu_gfx_meta_data_chained_ib 131 { 132 /* 10 DWORD, address must be 4KB aligned */ 133 struct amdgpu_ce_ib_state_chained_ib ce_payload; 134 uint32_t reserved1[54]; 135 /* 27 DWORD, address must be 64B aligned */ 136 struct amdgpu_de_ib_state_chained_ib de_payload; 137 /* PFP IB base address which get pre-empted */ 138 uint32_t DeIbBaseAddrLo; 139 uint32_t DeIbBaseAddrHi; 140 uint32_t reserved2[931]; 141 }; /* Total of 4K Bytes */ 142 143 #endif 144