1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 #include <linux/slab.h> 26 27 #include <drm/amdgpu_drm.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_atombios.h" 31 #include "amdgpu_ih.h" 32 #include "amdgpu_uvd.h" 33 #include "amdgpu_vce.h" 34 #include "amdgpu_ucode.h" 35 #include "atom.h" 36 #include "amd_pcie.h" 37 38 #include "gmc/gmc_8_1_d.h" 39 #include "gmc/gmc_8_1_sh_mask.h" 40 41 #include "oss/oss_3_0_d.h" 42 #include "oss/oss_3_0_sh_mask.h" 43 44 #include "bif/bif_5_0_d.h" 45 #include "bif/bif_5_0_sh_mask.h" 46 47 #include "gca/gfx_8_0_d.h" 48 #include "gca/gfx_8_0_sh_mask.h" 49 50 #include "smu/smu_7_1_1_d.h" 51 #include "smu/smu_7_1_1_sh_mask.h" 52 53 #include "uvd/uvd_5_0_d.h" 54 #include "uvd/uvd_5_0_sh_mask.h" 55 56 #include "vce/vce_3_0_d.h" 57 #include "vce/vce_3_0_sh_mask.h" 58 59 #include "dce/dce_10_0_d.h" 60 #include "dce/dce_10_0_sh_mask.h" 61 62 #include "vid.h" 63 #include "vi.h" 64 #include "gmc_v8_0.h" 65 #include "gmc_v7_0.h" 66 #include "gfx_v8_0.h" 67 #include "sdma_v2_4.h" 68 #include "sdma_v3_0.h" 69 #include "dce_v10_0.h" 70 #include "dce_v11_0.h" 71 #include "iceland_ih.h" 72 #include "tonga_ih.h" 73 #include "cz_ih.h" 74 #include "uvd_v5_0.h" 75 #include "uvd_v6_0.h" 76 #include "vce_v3_0.h" 77 #if defined(CONFIG_DRM_AMD_ACP) 78 #include "amdgpu_acp.h" 79 #endif 80 #include "amdgpu_vkms.h" 81 #include "mxgpu_vi.h" 82 #include "amdgpu_dm.h" 83 84 #define ixPCIE_LC_L1_PM_SUBSTATE 0x100100C6 85 #define PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L 86 #define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L 87 #define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK 0x00000004L 88 #define PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 0x00000008L 89 #define PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 0x00000010L 90 #define ixPCIE_L1_PM_SUB_CNTL 0x378 91 #define PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L 92 #define PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L 93 #define PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L 94 #define PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L 95 #define PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK 0x00200000L 96 #define LINK_CAP 0x64 97 #define PCIE_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L 98 #define ixCPM_CONTROL 0x1400118 99 #define ixPCIE_LC_CNTL7 0x100100BC 100 #define PCIE_LC_CNTL7__LC_L1_SIDEBAND_CLKREQ_PDWN_EN_MASK 0x00000400L 101 #define PCIE_LC_CNTL__LC_L0S_INACTIVITY_DEFAULT 0x00000007 102 #define PCIE_LC_CNTL__LC_L1_INACTIVITY_DEFAULT 0x00000009 103 #define CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE_MASK 0x01000000L 104 #define PCIE_L1_PM_SUB_CNTL 0x378 105 #define ASIC_IS_P22(asic_type, rid) ((asic_type >= CHIP_POLARIS10) && \ 106 (asic_type <= CHIP_POLARIS12) && \ 107 (rid >= 0x6E)) 108 /* Topaz */ 109 static const struct amdgpu_video_codecs topaz_video_codecs_encode = 110 { 111 .codec_count = 0, 112 .codec_array = NULL, 113 }; 114 115 /* Tonga, CZ, ST, Fiji */ 116 static const struct amdgpu_video_codec_info tonga_video_codecs_encode_array[] = 117 { 118 { 119 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 120 .max_width = 4096, 121 .max_height = 2304, 122 .max_pixels_per_frame = 4096 * 2304, 123 .max_level = 0, 124 }, 125 }; 126 127 static const struct amdgpu_video_codecs tonga_video_codecs_encode = 128 { 129 .codec_count = ARRAY_SIZE(tonga_video_codecs_encode_array), 130 .codec_array = tonga_video_codecs_encode_array, 131 }; 132 133 /* Polaris */ 134 static const struct amdgpu_video_codec_info polaris_video_codecs_encode_array[] = 135 { 136 { 137 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 138 .max_width = 4096, 139 .max_height = 2304, 140 .max_pixels_per_frame = 4096 * 2304, 141 .max_level = 0, 142 }, 143 { 144 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 145 .max_width = 4096, 146 .max_height = 2304, 147 .max_pixels_per_frame = 4096 * 2304, 148 .max_level = 0, 149 }, 150 }; 151 152 static const struct amdgpu_video_codecs polaris_video_codecs_encode = 153 { 154 .codec_count = ARRAY_SIZE(polaris_video_codecs_encode_array), 155 .codec_array = polaris_video_codecs_encode_array, 156 }; 157 158 /* Topaz */ 159 static const struct amdgpu_video_codecs topaz_video_codecs_decode = 160 { 161 .codec_count = 0, 162 .codec_array = NULL, 163 }; 164 165 /* Tonga */ 166 static const struct amdgpu_video_codec_info tonga_video_codecs_decode_array[] = 167 { 168 { 169 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 170 .max_width = 4096, 171 .max_height = 4096, 172 .max_pixels_per_frame = 4096 * 4096, 173 .max_level = 3, 174 }, 175 { 176 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 177 .max_width = 4096, 178 .max_height = 4096, 179 .max_pixels_per_frame = 4096 * 4096, 180 .max_level = 5, 181 }, 182 { 183 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 184 .max_width = 4096, 185 .max_height = 4096, 186 .max_pixels_per_frame = 4096 * 4096, 187 .max_level = 52, 188 }, 189 { 190 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 191 .max_width = 4096, 192 .max_height = 4096, 193 .max_pixels_per_frame = 4096 * 4096, 194 .max_level = 4, 195 }, 196 }; 197 198 static const struct amdgpu_video_codecs tonga_video_codecs_decode = 199 { 200 .codec_count = ARRAY_SIZE(tonga_video_codecs_decode_array), 201 .codec_array = tonga_video_codecs_decode_array, 202 }; 203 204 /* CZ, ST, Fiji, Polaris */ 205 static const struct amdgpu_video_codec_info cz_video_codecs_decode_array[] = 206 { 207 { 208 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 209 .max_width = 4096, 210 .max_height = 4096, 211 .max_pixels_per_frame = 4096 * 4096, 212 .max_level = 3, 213 }, 214 { 215 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 216 .max_width = 4096, 217 .max_height = 4096, 218 .max_pixels_per_frame = 4096 * 4096, 219 .max_level = 5, 220 }, 221 { 222 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 223 .max_width = 4096, 224 .max_height = 4096, 225 .max_pixels_per_frame = 4096 * 4096, 226 .max_level = 52, 227 }, 228 { 229 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 230 .max_width = 4096, 231 .max_height = 4096, 232 .max_pixels_per_frame = 4096 * 4096, 233 .max_level = 4, 234 }, 235 { 236 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 237 .max_width = 4096, 238 .max_height = 4096, 239 .max_pixels_per_frame = 4096 * 4096, 240 .max_level = 186, 241 }, 242 { 243 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 244 .max_width = 4096, 245 .max_height = 4096, 246 .max_pixels_per_frame = 4096 * 4096, 247 .max_level = 0, 248 }, 249 }; 250 251 static const struct amdgpu_video_codecs cz_video_codecs_decode = 252 { 253 .codec_count = ARRAY_SIZE(cz_video_codecs_decode_array), 254 .codec_array = cz_video_codecs_decode_array, 255 }; 256 257 static int vi_query_video_codecs(struct amdgpu_device *adev, bool encode, 258 const struct amdgpu_video_codecs **codecs) 259 { 260 switch (adev->asic_type) { 261 case CHIP_TOPAZ: 262 if (encode) 263 *codecs = &topaz_video_codecs_encode; 264 else 265 *codecs = &topaz_video_codecs_decode; 266 return 0; 267 case CHIP_TONGA: 268 if (encode) 269 *codecs = &tonga_video_codecs_encode; 270 else 271 *codecs = &tonga_video_codecs_decode; 272 return 0; 273 case CHIP_POLARIS10: 274 case CHIP_POLARIS11: 275 case CHIP_POLARIS12: 276 case CHIP_VEGAM: 277 if (encode) 278 *codecs = &polaris_video_codecs_encode; 279 else 280 *codecs = &cz_video_codecs_decode; 281 return 0; 282 case CHIP_FIJI: 283 case CHIP_CARRIZO: 284 case CHIP_STONEY: 285 if (encode) 286 *codecs = &tonga_video_codecs_encode; 287 else 288 *codecs = &cz_video_codecs_decode; 289 return 0; 290 default: 291 return -EINVAL; 292 } 293 } 294 295 /* 296 * Indirect registers accessor 297 */ 298 static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg) 299 { 300 unsigned long flags; 301 u32 r; 302 303 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 304 WREG32_NO_KIQ(mmPCIE_INDEX, reg); 305 (void)RREG32_NO_KIQ(mmPCIE_INDEX); 306 r = RREG32_NO_KIQ(mmPCIE_DATA); 307 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 308 return r; 309 } 310 311 static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 312 { 313 unsigned long flags; 314 315 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 316 WREG32_NO_KIQ(mmPCIE_INDEX, reg); 317 (void)RREG32_NO_KIQ(mmPCIE_INDEX); 318 WREG32_NO_KIQ(mmPCIE_DATA, v); 319 (void)RREG32_NO_KIQ(mmPCIE_DATA); 320 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 321 } 322 323 static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg) 324 { 325 unsigned long flags; 326 u32 r; 327 328 spin_lock_irqsave(&adev->smc_idx_lock, flags); 329 WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg)); 330 r = RREG32_NO_KIQ(mmSMC_IND_DATA_11); 331 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 332 return r; 333 } 334 335 static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 336 { 337 unsigned long flags; 338 339 spin_lock_irqsave(&adev->smc_idx_lock, flags); 340 WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg)); 341 WREG32_NO_KIQ(mmSMC_IND_DATA_11, (v)); 342 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 343 } 344 345 /* smu_8_0_d.h */ 346 #define mmMP0PUB_IND_INDEX 0x180 347 #define mmMP0PUB_IND_DATA 0x181 348 349 static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg) 350 { 351 unsigned long flags; 352 u32 r; 353 354 spin_lock_irqsave(&adev->smc_idx_lock, flags); 355 WREG32(mmMP0PUB_IND_INDEX, (reg)); 356 r = RREG32(mmMP0PUB_IND_DATA); 357 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 358 return r; 359 } 360 361 static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 362 { 363 unsigned long flags; 364 365 spin_lock_irqsave(&adev->smc_idx_lock, flags); 366 WREG32(mmMP0PUB_IND_INDEX, (reg)); 367 WREG32(mmMP0PUB_IND_DATA, (v)); 368 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 369 } 370 371 static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) 372 { 373 unsigned long flags; 374 u32 r; 375 376 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 377 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); 378 r = RREG32(mmUVD_CTX_DATA); 379 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 380 return r; 381 } 382 383 static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 384 { 385 unsigned long flags; 386 387 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 388 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); 389 WREG32(mmUVD_CTX_DATA, (v)); 390 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 391 } 392 393 static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg) 394 { 395 unsigned long flags; 396 u32 r; 397 398 spin_lock_irqsave(&adev->didt_idx_lock, flags); 399 WREG32(mmDIDT_IND_INDEX, (reg)); 400 r = RREG32(mmDIDT_IND_DATA); 401 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 402 return r; 403 } 404 405 static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 406 { 407 unsigned long flags; 408 409 spin_lock_irqsave(&adev->didt_idx_lock, flags); 410 WREG32(mmDIDT_IND_INDEX, (reg)); 411 WREG32(mmDIDT_IND_DATA, (v)); 412 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 413 } 414 415 static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) 416 { 417 unsigned long flags; 418 u32 r; 419 420 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 421 WREG32(mmGC_CAC_IND_INDEX, (reg)); 422 r = RREG32(mmGC_CAC_IND_DATA); 423 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 424 return r; 425 } 426 427 static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 428 { 429 unsigned long flags; 430 431 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 432 WREG32(mmGC_CAC_IND_INDEX, (reg)); 433 WREG32(mmGC_CAC_IND_DATA, (v)); 434 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 435 } 436 437 438 static const u32 tonga_mgcg_cgcg_init[] = 439 { 440 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100, 441 mmPCIE_INDEX, 0xffffffff, 0x0140001c, 442 mmPCIE_DATA, 0x000f0000, 0x00000000, 443 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C, 444 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100, 445 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 446 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 447 }; 448 449 static const u32 fiji_mgcg_cgcg_init[] = 450 { 451 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100, 452 mmPCIE_INDEX, 0xffffffff, 0x0140001c, 453 mmPCIE_DATA, 0x000f0000, 0x00000000, 454 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C, 455 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100, 456 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 457 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 458 }; 459 460 static const u32 iceland_mgcg_cgcg_init[] = 461 { 462 mmPCIE_INDEX, 0xffffffff, ixPCIE_CNTL2, 463 mmPCIE_DATA, 0x000f0000, 0x00000000, 464 mmSMC_IND_INDEX_4, 0xffffffff, ixCGTT_ROM_CLK_CTRL0, 465 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100, 466 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 467 }; 468 469 static const u32 cz_mgcg_cgcg_init[] = 470 { 471 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100, 472 mmPCIE_INDEX, 0xffffffff, 0x0140001c, 473 mmPCIE_DATA, 0x000f0000, 0x00000000, 474 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 475 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 476 }; 477 478 static const u32 stoney_mgcg_cgcg_init[] = 479 { 480 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00000100, 481 mmHDP_XDP_CGTT_BLK_CTRL, 0xffffffff, 0x00000104, 482 mmHDP_HOST_PATH_CNTL, 0xffffffff, 0x0f000027, 483 }; 484 485 static void vi_init_golden_registers(struct amdgpu_device *adev) 486 { 487 /* Some of the registers might be dependent on GRBM_GFX_INDEX */ 488 mutex_lock(&adev->grbm_idx_mutex); 489 490 if (amdgpu_sriov_vf(adev)) { 491 xgpu_vi_init_golden_registers(adev); 492 mutex_unlock(&adev->grbm_idx_mutex); 493 return; 494 } 495 496 switch (adev->asic_type) { 497 case CHIP_TOPAZ: 498 amdgpu_device_program_register_sequence(adev, 499 iceland_mgcg_cgcg_init, 500 ARRAY_SIZE(iceland_mgcg_cgcg_init)); 501 break; 502 case CHIP_FIJI: 503 amdgpu_device_program_register_sequence(adev, 504 fiji_mgcg_cgcg_init, 505 ARRAY_SIZE(fiji_mgcg_cgcg_init)); 506 break; 507 case CHIP_TONGA: 508 amdgpu_device_program_register_sequence(adev, 509 tonga_mgcg_cgcg_init, 510 ARRAY_SIZE(tonga_mgcg_cgcg_init)); 511 break; 512 case CHIP_CARRIZO: 513 amdgpu_device_program_register_sequence(adev, 514 cz_mgcg_cgcg_init, 515 ARRAY_SIZE(cz_mgcg_cgcg_init)); 516 break; 517 case CHIP_STONEY: 518 amdgpu_device_program_register_sequence(adev, 519 stoney_mgcg_cgcg_init, 520 ARRAY_SIZE(stoney_mgcg_cgcg_init)); 521 break; 522 case CHIP_POLARIS10: 523 case CHIP_POLARIS11: 524 case CHIP_POLARIS12: 525 case CHIP_VEGAM: 526 default: 527 break; 528 } 529 mutex_unlock(&adev->grbm_idx_mutex); 530 } 531 532 /** 533 * vi_get_xclk - get the xclk 534 * 535 * @adev: amdgpu_device pointer 536 * 537 * Returns the reference clock used by the gfx engine 538 * (VI). 539 */ 540 static u32 vi_get_xclk(struct amdgpu_device *adev) 541 { 542 u32 reference_clock = adev->clock.spll.reference_freq; 543 u32 tmp; 544 545 if (adev->flags & AMD_IS_APU) 546 return reference_clock; 547 548 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2); 549 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK)) 550 return 1000; 551 552 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL); 553 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE)) 554 return reference_clock / 4; 555 556 return reference_clock; 557 } 558 559 /** 560 * vi_srbm_select - select specific register instances 561 * 562 * @adev: amdgpu_device pointer 563 * @me: selected ME (micro engine) 564 * @pipe: pipe 565 * @queue: queue 566 * @vmid: VMID 567 * 568 * Switches the currently active registers instances. Some 569 * registers are instanced per VMID, others are instanced per 570 * me/pipe/queue combination. 571 */ 572 void vi_srbm_select(struct amdgpu_device *adev, 573 u32 me, u32 pipe, u32 queue, u32 vmid) 574 { 575 u32 srbm_gfx_cntl = 0; 576 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe); 577 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me); 578 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid); 579 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, QUEUEID, queue); 580 WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl); 581 } 582 583 static void vi_vga_set_state(struct amdgpu_device *adev, bool state) 584 { 585 /* todo */ 586 } 587 588 static bool vi_read_disabled_bios(struct amdgpu_device *adev) 589 { 590 u32 bus_cntl; 591 u32 d1vga_control = 0; 592 u32 d2vga_control = 0; 593 u32 vga_render_control = 0; 594 u32 rom_cntl; 595 bool r; 596 597 bus_cntl = RREG32(mmBUS_CNTL); 598 if (adev->mode_info.num_crtc) { 599 d1vga_control = RREG32(mmD1VGA_CONTROL); 600 d2vga_control = RREG32(mmD2VGA_CONTROL); 601 vga_render_control = RREG32(mmVGA_RENDER_CONTROL); 602 } 603 rom_cntl = RREG32_SMC(ixROM_CNTL); 604 605 /* enable the rom */ 606 WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK)); 607 if (adev->mode_info.num_crtc) { 608 /* Disable VGA mode */ 609 WREG32(mmD1VGA_CONTROL, 610 (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK | 611 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK))); 612 WREG32(mmD2VGA_CONTROL, 613 (d2vga_control & ~(D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK | 614 D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK))); 615 WREG32(mmVGA_RENDER_CONTROL, 616 (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK)); 617 } 618 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK); 619 620 r = amdgpu_read_bios(adev); 621 622 /* restore regs */ 623 WREG32(mmBUS_CNTL, bus_cntl); 624 if (adev->mode_info.num_crtc) { 625 WREG32(mmD1VGA_CONTROL, d1vga_control); 626 WREG32(mmD2VGA_CONTROL, d2vga_control); 627 WREG32(mmVGA_RENDER_CONTROL, vga_render_control); 628 } 629 WREG32_SMC(ixROM_CNTL, rom_cntl); 630 return r; 631 } 632 633 static bool vi_read_bios_from_rom(struct amdgpu_device *adev, 634 u8 *bios, u32 length_bytes) 635 { 636 u32 *dw_ptr; 637 unsigned long flags; 638 u32 i, length_dw; 639 640 if (bios == NULL) 641 return false; 642 if (length_bytes == 0) 643 return false; 644 /* APU vbios image is part of sbios image */ 645 if (adev->flags & AMD_IS_APU) 646 return false; 647 648 dw_ptr = (u32 *)bios; 649 length_dw = ALIGN(length_bytes, 4) / 4; 650 /* take the smc lock since we are using the smc index */ 651 spin_lock_irqsave(&adev->smc_idx_lock, flags); 652 /* set rom index to 0 */ 653 WREG32(mmSMC_IND_INDEX_11, ixROM_INDEX); 654 WREG32(mmSMC_IND_DATA_11, 0); 655 /* set index to data for continous read */ 656 WREG32(mmSMC_IND_INDEX_11, ixROM_DATA); 657 for (i = 0; i < length_dw; i++) 658 dw_ptr[i] = RREG32(mmSMC_IND_DATA_11); 659 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 660 661 return true; 662 } 663 664 static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = { 665 {mmGRBM_STATUS}, 666 {mmGRBM_STATUS2}, 667 {mmGRBM_STATUS_SE0}, 668 {mmGRBM_STATUS_SE1}, 669 {mmGRBM_STATUS_SE2}, 670 {mmGRBM_STATUS_SE3}, 671 {mmSRBM_STATUS}, 672 {mmSRBM_STATUS2}, 673 {mmSRBM_STATUS3}, 674 {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET}, 675 {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET}, 676 {mmCP_STAT}, 677 {mmCP_STALLED_STAT1}, 678 {mmCP_STALLED_STAT2}, 679 {mmCP_STALLED_STAT3}, 680 {mmCP_CPF_BUSY_STAT}, 681 {mmCP_CPF_STALLED_STAT1}, 682 {mmCP_CPF_STATUS}, 683 {mmCP_CPC_BUSY_STAT}, 684 {mmCP_CPC_STALLED_STAT1}, 685 {mmCP_CPC_STATUS}, 686 {mmGB_ADDR_CONFIG}, 687 {mmMC_ARB_RAMCFG}, 688 {mmGB_TILE_MODE0}, 689 {mmGB_TILE_MODE1}, 690 {mmGB_TILE_MODE2}, 691 {mmGB_TILE_MODE3}, 692 {mmGB_TILE_MODE4}, 693 {mmGB_TILE_MODE5}, 694 {mmGB_TILE_MODE6}, 695 {mmGB_TILE_MODE7}, 696 {mmGB_TILE_MODE8}, 697 {mmGB_TILE_MODE9}, 698 {mmGB_TILE_MODE10}, 699 {mmGB_TILE_MODE11}, 700 {mmGB_TILE_MODE12}, 701 {mmGB_TILE_MODE13}, 702 {mmGB_TILE_MODE14}, 703 {mmGB_TILE_MODE15}, 704 {mmGB_TILE_MODE16}, 705 {mmGB_TILE_MODE17}, 706 {mmGB_TILE_MODE18}, 707 {mmGB_TILE_MODE19}, 708 {mmGB_TILE_MODE20}, 709 {mmGB_TILE_MODE21}, 710 {mmGB_TILE_MODE22}, 711 {mmGB_TILE_MODE23}, 712 {mmGB_TILE_MODE24}, 713 {mmGB_TILE_MODE25}, 714 {mmGB_TILE_MODE26}, 715 {mmGB_TILE_MODE27}, 716 {mmGB_TILE_MODE28}, 717 {mmGB_TILE_MODE29}, 718 {mmGB_TILE_MODE30}, 719 {mmGB_TILE_MODE31}, 720 {mmGB_MACROTILE_MODE0}, 721 {mmGB_MACROTILE_MODE1}, 722 {mmGB_MACROTILE_MODE2}, 723 {mmGB_MACROTILE_MODE3}, 724 {mmGB_MACROTILE_MODE4}, 725 {mmGB_MACROTILE_MODE5}, 726 {mmGB_MACROTILE_MODE6}, 727 {mmGB_MACROTILE_MODE7}, 728 {mmGB_MACROTILE_MODE8}, 729 {mmGB_MACROTILE_MODE9}, 730 {mmGB_MACROTILE_MODE10}, 731 {mmGB_MACROTILE_MODE11}, 732 {mmGB_MACROTILE_MODE12}, 733 {mmGB_MACROTILE_MODE13}, 734 {mmGB_MACROTILE_MODE14}, 735 {mmGB_MACROTILE_MODE15}, 736 {mmCC_RB_BACKEND_DISABLE, true}, 737 {mmGC_USER_RB_BACKEND_DISABLE, true}, 738 {mmGB_BACKEND_MAP, false}, 739 {mmPA_SC_RASTER_CONFIG, true}, 740 {mmPA_SC_RASTER_CONFIG_1, true}, 741 }; 742 743 static uint32_t vi_get_register_value(struct amdgpu_device *adev, 744 bool indexed, u32 se_num, 745 u32 sh_num, u32 reg_offset) 746 { 747 if (indexed) { 748 uint32_t val; 749 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num; 750 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; 751 752 switch (reg_offset) { 753 case mmCC_RB_BACKEND_DISABLE: 754 return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable; 755 case mmGC_USER_RB_BACKEND_DISABLE: 756 return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable; 757 case mmPA_SC_RASTER_CONFIG: 758 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config; 759 case mmPA_SC_RASTER_CONFIG_1: 760 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1; 761 } 762 763 mutex_lock(&adev->grbm_idx_mutex); 764 if (se_num != 0xffffffff || sh_num != 0xffffffff) 765 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 766 767 val = RREG32(reg_offset); 768 769 if (se_num != 0xffffffff || sh_num != 0xffffffff) 770 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 771 mutex_unlock(&adev->grbm_idx_mutex); 772 return val; 773 } else { 774 unsigned idx; 775 776 switch (reg_offset) { 777 case mmGB_ADDR_CONFIG: 778 return adev->gfx.config.gb_addr_config; 779 case mmMC_ARB_RAMCFG: 780 return adev->gfx.config.mc_arb_ramcfg; 781 case mmGB_TILE_MODE0: 782 case mmGB_TILE_MODE1: 783 case mmGB_TILE_MODE2: 784 case mmGB_TILE_MODE3: 785 case mmGB_TILE_MODE4: 786 case mmGB_TILE_MODE5: 787 case mmGB_TILE_MODE6: 788 case mmGB_TILE_MODE7: 789 case mmGB_TILE_MODE8: 790 case mmGB_TILE_MODE9: 791 case mmGB_TILE_MODE10: 792 case mmGB_TILE_MODE11: 793 case mmGB_TILE_MODE12: 794 case mmGB_TILE_MODE13: 795 case mmGB_TILE_MODE14: 796 case mmGB_TILE_MODE15: 797 case mmGB_TILE_MODE16: 798 case mmGB_TILE_MODE17: 799 case mmGB_TILE_MODE18: 800 case mmGB_TILE_MODE19: 801 case mmGB_TILE_MODE20: 802 case mmGB_TILE_MODE21: 803 case mmGB_TILE_MODE22: 804 case mmGB_TILE_MODE23: 805 case mmGB_TILE_MODE24: 806 case mmGB_TILE_MODE25: 807 case mmGB_TILE_MODE26: 808 case mmGB_TILE_MODE27: 809 case mmGB_TILE_MODE28: 810 case mmGB_TILE_MODE29: 811 case mmGB_TILE_MODE30: 812 case mmGB_TILE_MODE31: 813 idx = (reg_offset - mmGB_TILE_MODE0); 814 return adev->gfx.config.tile_mode_array[idx]; 815 case mmGB_MACROTILE_MODE0: 816 case mmGB_MACROTILE_MODE1: 817 case mmGB_MACROTILE_MODE2: 818 case mmGB_MACROTILE_MODE3: 819 case mmGB_MACROTILE_MODE4: 820 case mmGB_MACROTILE_MODE5: 821 case mmGB_MACROTILE_MODE6: 822 case mmGB_MACROTILE_MODE7: 823 case mmGB_MACROTILE_MODE8: 824 case mmGB_MACROTILE_MODE9: 825 case mmGB_MACROTILE_MODE10: 826 case mmGB_MACROTILE_MODE11: 827 case mmGB_MACROTILE_MODE12: 828 case mmGB_MACROTILE_MODE13: 829 case mmGB_MACROTILE_MODE14: 830 case mmGB_MACROTILE_MODE15: 831 idx = (reg_offset - mmGB_MACROTILE_MODE0); 832 return adev->gfx.config.macrotile_mode_array[idx]; 833 default: 834 return RREG32(reg_offset); 835 } 836 } 837 } 838 839 static int vi_read_register(struct amdgpu_device *adev, u32 se_num, 840 u32 sh_num, u32 reg_offset, u32 *value) 841 { 842 uint32_t i; 843 844 *value = 0; 845 for (i = 0; i < ARRAY_SIZE(vi_allowed_read_registers); i++) { 846 bool indexed = vi_allowed_read_registers[i].grbm_indexed; 847 848 if (reg_offset != vi_allowed_read_registers[i].reg_offset) 849 continue; 850 851 *value = vi_get_register_value(adev, indexed, se_num, sh_num, 852 reg_offset); 853 return 0; 854 } 855 return -EINVAL; 856 } 857 858 /** 859 * vi_asic_pci_config_reset - soft reset GPU 860 * 861 * @adev: amdgpu_device pointer 862 * 863 * Use PCI Config method to reset the GPU. 864 * 865 * Returns 0 for success. 866 */ 867 static int vi_asic_pci_config_reset(struct amdgpu_device *adev) 868 { 869 u32 i; 870 int r = -EINVAL; 871 872 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 873 874 /* disable BM */ 875 pci_clear_master(adev->pdev); 876 /* reset */ 877 amdgpu_device_pci_config_reset(adev); 878 879 udelay(100); 880 881 /* wait for asic to come out of reset */ 882 for (i = 0; i < adev->usec_timeout; i++) { 883 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) { 884 /* enable BM */ 885 pci_set_master(adev->pdev); 886 adev->has_hw_reset = true; 887 r = 0; 888 break; 889 } 890 udelay(1); 891 } 892 893 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 894 895 return r; 896 } 897 898 static bool vi_asic_supports_baco(struct amdgpu_device *adev) 899 { 900 switch (adev->asic_type) { 901 case CHIP_FIJI: 902 case CHIP_TONGA: 903 case CHIP_POLARIS10: 904 case CHIP_POLARIS11: 905 case CHIP_POLARIS12: 906 case CHIP_TOPAZ: 907 return amdgpu_dpm_is_baco_supported(adev); 908 default: 909 return false; 910 } 911 } 912 913 static enum amd_reset_method 914 vi_asic_reset_method(struct amdgpu_device *adev) 915 { 916 bool baco_reset; 917 918 if (amdgpu_reset_method == AMD_RESET_METHOD_LEGACY || 919 amdgpu_reset_method == AMD_RESET_METHOD_BACO) 920 return amdgpu_reset_method; 921 922 if (amdgpu_reset_method != -1) 923 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 924 amdgpu_reset_method); 925 926 switch (adev->asic_type) { 927 case CHIP_FIJI: 928 case CHIP_TONGA: 929 case CHIP_POLARIS10: 930 case CHIP_POLARIS11: 931 case CHIP_POLARIS12: 932 case CHIP_TOPAZ: 933 baco_reset = amdgpu_dpm_is_baco_supported(adev); 934 break; 935 default: 936 baco_reset = false; 937 break; 938 } 939 940 if (baco_reset) 941 return AMD_RESET_METHOD_BACO; 942 else 943 return AMD_RESET_METHOD_LEGACY; 944 } 945 946 /** 947 * vi_asic_reset - soft reset GPU 948 * 949 * @adev: amdgpu_device pointer 950 * 951 * Look up which blocks are hung and attempt 952 * to reset them. 953 * Returns 0 for success. 954 */ 955 static int vi_asic_reset(struct amdgpu_device *adev) 956 { 957 int r; 958 959 /* APUs don't have full asic reset */ 960 if (adev->flags & AMD_IS_APU) 961 return 0; 962 963 if (vi_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { 964 dev_info(adev->dev, "BACO reset\n"); 965 r = amdgpu_dpm_baco_reset(adev); 966 } else { 967 dev_info(adev->dev, "PCI CONFIG reset\n"); 968 r = vi_asic_pci_config_reset(adev); 969 } 970 971 return r; 972 } 973 974 static u32 vi_get_config_memsize(struct amdgpu_device *adev) 975 { 976 return RREG32(mmCONFIG_MEMSIZE); 977 } 978 979 static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock, 980 u32 cntl_reg, u32 status_reg) 981 { 982 int r, i; 983 struct atom_clock_dividers dividers; 984 uint32_t tmp; 985 986 r = amdgpu_atombios_get_clock_dividers(adev, 987 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 988 clock, false, ÷rs); 989 if (r) 990 return r; 991 992 tmp = RREG32_SMC(cntl_reg); 993 994 if (adev->flags & AMD_IS_APU) 995 tmp &= ~CG_DCLK_CNTL__DCLK_DIVIDER_MASK; 996 else 997 tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK | 998 CG_DCLK_CNTL__DCLK_DIVIDER_MASK); 999 tmp |= dividers.post_divider; 1000 WREG32_SMC(cntl_reg, tmp); 1001 1002 for (i = 0; i < 100; i++) { 1003 tmp = RREG32_SMC(status_reg); 1004 if (adev->flags & AMD_IS_APU) { 1005 if (tmp & 0x10000) 1006 break; 1007 } else { 1008 if (tmp & CG_DCLK_STATUS__DCLK_STATUS_MASK) 1009 break; 1010 } 1011 mdelay(10); 1012 } 1013 if (i == 100) 1014 return -ETIMEDOUT; 1015 return 0; 1016 } 1017 1018 #define ixGNB_CLK1_DFS_CNTL 0xD82200F0 1019 #define ixGNB_CLK1_STATUS 0xD822010C 1020 #define ixGNB_CLK2_DFS_CNTL 0xD8220110 1021 #define ixGNB_CLK2_STATUS 0xD822012C 1022 #define ixGNB_CLK3_DFS_CNTL 0xD8220130 1023 #define ixGNB_CLK3_STATUS 0xD822014C 1024 1025 static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 1026 { 1027 int r; 1028 1029 if (adev->flags & AMD_IS_APU) { 1030 r = vi_set_uvd_clock(adev, vclk, ixGNB_CLK2_DFS_CNTL, ixGNB_CLK2_STATUS); 1031 if (r) 1032 return r; 1033 1034 r = vi_set_uvd_clock(adev, dclk, ixGNB_CLK1_DFS_CNTL, ixGNB_CLK1_STATUS); 1035 if (r) 1036 return r; 1037 } else { 1038 r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); 1039 if (r) 1040 return r; 1041 1042 r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); 1043 if (r) 1044 return r; 1045 } 1046 1047 return 0; 1048 } 1049 1050 static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 1051 { 1052 int r, i; 1053 struct atom_clock_dividers dividers; 1054 u32 tmp; 1055 u32 reg_ctrl; 1056 u32 reg_status; 1057 u32 status_mask; 1058 u32 reg_mask; 1059 1060 if (adev->flags & AMD_IS_APU) { 1061 reg_ctrl = ixGNB_CLK3_DFS_CNTL; 1062 reg_status = ixGNB_CLK3_STATUS; 1063 status_mask = 0x00010000; 1064 reg_mask = CG_ECLK_CNTL__ECLK_DIVIDER_MASK; 1065 } else { 1066 reg_ctrl = ixCG_ECLK_CNTL; 1067 reg_status = ixCG_ECLK_STATUS; 1068 status_mask = CG_ECLK_STATUS__ECLK_STATUS_MASK; 1069 reg_mask = CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK | CG_ECLK_CNTL__ECLK_DIVIDER_MASK; 1070 } 1071 1072 r = amdgpu_atombios_get_clock_dividers(adev, 1073 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 1074 ecclk, false, ÷rs); 1075 if (r) 1076 return r; 1077 1078 for (i = 0; i < 100; i++) { 1079 if (RREG32_SMC(reg_status) & status_mask) 1080 break; 1081 mdelay(10); 1082 } 1083 1084 if (i == 100) 1085 return -ETIMEDOUT; 1086 1087 tmp = RREG32_SMC(reg_ctrl); 1088 tmp &= ~reg_mask; 1089 tmp |= dividers.post_divider; 1090 WREG32_SMC(reg_ctrl, tmp); 1091 1092 for (i = 0; i < 100; i++) { 1093 if (RREG32_SMC(reg_status) & status_mask) 1094 break; 1095 mdelay(10); 1096 } 1097 1098 if (i == 100) 1099 return -ETIMEDOUT; 1100 1101 return 0; 1102 } 1103 1104 static void vi_pcie_gen3_enable(struct amdgpu_device *adev) 1105 { 1106 if (pci_is_root_bus(adev->pdev->bus)) 1107 return; 1108 1109 if (amdgpu_pcie_gen2 == 0) 1110 return; 1111 1112 if (adev->flags & AMD_IS_APU) 1113 return; 1114 1115 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 1116 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 1117 return; 1118 1119 /* todo */ 1120 } 1121 1122 static void vi_enable_aspm(struct amdgpu_device *adev) 1123 { 1124 u32 data, orig; 1125 1126 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL); 1127 data |= PCIE_LC_CNTL__LC_L0S_INACTIVITY_DEFAULT << 1128 PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT; 1129 data |= PCIE_LC_CNTL__LC_L1_INACTIVITY_DEFAULT << 1130 PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; 1131 data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; 1132 data |= PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK; 1133 if (orig != data) 1134 WREG32_PCIE(ixPCIE_LC_CNTL, data); 1135 } 1136 1137 static void vi_program_aspm(struct amdgpu_device *adev) 1138 { 1139 u32 data, data1, orig; 1140 bool bL1SS = false; 1141 bool bClkReqSupport = true; 1142 1143 if (!amdgpu_aspm) 1144 return; 1145 1146 if (adev->flags & AMD_IS_APU || 1147 adev->asic_type < CHIP_POLARIS10) 1148 return; 1149 1150 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL); 1151 data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK; 1152 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; 1153 data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; 1154 if (orig != data) 1155 WREG32_PCIE(ixPCIE_LC_CNTL, data); 1156 1157 orig = data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL); 1158 data &= ~PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK; 1159 data |= 0x0024 << PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT; 1160 data |= PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK; 1161 if (orig != data) 1162 WREG32_PCIE(ixPCIE_LC_N_FTS_CNTL, data); 1163 1164 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL3); 1165 data |= PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK; 1166 if (orig != data) 1167 WREG32_PCIE(ixPCIE_LC_CNTL3, data); 1168 1169 orig = data = RREG32_PCIE(ixPCIE_P_CNTL); 1170 data |= PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK; 1171 if (orig != data) 1172 WREG32_PCIE(ixPCIE_P_CNTL, data); 1173 1174 data = RREG32_PCIE(ixPCIE_LC_L1_PM_SUBSTATE); 1175 pci_read_config_dword(adev->pdev, PCIE_L1_PM_SUB_CNTL, &data1); 1176 if (data & PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK && 1177 (data & (PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK | 1178 PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK | 1179 PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK | 1180 PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK))) { 1181 bL1SS = true; 1182 } else if (data1 & (PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK | 1183 PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK | 1184 PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK | 1185 PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK)) { 1186 bL1SS = true; 1187 } 1188 1189 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL6); 1190 data |= PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK; 1191 if (orig != data) 1192 WREG32_PCIE(ixPCIE_LC_CNTL6, data); 1193 1194 orig = data = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL); 1195 data |= PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK; 1196 if (orig != data) 1197 WREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL, data); 1198 1199 pci_read_config_dword(adev->pdev, LINK_CAP, &data); 1200 if (!(data & PCIE_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK)) 1201 bClkReqSupport = false; 1202 1203 if (bClkReqSupport) { 1204 orig = data = RREG32_SMC(ixTHM_CLK_CNTL); 1205 data &= ~(THM_CLK_CNTL__CMON_CLK_SEL_MASK | THM_CLK_CNTL__TMON_CLK_SEL_MASK); 1206 data |= (1 << THM_CLK_CNTL__CMON_CLK_SEL__SHIFT) | 1207 (1 << THM_CLK_CNTL__TMON_CLK_SEL__SHIFT); 1208 if (orig != data) 1209 WREG32_SMC(ixTHM_CLK_CNTL, data); 1210 1211 orig = data = RREG32_SMC(ixMISC_CLK_CTRL); 1212 data &= ~(MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK | 1213 MISC_CLK_CTRL__ZCLK_SEL_MASK | MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK); 1214 data |= (1 << MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT) | 1215 (1 << MISC_CLK_CTRL__ZCLK_SEL__SHIFT); 1216 data |= (0x20 << MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT); 1217 if (orig != data) 1218 WREG32_SMC(ixMISC_CLK_CTRL, data); 1219 1220 orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL); 1221 data |= CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK; 1222 if (orig != data) 1223 WREG32_SMC(ixCG_CLKPIN_CNTL, data); 1224 1225 orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL_2); 1226 data |= CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK; 1227 if (orig != data) 1228 WREG32_SMC(ixCG_CLKPIN_CNTL, data); 1229 1230 orig = data = RREG32_SMC(ixMPLL_BYPASSCLK_SEL); 1231 data &= ~MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK; 1232 data |= (4 << MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT); 1233 if (orig != data) 1234 WREG32_SMC(ixMPLL_BYPASSCLK_SEL, data); 1235 1236 orig = data = RREG32_PCIE(ixCPM_CONTROL); 1237 data |= (CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK | 1238 CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE_MASK); 1239 if (orig != data) 1240 WREG32_PCIE(ixCPM_CONTROL, data); 1241 1242 orig = data = RREG32_PCIE(ixPCIE_CONFIG_CNTL); 1243 data &= ~PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK; 1244 data |= (0xE << PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT); 1245 if (orig != data) 1246 WREG32_PCIE(ixPCIE_CONFIG_CNTL, data); 1247 1248 orig = data = RREG32(mmBIF_CLK_CTRL); 1249 data |= BIF_CLK_CTRL__BIF_XSTCLK_READY_MASK; 1250 if (orig != data) 1251 WREG32(mmBIF_CLK_CTRL, data); 1252 1253 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL7); 1254 data |= PCIE_LC_CNTL7__LC_L1_SIDEBAND_CLKREQ_PDWN_EN_MASK; 1255 if (orig != data) 1256 WREG32_PCIE(ixPCIE_LC_CNTL7, data); 1257 1258 orig = data = RREG32_PCIE(ixPCIE_HW_DEBUG); 1259 data |= PCIE_HW_DEBUG__HW_01_DEBUG_MASK; 1260 if (orig != data) 1261 WREG32_PCIE(ixPCIE_HW_DEBUG, data); 1262 1263 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL2); 1264 data |= PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK; 1265 data |= PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK; 1266 if (bL1SS) 1267 data &= ~PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK; 1268 if (orig != data) 1269 WREG32_PCIE(ixPCIE_LC_CNTL2, data); 1270 1271 } 1272 1273 vi_enable_aspm(adev); 1274 1275 data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL); 1276 data1 = RREG32_PCIE(ixPCIE_LC_STATUS1); 1277 if (((data & PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK) == PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK) && 1278 data1 & PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK && 1279 data1 & PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK) { 1280 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL); 1281 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; 1282 if (orig != data) 1283 WREG32_PCIE(ixPCIE_LC_CNTL, data); 1284 } 1285 1286 if ((adev->asic_type == CHIP_POLARIS12 && 1287 !(ASICID_IS_P23(adev->pdev->device, adev->pdev->revision))) || 1288 ASIC_IS_P22(adev->asic_type, adev->external_rev_id)) { 1289 orig = data = RREG32_PCIE(ixPCIE_LC_TRAINING_CNTL); 1290 data &= ~PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK; 1291 if (orig != data) 1292 WREG32_PCIE(ixPCIE_LC_TRAINING_CNTL, data); 1293 } 1294 } 1295 1296 static void vi_enable_doorbell_aperture(struct amdgpu_device *adev, 1297 bool enable) 1298 { 1299 u32 tmp; 1300 1301 /* not necessary on CZ */ 1302 if (adev->flags & AMD_IS_APU) 1303 return; 1304 1305 tmp = RREG32(mmBIF_DOORBELL_APER_EN); 1306 if (enable) 1307 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1); 1308 else 1309 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0); 1310 1311 WREG32(mmBIF_DOORBELL_APER_EN, tmp); 1312 } 1313 1314 #define ATI_REV_ID_FUSE_MACRO__ADDRESS 0xC0014044 1315 #define ATI_REV_ID_FUSE_MACRO__SHIFT 9 1316 #define ATI_REV_ID_FUSE_MACRO__MASK 0x00001E00 1317 1318 static uint32_t vi_get_rev_id(struct amdgpu_device *adev) 1319 { 1320 if (adev->flags & AMD_IS_APU) 1321 return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK) 1322 >> ATI_REV_ID_FUSE_MACRO__SHIFT; 1323 else 1324 return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK) 1325 >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT; 1326 } 1327 1328 static void vi_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 1329 { 1330 if (!ring || !ring->funcs->emit_wreg) { 1331 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); 1332 RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL); 1333 } else { 1334 amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); 1335 } 1336 } 1337 1338 static void vi_invalidate_hdp(struct amdgpu_device *adev, 1339 struct amdgpu_ring *ring) 1340 { 1341 if (!ring || !ring->funcs->emit_wreg) { 1342 WREG32(mmHDP_DEBUG0, 1); 1343 RREG32(mmHDP_DEBUG0); 1344 } else { 1345 amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1); 1346 } 1347 } 1348 1349 static bool vi_need_full_reset(struct amdgpu_device *adev) 1350 { 1351 switch (adev->asic_type) { 1352 case CHIP_CARRIZO: 1353 case CHIP_STONEY: 1354 /* CZ has hang issues with full reset at the moment */ 1355 return false; 1356 case CHIP_FIJI: 1357 case CHIP_TONGA: 1358 /* XXX: soft reset should work on fiji and tonga */ 1359 return true; 1360 case CHIP_POLARIS10: 1361 case CHIP_POLARIS11: 1362 case CHIP_POLARIS12: 1363 case CHIP_TOPAZ: 1364 default: 1365 /* change this when we support soft reset */ 1366 return true; 1367 } 1368 } 1369 1370 static void vi_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 1371 uint64_t *count1) 1372 { 1373 uint32_t perfctr = 0; 1374 uint64_t cnt0_of, cnt1_of; 1375 int tmp; 1376 1377 /* This reports 0 on APUs, so return to avoid writing/reading registers 1378 * that may or may not be different from their GPU counterparts 1379 */ 1380 if (adev->flags & AMD_IS_APU) 1381 return; 1382 1383 /* Set the 2 events that we wish to watch, defined above */ 1384 /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */ 1385 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40); 1386 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104); 1387 1388 /* Write to enable desired perf counters */ 1389 WREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK, perfctr); 1390 /* Zero out and enable the perf counters 1391 * Write 0x5: 1392 * Bit 0 = Start all counters(1) 1393 * Bit 2 = Global counter reset enable(1) 1394 */ 1395 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000005); 1396 1397 msleep(1000); 1398 1399 /* Load the shadow and disable the perf counters 1400 * Write 0x2: 1401 * Bit 0 = Stop counters(0) 1402 * Bit 1 = Load the shadow counters(1) 1403 */ 1404 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000002); 1405 1406 /* Read register values to get any >32bit overflow */ 1407 tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK); 1408 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); 1409 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); 1410 1411 /* Get the values and add the overflow */ 1412 *count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); 1413 *count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); 1414 } 1415 1416 static uint64_t vi_get_pcie_replay_count(struct amdgpu_device *adev) 1417 { 1418 uint64_t nak_r, nak_g; 1419 1420 /* Get the number of NAKs received and generated */ 1421 nak_r = RREG32_PCIE(ixPCIE_RX_NUM_NAK); 1422 nak_g = RREG32_PCIE(ixPCIE_RX_NUM_NAK_GENERATED); 1423 1424 /* Add the total number of NAKs, i.e the number of replays */ 1425 return (nak_r + nak_g); 1426 } 1427 1428 static bool vi_need_reset_on_init(struct amdgpu_device *adev) 1429 { 1430 u32 clock_cntl, pc; 1431 1432 if (adev->flags & AMD_IS_APU) 1433 return false; 1434 1435 /* check if the SMC is already running */ 1436 clock_cntl = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); 1437 pc = RREG32_SMC(ixSMC_PC_C); 1438 if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) && 1439 (0x20100 <= pc)) 1440 return true; 1441 1442 return false; 1443 } 1444 1445 static void vi_pre_asic_init(struct amdgpu_device *adev) 1446 { 1447 } 1448 1449 static const struct amdgpu_asic_funcs vi_asic_funcs = 1450 { 1451 .read_disabled_bios = &vi_read_disabled_bios, 1452 .read_bios_from_rom = &vi_read_bios_from_rom, 1453 .read_register = &vi_read_register, 1454 .reset = &vi_asic_reset, 1455 .reset_method = &vi_asic_reset_method, 1456 .set_vga_state = &vi_vga_set_state, 1457 .get_xclk = &vi_get_xclk, 1458 .set_uvd_clocks = &vi_set_uvd_clocks, 1459 .set_vce_clocks = &vi_set_vce_clocks, 1460 .get_config_memsize = &vi_get_config_memsize, 1461 .flush_hdp = &vi_flush_hdp, 1462 .invalidate_hdp = &vi_invalidate_hdp, 1463 .need_full_reset = &vi_need_full_reset, 1464 .init_doorbell_index = &legacy_doorbell_index_init, 1465 .get_pcie_usage = &vi_get_pcie_usage, 1466 .need_reset_on_init = &vi_need_reset_on_init, 1467 .get_pcie_replay_count = &vi_get_pcie_replay_count, 1468 .supports_baco = &vi_asic_supports_baco, 1469 .pre_asic_init = &vi_pre_asic_init, 1470 .query_video_codecs = &vi_query_video_codecs, 1471 }; 1472 1473 #define CZ_REV_BRISTOL(rev) \ 1474 ((rev >= 0xC8 && rev <= 0xCE) || (rev >= 0xE1 && rev <= 0xE6)) 1475 1476 static int vi_common_early_init(void *handle) 1477 { 1478 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1479 1480 if (adev->flags & AMD_IS_APU) { 1481 adev->smc_rreg = &cz_smc_rreg; 1482 adev->smc_wreg = &cz_smc_wreg; 1483 } else { 1484 adev->smc_rreg = &vi_smc_rreg; 1485 adev->smc_wreg = &vi_smc_wreg; 1486 } 1487 adev->pcie_rreg = &vi_pcie_rreg; 1488 adev->pcie_wreg = &vi_pcie_wreg; 1489 adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg; 1490 adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg; 1491 adev->didt_rreg = &vi_didt_rreg; 1492 adev->didt_wreg = &vi_didt_wreg; 1493 adev->gc_cac_rreg = &vi_gc_cac_rreg; 1494 adev->gc_cac_wreg = &vi_gc_cac_wreg; 1495 1496 adev->asic_funcs = &vi_asic_funcs; 1497 1498 adev->rev_id = vi_get_rev_id(adev); 1499 adev->external_rev_id = 0xFF; 1500 switch (adev->asic_type) { 1501 case CHIP_TOPAZ: 1502 adev->cg_flags = 0; 1503 adev->pg_flags = 0; 1504 adev->external_rev_id = 0x1; 1505 break; 1506 case CHIP_FIJI: 1507 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1508 AMD_CG_SUPPORT_GFX_MGLS | 1509 AMD_CG_SUPPORT_GFX_RLC_LS | 1510 AMD_CG_SUPPORT_GFX_CP_LS | 1511 AMD_CG_SUPPORT_GFX_CGTS | 1512 AMD_CG_SUPPORT_GFX_CGTS_LS | 1513 AMD_CG_SUPPORT_GFX_CGCG | 1514 AMD_CG_SUPPORT_GFX_CGLS | 1515 AMD_CG_SUPPORT_SDMA_MGCG | 1516 AMD_CG_SUPPORT_SDMA_LS | 1517 AMD_CG_SUPPORT_BIF_LS | 1518 AMD_CG_SUPPORT_HDP_MGCG | 1519 AMD_CG_SUPPORT_HDP_LS | 1520 AMD_CG_SUPPORT_ROM_MGCG | 1521 AMD_CG_SUPPORT_MC_MGCG | 1522 AMD_CG_SUPPORT_MC_LS | 1523 AMD_CG_SUPPORT_UVD_MGCG; 1524 adev->pg_flags = 0; 1525 adev->external_rev_id = adev->rev_id + 0x3c; 1526 break; 1527 case CHIP_TONGA: 1528 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1529 AMD_CG_SUPPORT_GFX_CGCG | 1530 AMD_CG_SUPPORT_GFX_CGLS | 1531 AMD_CG_SUPPORT_SDMA_MGCG | 1532 AMD_CG_SUPPORT_SDMA_LS | 1533 AMD_CG_SUPPORT_BIF_LS | 1534 AMD_CG_SUPPORT_HDP_MGCG | 1535 AMD_CG_SUPPORT_HDP_LS | 1536 AMD_CG_SUPPORT_ROM_MGCG | 1537 AMD_CG_SUPPORT_MC_MGCG | 1538 AMD_CG_SUPPORT_MC_LS | 1539 AMD_CG_SUPPORT_DRM_LS | 1540 AMD_CG_SUPPORT_UVD_MGCG; 1541 adev->pg_flags = 0; 1542 adev->external_rev_id = adev->rev_id + 0x14; 1543 break; 1544 case CHIP_POLARIS11: 1545 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1546 AMD_CG_SUPPORT_GFX_RLC_LS | 1547 AMD_CG_SUPPORT_GFX_CP_LS | 1548 AMD_CG_SUPPORT_GFX_CGCG | 1549 AMD_CG_SUPPORT_GFX_CGLS | 1550 AMD_CG_SUPPORT_GFX_3D_CGCG | 1551 AMD_CG_SUPPORT_GFX_3D_CGLS | 1552 AMD_CG_SUPPORT_SDMA_MGCG | 1553 AMD_CG_SUPPORT_SDMA_LS | 1554 AMD_CG_SUPPORT_BIF_MGCG | 1555 AMD_CG_SUPPORT_BIF_LS | 1556 AMD_CG_SUPPORT_HDP_MGCG | 1557 AMD_CG_SUPPORT_HDP_LS | 1558 AMD_CG_SUPPORT_ROM_MGCG | 1559 AMD_CG_SUPPORT_MC_MGCG | 1560 AMD_CG_SUPPORT_MC_LS | 1561 AMD_CG_SUPPORT_DRM_LS | 1562 AMD_CG_SUPPORT_UVD_MGCG | 1563 AMD_CG_SUPPORT_VCE_MGCG; 1564 adev->pg_flags = 0; 1565 adev->external_rev_id = adev->rev_id + 0x5A; 1566 break; 1567 case CHIP_POLARIS10: 1568 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1569 AMD_CG_SUPPORT_GFX_RLC_LS | 1570 AMD_CG_SUPPORT_GFX_CP_LS | 1571 AMD_CG_SUPPORT_GFX_CGCG | 1572 AMD_CG_SUPPORT_GFX_CGLS | 1573 AMD_CG_SUPPORT_GFX_3D_CGCG | 1574 AMD_CG_SUPPORT_GFX_3D_CGLS | 1575 AMD_CG_SUPPORT_SDMA_MGCG | 1576 AMD_CG_SUPPORT_SDMA_LS | 1577 AMD_CG_SUPPORT_BIF_MGCG | 1578 AMD_CG_SUPPORT_BIF_LS | 1579 AMD_CG_SUPPORT_HDP_MGCG | 1580 AMD_CG_SUPPORT_HDP_LS | 1581 AMD_CG_SUPPORT_ROM_MGCG | 1582 AMD_CG_SUPPORT_MC_MGCG | 1583 AMD_CG_SUPPORT_MC_LS | 1584 AMD_CG_SUPPORT_DRM_LS | 1585 AMD_CG_SUPPORT_UVD_MGCG | 1586 AMD_CG_SUPPORT_VCE_MGCG; 1587 adev->pg_flags = 0; 1588 adev->external_rev_id = adev->rev_id + 0x50; 1589 break; 1590 case CHIP_POLARIS12: 1591 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1592 AMD_CG_SUPPORT_GFX_RLC_LS | 1593 AMD_CG_SUPPORT_GFX_CP_LS | 1594 AMD_CG_SUPPORT_GFX_CGCG | 1595 AMD_CG_SUPPORT_GFX_CGLS | 1596 AMD_CG_SUPPORT_GFX_3D_CGCG | 1597 AMD_CG_SUPPORT_GFX_3D_CGLS | 1598 AMD_CG_SUPPORT_SDMA_MGCG | 1599 AMD_CG_SUPPORT_SDMA_LS | 1600 AMD_CG_SUPPORT_BIF_MGCG | 1601 AMD_CG_SUPPORT_BIF_LS | 1602 AMD_CG_SUPPORT_HDP_MGCG | 1603 AMD_CG_SUPPORT_HDP_LS | 1604 AMD_CG_SUPPORT_ROM_MGCG | 1605 AMD_CG_SUPPORT_MC_MGCG | 1606 AMD_CG_SUPPORT_MC_LS | 1607 AMD_CG_SUPPORT_DRM_LS | 1608 AMD_CG_SUPPORT_UVD_MGCG | 1609 AMD_CG_SUPPORT_VCE_MGCG; 1610 adev->pg_flags = 0; 1611 adev->external_rev_id = adev->rev_id + 0x64; 1612 break; 1613 case CHIP_VEGAM: 1614 adev->cg_flags = 0; 1615 /*AMD_CG_SUPPORT_GFX_MGCG | 1616 AMD_CG_SUPPORT_GFX_RLC_LS | 1617 AMD_CG_SUPPORT_GFX_CP_LS | 1618 AMD_CG_SUPPORT_GFX_CGCG | 1619 AMD_CG_SUPPORT_GFX_CGLS | 1620 AMD_CG_SUPPORT_GFX_3D_CGCG | 1621 AMD_CG_SUPPORT_GFX_3D_CGLS | 1622 AMD_CG_SUPPORT_SDMA_MGCG | 1623 AMD_CG_SUPPORT_SDMA_LS | 1624 AMD_CG_SUPPORT_BIF_MGCG | 1625 AMD_CG_SUPPORT_BIF_LS | 1626 AMD_CG_SUPPORT_HDP_MGCG | 1627 AMD_CG_SUPPORT_HDP_LS | 1628 AMD_CG_SUPPORT_ROM_MGCG | 1629 AMD_CG_SUPPORT_MC_MGCG | 1630 AMD_CG_SUPPORT_MC_LS | 1631 AMD_CG_SUPPORT_DRM_LS | 1632 AMD_CG_SUPPORT_UVD_MGCG | 1633 AMD_CG_SUPPORT_VCE_MGCG;*/ 1634 adev->pg_flags = 0; 1635 adev->external_rev_id = adev->rev_id + 0x6E; 1636 break; 1637 case CHIP_CARRIZO: 1638 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG | 1639 AMD_CG_SUPPORT_GFX_MGCG | 1640 AMD_CG_SUPPORT_GFX_MGLS | 1641 AMD_CG_SUPPORT_GFX_RLC_LS | 1642 AMD_CG_SUPPORT_GFX_CP_LS | 1643 AMD_CG_SUPPORT_GFX_CGTS | 1644 AMD_CG_SUPPORT_GFX_CGTS_LS | 1645 AMD_CG_SUPPORT_GFX_CGCG | 1646 AMD_CG_SUPPORT_GFX_CGLS | 1647 AMD_CG_SUPPORT_BIF_LS | 1648 AMD_CG_SUPPORT_HDP_MGCG | 1649 AMD_CG_SUPPORT_HDP_LS | 1650 AMD_CG_SUPPORT_SDMA_MGCG | 1651 AMD_CG_SUPPORT_SDMA_LS | 1652 AMD_CG_SUPPORT_VCE_MGCG; 1653 /* rev0 hardware requires workarounds to support PG */ 1654 adev->pg_flags = 0; 1655 if (adev->rev_id != 0x00 || CZ_REV_BRISTOL(adev->pdev->revision)) { 1656 adev->pg_flags |= AMD_PG_SUPPORT_GFX_SMG | 1657 AMD_PG_SUPPORT_GFX_PIPELINE | 1658 AMD_PG_SUPPORT_CP | 1659 AMD_PG_SUPPORT_UVD | 1660 AMD_PG_SUPPORT_VCE; 1661 } 1662 adev->external_rev_id = adev->rev_id + 0x1; 1663 break; 1664 case CHIP_STONEY: 1665 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG | 1666 AMD_CG_SUPPORT_GFX_MGCG | 1667 AMD_CG_SUPPORT_GFX_MGLS | 1668 AMD_CG_SUPPORT_GFX_RLC_LS | 1669 AMD_CG_SUPPORT_GFX_CP_LS | 1670 AMD_CG_SUPPORT_GFX_CGTS | 1671 AMD_CG_SUPPORT_GFX_CGTS_LS | 1672 AMD_CG_SUPPORT_GFX_CGLS | 1673 AMD_CG_SUPPORT_BIF_LS | 1674 AMD_CG_SUPPORT_HDP_MGCG | 1675 AMD_CG_SUPPORT_HDP_LS | 1676 AMD_CG_SUPPORT_SDMA_MGCG | 1677 AMD_CG_SUPPORT_SDMA_LS | 1678 AMD_CG_SUPPORT_VCE_MGCG; 1679 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 1680 AMD_PG_SUPPORT_GFX_SMG | 1681 AMD_PG_SUPPORT_GFX_PIPELINE | 1682 AMD_PG_SUPPORT_CP | 1683 AMD_PG_SUPPORT_UVD | 1684 AMD_PG_SUPPORT_VCE; 1685 adev->external_rev_id = adev->rev_id + 0x61; 1686 break; 1687 default: 1688 /* FIXME: not supported yet */ 1689 return -EINVAL; 1690 } 1691 1692 if (amdgpu_sriov_vf(adev)) { 1693 amdgpu_virt_init_setting(adev); 1694 xgpu_vi_mailbox_set_irq_funcs(adev); 1695 } 1696 1697 return 0; 1698 } 1699 1700 static int vi_common_late_init(void *handle) 1701 { 1702 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1703 1704 if (amdgpu_sriov_vf(adev)) 1705 xgpu_vi_mailbox_get_irq(adev); 1706 1707 return 0; 1708 } 1709 1710 static int vi_common_sw_init(void *handle) 1711 { 1712 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1713 1714 if (amdgpu_sriov_vf(adev)) 1715 xgpu_vi_mailbox_add_irq_id(adev); 1716 1717 return 0; 1718 } 1719 1720 static int vi_common_sw_fini(void *handle) 1721 { 1722 return 0; 1723 } 1724 1725 static int vi_common_hw_init(void *handle) 1726 { 1727 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1728 1729 /* move the golden regs per IP block */ 1730 vi_init_golden_registers(adev); 1731 /* enable pcie gen2/3 link */ 1732 vi_pcie_gen3_enable(adev); 1733 /* enable aspm */ 1734 vi_program_aspm(adev); 1735 /* enable the doorbell aperture */ 1736 vi_enable_doorbell_aperture(adev, true); 1737 1738 return 0; 1739 } 1740 1741 static int vi_common_hw_fini(void *handle) 1742 { 1743 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1744 1745 /* enable the doorbell aperture */ 1746 vi_enable_doorbell_aperture(adev, false); 1747 1748 if (amdgpu_sriov_vf(adev)) 1749 xgpu_vi_mailbox_put_irq(adev); 1750 1751 return 0; 1752 } 1753 1754 static int vi_common_suspend(void *handle) 1755 { 1756 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1757 1758 return vi_common_hw_fini(adev); 1759 } 1760 1761 static int vi_common_resume(void *handle) 1762 { 1763 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1764 1765 return vi_common_hw_init(adev); 1766 } 1767 1768 static bool vi_common_is_idle(void *handle) 1769 { 1770 return true; 1771 } 1772 1773 static int vi_common_wait_for_idle(void *handle) 1774 { 1775 return 0; 1776 } 1777 1778 static int vi_common_soft_reset(void *handle) 1779 { 1780 return 0; 1781 } 1782 1783 static void vi_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev, 1784 bool enable) 1785 { 1786 uint32_t temp, data; 1787 1788 temp = data = RREG32_PCIE(ixPCIE_CNTL2); 1789 1790 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) 1791 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 1792 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 1793 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK; 1794 else 1795 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 1796 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 1797 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 1798 1799 if (temp != data) 1800 WREG32_PCIE(ixPCIE_CNTL2, data); 1801 } 1802 1803 static void vi_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev, 1804 bool enable) 1805 { 1806 uint32_t temp, data; 1807 1808 temp = data = RREG32(mmHDP_HOST_PATH_CNTL); 1809 1810 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 1811 data &= ~HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK; 1812 else 1813 data |= HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK; 1814 1815 if (temp != data) 1816 WREG32(mmHDP_HOST_PATH_CNTL, data); 1817 } 1818 1819 static void vi_update_hdp_light_sleep(struct amdgpu_device *adev, 1820 bool enable) 1821 { 1822 uint32_t temp, data; 1823 1824 temp = data = RREG32(mmHDP_MEM_POWER_LS); 1825 1826 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 1827 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK; 1828 else 1829 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK; 1830 1831 if (temp != data) 1832 WREG32(mmHDP_MEM_POWER_LS, data); 1833 } 1834 1835 static void vi_update_drm_light_sleep(struct amdgpu_device *adev, 1836 bool enable) 1837 { 1838 uint32_t temp, data; 1839 1840 temp = data = RREG32(0x157a); 1841 1842 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) 1843 data |= 1; 1844 else 1845 data &= ~1; 1846 1847 if (temp != data) 1848 WREG32(0x157a, data); 1849 } 1850 1851 1852 static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev, 1853 bool enable) 1854 { 1855 uint32_t temp, data; 1856 1857 temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0); 1858 1859 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG)) 1860 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | 1861 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK); 1862 else 1863 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | 1864 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK; 1865 1866 if (temp != data) 1867 WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data); 1868 } 1869 1870 static int vi_common_set_clockgating_state_by_smu(void *handle, 1871 enum amd_clockgating_state state) 1872 { 1873 uint32_t msg_id, pp_state = 0; 1874 uint32_t pp_support_state = 0; 1875 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1876 1877 if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) { 1878 if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) { 1879 pp_support_state = PP_STATE_SUPPORT_LS; 1880 pp_state = PP_STATE_LS; 1881 } 1882 if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) { 1883 pp_support_state |= PP_STATE_SUPPORT_CG; 1884 pp_state |= PP_STATE_CG; 1885 } 1886 if (state == AMD_CG_STATE_UNGATE) 1887 pp_state = 0; 1888 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1889 PP_BLOCK_SYS_MC, 1890 pp_support_state, 1891 pp_state); 1892 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); 1893 } 1894 1895 if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) { 1896 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS) { 1897 pp_support_state = PP_STATE_SUPPORT_LS; 1898 pp_state = PP_STATE_LS; 1899 } 1900 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG) { 1901 pp_support_state |= PP_STATE_SUPPORT_CG; 1902 pp_state |= PP_STATE_CG; 1903 } 1904 if (state == AMD_CG_STATE_UNGATE) 1905 pp_state = 0; 1906 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1907 PP_BLOCK_SYS_SDMA, 1908 pp_support_state, 1909 pp_state); 1910 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); 1911 } 1912 1913 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) { 1914 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { 1915 pp_support_state = PP_STATE_SUPPORT_LS; 1916 pp_state = PP_STATE_LS; 1917 } 1918 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG) { 1919 pp_support_state |= PP_STATE_SUPPORT_CG; 1920 pp_state |= PP_STATE_CG; 1921 } 1922 if (state == AMD_CG_STATE_UNGATE) 1923 pp_state = 0; 1924 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1925 PP_BLOCK_SYS_HDP, 1926 pp_support_state, 1927 pp_state); 1928 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); 1929 } 1930 1931 1932 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS) { 1933 if (state == AMD_CG_STATE_UNGATE) 1934 pp_state = 0; 1935 else 1936 pp_state = PP_STATE_LS; 1937 1938 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1939 PP_BLOCK_SYS_BIF, 1940 PP_STATE_SUPPORT_LS, 1941 pp_state); 1942 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); 1943 } 1944 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) { 1945 if (state == AMD_CG_STATE_UNGATE) 1946 pp_state = 0; 1947 else 1948 pp_state = PP_STATE_CG; 1949 1950 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1951 PP_BLOCK_SYS_BIF, 1952 PP_STATE_SUPPORT_CG, 1953 pp_state); 1954 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); 1955 } 1956 1957 if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) { 1958 1959 if (state == AMD_CG_STATE_UNGATE) 1960 pp_state = 0; 1961 else 1962 pp_state = PP_STATE_LS; 1963 1964 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1965 PP_BLOCK_SYS_DRM, 1966 PP_STATE_SUPPORT_LS, 1967 pp_state); 1968 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); 1969 } 1970 1971 if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) { 1972 1973 if (state == AMD_CG_STATE_UNGATE) 1974 pp_state = 0; 1975 else 1976 pp_state = PP_STATE_CG; 1977 1978 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1979 PP_BLOCK_SYS_ROM, 1980 PP_STATE_SUPPORT_CG, 1981 pp_state); 1982 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id); 1983 } 1984 return 0; 1985 } 1986 1987 static int vi_common_set_clockgating_state(void *handle, 1988 enum amd_clockgating_state state) 1989 { 1990 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1991 1992 if (amdgpu_sriov_vf(adev)) 1993 return 0; 1994 1995 switch (adev->asic_type) { 1996 case CHIP_FIJI: 1997 vi_update_bif_medium_grain_light_sleep(adev, 1998 state == AMD_CG_STATE_GATE); 1999 vi_update_hdp_medium_grain_clock_gating(adev, 2000 state == AMD_CG_STATE_GATE); 2001 vi_update_hdp_light_sleep(adev, 2002 state == AMD_CG_STATE_GATE); 2003 vi_update_rom_medium_grain_clock_gating(adev, 2004 state == AMD_CG_STATE_GATE); 2005 break; 2006 case CHIP_CARRIZO: 2007 case CHIP_STONEY: 2008 vi_update_bif_medium_grain_light_sleep(adev, 2009 state == AMD_CG_STATE_GATE); 2010 vi_update_hdp_medium_grain_clock_gating(adev, 2011 state == AMD_CG_STATE_GATE); 2012 vi_update_hdp_light_sleep(adev, 2013 state == AMD_CG_STATE_GATE); 2014 vi_update_drm_light_sleep(adev, 2015 state == AMD_CG_STATE_GATE); 2016 break; 2017 case CHIP_TONGA: 2018 case CHIP_POLARIS10: 2019 case CHIP_POLARIS11: 2020 case CHIP_POLARIS12: 2021 case CHIP_VEGAM: 2022 vi_common_set_clockgating_state_by_smu(adev, state); 2023 break; 2024 default: 2025 break; 2026 } 2027 return 0; 2028 } 2029 2030 static int vi_common_set_powergating_state(void *handle, 2031 enum amd_powergating_state state) 2032 { 2033 return 0; 2034 } 2035 2036 static void vi_common_get_clockgating_state(void *handle, u32 *flags) 2037 { 2038 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2039 int data; 2040 2041 if (amdgpu_sriov_vf(adev)) 2042 *flags = 0; 2043 2044 /* AMD_CG_SUPPORT_BIF_LS */ 2045 data = RREG32_PCIE(ixPCIE_CNTL2); 2046 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) 2047 *flags |= AMD_CG_SUPPORT_BIF_LS; 2048 2049 /* AMD_CG_SUPPORT_HDP_LS */ 2050 data = RREG32(mmHDP_MEM_POWER_LS); 2051 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK) 2052 *flags |= AMD_CG_SUPPORT_HDP_LS; 2053 2054 /* AMD_CG_SUPPORT_HDP_MGCG */ 2055 data = RREG32(mmHDP_HOST_PATH_CNTL); 2056 if (!(data & HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK)) 2057 *flags |= AMD_CG_SUPPORT_HDP_MGCG; 2058 2059 /* AMD_CG_SUPPORT_ROM_MGCG */ 2060 data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0); 2061 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK)) 2062 *flags |= AMD_CG_SUPPORT_ROM_MGCG; 2063 } 2064 2065 static const struct amd_ip_funcs vi_common_ip_funcs = { 2066 .name = "vi_common", 2067 .early_init = vi_common_early_init, 2068 .late_init = vi_common_late_init, 2069 .sw_init = vi_common_sw_init, 2070 .sw_fini = vi_common_sw_fini, 2071 .hw_init = vi_common_hw_init, 2072 .hw_fini = vi_common_hw_fini, 2073 .suspend = vi_common_suspend, 2074 .resume = vi_common_resume, 2075 .is_idle = vi_common_is_idle, 2076 .wait_for_idle = vi_common_wait_for_idle, 2077 .soft_reset = vi_common_soft_reset, 2078 .set_clockgating_state = vi_common_set_clockgating_state, 2079 .set_powergating_state = vi_common_set_powergating_state, 2080 .get_clockgating_state = vi_common_get_clockgating_state, 2081 }; 2082 2083 static const struct amdgpu_ip_block_version vi_common_ip_block = 2084 { 2085 .type = AMD_IP_BLOCK_TYPE_COMMON, 2086 .major = 1, 2087 .minor = 0, 2088 .rev = 0, 2089 .funcs = &vi_common_ip_funcs, 2090 }; 2091 2092 void vi_set_virt_ops(struct amdgpu_device *adev) 2093 { 2094 adev->virt.ops = &xgpu_vi_virt_ops; 2095 } 2096 2097 int vi_set_ip_blocks(struct amdgpu_device *adev) 2098 { 2099 switch (adev->asic_type) { 2100 case CHIP_TOPAZ: 2101 /* topaz has no DCE, UVD, VCE */ 2102 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); 2103 amdgpu_device_ip_block_add(adev, &gmc_v7_4_ip_block); 2104 amdgpu_device_ip_block_add(adev, &iceland_ih_ip_block); 2105 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); 2106 amdgpu_device_ip_block_add(adev, &sdma_v2_4_ip_block); 2107 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 2108 if (adev->enable_virtual_display) 2109 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2110 break; 2111 case CHIP_FIJI: 2112 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); 2113 amdgpu_device_ip_block_add(adev, &gmc_v8_5_ip_block); 2114 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block); 2115 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); 2116 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); 2117 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 2118 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 2119 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2120 #if defined(CONFIG_DRM_AMD_DC) 2121 else if (amdgpu_device_has_dc_support(adev)) 2122 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2123 #endif 2124 else 2125 amdgpu_device_ip_block_add(adev, &dce_v10_1_ip_block); 2126 if (!amdgpu_sriov_vf(adev)) { 2127 amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block); 2128 amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block); 2129 } 2130 break; 2131 case CHIP_TONGA: 2132 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); 2133 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block); 2134 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block); 2135 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); 2136 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); 2137 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 2138 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 2139 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2140 #if defined(CONFIG_DRM_AMD_DC) 2141 else if (amdgpu_device_has_dc_support(adev)) 2142 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2143 #endif 2144 else 2145 amdgpu_device_ip_block_add(adev, &dce_v10_0_ip_block); 2146 if (!amdgpu_sriov_vf(adev)) { 2147 amdgpu_device_ip_block_add(adev, &uvd_v5_0_ip_block); 2148 amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block); 2149 } 2150 break; 2151 case CHIP_POLARIS10: 2152 case CHIP_POLARIS11: 2153 case CHIP_POLARIS12: 2154 case CHIP_VEGAM: 2155 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); 2156 amdgpu_device_ip_block_add(adev, &gmc_v8_1_ip_block); 2157 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block); 2158 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); 2159 amdgpu_device_ip_block_add(adev, &sdma_v3_1_ip_block); 2160 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 2161 if (adev->enable_virtual_display) 2162 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2163 #if defined(CONFIG_DRM_AMD_DC) 2164 else if (amdgpu_device_has_dc_support(adev)) 2165 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2166 #endif 2167 else 2168 amdgpu_device_ip_block_add(adev, &dce_v11_2_ip_block); 2169 amdgpu_device_ip_block_add(adev, &uvd_v6_3_ip_block); 2170 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block); 2171 break; 2172 case CHIP_CARRIZO: 2173 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); 2174 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block); 2175 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block); 2176 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); 2177 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); 2178 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 2179 if (adev->enable_virtual_display) 2180 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2181 #if defined(CONFIG_DRM_AMD_DC) 2182 else if (amdgpu_device_has_dc_support(adev)) 2183 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2184 #endif 2185 else 2186 amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block); 2187 amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block); 2188 amdgpu_device_ip_block_add(adev, &vce_v3_1_ip_block); 2189 #if defined(CONFIG_DRM_AMD_ACP) 2190 amdgpu_device_ip_block_add(adev, &acp_ip_block); 2191 #endif 2192 break; 2193 case CHIP_STONEY: 2194 amdgpu_device_ip_block_add(adev, &vi_common_ip_block); 2195 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block); 2196 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block); 2197 amdgpu_device_ip_block_add(adev, &gfx_v8_1_ip_block); 2198 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); 2199 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 2200 if (adev->enable_virtual_display) 2201 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2202 #if defined(CONFIG_DRM_AMD_DC) 2203 else if (amdgpu_device_has_dc_support(adev)) 2204 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2205 #endif 2206 else 2207 amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block); 2208 amdgpu_device_ip_block_add(adev, &uvd_v6_2_ip_block); 2209 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block); 2210 #if defined(CONFIG_DRM_AMD_ACP) 2211 amdgpu_device_ip_block_add(adev, &acp_ip_block); 2212 #endif 2213 break; 2214 default: 2215 /* FIXME: not supported yet */ 2216 return -EINVAL; 2217 } 2218 2219 return 0; 2220 } 2221 2222 void legacy_doorbell_index_init(struct amdgpu_device *adev) 2223 { 2224 adev->doorbell_index.kiq = AMDGPU_DOORBELL_KIQ; 2225 adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL_MEC_RING0; 2226 adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL_MEC_RING1; 2227 adev->doorbell_index.mec_ring2 = AMDGPU_DOORBELL_MEC_RING2; 2228 adev->doorbell_index.mec_ring3 = AMDGPU_DOORBELL_MEC_RING3; 2229 adev->doorbell_index.mec_ring4 = AMDGPU_DOORBELL_MEC_RING4; 2230 adev->doorbell_index.mec_ring5 = AMDGPU_DOORBELL_MEC_RING5; 2231 adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL_MEC_RING6; 2232 adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL_MEC_RING7; 2233 adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL_GFX_RING0; 2234 adev->doorbell_index.sdma_engine[0] = AMDGPU_DOORBELL_sDMA_ENGINE0; 2235 adev->doorbell_index.sdma_engine[1] = AMDGPU_DOORBELL_sDMA_ENGINE1; 2236 adev->doorbell_index.ih = AMDGPU_DOORBELL_IH; 2237 adev->doorbell_index.max_assignment = AMDGPU_DOORBELL_MAX_ASSIGNMENT; 2238 } 2239