1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/slab.h> 24 #include "drmP.h" 25 #include "amdgpu.h" 26 #include "amdgpu_atombios.h" 27 #include "amdgpu_ih.h" 28 #include "amdgpu_uvd.h" 29 #include "amdgpu_vce.h" 30 #include "amdgpu_ucode.h" 31 #include "atom.h" 32 #include "amd_pcie.h" 33 34 #include "gmc/gmc_8_1_d.h" 35 #include "gmc/gmc_8_1_sh_mask.h" 36 37 #include "oss/oss_3_0_d.h" 38 #include "oss/oss_3_0_sh_mask.h" 39 40 #include "bif/bif_5_0_d.h" 41 #include "bif/bif_5_0_sh_mask.h" 42 43 #include "gca/gfx_8_0_d.h" 44 #include "gca/gfx_8_0_sh_mask.h" 45 46 #include "smu/smu_7_1_1_d.h" 47 #include "smu/smu_7_1_1_sh_mask.h" 48 49 #include "uvd/uvd_5_0_d.h" 50 #include "uvd/uvd_5_0_sh_mask.h" 51 52 #include "vce/vce_3_0_d.h" 53 #include "vce/vce_3_0_sh_mask.h" 54 55 #include "dce/dce_10_0_d.h" 56 #include "dce/dce_10_0_sh_mask.h" 57 58 #include "vid.h" 59 #include "vi.h" 60 #include "vi_dpm.h" 61 #include "gmc_v8_0.h" 62 #include "gmc_v7_0.h" 63 #include "gfx_v8_0.h" 64 #include "sdma_v2_4.h" 65 #include "sdma_v3_0.h" 66 #include "dce_v10_0.h" 67 #include "dce_v11_0.h" 68 #include "iceland_ih.h" 69 #include "tonga_ih.h" 70 #include "cz_ih.h" 71 #include "uvd_v5_0.h" 72 #include "uvd_v6_0.h" 73 #include "vce_v3_0.h" 74 #include "amdgpu_powerplay.h" 75 #if defined(CONFIG_DRM_AMD_ACP) 76 #include "amdgpu_acp.h" 77 #endif 78 #include "dce_virtual.h" 79 #include "mxgpu_vi.h" 80 81 /* 82 * Indirect registers accessor 83 */ 84 static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg) 85 { 86 unsigned long flags; 87 u32 r; 88 89 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 90 WREG32(mmPCIE_INDEX, reg); 91 (void)RREG32(mmPCIE_INDEX); 92 r = RREG32(mmPCIE_DATA); 93 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 94 return r; 95 } 96 97 static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 98 { 99 unsigned long flags; 100 101 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 102 WREG32(mmPCIE_INDEX, reg); 103 (void)RREG32(mmPCIE_INDEX); 104 WREG32(mmPCIE_DATA, v); 105 (void)RREG32(mmPCIE_DATA); 106 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 107 } 108 109 static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg) 110 { 111 unsigned long flags; 112 u32 r; 113 114 spin_lock_irqsave(&adev->smc_idx_lock, flags); 115 WREG32(mmSMC_IND_INDEX_11, (reg)); 116 r = RREG32(mmSMC_IND_DATA_11); 117 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 118 return r; 119 } 120 121 static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 122 { 123 unsigned long flags; 124 125 spin_lock_irqsave(&adev->smc_idx_lock, flags); 126 WREG32(mmSMC_IND_INDEX_11, (reg)); 127 WREG32(mmSMC_IND_DATA_11, (v)); 128 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 129 } 130 131 /* smu_8_0_d.h */ 132 #define mmMP0PUB_IND_INDEX 0x180 133 #define mmMP0PUB_IND_DATA 0x181 134 135 static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg) 136 { 137 unsigned long flags; 138 u32 r; 139 140 spin_lock_irqsave(&adev->smc_idx_lock, flags); 141 WREG32(mmMP0PUB_IND_INDEX, (reg)); 142 r = RREG32(mmMP0PUB_IND_DATA); 143 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 144 return r; 145 } 146 147 static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 148 { 149 unsigned long flags; 150 151 spin_lock_irqsave(&adev->smc_idx_lock, flags); 152 WREG32(mmMP0PUB_IND_INDEX, (reg)); 153 WREG32(mmMP0PUB_IND_DATA, (v)); 154 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 155 } 156 157 static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) 158 { 159 unsigned long flags; 160 u32 r; 161 162 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 163 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); 164 r = RREG32(mmUVD_CTX_DATA); 165 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 166 return r; 167 } 168 169 static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 170 { 171 unsigned long flags; 172 173 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 174 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); 175 WREG32(mmUVD_CTX_DATA, (v)); 176 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 177 } 178 179 static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg) 180 { 181 unsigned long flags; 182 u32 r; 183 184 spin_lock_irqsave(&adev->didt_idx_lock, flags); 185 WREG32(mmDIDT_IND_INDEX, (reg)); 186 r = RREG32(mmDIDT_IND_DATA); 187 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 188 return r; 189 } 190 191 static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 192 { 193 unsigned long flags; 194 195 spin_lock_irqsave(&adev->didt_idx_lock, flags); 196 WREG32(mmDIDT_IND_INDEX, (reg)); 197 WREG32(mmDIDT_IND_DATA, (v)); 198 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 199 } 200 201 static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) 202 { 203 unsigned long flags; 204 u32 r; 205 206 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 207 WREG32(mmGC_CAC_IND_INDEX, (reg)); 208 r = RREG32(mmGC_CAC_IND_DATA); 209 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 210 return r; 211 } 212 213 static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 214 { 215 unsigned long flags; 216 217 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 218 WREG32(mmGC_CAC_IND_INDEX, (reg)); 219 WREG32(mmGC_CAC_IND_DATA, (v)); 220 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 221 } 222 223 224 static const u32 tonga_mgcg_cgcg_init[] = 225 { 226 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100, 227 mmPCIE_INDEX, 0xffffffff, 0x0140001c, 228 mmPCIE_DATA, 0x000f0000, 0x00000000, 229 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C, 230 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100, 231 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 232 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 233 }; 234 235 static const u32 fiji_mgcg_cgcg_init[] = 236 { 237 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100, 238 mmPCIE_INDEX, 0xffffffff, 0x0140001c, 239 mmPCIE_DATA, 0x000f0000, 0x00000000, 240 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C, 241 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100, 242 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 243 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 244 }; 245 246 static const u32 iceland_mgcg_cgcg_init[] = 247 { 248 mmPCIE_INDEX, 0xffffffff, ixPCIE_CNTL2, 249 mmPCIE_DATA, 0x000f0000, 0x00000000, 250 mmSMC_IND_INDEX_4, 0xffffffff, ixCGTT_ROM_CLK_CTRL0, 251 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100, 252 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 253 }; 254 255 static const u32 cz_mgcg_cgcg_init[] = 256 { 257 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100, 258 mmPCIE_INDEX, 0xffffffff, 0x0140001c, 259 mmPCIE_DATA, 0x000f0000, 0x00000000, 260 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 261 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 262 }; 263 264 static const u32 stoney_mgcg_cgcg_init[] = 265 { 266 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00000100, 267 mmHDP_XDP_CGTT_BLK_CTRL, 0xffffffff, 0x00000104, 268 mmHDP_HOST_PATH_CNTL, 0xffffffff, 0x0f000027, 269 }; 270 271 static void vi_init_golden_registers(struct amdgpu_device *adev) 272 { 273 /* Some of the registers might be dependent on GRBM_GFX_INDEX */ 274 mutex_lock(&adev->grbm_idx_mutex); 275 276 if (amdgpu_sriov_vf(adev)) { 277 xgpu_vi_init_golden_registers(adev); 278 mutex_unlock(&adev->grbm_idx_mutex); 279 return; 280 } 281 282 switch (adev->asic_type) { 283 case CHIP_TOPAZ: 284 amdgpu_program_register_sequence(adev, 285 iceland_mgcg_cgcg_init, 286 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init)); 287 break; 288 case CHIP_FIJI: 289 amdgpu_program_register_sequence(adev, 290 fiji_mgcg_cgcg_init, 291 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); 292 break; 293 case CHIP_TONGA: 294 amdgpu_program_register_sequence(adev, 295 tonga_mgcg_cgcg_init, 296 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); 297 break; 298 case CHIP_CARRIZO: 299 amdgpu_program_register_sequence(adev, 300 cz_mgcg_cgcg_init, 301 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); 302 break; 303 case CHIP_STONEY: 304 amdgpu_program_register_sequence(adev, 305 stoney_mgcg_cgcg_init, 306 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); 307 break; 308 case CHIP_POLARIS11: 309 case CHIP_POLARIS10: 310 case CHIP_POLARIS12: 311 default: 312 break; 313 } 314 mutex_unlock(&adev->grbm_idx_mutex); 315 } 316 317 /** 318 * vi_get_xclk - get the xclk 319 * 320 * @adev: amdgpu_device pointer 321 * 322 * Returns the reference clock used by the gfx engine 323 * (VI). 324 */ 325 static u32 vi_get_xclk(struct amdgpu_device *adev) 326 { 327 u32 reference_clock = adev->clock.spll.reference_freq; 328 u32 tmp; 329 330 if (adev->flags & AMD_IS_APU) 331 return reference_clock; 332 333 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2); 334 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK)) 335 return 1000; 336 337 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL); 338 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE)) 339 return reference_clock / 4; 340 341 return reference_clock; 342 } 343 344 /** 345 * vi_srbm_select - select specific register instances 346 * 347 * @adev: amdgpu_device pointer 348 * @me: selected ME (micro engine) 349 * @pipe: pipe 350 * @queue: queue 351 * @vmid: VMID 352 * 353 * Switches the currently active registers instances. Some 354 * registers are instanced per VMID, others are instanced per 355 * me/pipe/queue combination. 356 */ 357 void vi_srbm_select(struct amdgpu_device *adev, 358 u32 me, u32 pipe, u32 queue, u32 vmid) 359 { 360 u32 srbm_gfx_cntl = 0; 361 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe); 362 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me); 363 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid); 364 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, QUEUEID, queue); 365 WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl); 366 } 367 368 static void vi_vga_set_state(struct amdgpu_device *adev, bool state) 369 { 370 /* todo */ 371 } 372 373 static bool vi_read_disabled_bios(struct amdgpu_device *adev) 374 { 375 u32 bus_cntl; 376 u32 d1vga_control = 0; 377 u32 d2vga_control = 0; 378 u32 vga_render_control = 0; 379 u32 rom_cntl; 380 bool r; 381 382 bus_cntl = RREG32(mmBUS_CNTL); 383 if (adev->mode_info.num_crtc) { 384 d1vga_control = RREG32(mmD1VGA_CONTROL); 385 d2vga_control = RREG32(mmD2VGA_CONTROL); 386 vga_render_control = RREG32(mmVGA_RENDER_CONTROL); 387 } 388 rom_cntl = RREG32_SMC(ixROM_CNTL); 389 390 /* enable the rom */ 391 WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK)); 392 if (adev->mode_info.num_crtc) { 393 /* Disable VGA mode */ 394 WREG32(mmD1VGA_CONTROL, 395 (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK | 396 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK))); 397 WREG32(mmD2VGA_CONTROL, 398 (d2vga_control & ~(D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK | 399 D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK))); 400 WREG32(mmVGA_RENDER_CONTROL, 401 (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK)); 402 } 403 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK); 404 405 r = amdgpu_read_bios(adev); 406 407 /* restore regs */ 408 WREG32(mmBUS_CNTL, bus_cntl); 409 if (adev->mode_info.num_crtc) { 410 WREG32(mmD1VGA_CONTROL, d1vga_control); 411 WREG32(mmD2VGA_CONTROL, d2vga_control); 412 WREG32(mmVGA_RENDER_CONTROL, vga_render_control); 413 } 414 WREG32_SMC(ixROM_CNTL, rom_cntl); 415 return r; 416 } 417 418 static bool vi_read_bios_from_rom(struct amdgpu_device *adev, 419 u8 *bios, u32 length_bytes) 420 { 421 u32 *dw_ptr; 422 unsigned long flags; 423 u32 i, length_dw; 424 425 if (bios == NULL) 426 return false; 427 if (length_bytes == 0) 428 return false; 429 /* APU vbios image is part of sbios image */ 430 if (adev->flags & AMD_IS_APU) 431 return false; 432 433 dw_ptr = (u32 *)bios; 434 length_dw = ALIGN(length_bytes, 4) / 4; 435 /* take the smc lock since we are using the smc index */ 436 spin_lock_irqsave(&adev->smc_idx_lock, flags); 437 /* set rom index to 0 */ 438 WREG32(mmSMC_IND_INDEX_11, ixROM_INDEX); 439 WREG32(mmSMC_IND_DATA_11, 0); 440 /* set index to data for continous read */ 441 WREG32(mmSMC_IND_INDEX_11, ixROM_DATA); 442 for (i = 0; i < length_dw; i++) 443 dw_ptr[i] = RREG32(mmSMC_IND_DATA_11); 444 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 445 446 return true; 447 } 448 449 static void vi_detect_hw_virtualization(struct amdgpu_device *adev) 450 { 451 uint32_t reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER); 452 /* bit0: 0 means pf and 1 means vf */ 453 /* bit31: 0 means disable IOV and 1 means enable */ 454 if (reg & 1) 455 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF; 456 457 if (reg & 0x80000000) 458 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV; 459 460 if (reg == 0) { 461 if (is_virtual_machine()) /* passthrough mode exclus sr-iov mode */ 462 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; 463 } 464 } 465 466 static const struct amdgpu_allowed_register_entry tonga_allowed_read_registers[] = { 467 {mmGB_MACROTILE_MODE7, true}, 468 }; 469 470 static const struct amdgpu_allowed_register_entry cz_allowed_read_registers[] = { 471 {mmGB_TILE_MODE7, true}, 472 {mmGB_TILE_MODE12, true}, 473 {mmGB_TILE_MODE17, true}, 474 {mmGB_TILE_MODE23, true}, 475 {mmGB_MACROTILE_MODE7, true}, 476 }; 477 478 static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = { 479 {mmGRBM_STATUS, false}, 480 {mmGRBM_STATUS2, false}, 481 {mmGRBM_STATUS_SE0, false}, 482 {mmGRBM_STATUS_SE1, false}, 483 {mmGRBM_STATUS_SE2, false}, 484 {mmGRBM_STATUS_SE3, false}, 485 {mmSRBM_STATUS, false}, 486 {mmSRBM_STATUS2, false}, 487 {mmSRBM_STATUS3, false}, 488 {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET, false}, 489 {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET, false}, 490 {mmCP_STAT, false}, 491 {mmCP_STALLED_STAT1, false}, 492 {mmCP_STALLED_STAT2, false}, 493 {mmCP_STALLED_STAT3, false}, 494 {mmCP_CPF_BUSY_STAT, false}, 495 {mmCP_CPF_STALLED_STAT1, false}, 496 {mmCP_CPF_STATUS, false}, 497 {mmCP_CPC_BUSY_STAT, false}, 498 {mmCP_CPC_STALLED_STAT1, false}, 499 {mmCP_CPC_STATUS, false}, 500 {mmGB_ADDR_CONFIG, false}, 501 {mmMC_ARB_RAMCFG, false}, 502 {mmGB_TILE_MODE0, false}, 503 {mmGB_TILE_MODE1, false}, 504 {mmGB_TILE_MODE2, false}, 505 {mmGB_TILE_MODE3, false}, 506 {mmGB_TILE_MODE4, false}, 507 {mmGB_TILE_MODE5, false}, 508 {mmGB_TILE_MODE6, false}, 509 {mmGB_TILE_MODE7, false}, 510 {mmGB_TILE_MODE8, false}, 511 {mmGB_TILE_MODE9, false}, 512 {mmGB_TILE_MODE10, false}, 513 {mmGB_TILE_MODE11, false}, 514 {mmGB_TILE_MODE12, false}, 515 {mmGB_TILE_MODE13, false}, 516 {mmGB_TILE_MODE14, false}, 517 {mmGB_TILE_MODE15, false}, 518 {mmGB_TILE_MODE16, false}, 519 {mmGB_TILE_MODE17, false}, 520 {mmGB_TILE_MODE18, false}, 521 {mmGB_TILE_MODE19, false}, 522 {mmGB_TILE_MODE20, false}, 523 {mmGB_TILE_MODE21, false}, 524 {mmGB_TILE_MODE22, false}, 525 {mmGB_TILE_MODE23, false}, 526 {mmGB_TILE_MODE24, false}, 527 {mmGB_TILE_MODE25, false}, 528 {mmGB_TILE_MODE26, false}, 529 {mmGB_TILE_MODE27, false}, 530 {mmGB_TILE_MODE28, false}, 531 {mmGB_TILE_MODE29, false}, 532 {mmGB_TILE_MODE30, false}, 533 {mmGB_TILE_MODE31, false}, 534 {mmGB_MACROTILE_MODE0, false}, 535 {mmGB_MACROTILE_MODE1, false}, 536 {mmGB_MACROTILE_MODE2, false}, 537 {mmGB_MACROTILE_MODE3, false}, 538 {mmGB_MACROTILE_MODE4, false}, 539 {mmGB_MACROTILE_MODE5, false}, 540 {mmGB_MACROTILE_MODE6, false}, 541 {mmGB_MACROTILE_MODE7, false}, 542 {mmGB_MACROTILE_MODE8, false}, 543 {mmGB_MACROTILE_MODE9, false}, 544 {mmGB_MACROTILE_MODE10, false}, 545 {mmGB_MACROTILE_MODE11, false}, 546 {mmGB_MACROTILE_MODE12, false}, 547 {mmGB_MACROTILE_MODE13, false}, 548 {mmGB_MACROTILE_MODE14, false}, 549 {mmGB_MACROTILE_MODE15, false}, 550 {mmCC_RB_BACKEND_DISABLE, false, true}, 551 {mmGC_USER_RB_BACKEND_DISABLE, false, true}, 552 {mmGB_BACKEND_MAP, false, false}, 553 {mmPA_SC_RASTER_CONFIG, false, true}, 554 {mmPA_SC_RASTER_CONFIG_1, false, true}, 555 }; 556 557 static uint32_t vi_get_register_value(struct amdgpu_device *adev, 558 bool indexed, u32 se_num, 559 u32 sh_num, u32 reg_offset) 560 { 561 if (indexed) { 562 uint32_t val; 563 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num; 564 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; 565 566 switch (reg_offset) { 567 case mmCC_RB_BACKEND_DISABLE: 568 return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable; 569 case mmGC_USER_RB_BACKEND_DISABLE: 570 return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable; 571 case mmPA_SC_RASTER_CONFIG: 572 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config; 573 case mmPA_SC_RASTER_CONFIG_1: 574 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1; 575 } 576 577 mutex_lock(&adev->grbm_idx_mutex); 578 if (se_num != 0xffffffff || sh_num != 0xffffffff) 579 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 580 581 val = RREG32(reg_offset); 582 583 if (se_num != 0xffffffff || sh_num != 0xffffffff) 584 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 585 mutex_unlock(&adev->grbm_idx_mutex); 586 return val; 587 } else { 588 unsigned idx; 589 590 switch (reg_offset) { 591 case mmGB_ADDR_CONFIG: 592 return adev->gfx.config.gb_addr_config; 593 case mmMC_ARB_RAMCFG: 594 return adev->gfx.config.mc_arb_ramcfg; 595 case mmGB_TILE_MODE0: 596 case mmGB_TILE_MODE1: 597 case mmGB_TILE_MODE2: 598 case mmGB_TILE_MODE3: 599 case mmGB_TILE_MODE4: 600 case mmGB_TILE_MODE5: 601 case mmGB_TILE_MODE6: 602 case mmGB_TILE_MODE7: 603 case mmGB_TILE_MODE8: 604 case mmGB_TILE_MODE9: 605 case mmGB_TILE_MODE10: 606 case mmGB_TILE_MODE11: 607 case mmGB_TILE_MODE12: 608 case mmGB_TILE_MODE13: 609 case mmGB_TILE_MODE14: 610 case mmGB_TILE_MODE15: 611 case mmGB_TILE_MODE16: 612 case mmGB_TILE_MODE17: 613 case mmGB_TILE_MODE18: 614 case mmGB_TILE_MODE19: 615 case mmGB_TILE_MODE20: 616 case mmGB_TILE_MODE21: 617 case mmGB_TILE_MODE22: 618 case mmGB_TILE_MODE23: 619 case mmGB_TILE_MODE24: 620 case mmGB_TILE_MODE25: 621 case mmGB_TILE_MODE26: 622 case mmGB_TILE_MODE27: 623 case mmGB_TILE_MODE28: 624 case mmGB_TILE_MODE29: 625 case mmGB_TILE_MODE30: 626 case mmGB_TILE_MODE31: 627 idx = (reg_offset - mmGB_TILE_MODE0); 628 return adev->gfx.config.tile_mode_array[idx]; 629 case mmGB_MACROTILE_MODE0: 630 case mmGB_MACROTILE_MODE1: 631 case mmGB_MACROTILE_MODE2: 632 case mmGB_MACROTILE_MODE3: 633 case mmGB_MACROTILE_MODE4: 634 case mmGB_MACROTILE_MODE5: 635 case mmGB_MACROTILE_MODE6: 636 case mmGB_MACROTILE_MODE7: 637 case mmGB_MACROTILE_MODE8: 638 case mmGB_MACROTILE_MODE9: 639 case mmGB_MACROTILE_MODE10: 640 case mmGB_MACROTILE_MODE11: 641 case mmGB_MACROTILE_MODE12: 642 case mmGB_MACROTILE_MODE13: 643 case mmGB_MACROTILE_MODE14: 644 case mmGB_MACROTILE_MODE15: 645 idx = (reg_offset - mmGB_MACROTILE_MODE0); 646 return adev->gfx.config.macrotile_mode_array[idx]; 647 default: 648 return RREG32(reg_offset); 649 } 650 } 651 } 652 653 static int vi_read_register(struct amdgpu_device *adev, u32 se_num, 654 u32 sh_num, u32 reg_offset, u32 *value) 655 { 656 const struct amdgpu_allowed_register_entry *asic_register_table = NULL; 657 const struct amdgpu_allowed_register_entry *asic_register_entry; 658 uint32_t size, i; 659 660 *value = 0; 661 switch (adev->asic_type) { 662 case CHIP_TOPAZ: 663 asic_register_table = tonga_allowed_read_registers; 664 size = ARRAY_SIZE(tonga_allowed_read_registers); 665 break; 666 case CHIP_FIJI: 667 case CHIP_TONGA: 668 case CHIP_POLARIS11: 669 case CHIP_POLARIS10: 670 case CHIP_POLARIS12: 671 case CHIP_CARRIZO: 672 case CHIP_STONEY: 673 asic_register_table = cz_allowed_read_registers; 674 size = ARRAY_SIZE(cz_allowed_read_registers); 675 break; 676 default: 677 return -EINVAL; 678 } 679 680 if (asic_register_table) { 681 for (i = 0; i < size; i++) { 682 asic_register_entry = asic_register_table + i; 683 if (reg_offset != asic_register_entry->reg_offset) 684 continue; 685 if (!asic_register_entry->untouched) 686 *value = vi_get_register_value(adev, 687 asic_register_entry->grbm_indexed, 688 se_num, sh_num, reg_offset); 689 return 0; 690 } 691 } 692 693 for (i = 0; i < ARRAY_SIZE(vi_allowed_read_registers); i++) { 694 if (reg_offset != vi_allowed_read_registers[i].reg_offset) 695 continue; 696 697 if (!vi_allowed_read_registers[i].untouched) 698 *value = vi_get_register_value(adev, 699 vi_allowed_read_registers[i].grbm_indexed, 700 se_num, sh_num, reg_offset); 701 return 0; 702 } 703 return -EINVAL; 704 } 705 706 static int vi_gpu_pci_config_reset(struct amdgpu_device *adev) 707 { 708 u32 i; 709 710 dev_info(adev->dev, "GPU pci config reset\n"); 711 712 /* disable BM */ 713 pci_clear_master(adev->pdev); 714 /* reset */ 715 amdgpu_pci_config_reset(adev); 716 717 udelay(100); 718 719 /* wait for asic to come out of reset */ 720 for (i = 0; i < adev->usec_timeout; i++) { 721 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) { 722 /* enable BM */ 723 pci_set_master(adev->pdev); 724 adev->has_hw_reset = true; 725 return 0; 726 } 727 udelay(1); 728 } 729 return -EINVAL; 730 } 731 732 /** 733 * vi_asic_reset - soft reset GPU 734 * 735 * @adev: amdgpu_device pointer 736 * 737 * Look up which blocks are hung and attempt 738 * to reset them. 739 * Returns 0 for success. 740 */ 741 static int vi_asic_reset(struct amdgpu_device *adev) 742 { 743 int r; 744 745 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 746 747 r = vi_gpu_pci_config_reset(adev); 748 749 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 750 751 return r; 752 } 753 754 static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock, 755 u32 cntl_reg, u32 status_reg) 756 { 757 int r, i; 758 struct atom_clock_dividers dividers; 759 uint32_t tmp; 760 761 r = amdgpu_atombios_get_clock_dividers(adev, 762 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 763 clock, false, ÷rs); 764 if (r) 765 return r; 766 767 tmp = RREG32_SMC(cntl_reg); 768 tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK | 769 CG_DCLK_CNTL__DCLK_DIVIDER_MASK); 770 tmp |= dividers.post_divider; 771 WREG32_SMC(cntl_reg, tmp); 772 773 for (i = 0; i < 100; i++) { 774 if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK) 775 break; 776 mdelay(10); 777 } 778 if (i == 100) 779 return -ETIMEDOUT; 780 781 return 0; 782 } 783 784 static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 785 { 786 int r; 787 788 r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); 789 if (r) 790 return r; 791 792 r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); 793 794 return 0; 795 } 796 797 static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 798 { 799 int r, i; 800 struct atom_clock_dividers dividers; 801 u32 tmp; 802 803 r = amdgpu_atombios_get_clock_dividers(adev, 804 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 805 ecclk, false, ÷rs); 806 if (r) 807 return r; 808 809 for (i = 0; i < 100; i++) { 810 if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK) 811 break; 812 mdelay(10); 813 } 814 if (i == 100) 815 return -ETIMEDOUT; 816 817 tmp = RREG32_SMC(ixCG_ECLK_CNTL); 818 tmp &= ~(CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK | 819 CG_ECLK_CNTL__ECLK_DIVIDER_MASK); 820 tmp |= dividers.post_divider; 821 WREG32_SMC(ixCG_ECLK_CNTL, tmp); 822 823 for (i = 0; i < 100; i++) { 824 if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK) 825 break; 826 mdelay(10); 827 } 828 if (i == 100) 829 return -ETIMEDOUT; 830 831 return 0; 832 } 833 834 static void vi_pcie_gen3_enable(struct amdgpu_device *adev) 835 { 836 if (pci_is_root_bus(adev->pdev->bus)) 837 return; 838 839 if (amdgpu_pcie_gen2 == 0) 840 return; 841 842 if (adev->flags & AMD_IS_APU) 843 return; 844 845 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 846 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 847 return; 848 849 /* todo */ 850 } 851 852 static void vi_program_aspm(struct amdgpu_device *adev) 853 { 854 855 if (amdgpu_aspm == 0) 856 return; 857 858 /* todo */ 859 } 860 861 static void vi_enable_doorbell_aperture(struct amdgpu_device *adev, 862 bool enable) 863 { 864 u32 tmp; 865 866 /* not necessary on CZ */ 867 if (adev->flags & AMD_IS_APU) 868 return; 869 870 tmp = RREG32(mmBIF_DOORBELL_APER_EN); 871 if (enable) 872 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1); 873 else 874 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0); 875 876 WREG32(mmBIF_DOORBELL_APER_EN, tmp); 877 } 878 879 #define ATI_REV_ID_FUSE_MACRO__ADDRESS 0xC0014044 880 #define ATI_REV_ID_FUSE_MACRO__SHIFT 9 881 #define ATI_REV_ID_FUSE_MACRO__MASK 0x00001E00 882 883 static uint32_t vi_get_rev_id(struct amdgpu_device *adev) 884 { 885 if (adev->flags & AMD_IS_APU) 886 return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK) 887 >> ATI_REV_ID_FUSE_MACRO__SHIFT; 888 else 889 return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK) 890 >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT; 891 } 892 893 static const struct amdgpu_asic_funcs vi_asic_funcs = 894 { 895 .read_disabled_bios = &vi_read_disabled_bios, 896 .read_bios_from_rom = &vi_read_bios_from_rom, 897 .read_register = &vi_read_register, 898 .reset = &vi_asic_reset, 899 .set_vga_state = &vi_vga_set_state, 900 .get_xclk = &vi_get_xclk, 901 .set_uvd_clocks = &vi_set_uvd_clocks, 902 .set_vce_clocks = &vi_set_vce_clocks, 903 }; 904 905 static int vi_common_early_init(void *handle) 906 { 907 bool smc_enabled = false; 908 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 909 910 if (adev->flags & AMD_IS_APU) { 911 adev->smc_rreg = &cz_smc_rreg; 912 adev->smc_wreg = &cz_smc_wreg; 913 } else { 914 adev->smc_rreg = &vi_smc_rreg; 915 adev->smc_wreg = &vi_smc_wreg; 916 } 917 adev->pcie_rreg = &vi_pcie_rreg; 918 adev->pcie_wreg = &vi_pcie_wreg; 919 adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg; 920 adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg; 921 adev->didt_rreg = &vi_didt_rreg; 922 adev->didt_wreg = &vi_didt_wreg; 923 adev->gc_cac_rreg = &vi_gc_cac_rreg; 924 adev->gc_cac_wreg = &vi_gc_cac_wreg; 925 926 adev->asic_funcs = &vi_asic_funcs; 927 928 if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC) && 929 (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_SMC))) 930 smc_enabled = true; 931 932 if (amdgpu_sriov_vf(adev)) { 933 amdgpu_virt_init_setting(adev); 934 xgpu_vi_mailbox_set_irq_funcs(adev); 935 } 936 937 adev->rev_id = vi_get_rev_id(adev); 938 adev->external_rev_id = 0xFF; 939 switch (adev->asic_type) { 940 case CHIP_TOPAZ: 941 adev->cg_flags = 0; 942 adev->pg_flags = 0; 943 adev->external_rev_id = 0x1; 944 break; 945 case CHIP_FIJI: 946 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 947 AMD_CG_SUPPORT_GFX_MGLS | 948 AMD_CG_SUPPORT_GFX_RLC_LS | 949 AMD_CG_SUPPORT_GFX_CP_LS | 950 AMD_CG_SUPPORT_GFX_CGTS | 951 AMD_CG_SUPPORT_GFX_CGTS_LS | 952 AMD_CG_SUPPORT_GFX_CGCG | 953 AMD_CG_SUPPORT_GFX_CGLS | 954 AMD_CG_SUPPORT_SDMA_MGCG | 955 AMD_CG_SUPPORT_SDMA_LS | 956 AMD_CG_SUPPORT_BIF_LS | 957 AMD_CG_SUPPORT_HDP_MGCG | 958 AMD_CG_SUPPORT_HDP_LS | 959 AMD_CG_SUPPORT_ROM_MGCG | 960 AMD_CG_SUPPORT_MC_MGCG | 961 AMD_CG_SUPPORT_MC_LS | 962 AMD_CG_SUPPORT_UVD_MGCG; 963 adev->pg_flags = 0; 964 adev->external_rev_id = adev->rev_id + 0x3c; 965 break; 966 case CHIP_TONGA: 967 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 968 AMD_CG_SUPPORT_GFX_CGCG | 969 AMD_CG_SUPPORT_GFX_CGLS | 970 AMD_CG_SUPPORT_SDMA_MGCG | 971 AMD_CG_SUPPORT_SDMA_LS | 972 AMD_CG_SUPPORT_BIF_LS | 973 AMD_CG_SUPPORT_HDP_MGCG | 974 AMD_CG_SUPPORT_HDP_LS | 975 AMD_CG_SUPPORT_ROM_MGCG | 976 AMD_CG_SUPPORT_MC_MGCG | 977 AMD_CG_SUPPORT_MC_LS | 978 AMD_CG_SUPPORT_DRM_LS | 979 AMD_CG_SUPPORT_UVD_MGCG; 980 adev->pg_flags = 0; 981 adev->external_rev_id = adev->rev_id + 0x14; 982 break; 983 case CHIP_POLARIS11: 984 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 985 AMD_CG_SUPPORT_GFX_RLC_LS | 986 AMD_CG_SUPPORT_GFX_CP_LS | 987 AMD_CG_SUPPORT_GFX_CGCG | 988 AMD_CG_SUPPORT_GFX_CGLS | 989 AMD_CG_SUPPORT_GFX_3D_CGCG | 990 AMD_CG_SUPPORT_GFX_3D_CGLS | 991 AMD_CG_SUPPORT_SDMA_MGCG | 992 AMD_CG_SUPPORT_SDMA_LS | 993 AMD_CG_SUPPORT_BIF_MGCG | 994 AMD_CG_SUPPORT_BIF_LS | 995 AMD_CG_SUPPORT_HDP_MGCG | 996 AMD_CG_SUPPORT_HDP_LS | 997 AMD_CG_SUPPORT_ROM_MGCG | 998 AMD_CG_SUPPORT_MC_MGCG | 999 AMD_CG_SUPPORT_MC_LS | 1000 AMD_CG_SUPPORT_DRM_LS | 1001 AMD_CG_SUPPORT_UVD_MGCG | 1002 AMD_CG_SUPPORT_VCE_MGCG; 1003 adev->pg_flags = 0; 1004 adev->external_rev_id = adev->rev_id + 0x5A; 1005 break; 1006 case CHIP_POLARIS10: 1007 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1008 AMD_CG_SUPPORT_GFX_RLC_LS | 1009 AMD_CG_SUPPORT_GFX_CP_LS | 1010 AMD_CG_SUPPORT_GFX_CGCG | 1011 AMD_CG_SUPPORT_GFX_CGLS | 1012 AMD_CG_SUPPORT_GFX_3D_CGCG | 1013 AMD_CG_SUPPORT_GFX_3D_CGLS | 1014 AMD_CG_SUPPORT_SDMA_MGCG | 1015 AMD_CG_SUPPORT_SDMA_LS | 1016 AMD_CG_SUPPORT_BIF_MGCG | 1017 AMD_CG_SUPPORT_BIF_LS | 1018 AMD_CG_SUPPORT_HDP_MGCG | 1019 AMD_CG_SUPPORT_HDP_LS | 1020 AMD_CG_SUPPORT_ROM_MGCG | 1021 AMD_CG_SUPPORT_MC_MGCG | 1022 AMD_CG_SUPPORT_MC_LS | 1023 AMD_CG_SUPPORT_DRM_LS | 1024 AMD_CG_SUPPORT_UVD_MGCG | 1025 AMD_CG_SUPPORT_VCE_MGCG; 1026 adev->pg_flags = 0; 1027 adev->external_rev_id = adev->rev_id + 0x50; 1028 break; 1029 case CHIP_POLARIS12: 1030 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG; 1031 adev->pg_flags = 0; 1032 adev->external_rev_id = adev->rev_id + 0x64; 1033 break; 1034 case CHIP_CARRIZO: 1035 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG | 1036 AMD_CG_SUPPORT_GFX_MGCG | 1037 AMD_CG_SUPPORT_GFX_MGLS | 1038 AMD_CG_SUPPORT_GFX_RLC_LS | 1039 AMD_CG_SUPPORT_GFX_CP_LS | 1040 AMD_CG_SUPPORT_GFX_CGTS | 1041 AMD_CG_SUPPORT_GFX_MGLS | 1042 AMD_CG_SUPPORT_GFX_CGTS_LS | 1043 AMD_CG_SUPPORT_GFX_CGCG | 1044 AMD_CG_SUPPORT_GFX_CGLS | 1045 AMD_CG_SUPPORT_BIF_LS | 1046 AMD_CG_SUPPORT_HDP_MGCG | 1047 AMD_CG_SUPPORT_HDP_LS | 1048 AMD_CG_SUPPORT_SDMA_MGCG | 1049 AMD_CG_SUPPORT_SDMA_LS | 1050 AMD_CG_SUPPORT_VCE_MGCG; 1051 /* rev0 hardware requires workarounds to support PG */ 1052 adev->pg_flags = 0; 1053 if (adev->rev_id != 0x00) { 1054 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | 1055 AMD_PG_SUPPORT_GFX_SMG | 1056 AMD_PG_SUPPORT_GFX_PIPELINE | 1057 AMD_PG_SUPPORT_CP | 1058 AMD_PG_SUPPORT_UVD | 1059 AMD_PG_SUPPORT_VCE; 1060 } 1061 adev->external_rev_id = adev->rev_id + 0x1; 1062 break; 1063 case CHIP_STONEY: 1064 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG | 1065 AMD_CG_SUPPORT_GFX_MGCG | 1066 AMD_CG_SUPPORT_GFX_MGLS | 1067 AMD_CG_SUPPORT_GFX_RLC_LS | 1068 AMD_CG_SUPPORT_GFX_CP_LS | 1069 AMD_CG_SUPPORT_GFX_CGTS | 1070 AMD_CG_SUPPORT_GFX_MGLS | 1071 AMD_CG_SUPPORT_GFX_CGTS_LS | 1072 AMD_CG_SUPPORT_GFX_CGCG | 1073 AMD_CG_SUPPORT_GFX_CGLS | 1074 AMD_CG_SUPPORT_BIF_LS | 1075 AMD_CG_SUPPORT_HDP_MGCG | 1076 AMD_CG_SUPPORT_HDP_LS | 1077 AMD_CG_SUPPORT_SDMA_MGCG | 1078 AMD_CG_SUPPORT_SDMA_LS | 1079 AMD_CG_SUPPORT_VCE_MGCG; 1080 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 1081 AMD_PG_SUPPORT_GFX_SMG | 1082 AMD_PG_SUPPORT_GFX_PIPELINE | 1083 AMD_PG_SUPPORT_CP | 1084 AMD_PG_SUPPORT_UVD | 1085 AMD_PG_SUPPORT_VCE; 1086 adev->external_rev_id = adev->rev_id + 0x61; 1087 break; 1088 default: 1089 /* FIXME: not supported yet */ 1090 return -EINVAL; 1091 } 1092 1093 if (amdgpu_smc_load_fw && smc_enabled) 1094 adev->firmware.smu_load = true; 1095 1096 amdgpu_get_pcie_info(adev); 1097 1098 return 0; 1099 } 1100 1101 static int vi_common_late_init(void *handle) 1102 { 1103 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1104 1105 if (amdgpu_sriov_vf(adev)) 1106 xgpu_vi_mailbox_get_irq(adev); 1107 1108 return 0; 1109 } 1110 1111 static int vi_common_sw_init(void *handle) 1112 { 1113 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1114 1115 if (amdgpu_sriov_vf(adev)) 1116 xgpu_vi_mailbox_add_irq_id(adev); 1117 1118 return 0; 1119 } 1120 1121 static int vi_common_sw_fini(void *handle) 1122 { 1123 return 0; 1124 } 1125 1126 static int vi_common_hw_init(void *handle) 1127 { 1128 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1129 1130 /* move the golden regs per IP block */ 1131 vi_init_golden_registers(adev); 1132 /* enable pcie gen2/3 link */ 1133 vi_pcie_gen3_enable(adev); 1134 /* enable aspm */ 1135 vi_program_aspm(adev); 1136 /* enable the doorbell aperture */ 1137 vi_enable_doorbell_aperture(adev, true); 1138 1139 return 0; 1140 } 1141 1142 static int vi_common_hw_fini(void *handle) 1143 { 1144 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1145 1146 /* enable the doorbell aperture */ 1147 vi_enable_doorbell_aperture(adev, false); 1148 1149 if (amdgpu_sriov_vf(adev)) 1150 xgpu_vi_mailbox_put_irq(adev); 1151 1152 return 0; 1153 } 1154 1155 static int vi_common_suspend(void *handle) 1156 { 1157 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1158 1159 return vi_common_hw_fini(adev); 1160 } 1161 1162 static int vi_common_resume(void *handle) 1163 { 1164 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1165 1166 return vi_common_hw_init(adev); 1167 } 1168 1169 static bool vi_common_is_idle(void *handle) 1170 { 1171 return true; 1172 } 1173 1174 static int vi_common_wait_for_idle(void *handle) 1175 { 1176 return 0; 1177 } 1178 1179 static int vi_common_soft_reset(void *handle) 1180 { 1181 return 0; 1182 } 1183 1184 static void vi_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev, 1185 bool enable) 1186 { 1187 uint32_t temp, data; 1188 1189 temp = data = RREG32_PCIE(ixPCIE_CNTL2); 1190 1191 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) 1192 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 1193 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 1194 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK; 1195 else 1196 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 1197 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 1198 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 1199 1200 if (temp != data) 1201 WREG32_PCIE(ixPCIE_CNTL2, data); 1202 } 1203 1204 static void vi_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev, 1205 bool enable) 1206 { 1207 uint32_t temp, data; 1208 1209 temp = data = RREG32(mmHDP_HOST_PATH_CNTL); 1210 1211 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 1212 data &= ~HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK; 1213 else 1214 data |= HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK; 1215 1216 if (temp != data) 1217 WREG32(mmHDP_HOST_PATH_CNTL, data); 1218 } 1219 1220 static void vi_update_hdp_light_sleep(struct amdgpu_device *adev, 1221 bool enable) 1222 { 1223 uint32_t temp, data; 1224 1225 temp = data = RREG32(mmHDP_MEM_POWER_LS); 1226 1227 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 1228 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK; 1229 else 1230 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK; 1231 1232 if (temp != data) 1233 WREG32(mmHDP_MEM_POWER_LS, data); 1234 } 1235 1236 static void vi_update_drm_light_sleep(struct amdgpu_device *adev, 1237 bool enable) 1238 { 1239 uint32_t temp, data; 1240 1241 temp = data = RREG32(0x157a); 1242 1243 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) 1244 data |= 1; 1245 else 1246 data &= ~1; 1247 1248 if (temp != data) 1249 WREG32(0x157a, data); 1250 } 1251 1252 1253 static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev, 1254 bool enable) 1255 { 1256 uint32_t temp, data; 1257 1258 temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0); 1259 1260 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG)) 1261 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | 1262 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK); 1263 else 1264 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | 1265 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK; 1266 1267 if (temp != data) 1268 WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data); 1269 } 1270 1271 static int vi_common_set_clockgating_state_by_smu(void *handle, 1272 enum amd_clockgating_state state) 1273 { 1274 uint32_t msg_id, pp_state = 0; 1275 uint32_t pp_support_state = 0; 1276 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1277 void *pp_handle = adev->powerplay.pp_handle; 1278 1279 if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) { 1280 if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) { 1281 pp_support_state = AMD_CG_SUPPORT_MC_LS; 1282 pp_state = PP_STATE_LS; 1283 } 1284 if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) { 1285 pp_support_state |= AMD_CG_SUPPORT_MC_MGCG; 1286 pp_state |= PP_STATE_CG; 1287 } 1288 if (state == AMD_CG_STATE_UNGATE) 1289 pp_state = 0; 1290 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1291 PP_BLOCK_SYS_MC, 1292 pp_support_state, 1293 pp_state); 1294 amd_set_clockgating_by_smu(pp_handle, msg_id); 1295 } 1296 1297 if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) { 1298 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS) { 1299 pp_support_state = AMD_CG_SUPPORT_SDMA_LS; 1300 pp_state = PP_STATE_LS; 1301 } 1302 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG) { 1303 pp_support_state |= AMD_CG_SUPPORT_SDMA_MGCG; 1304 pp_state |= PP_STATE_CG; 1305 } 1306 if (state == AMD_CG_STATE_UNGATE) 1307 pp_state = 0; 1308 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1309 PP_BLOCK_SYS_SDMA, 1310 pp_support_state, 1311 pp_state); 1312 amd_set_clockgating_by_smu(pp_handle, msg_id); 1313 } 1314 1315 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) { 1316 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { 1317 pp_support_state = AMD_CG_SUPPORT_HDP_LS; 1318 pp_state = PP_STATE_LS; 1319 } 1320 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG) { 1321 pp_support_state |= AMD_CG_SUPPORT_HDP_MGCG; 1322 pp_state |= PP_STATE_CG; 1323 } 1324 if (state == AMD_CG_STATE_UNGATE) 1325 pp_state = 0; 1326 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1327 PP_BLOCK_SYS_HDP, 1328 pp_support_state, 1329 pp_state); 1330 amd_set_clockgating_by_smu(pp_handle, msg_id); 1331 } 1332 1333 1334 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS) { 1335 if (state == AMD_CG_STATE_UNGATE) 1336 pp_state = 0; 1337 else 1338 pp_state = PP_STATE_LS; 1339 1340 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1341 PP_BLOCK_SYS_BIF, 1342 PP_STATE_SUPPORT_LS, 1343 pp_state); 1344 amd_set_clockgating_by_smu(pp_handle, msg_id); 1345 } 1346 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) { 1347 if (state == AMD_CG_STATE_UNGATE) 1348 pp_state = 0; 1349 else 1350 pp_state = PP_STATE_CG; 1351 1352 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1353 PP_BLOCK_SYS_BIF, 1354 PP_STATE_SUPPORT_CG, 1355 pp_state); 1356 amd_set_clockgating_by_smu(pp_handle, msg_id); 1357 } 1358 1359 if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) { 1360 1361 if (state == AMD_CG_STATE_UNGATE) 1362 pp_state = 0; 1363 else 1364 pp_state = PP_STATE_LS; 1365 1366 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1367 PP_BLOCK_SYS_DRM, 1368 PP_STATE_SUPPORT_LS, 1369 pp_state); 1370 amd_set_clockgating_by_smu(pp_handle, msg_id); 1371 } 1372 1373 if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) { 1374 1375 if (state == AMD_CG_STATE_UNGATE) 1376 pp_state = 0; 1377 else 1378 pp_state = PP_STATE_CG; 1379 1380 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS, 1381 PP_BLOCK_SYS_ROM, 1382 PP_STATE_SUPPORT_CG, 1383 pp_state); 1384 amd_set_clockgating_by_smu(pp_handle, msg_id); 1385 } 1386 return 0; 1387 } 1388 1389 static int vi_common_set_clockgating_state(void *handle, 1390 enum amd_clockgating_state state) 1391 { 1392 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1393 1394 switch (adev->asic_type) { 1395 case CHIP_FIJI: 1396 vi_update_bif_medium_grain_light_sleep(adev, 1397 state == AMD_CG_STATE_GATE ? true : false); 1398 vi_update_hdp_medium_grain_clock_gating(adev, 1399 state == AMD_CG_STATE_GATE ? true : false); 1400 vi_update_hdp_light_sleep(adev, 1401 state == AMD_CG_STATE_GATE ? true : false); 1402 vi_update_rom_medium_grain_clock_gating(adev, 1403 state == AMD_CG_STATE_GATE ? true : false); 1404 break; 1405 case CHIP_CARRIZO: 1406 case CHIP_STONEY: 1407 vi_update_bif_medium_grain_light_sleep(adev, 1408 state == AMD_CG_STATE_GATE ? true : false); 1409 vi_update_hdp_medium_grain_clock_gating(adev, 1410 state == AMD_CG_STATE_GATE ? true : false); 1411 vi_update_hdp_light_sleep(adev, 1412 state == AMD_CG_STATE_GATE ? true : false); 1413 vi_update_drm_light_sleep(adev, 1414 state == AMD_CG_STATE_GATE ? true : false); 1415 break; 1416 case CHIP_TONGA: 1417 case CHIP_POLARIS10: 1418 case CHIP_POLARIS11: 1419 case CHIP_POLARIS12: 1420 vi_common_set_clockgating_state_by_smu(adev, state); 1421 default: 1422 break; 1423 } 1424 return 0; 1425 } 1426 1427 static int vi_common_set_powergating_state(void *handle, 1428 enum amd_powergating_state state) 1429 { 1430 return 0; 1431 } 1432 1433 static void vi_common_get_clockgating_state(void *handle, u32 *flags) 1434 { 1435 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1436 int data; 1437 1438 /* AMD_CG_SUPPORT_BIF_LS */ 1439 data = RREG32_PCIE(ixPCIE_CNTL2); 1440 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) 1441 *flags |= AMD_CG_SUPPORT_BIF_LS; 1442 1443 /* AMD_CG_SUPPORT_HDP_LS */ 1444 data = RREG32(mmHDP_MEM_POWER_LS); 1445 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK) 1446 *flags |= AMD_CG_SUPPORT_HDP_LS; 1447 1448 /* AMD_CG_SUPPORT_HDP_MGCG */ 1449 data = RREG32(mmHDP_HOST_PATH_CNTL); 1450 if (!(data & HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK)) 1451 *flags |= AMD_CG_SUPPORT_HDP_MGCG; 1452 1453 /* AMD_CG_SUPPORT_ROM_MGCG */ 1454 data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0); 1455 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK)) 1456 *flags |= AMD_CG_SUPPORT_ROM_MGCG; 1457 } 1458 1459 static const struct amd_ip_funcs vi_common_ip_funcs = { 1460 .name = "vi_common", 1461 .early_init = vi_common_early_init, 1462 .late_init = vi_common_late_init, 1463 .sw_init = vi_common_sw_init, 1464 .sw_fini = vi_common_sw_fini, 1465 .hw_init = vi_common_hw_init, 1466 .hw_fini = vi_common_hw_fini, 1467 .suspend = vi_common_suspend, 1468 .resume = vi_common_resume, 1469 .is_idle = vi_common_is_idle, 1470 .wait_for_idle = vi_common_wait_for_idle, 1471 .soft_reset = vi_common_soft_reset, 1472 .set_clockgating_state = vi_common_set_clockgating_state, 1473 .set_powergating_state = vi_common_set_powergating_state, 1474 .get_clockgating_state = vi_common_get_clockgating_state, 1475 }; 1476 1477 static const struct amdgpu_ip_block_version vi_common_ip_block = 1478 { 1479 .type = AMD_IP_BLOCK_TYPE_COMMON, 1480 .major = 1, 1481 .minor = 0, 1482 .rev = 0, 1483 .funcs = &vi_common_ip_funcs, 1484 }; 1485 1486 int vi_set_ip_blocks(struct amdgpu_device *adev) 1487 { 1488 /* in early init stage, vbios code won't work */ 1489 vi_detect_hw_virtualization(adev); 1490 1491 if (amdgpu_sriov_vf(adev)) 1492 adev->virt.ops = &xgpu_vi_virt_ops; 1493 1494 switch (adev->asic_type) { 1495 case CHIP_TOPAZ: 1496 /* topaz has no DCE, UVD, VCE */ 1497 amdgpu_ip_block_add(adev, &vi_common_ip_block); 1498 amdgpu_ip_block_add(adev, &gmc_v7_4_ip_block); 1499 amdgpu_ip_block_add(adev, &iceland_ih_ip_block); 1500 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); 1501 if (adev->enable_virtual_display) 1502 amdgpu_ip_block_add(adev, &dce_virtual_ip_block); 1503 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block); 1504 amdgpu_ip_block_add(adev, &sdma_v2_4_ip_block); 1505 break; 1506 case CHIP_FIJI: 1507 amdgpu_ip_block_add(adev, &vi_common_ip_block); 1508 amdgpu_ip_block_add(adev, &gmc_v8_5_ip_block); 1509 amdgpu_ip_block_add(adev, &tonga_ih_ip_block); 1510 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); 1511 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 1512 amdgpu_ip_block_add(adev, &dce_virtual_ip_block); 1513 else 1514 amdgpu_ip_block_add(adev, &dce_v10_1_ip_block); 1515 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block); 1516 amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block); 1517 if (!amdgpu_sriov_vf(adev)) { 1518 amdgpu_ip_block_add(adev, &uvd_v6_0_ip_block); 1519 amdgpu_ip_block_add(adev, &vce_v3_0_ip_block); 1520 } 1521 break; 1522 case CHIP_TONGA: 1523 amdgpu_ip_block_add(adev, &vi_common_ip_block); 1524 amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block); 1525 amdgpu_ip_block_add(adev, &tonga_ih_ip_block); 1526 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); 1527 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 1528 amdgpu_ip_block_add(adev, &dce_virtual_ip_block); 1529 else 1530 amdgpu_ip_block_add(adev, &dce_v10_0_ip_block); 1531 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block); 1532 amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block); 1533 if (!amdgpu_sriov_vf(adev)) { 1534 amdgpu_ip_block_add(adev, &uvd_v5_0_ip_block); 1535 amdgpu_ip_block_add(adev, &vce_v3_0_ip_block); 1536 } 1537 break; 1538 case CHIP_POLARIS11: 1539 case CHIP_POLARIS10: 1540 case CHIP_POLARIS12: 1541 amdgpu_ip_block_add(adev, &vi_common_ip_block); 1542 amdgpu_ip_block_add(adev, &gmc_v8_1_ip_block); 1543 amdgpu_ip_block_add(adev, &tonga_ih_ip_block); 1544 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); 1545 if (adev->enable_virtual_display) 1546 amdgpu_ip_block_add(adev, &dce_virtual_ip_block); 1547 else 1548 amdgpu_ip_block_add(adev, &dce_v11_2_ip_block); 1549 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block); 1550 amdgpu_ip_block_add(adev, &sdma_v3_1_ip_block); 1551 amdgpu_ip_block_add(adev, &uvd_v6_3_ip_block); 1552 amdgpu_ip_block_add(adev, &vce_v3_4_ip_block); 1553 break; 1554 case CHIP_CARRIZO: 1555 amdgpu_ip_block_add(adev, &vi_common_ip_block); 1556 amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block); 1557 amdgpu_ip_block_add(adev, &cz_ih_ip_block); 1558 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); 1559 if (adev->enable_virtual_display) 1560 amdgpu_ip_block_add(adev, &dce_virtual_ip_block); 1561 else 1562 amdgpu_ip_block_add(adev, &dce_v11_0_ip_block); 1563 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block); 1564 amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block); 1565 amdgpu_ip_block_add(adev, &uvd_v6_0_ip_block); 1566 amdgpu_ip_block_add(adev, &vce_v3_1_ip_block); 1567 #if defined(CONFIG_DRM_AMD_ACP) 1568 amdgpu_ip_block_add(adev, &acp_ip_block); 1569 #endif 1570 break; 1571 case CHIP_STONEY: 1572 amdgpu_ip_block_add(adev, &vi_common_ip_block); 1573 amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block); 1574 amdgpu_ip_block_add(adev, &cz_ih_ip_block); 1575 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); 1576 if (adev->enable_virtual_display) 1577 amdgpu_ip_block_add(adev, &dce_virtual_ip_block); 1578 else 1579 amdgpu_ip_block_add(adev, &dce_v11_0_ip_block); 1580 amdgpu_ip_block_add(adev, &gfx_v8_1_ip_block); 1581 amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block); 1582 amdgpu_ip_block_add(adev, &uvd_v6_2_ip_block); 1583 amdgpu_ip_block_add(adev, &vce_v3_4_ip_block); 1584 #if defined(CONFIG_DRM_AMD_ACP) 1585 amdgpu_ip_block_add(adev, &acp_ip_block); 1586 #endif 1587 break; 1588 default: 1589 /* FIXME: not supported yet */ 1590 return -EINVAL; 1591 } 1592 1593 return 0; 1594 } 1595