1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include "drmP.h" 27 #include "amdgpu.h" 28 #include "amdgpu_atombios.h" 29 #include "amdgpu_ih.h" 30 #include "amdgpu_uvd.h" 31 #include "amdgpu_vce.h" 32 #include "amdgpu_ucode.h" 33 #include "atom.h" 34 #include "amd_pcie.h" 35 36 #include "gmc/gmc_8_1_d.h" 37 #include "gmc/gmc_8_1_sh_mask.h" 38 39 #include "oss/oss_3_0_d.h" 40 #include "oss/oss_3_0_sh_mask.h" 41 42 #include "bif/bif_5_0_d.h" 43 #include "bif/bif_5_0_sh_mask.h" 44 45 #include "gca/gfx_8_0_d.h" 46 #include "gca/gfx_8_0_sh_mask.h" 47 48 #include "smu/smu_7_1_1_d.h" 49 #include "smu/smu_7_1_1_sh_mask.h" 50 51 #include "uvd/uvd_5_0_d.h" 52 #include "uvd/uvd_5_0_sh_mask.h" 53 54 #include "vce/vce_3_0_d.h" 55 #include "vce/vce_3_0_sh_mask.h" 56 57 #include "dce/dce_10_0_d.h" 58 #include "dce/dce_10_0_sh_mask.h" 59 60 #include "vid.h" 61 #include "vi.h" 62 #include "vi_dpm.h" 63 #include "gmc_v8_0.h" 64 #include "gmc_v7_0.h" 65 #include "gfx_v8_0.h" 66 #include "sdma_v2_4.h" 67 #include "sdma_v3_0.h" 68 #include "dce_v10_0.h" 69 #include "dce_v11_0.h" 70 #include "iceland_ih.h" 71 #include "tonga_ih.h" 72 #include "cz_ih.h" 73 #include "uvd_v5_0.h" 74 #include "uvd_v6_0.h" 75 #include "vce_v3_0.h" 76 #include "amdgpu_powerplay.h" 77 #if defined(CONFIG_DRM_AMD_ACP) 78 #include "amdgpu_acp.h" 79 #endif 80 81 MODULE_FIRMWARE("amdgpu/polaris10_smc.bin"); 82 MODULE_FIRMWARE("amdgpu/polaris10_smc_sk.bin"); 83 MODULE_FIRMWARE("amdgpu/polaris11_smc.bin"); 84 MODULE_FIRMWARE("amdgpu/polaris11_smc_sk.bin"); 85 86 /* 87 * Indirect registers accessor 88 */ 89 static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg) 90 { 91 unsigned long flags; 92 u32 r; 93 94 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 95 WREG32(mmPCIE_INDEX, reg); 96 (void)RREG32(mmPCIE_INDEX); 97 r = RREG32(mmPCIE_DATA); 98 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 99 return r; 100 } 101 102 static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 103 { 104 unsigned long flags; 105 106 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 107 WREG32(mmPCIE_INDEX, reg); 108 (void)RREG32(mmPCIE_INDEX); 109 WREG32(mmPCIE_DATA, v); 110 (void)RREG32(mmPCIE_DATA); 111 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 112 } 113 114 static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg) 115 { 116 unsigned long flags; 117 u32 r; 118 119 spin_lock_irqsave(&adev->smc_idx_lock, flags); 120 WREG32(mmSMC_IND_INDEX_0, (reg)); 121 r = RREG32(mmSMC_IND_DATA_0); 122 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 123 return r; 124 } 125 126 static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 127 { 128 unsigned long flags; 129 130 spin_lock_irqsave(&adev->smc_idx_lock, flags); 131 WREG32(mmSMC_IND_INDEX_0, (reg)); 132 WREG32(mmSMC_IND_DATA_0, (v)); 133 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 134 } 135 136 /* smu_8_0_d.h */ 137 #define mmMP0PUB_IND_INDEX 0x180 138 #define mmMP0PUB_IND_DATA 0x181 139 140 static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg) 141 { 142 unsigned long flags; 143 u32 r; 144 145 spin_lock_irqsave(&adev->smc_idx_lock, flags); 146 WREG32(mmMP0PUB_IND_INDEX, (reg)); 147 r = RREG32(mmMP0PUB_IND_DATA); 148 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 149 return r; 150 } 151 152 static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 153 { 154 unsigned long flags; 155 156 spin_lock_irqsave(&adev->smc_idx_lock, flags); 157 WREG32(mmMP0PUB_IND_INDEX, (reg)); 158 WREG32(mmMP0PUB_IND_DATA, (v)); 159 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 160 } 161 162 static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) 163 { 164 unsigned long flags; 165 u32 r; 166 167 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 168 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); 169 r = RREG32(mmUVD_CTX_DATA); 170 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 171 return r; 172 } 173 174 static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 175 { 176 unsigned long flags; 177 178 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 179 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); 180 WREG32(mmUVD_CTX_DATA, (v)); 181 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 182 } 183 184 static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg) 185 { 186 unsigned long flags; 187 u32 r; 188 189 spin_lock_irqsave(&adev->didt_idx_lock, flags); 190 WREG32(mmDIDT_IND_INDEX, (reg)); 191 r = RREG32(mmDIDT_IND_DATA); 192 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 193 return r; 194 } 195 196 static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 197 { 198 unsigned long flags; 199 200 spin_lock_irqsave(&adev->didt_idx_lock, flags); 201 WREG32(mmDIDT_IND_INDEX, (reg)); 202 WREG32(mmDIDT_IND_DATA, (v)); 203 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 204 } 205 206 static const u32 tonga_mgcg_cgcg_init[] = 207 { 208 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100, 209 mmPCIE_INDEX, 0xffffffff, 0x0140001c, 210 mmPCIE_DATA, 0x000f0000, 0x00000000, 211 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C, 212 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100, 213 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 214 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 215 }; 216 217 static const u32 fiji_mgcg_cgcg_init[] = 218 { 219 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100, 220 mmPCIE_INDEX, 0xffffffff, 0x0140001c, 221 mmPCIE_DATA, 0x000f0000, 0x00000000, 222 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C, 223 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100, 224 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 225 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 226 }; 227 228 static const u32 iceland_mgcg_cgcg_init[] = 229 { 230 mmPCIE_INDEX, 0xffffffff, ixPCIE_CNTL2, 231 mmPCIE_DATA, 0x000f0000, 0x00000000, 232 mmSMC_IND_INDEX_4, 0xffffffff, ixCGTT_ROM_CLK_CTRL0, 233 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100, 234 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 235 }; 236 237 static const u32 cz_mgcg_cgcg_init[] = 238 { 239 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100, 240 mmPCIE_INDEX, 0xffffffff, 0x0140001c, 241 mmPCIE_DATA, 0x000f0000, 0x00000000, 242 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 243 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 244 }; 245 246 static const u32 stoney_mgcg_cgcg_init[] = 247 { 248 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00000100, 249 mmHDP_XDP_CGTT_BLK_CTRL, 0xffffffff, 0x00000104, 250 mmHDP_HOST_PATH_CNTL, 0xffffffff, 0x0f000027, 251 }; 252 253 static void vi_init_golden_registers(struct amdgpu_device *adev) 254 { 255 /* Some of the registers might be dependent on GRBM_GFX_INDEX */ 256 mutex_lock(&adev->grbm_idx_mutex); 257 258 switch (adev->asic_type) { 259 case CHIP_TOPAZ: 260 amdgpu_program_register_sequence(adev, 261 iceland_mgcg_cgcg_init, 262 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init)); 263 break; 264 case CHIP_FIJI: 265 amdgpu_program_register_sequence(adev, 266 fiji_mgcg_cgcg_init, 267 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); 268 break; 269 case CHIP_TONGA: 270 amdgpu_program_register_sequence(adev, 271 tonga_mgcg_cgcg_init, 272 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); 273 break; 274 case CHIP_CARRIZO: 275 amdgpu_program_register_sequence(adev, 276 cz_mgcg_cgcg_init, 277 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); 278 break; 279 case CHIP_STONEY: 280 amdgpu_program_register_sequence(adev, 281 stoney_mgcg_cgcg_init, 282 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); 283 break; 284 case CHIP_POLARIS11: 285 case CHIP_POLARIS10: 286 default: 287 break; 288 } 289 mutex_unlock(&adev->grbm_idx_mutex); 290 } 291 292 /** 293 * vi_get_xclk - get the xclk 294 * 295 * @adev: amdgpu_device pointer 296 * 297 * Returns the reference clock used by the gfx engine 298 * (VI). 299 */ 300 static u32 vi_get_xclk(struct amdgpu_device *adev) 301 { 302 u32 reference_clock = adev->clock.spll.reference_freq; 303 u32 tmp; 304 305 if (adev->flags & AMD_IS_APU) 306 return reference_clock; 307 308 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2); 309 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK)) 310 return 1000; 311 312 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL); 313 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE)) 314 return reference_clock / 4; 315 316 return reference_clock; 317 } 318 319 /** 320 * vi_srbm_select - select specific register instances 321 * 322 * @adev: amdgpu_device pointer 323 * @me: selected ME (micro engine) 324 * @pipe: pipe 325 * @queue: queue 326 * @vmid: VMID 327 * 328 * Switches the currently active registers instances. Some 329 * registers are instanced per VMID, others are instanced per 330 * me/pipe/queue combination. 331 */ 332 void vi_srbm_select(struct amdgpu_device *adev, 333 u32 me, u32 pipe, u32 queue, u32 vmid) 334 { 335 u32 srbm_gfx_cntl = 0; 336 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe); 337 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me); 338 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid); 339 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, QUEUEID, queue); 340 WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl); 341 } 342 343 static void vi_vga_set_state(struct amdgpu_device *adev, bool state) 344 { 345 /* todo */ 346 } 347 348 static bool vi_read_disabled_bios(struct amdgpu_device *adev) 349 { 350 u32 bus_cntl; 351 u32 d1vga_control = 0; 352 u32 d2vga_control = 0; 353 u32 vga_render_control = 0; 354 u32 rom_cntl; 355 bool r; 356 357 bus_cntl = RREG32(mmBUS_CNTL); 358 if (adev->mode_info.num_crtc) { 359 d1vga_control = RREG32(mmD1VGA_CONTROL); 360 d2vga_control = RREG32(mmD2VGA_CONTROL); 361 vga_render_control = RREG32(mmVGA_RENDER_CONTROL); 362 } 363 rom_cntl = RREG32_SMC(ixROM_CNTL); 364 365 /* enable the rom */ 366 WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK)); 367 if (adev->mode_info.num_crtc) { 368 /* Disable VGA mode */ 369 WREG32(mmD1VGA_CONTROL, 370 (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK | 371 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK))); 372 WREG32(mmD2VGA_CONTROL, 373 (d2vga_control & ~(D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK | 374 D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK))); 375 WREG32(mmVGA_RENDER_CONTROL, 376 (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK)); 377 } 378 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK); 379 380 r = amdgpu_read_bios(adev); 381 382 /* restore regs */ 383 WREG32(mmBUS_CNTL, bus_cntl); 384 if (adev->mode_info.num_crtc) { 385 WREG32(mmD1VGA_CONTROL, d1vga_control); 386 WREG32(mmD2VGA_CONTROL, d2vga_control); 387 WREG32(mmVGA_RENDER_CONTROL, vga_render_control); 388 } 389 WREG32_SMC(ixROM_CNTL, rom_cntl); 390 return r; 391 } 392 393 static bool vi_read_bios_from_rom(struct amdgpu_device *adev, 394 u8 *bios, u32 length_bytes) 395 { 396 u32 *dw_ptr; 397 unsigned long flags; 398 u32 i, length_dw; 399 400 if (bios == NULL) 401 return false; 402 if (length_bytes == 0) 403 return false; 404 /* APU vbios image is part of sbios image */ 405 if (adev->flags & AMD_IS_APU) 406 return false; 407 408 dw_ptr = (u32 *)bios; 409 length_dw = ALIGN(length_bytes, 4) / 4; 410 /* take the smc lock since we are using the smc index */ 411 spin_lock_irqsave(&adev->smc_idx_lock, flags); 412 /* set rom index to 0 */ 413 WREG32(mmSMC_IND_INDEX_0, ixROM_INDEX); 414 WREG32(mmSMC_IND_DATA_0, 0); 415 /* set index to data for continous read */ 416 WREG32(mmSMC_IND_INDEX_0, ixROM_DATA); 417 for (i = 0; i < length_dw; i++) 418 dw_ptr[i] = RREG32(mmSMC_IND_DATA_0); 419 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 420 421 return true; 422 } 423 424 static u32 vi_get_virtual_caps(struct amdgpu_device *adev) 425 { 426 u32 caps = 0; 427 u32 reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER); 428 429 if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, IOV_ENABLE)) 430 caps |= AMDGPU_VIRT_CAPS_SRIOV_EN; 431 432 if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, FUNC_IDENTIFIER)) 433 caps |= AMDGPU_VIRT_CAPS_IS_VF; 434 435 return caps; 436 } 437 438 static const struct amdgpu_allowed_register_entry tonga_allowed_read_registers[] = { 439 {mmGB_MACROTILE_MODE7, true}, 440 }; 441 442 static const struct amdgpu_allowed_register_entry cz_allowed_read_registers[] = { 443 {mmGB_TILE_MODE7, true}, 444 {mmGB_TILE_MODE12, true}, 445 {mmGB_TILE_MODE17, true}, 446 {mmGB_TILE_MODE23, true}, 447 {mmGB_MACROTILE_MODE7, true}, 448 }; 449 450 static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = { 451 {mmGRBM_STATUS, false}, 452 {mmGRBM_STATUS2, false}, 453 {mmGRBM_STATUS_SE0, false}, 454 {mmGRBM_STATUS_SE1, false}, 455 {mmGRBM_STATUS_SE2, false}, 456 {mmGRBM_STATUS_SE3, false}, 457 {mmSRBM_STATUS, false}, 458 {mmSRBM_STATUS2, false}, 459 {mmSRBM_STATUS3, false}, 460 {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET, false}, 461 {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET, false}, 462 {mmCP_STAT, false}, 463 {mmCP_STALLED_STAT1, false}, 464 {mmCP_STALLED_STAT2, false}, 465 {mmCP_STALLED_STAT3, false}, 466 {mmCP_CPF_BUSY_STAT, false}, 467 {mmCP_CPF_STALLED_STAT1, false}, 468 {mmCP_CPF_STATUS, false}, 469 {mmCP_CPC_BUSY_STAT, false}, 470 {mmCP_CPC_STALLED_STAT1, false}, 471 {mmCP_CPC_STATUS, false}, 472 {mmGB_ADDR_CONFIG, false}, 473 {mmMC_ARB_RAMCFG, false}, 474 {mmGB_TILE_MODE0, false}, 475 {mmGB_TILE_MODE1, false}, 476 {mmGB_TILE_MODE2, false}, 477 {mmGB_TILE_MODE3, false}, 478 {mmGB_TILE_MODE4, false}, 479 {mmGB_TILE_MODE5, false}, 480 {mmGB_TILE_MODE6, false}, 481 {mmGB_TILE_MODE7, false}, 482 {mmGB_TILE_MODE8, false}, 483 {mmGB_TILE_MODE9, false}, 484 {mmGB_TILE_MODE10, false}, 485 {mmGB_TILE_MODE11, false}, 486 {mmGB_TILE_MODE12, false}, 487 {mmGB_TILE_MODE13, false}, 488 {mmGB_TILE_MODE14, false}, 489 {mmGB_TILE_MODE15, false}, 490 {mmGB_TILE_MODE16, false}, 491 {mmGB_TILE_MODE17, false}, 492 {mmGB_TILE_MODE18, false}, 493 {mmGB_TILE_MODE19, false}, 494 {mmGB_TILE_MODE20, false}, 495 {mmGB_TILE_MODE21, false}, 496 {mmGB_TILE_MODE22, false}, 497 {mmGB_TILE_MODE23, false}, 498 {mmGB_TILE_MODE24, false}, 499 {mmGB_TILE_MODE25, false}, 500 {mmGB_TILE_MODE26, false}, 501 {mmGB_TILE_MODE27, false}, 502 {mmGB_TILE_MODE28, false}, 503 {mmGB_TILE_MODE29, false}, 504 {mmGB_TILE_MODE30, false}, 505 {mmGB_TILE_MODE31, false}, 506 {mmGB_MACROTILE_MODE0, false}, 507 {mmGB_MACROTILE_MODE1, false}, 508 {mmGB_MACROTILE_MODE2, false}, 509 {mmGB_MACROTILE_MODE3, false}, 510 {mmGB_MACROTILE_MODE4, false}, 511 {mmGB_MACROTILE_MODE5, false}, 512 {mmGB_MACROTILE_MODE6, false}, 513 {mmGB_MACROTILE_MODE7, false}, 514 {mmGB_MACROTILE_MODE8, false}, 515 {mmGB_MACROTILE_MODE9, false}, 516 {mmGB_MACROTILE_MODE10, false}, 517 {mmGB_MACROTILE_MODE11, false}, 518 {mmGB_MACROTILE_MODE12, false}, 519 {mmGB_MACROTILE_MODE13, false}, 520 {mmGB_MACROTILE_MODE14, false}, 521 {mmGB_MACROTILE_MODE15, false}, 522 {mmCC_RB_BACKEND_DISABLE, false, true}, 523 {mmGC_USER_RB_BACKEND_DISABLE, false, true}, 524 {mmGB_BACKEND_MAP, false, false}, 525 {mmPA_SC_RASTER_CONFIG, false, true}, 526 {mmPA_SC_RASTER_CONFIG_1, false, true}, 527 }; 528 529 static uint32_t vi_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 530 u32 sh_num, u32 reg_offset) 531 { 532 uint32_t val; 533 534 mutex_lock(&adev->grbm_idx_mutex); 535 if (se_num != 0xffffffff || sh_num != 0xffffffff) 536 gfx_v8_0_select_se_sh(adev, se_num, sh_num); 537 538 val = RREG32(reg_offset); 539 540 if (se_num != 0xffffffff || sh_num != 0xffffffff) 541 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff); 542 mutex_unlock(&adev->grbm_idx_mutex); 543 return val; 544 } 545 546 static int vi_read_register(struct amdgpu_device *adev, u32 se_num, 547 u32 sh_num, u32 reg_offset, u32 *value) 548 { 549 const struct amdgpu_allowed_register_entry *asic_register_table = NULL; 550 const struct amdgpu_allowed_register_entry *asic_register_entry; 551 uint32_t size, i; 552 553 *value = 0; 554 switch (adev->asic_type) { 555 case CHIP_TOPAZ: 556 asic_register_table = tonga_allowed_read_registers; 557 size = ARRAY_SIZE(tonga_allowed_read_registers); 558 break; 559 case CHIP_FIJI: 560 case CHIP_TONGA: 561 case CHIP_POLARIS11: 562 case CHIP_POLARIS10: 563 case CHIP_CARRIZO: 564 case CHIP_STONEY: 565 asic_register_table = cz_allowed_read_registers; 566 size = ARRAY_SIZE(cz_allowed_read_registers); 567 break; 568 default: 569 return -EINVAL; 570 } 571 572 if (asic_register_table) { 573 for (i = 0; i < size; i++) { 574 asic_register_entry = asic_register_table + i; 575 if (reg_offset != asic_register_entry->reg_offset) 576 continue; 577 if (!asic_register_entry->untouched) 578 *value = asic_register_entry->grbm_indexed ? 579 vi_read_indexed_register(adev, se_num, 580 sh_num, reg_offset) : 581 RREG32(reg_offset); 582 return 0; 583 } 584 } 585 586 for (i = 0; i < ARRAY_SIZE(vi_allowed_read_registers); i++) { 587 if (reg_offset != vi_allowed_read_registers[i].reg_offset) 588 continue; 589 590 if (!vi_allowed_read_registers[i].untouched) 591 *value = vi_allowed_read_registers[i].grbm_indexed ? 592 vi_read_indexed_register(adev, se_num, 593 sh_num, reg_offset) : 594 RREG32(reg_offset); 595 return 0; 596 } 597 return -EINVAL; 598 } 599 600 static void vi_gpu_pci_config_reset(struct amdgpu_device *adev) 601 { 602 u32 i; 603 604 dev_info(adev->dev, "GPU pci config reset\n"); 605 606 /* disable BM */ 607 pci_clear_master(adev->pdev); 608 /* reset */ 609 amdgpu_pci_config_reset(adev); 610 611 udelay(100); 612 613 /* wait for asic to come out of reset */ 614 for (i = 0; i < adev->usec_timeout; i++) { 615 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) 616 break; 617 udelay(1); 618 } 619 620 } 621 622 static void vi_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hung) 623 { 624 u32 tmp = RREG32(mmBIOS_SCRATCH_3); 625 626 if (hung) 627 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG; 628 else 629 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG; 630 631 WREG32(mmBIOS_SCRATCH_3, tmp); 632 } 633 634 /** 635 * vi_asic_reset - soft reset GPU 636 * 637 * @adev: amdgpu_device pointer 638 * 639 * Look up which blocks are hung and attempt 640 * to reset them. 641 * Returns 0 for success. 642 */ 643 static int vi_asic_reset(struct amdgpu_device *adev) 644 { 645 vi_set_bios_scratch_engine_hung(adev, true); 646 647 vi_gpu_pci_config_reset(adev); 648 649 vi_set_bios_scratch_engine_hung(adev, false); 650 651 return 0; 652 } 653 654 static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock, 655 u32 cntl_reg, u32 status_reg) 656 { 657 int r, i; 658 struct atom_clock_dividers dividers; 659 uint32_t tmp; 660 661 r = amdgpu_atombios_get_clock_dividers(adev, 662 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 663 clock, false, ÷rs); 664 if (r) 665 return r; 666 667 tmp = RREG32_SMC(cntl_reg); 668 tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK | 669 CG_DCLK_CNTL__DCLK_DIVIDER_MASK); 670 tmp |= dividers.post_divider; 671 WREG32_SMC(cntl_reg, tmp); 672 673 for (i = 0; i < 100; i++) { 674 if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK) 675 break; 676 mdelay(10); 677 } 678 if (i == 100) 679 return -ETIMEDOUT; 680 681 return 0; 682 } 683 684 static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 685 { 686 int r; 687 688 r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); 689 if (r) 690 return r; 691 692 r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); 693 694 return 0; 695 } 696 697 static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 698 { 699 /* todo */ 700 701 return 0; 702 } 703 704 static void vi_pcie_gen3_enable(struct amdgpu_device *adev) 705 { 706 if (pci_is_root_bus(adev->pdev->bus)) 707 return; 708 709 if (amdgpu_pcie_gen2 == 0) 710 return; 711 712 if (adev->flags & AMD_IS_APU) 713 return; 714 715 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 716 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 717 return; 718 719 /* todo */ 720 } 721 722 static void vi_program_aspm(struct amdgpu_device *adev) 723 { 724 725 if (amdgpu_aspm == 0) 726 return; 727 728 /* todo */ 729 } 730 731 static void vi_enable_doorbell_aperture(struct amdgpu_device *adev, 732 bool enable) 733 { 734 u32 tmp; 735 736 /* not necessary on CZ */ 737 if (adev->flags & AMD_IS_APU) 738 return; 739 740 tmp = RREG32(mmBIF_DOORBELL_APER_EN); 741 if (enable) 742 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1); 743 else 744 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0); 745 746 WREG32(mmBIF_DOORBELL_APER_EN, tmp); 747 } 748 749 /* topaz has no DCE, UVD, VCE */ 750 static const struct amdgpu_ip_block_version topaz_ip_blocks[] = 751 { 752 /* ORDER MATTERS! */ 753 { 754 .type = AMD_IP_BLOCK_TYPE_COMMON, 755 .major = 2, 756 .minor = 0, 757 .rev = 0, 758 .funcs = &vi_common_ip_funcs, 759 }, 760 { 761 .type = AMD_IP_BLOCK_TYPE_GMC, 762 .major = 7, 763 .minor = 4, 764 .rev = 0, 765 .funcs = &gmc_v7_0_ip_funcs, 766 }, 767 { 768 .type = AMD_IP_BLOCK_TYPE_IH, 769 .major = 2, 770 .minor = 4, 771 .rev = 0, 772 .funcs = &iceland_ih_ip_funcs, 773 }, 774 { 775 .type = AMD_IP_BLOCK_TYPE_SMC, 776 .major = 7, 777 .minor = 1, 778 .rev = 0, 779 .funcs = &amdgpu_pp_ip_funcs, 780 }, 781 { 782 .type = AMD_IP_BLOCK_TYPE_GFX, 783 .major = 8, 784 .minor = 0, 785 .rev = 0, 786 .funcs = &gfx_v8_0_ip_funcs, 787 }, 788 { 789 .type = AMD_IP_BLOCK_TYPE_SDMA, 790 .major = 2, 791 .minor = 4, 792 .rev = 0, 793 .funcs = &sdma_v2_4_ip_funcs, 794 }, 795 }; 796 797 static const struct amdgpu_ip_block_version tonga_ip_blocks[] = 798 { 799 /* ORDER MATTERS! */ 800 { 801 .type = AMD_IP_BLOCK_TYPE_COMMON, 802 .major = 2, 803 .minor = 0, 804 .rev = 0, 805 .funcs = &vi_common_ip_funcs, 806 }, 807 { 808 .type = AMD_IP_BLOCK_TYPE_GMC, 809 .major = 8, 810 .minor = 0, 811 .rev = 0, 812 .funcs = &gmc_v8_0_ip_funcs, 813 }, 814 { 815 .type = AMD_IP_BLOCK_TYPE_IH, 816 .major = 3, 817 .minor = 0, 818 .rev = 0, 819 .funcs = &tonga_ih_ip_funcs, 820 }, 821 { 822 .type = AMD_IP_BLOCK_TYPE_SMC, 823 .major = 7, 824 .minor = 1, 825 .rev = 0, 826 .funcs = &amdgpu_pp_ip_funcs, 827 }, 828 { 829 .type = AMD_IP_BLOCK_TYPE_DCE, 830 .major = 10, 831 .minor = 0, 832 .rev = 0, 833 .funcs = &dce_v10_0_ip_funcs, 834 }, 835 { 836 .type = AMD_IP_BLOCK_TYPE_GFX, 837 .major = 8, 838 .minor = 0, 839 .rev = 0, 840 .funcs = &gfx_v8_0_ip_funcs, 841 }, 842 { 843 .type = AMD_IP_BLOCK_TYPE_SDMA, 844 .major = 3, 845 .minor = 0, 846 .rev = 0, 847 .funcs = &sdma_v3_0_ip_funcs, 848 }, 849 { 850 .type = AMD_IP_BLOCK_TYPE_UVD, 851 .major = 5, 852 .minor = 0, 853 .rev = 0, 854 .funcs = &uvd_v5_0_ip_funcs, 855 }, 856 { 857 .type = AMD_IP_BLOCK_TYPE_VCE, 858 .major = 3, 859 .minor = 0, 860 .rev = 0, 861 .funcs = &vce_v3_0_ip_funcs, 862 }, 863 }; 864 865 static const struct amdgpu_ip_block_version fiji_ip_blocks[] = 866 { 867 /* ORDER MATTERS! */ 868 { 869 .type = AMD_IP_BLOCK_TYPE_COMMON, 870 .major = 2, 871 .minor = 0, 872 .rev = 0, 873 .funcs = &vi_common_ip_funcs, 874 }, 875 { 876 .type = AMD_IP_BLOCK_TYPE_GMC, 877 .major = 8, 878 .minor = 5, 879 .rev = 0, 880 .funcs = &gmc_v8_0_ip_funcs, 881 }, 882 { 883 .type = AMD_IP_BLOCK_TYPE_IH, 884 .major = 3, 885 .minor = 0, 886 .rev = 0, 887 .funcs = &tonga_ih_ip_funcs, 888 }, 889 { 890 .type = AMD_IP_BLOCK_TYPE_SMC, 891 .major = 7, 892 .minor = 1, 893 .rev = 0, 894 .funcs = &amdgpu_pp_ip_funcs, 895 }, 896 { 897 .type = AMD_IP_BLOCK_TYPE_DCE, 898 .major = 10, 899 .minor = 1, 900 .rev = 0, 901 .funcs = &dce_v10_0_ip_funcs, 902 }, 903 { 904 .type = AMD_IP_BLOCK_TYPE_GFX, 905 .major = 8, 906 .minor = 0, 907 .rev = 0, 908 .funcs = &gfx_v8_0_ip_funcs, 909 }, 910 { 911 .type = AMD_IP_BLOCK_TYPE_SDMA, 912 .major = 3, 913 .minor = 0, 914 .rev = 0, 915 .funcs = &sdma_v3_0_ip_funcs, 916 }, 917 { 918 .type = AMD_IP_BLOCK_TYPE_UVD, 919 .major = 6, 920 .minor = 0, 921 .rev = 0, 922 .funcs = &uvd_v6_0_ip_funcs, 923 }, 924 { 925 .type = AMD_IP_BLOCK_TYPE_VCE, 926 .major = 3, 927 .minor = 0, 928 .rev = 0, 929 .funcs = &vce_v3_0_ip_funcs, 930 }, 931 }; 932 933 static const struct amdgpu_ip_block_version polaris11_ip_blocks[] = 934 { 935 /* ORDER MATTERS! */ 936 { 937 .type = AMD_IP_BLOCK_TYPE_COMMON, 938 .major = 2, 939 .minor = 0, 940 .rev = 0, 941 .funcs = &vi_common_ip_funcs, 942 }, 943 { 944 .type = AMD_IP_BLOCK_TYPE_GMC, 945 .major = 8, 946 .minor = 1, 947 .rev = 0, 948 .funcs = &gmc_v8_0_ip_funcs, 949 }, 950 { 951 .type = AMD_IP_BLOCK_TYPE_IH, 952 .major = 3, 953 .minor = 1, 954 .rev = 0, 955 .funcs = &tonga_ih_ip_funcs, 956 }, 957 { 958 .type = AMD_IP_BLOCK_TYPE_SMC, 959 .major = 7, 960 .minor = 2, 961 .rev = 0, 962 .funcs = &amdgpu_pp_ip_funcs, 963 }, 964 { 965 .type = AMD_IP_BLOCK_TYPE_DCE, 966 .major = 11, 967 .minor = 2, 968 .rev = 0, 969 .funcs = &dce_v11_0_ip_funcs, 970 }, 971 { 972 .type = AMD_IP_BLOCK_TYPE_GFX, 973 .major = 8, 974 .minor = 0, 975 .rev = 0, 976 .funcs = &gfx_v8_0_ip_funcs, 977 }, 978 { 979 .type = AMD_IP_BLOCK_TYPE_SDMA, 980 .major = 3, 981 .minor = 1, 982 .rev = 0, 983 .funcs = &sdma_v3_0_ip_funcs, 984 }, 985 { 986 .type = AMD_IP_BLOCK_TYPE_UVD, 987 .major = 6, 988 .minor = 3, 989 .rev = 0, 990 .funcs = &uvd_v6_0_ip_funcs, 991 }, 992 { 993 .type = AMD_IP_BLOCK_TYPE_VCE, 994 .major = 3, 995 .minor = 4, 996 .rev = 0, 997 .funcs = &vce_v3_0_ip_funcs, 998 }, 999 }; 1000 1001 static const struct amdgpu_ip_block_version cz_ip_blocks[] = 1002 { 1003 /* ORDER MATTERS! */ 1004 { 1005 .type = AMD_IP_BLOCK_TYPE_COMMON, 1006 .major = 2, 1007 .minor = 0, 1008 .rev = 0, 1009 .funcs = &vi_common_ip_funcs, 1010 }, 1011 { 1012 .type = AMD_IP_BLOCK_TYPE_GMC, 1013 .major = 8, 1014 .minor = 0, 1015 .rev = 0, 1016 .funcs = &gmc_v8_0_ip_funcs, 1017 }, 1018 { 1019 .type = AMD_IP_BLOCK_TYPE_IH, 1020 .major = 3, 1021 .minor = 0, 1022 .rev = 0, 1023 .funcs = &cz_ih_ip_funcs, 1024 }, 1025 { 1026 .type = AMD_IP_BLOCK_TYPE_SMC, 1027 .major = 8, 1028 .minor = 0, 1029 .rev = 0, 1030 .funcs = &amdgpu_pp_ip_funcs 1031 }, 1032 { 1033 .type = AMD_IP_BLOCK_TYPE_DCE, 1034 .major = 11, 1035 .minor = 0, 1036 .rev = 0, 1037 .funcs = &dce_v11_0_ip_funcs, 1038 }, 1039 { 1040 .type = AMD_IP_BLOCK_TYPE_GFX, 1041 .major = 8, 1042 .minor = 0, 1043 .rev = 0, 1044 .funcs = &gfx_v8_0_ip_funcs, 1045 }, 1046 { 1047 .type = AMD_IP_BLOCK_TYPE_SDMA, 1048 .major = 3, 1049 .minor = 0, 1050 .rev = 0, 1051 .funcs = &sdma_v3_0_ip_funcs, 1052 }, 1053 { 1054 .type = AMD_IP_BLOCK_TYPE_UVD, 1055 .major = 6, 1056 .minor = 0, 1057 .rev = 0, 1058 .funcs = &uvd_v6_0_ip_funcs, 1059 }, 1060 { 1061 .type = AMD_IP_BLOCK_TYPE_VCE, 1062 .major = 3, 1063 .minor = 0, 1064 .rev = 0, 1065 .funcs = &vce_v3_0_ip_funcs, 1066 }, 1067 #if defined(CONFIG_DRM_AMD_ACP) 1068 { 1069 .type = AMD_IP_BLOCK_TYPE_ACP, 1070 .major = 2, 1071 .minor = 2, 1072 .rev = 0, 1073 .funcs = &acp_ip_funcs, 1074 }, 1075 #endif 1076 }; 1077 1078 int vi_set_ip_blocks(struct amdgpu_device *adev) 1079 { 1080 switch (adev->asic_type) { 1081 case CHIP_TOPAZ: 1082 adev->ip_blocks = topaz_ip_blocks; 1083 adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks); 1084 break; 1085 case CHIP_FIJI: 1086 adev->ip_blocks = fiji_ip_blocks; 1087 adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks); 1088 break; 1089 case CHIP_TONGA: 1090 adev->ip_blocks = tonga_ip_blocks; 1091 adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks); 1092 break; 1093 case CHIP_POLARIS11: 1094 case CHIP_POLARIS10: 1095 adev->ip_blocks = polaris11_ip_blocks; 1096 adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks); 1097 break; 1098 case CHIP_CARRIZO: 1099 case CHIP_STONEY: 1100 adev->ip_blocks = cz_ip_blocks; 1101 adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks); 1102 break; 1103 default: 1104 /* FIXME: not supported yet */ 1105 return -EINVAL; 1106 } 1107 1108 return 0; 1109 } 1110 1111 #define ATI_REV_ID_FUSE_MACRO__ADDRESS 0xC0014044 1112 #define ATI_REV_ID_FUSE_MACRO__SHIFT 9 1113 #define ATI_REV_ID_FUSE_MACRO__MASK 0x00001E00 1114 1115 static uint32_t vi_get_rev_id(struct amdgpu_device *adev) 1116 { 1117 if (adev->flags & AMD_IS_APU) 1118 return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK) 1119 >> ATI_REV_ID_FUSE_MACRO__SHIFT; 1120 else 1121 return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK) 1122 >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT; 1123 } 1124 1125 static const struct amdgpu_asic_funcs vi_asic_funcs = 1126 { 1127 .read_disabled_bios = &vi_read_disabled_bios, 1128 .read_bios_from_rom = &vi_read_bios_from_rom, 1129 .read_register = &vi_read_register, 1130 .reset = &vi_asic_reset, 1131 .set_vga_state = &vi_vga_set_state, 1132 .get_xclk = &vi_get_xclk, 1133 .set_uvd_clocks = &vi_set_uvd_clocks, 1134 .set_vce_clocks = &vi_set_vce_clocks, 1135 .get_virtual_caps = &vi_get_virtual_caps, 1136 /* these should be moved to their own ip modules */ 1137 .get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter, 1138 .wait_for_mc_idle = &gmc_v8_0_mc_wait_for_idle, 1139 }; 1140 1141 static int vi_common_early_init(void *handle) 1142 { 1143 bool smc_enabled = false; 1144 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1145 1146 if (adev->flags & AMD_IS_APU) { 1147 adev->smc_rreg = &cz_smc_rreg; 1148 adev->smc_wreg = &cz_smc_wreg; 1149 } else { 1150 adev->smc_rreg = &vi_smc_rreg; 1151 adev->smc_wreg = &vi_smc_wreg; 1152 } 1153 adev->pcie_rreg = &vi_pcie_rreg; 1154 adev->pcie_wreg = &vi_pcie_wreg; 1155 adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg; 1156 adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg; 1157 adev->didt_rreg = &vi_didt_rreg; 1158 adev->didt_wreg = &vi_didt_wreg; 1159 1160 adev->asic_funcs = &vi_asic_funcs; 1161 1162 if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC) && 1163 (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_SMC))) 1164 smc_enabled = true; 1165 1166 adev->rev_id = vi_get_rev_id(adev); 1167 adev->external_rev_id = 0xFF; 1168 switch (adev->asic_type) { 1169 case CHIP_TOPAZ: 1170 adev->cg_flags = 0; 1171 adev->pg_flags = 0; 1172 adev->external_rev_id = 0x1; 1173 break; 1174 case CHIP_FIJI: 1175 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1176 AMD_CG_SUPPORT_GFX_MGLS | 1177 AMD_CG_SUPPORT_GFX_RLC_LS | 1178 AMD_CG_SUPPORT_GFX_CP_LS | 1179 AMD_CG_SUPPORT_GFX_CGTS | 1180 AMD_CG_SUPPORT_GFX_CGTS_LS | 1181 AMD_CG_SUPPORT_GFX_CGCG | 1182 AMD_CG_SUPPORT_GFX_CGLS | 1183 AMD_CG_SUPPORT_SDMA_MGCG | 1184 AMD_CG_SUPPORT_SDMA_LS | 1185 AMD_CG_SUPPORT_BIF_LS | 1186 AMD_CG_SUPPORT_HDP_MGCG | 1187 AMD_CG_SUPPORT_HDP_LS | 1188 AMD_CG_SUPPORT_ROM_MGCG | 1189 AMD_CG_SUPPORT_MC_MGCG | 1190 AMD_CG_SUPPORT_MC_LS; 1191 adev->pg_flags = 0; 1192 adev->external_rev_id = adev->rev_id + 0x3c; 1193 break; 1194 case CHIP_TONGA: 1195 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG; 1196 adev->pg_flags = 0; 1197 adev->external_rev_id = adev->rev_id + 0x14; 1198 break; 1199 case CHIP_POLARIS11: 1200 adev->cg_flags = 0; 1201 adev->pg_flags = 0; 1202 adev->external_rev_id = adev->rev_id + 0x5A; 1203 break; 1204 case CHIP_POLARIS10: 1205 adev->cg_flags = 0; 1206 adev->pg_flags = 0; 1207 adev->external_rev_id = adev->rev_id + 0x50; 1208 break; 1209 case CHIP_CARRIZO: 1210 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG | 1211 AMD_CG_SUPPORT_GFX_MGCG | 1212 AMD_CG_SUPPORT_GFX_MGLS | 1213 AMD_CG_SUPPORT_GFX_RLC_LS | 1214 AMD_CG_SUPPORT_GFX_CP_LS | 1215 AMD_CG_SUPPORT_GFX_CGTS | 1216 AMD_CG_SUPPORT_GFX_MGLS | 1217 AMD_CG_SUPPORT_GFX_CGTS_LS | 1218 AMD_CG_SUPPORT_GFX_CGCG | 1219 AMD_CG_SUPPORT_GFX_CGLS | 1220 AMD_CG_SUPPORT_BIF_LS | 1221 AMD_CG_SUPPORT_HDP_MGCG | 1222 AMD_CG_SUPPORT_HDP_LS | 1223 AMD_CG_SUPPORT_SDMA_MGCG | 1224 AMD_CG_SUPPORT_SDMA_LS; 1225 adev->pg_flags = 0; 1226 adev->external_rev_id = adev->rev_id + 0x1; 1227 break; 1228 case CHIP_STONEY: 1229 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG | 1230 AMD_CG_SUPPORT_GFX_MGCG | 1231 AMD_CG_SUPPORT_GFX_MGLS | 1232 AMD_CG_SUPPORT_BIF_LS | 1233 AMD_CG_SUPPORT_HDP_MGCG | 1234 AMD_CG_SUPPORT_HDP_LS | 1235 AMD_CG_SUPPORT_SDMA_MGCG | 1236 AMD_CG_SUPPORT_SDMA_LS; 1237 adev->pg_flags = 0; 1238 adev->external_rev_id = adev->rev_id + 0x1; 1239 break; 1240 default: 1241 /* FIXME: not supported yet */ 1242 return -EINVAL; 1243 } 1244 1245 if (amdgpu_smc_load_fw && smc_enabled) 1246 adev->firmware.smu_load = true; 1247 1248 amdgpu_get_pcie_info(adev); 1249 1250 return 0; 1251 } 1252 1253 static int vi_common_sw_init(void *handle) 1254 { 1255 return 0; 1256 } 1257 1258 static int vi_common_sw_fini(void *handle) 1259 { 1260 return 0; 1261 } 1262 1263 static int vi_common_hw_init(void *handle) 1264 { 1265 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1266 1267 /* move the golden regs per IP block */ 1268 vi_init_golden_registers(adev); 1269 /* enable pcie gen2/3 link */ 1270 vi_pcie_gen3_enable(adev); 1271 /* enable aspm */ 1272 vi_program_aspm(adev); 1273 /* enable the doorbell aperture */ 1274 vi_enable_doorbell_aperture(adev, true); 1275 1276 return 0; 1277 } 1278 1279 static int vi_common_hw_fini(void *handle) 1280 { 1281 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1282 1283 /* enable the doorbell aperture */ 1284 vi_enable_doorbell_aperture(adev, false); 1285 1286 return 0; 1287 } 1288 1289 static int vi_common_suspend(void *handle) 1290 { 1291 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1292 1293 return vi_common_hw_fini(adev); 1294 } 1295 1296 static int vi_common_resume(void *handle) 1297 { 1298 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1299 1300 return vi_common_hw_init(adev); 1301 } 1302 1303 static bool vi_common_is_idle(void *handle) 1304 { 1305 return true; 1306 } 1307 1308 static int vi_common_wait_for_idle(void *handle) 1309 { 1310 return 0; 1311 } 1312 1313 static int vi_common_soft_reset(void *handle) 1314 { 1315 return 0; 1316 } 1317 1318 static void vi_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev, 1319 bool enable) 1320 { 1321 uint32_t temp, data; 1322 1323 temp = data = RREG32_PCIE(ixPCIE_CNTL2); 1324 1325 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) 1326 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 1327 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 1328 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK; 1329 else 1330 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 1331 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 1332 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 1333 1334 if (temp != data) 1335 WREG32_PCIE(ixPCIE_CNTL2, data); 1336 } 1337 1338 static void vi_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev, 1339 bool enable) 1340 { 1341 uint32_t temp, data; 1342 1343 temp = data = RREG32(mmHDP_HOST_PATH_CNTL); 1344 1345 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 1346 data &= ~HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK; 1347 else 1348 data |= HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK; 1349 1350 if (temp != data) 1351 WREG32(mmHDP_HOST_PATH_CNTL, data); 1352 } 1353 1354 static void vi_update_hdp_light_sleep(struct amdgpu_device *adev, 1355 bool enable) 1356 { 1357 uint32_t temp, data; 1358 1359 temp = data = RREG32(mmHDP_MEM_POWER_LS); 1360 1361 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 1362 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK; 1363 else 1364 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK; 1365 1366 if (temp != data) 1367 WREG32(mmHDP_MEM_POWER_LS, data); 1368 } 1369 1370 static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev, 1371 bool enable) 1372 { 1373 uint32_t temp, data; 1374 1375 temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0); 1376 1377 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG)) 1378 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | 1379 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK); 1380 else 1381 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | 1382 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK; 1383 1384 if (temp != data) 1385 WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data); 1386 } 1387 1388 static int vi_common_set_clockgating_state(void *handle, 1389 enum amd_clockgating_state state) 1390 { 1391 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1392 1393 switch (adev->asic_type) { 1394 case CHIP_FIJI: 1395 vi_update_bif_medium_grain_light_sleep(adev, 1396 state == AMD_CG_STATE_GATE ? true : false); 1397 vi_update_hdp_medium_grain_clock_gating(adev, 1398 state == AMD_CG_STATE_GATE ? true : false); 1399 vi_update_hdp_light_sleep(adev, 1400 state == AMD_CG_STATE_GATE ? true : false); 1401 vi_update_rom_medium_grain_clock_gating(adev, 1402 state == AMD_CG_STATE_GATE ? true : false); 1403 break; 1404 case CHIP_CARRIZO: 1405 case CHIP_STONEY: 1406 vi_update_bif_medium_grain_light_sleep(adev, 1407 state == AMD_CG_STATE_GATE ? true : false); 1408 vi_update_hdp_medium_grain_clock_gating(adev, 1409 state == AMD_CG_STATE_GATE ? true : false); 1410 vi_update_hdp_light_sleep(adev, 1411 state == AMD_CG_STATE_GATE ? true : false); 1412 break; 1413 default: 1414 break; 1415 } 1416 return 0; 1417 } 1418 1419 static int vi_common_set_powergating_state(void *handle, 1420 enum amd_powergating_state state) 1421 { 1422 return 0; 1423 } 1424 1425 const struct amd_ip_funcs vi_common_ip_funcs = { 1426 .name = "vi_common", 1427 .early_init = vi_common_early_init, 1428 .late_init = NULL, 1429 .sw_init = vi_common_sw_init, 1430 .sw_fini = vi_common_sw_fini, 1431 .hw_init = vi_common_hw_init, 1432 .hw_fini = vi_common_hw_fini, 1433 .suspend = vi_common_suspend, 1434 .resume = vi_common_resume, 1435 .is_idle = vi_common_is_idle, 1436 .wait_for_idle = vi_common_wait_for_idle, 1437 .soft_reset = vi_common_soft_reset, 1438 .set_clockgating_state = vi_common_set_clockgating_state, 1439 .set_powergating_state = vi_common_set_powergating_state, 1440 }; 1441 1442