1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 #include "soc15.h" 29 30 #include "oss/osssys_4_2_0_offset.h" 31 #include "oss/osssys_4_2_0_sh_mask.h" 32 33 #include "soc15_common.h" 34 #include "vega20_ih.h" 35 36 #define MAX_REARM_RETRY 10 37 38 #define mmIH_CHICKEN_ALDEBARAN 0x18d 39 #define mmIH_CHICKEN_ALDEBARAN_BASE_IDX 0 40 41 static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev); 42 43 /** 44 * vega20_ih_init_register_offset - Initialize register offset for ih rings 45 * 46 * @adev: amdgpu_device pointer 47 * 48 * Initialize register offset ih rings (VEGA20). 49 */ 50 static void vega20_ih_init_register_offset(struct amdgpu_device *adev) 51 { 52 struct amdgpu_ih_regs *ih_regs; 53 54 if (adev->irq.ih.ring_size) { 55 ih_regs = &adev->irq.ih.ih_regs; 56 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 57 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 58 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 59 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 60 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 61 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 62 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 63 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 64 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 65 } 66 67 if (adev->irq.ih1.ring_size) { 68 ih_regs = &adev->irq.ih1.ih_regs; 69 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 70 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 71 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 72 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 73 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 74 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 75 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 76 } 77 78 if (adev->irq.ih2.ring_size) { 79 ih_regs = &adev->irq.ih2.ih_regs; 80 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 81 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 82 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 83 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 84 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 85 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 86 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 87 } 88 } 89 90 /** 91 * vega20_ih_toggle_ring_interrupts - toggle the interrupt ring buffer 92 * 93 * @adev: amdgpu_device pointer 94 * @ih: amdgpu_ih_ring pointer 95 * @enable: true - enable the interrupts, false - disable the interrupts 96 * 97 * Toggle the interrupt ring buffer (VEGA20) 98 */ 99 static int vega20_ih_toggle_ring_interrupts(struct amdgpu_device *adev, 100 struct amdgpu_ih_ring *ih, 101 bool enable) 102 { 103 struct amdgpu_ih_regs *ih_regs; 104 uint32_t tmp; 105 106 ih_regs = &ih->ih_regs; 107 108 tmp = RREG32(ih_regs->ih_rb_cntl); 109 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); 110 /* enable_intr field is only valid in ring0 */ 111 if (ih == &adev->irq.ih) 112 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); 113 if (amdgpu_sriov_vf(adev)) { 114 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 115 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 116 return -ETIMEDOUT; 117 } 118 } else { 119 WREG32(ih_regs->ih_rb_cntl, tmp); 120 } 121 122 if (enable) { 123 ih->enabled = true; 124 } else { 125 /* set rptr, wptr to 0 */ 126 WREG32(ih_regs->ih_rb_rptr, 0); 127 WREG32(ih_regs->ih_rb_wptr, 0); 128 ih->enabled = false; 129 ih->rptr = 0; 130 } 131 132 return 0; 133 } 134 135 /** 136 * vega20_ih_toggle_interrupts - Toggle all the available interrupt ring buffers 137 * 138 * @adev: amdgpu_device pointer 139 * @enable: enable or disable interrupt ring buffers 140 * 141 * Toggle all the available interrupt ring buffers (VEGA20). 142 */ 143 static int vega20_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable) 144 { 145 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 146 int i; 147 int r; 148 149 for (i = 0; i < ARRAY_SIZE(ih); i++) { 150 if (ih[i]->ring_size) { 151 r = vega20_ih_toggle_ring_interrupts(adev, ih[i], enable); 152 if (r) 153 return r; 154 } 155 } 156 157 return 0; 158 } 159 160 static uint32_t vega20_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 161 { 162 int rb_bufsz = order_base_2(ih->ring_size / 4); 163 164 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 165 MC_SPACE, ih->use_bus_addr ? 1 : 4); 166 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 167 WPTR_OVERFLOW_CLEAR, 1); 168 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 169 WPTR_OVERFLOW_ENABLE, 1); 170 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 171 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 172 * value is written to memory 173 */ 174 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 175 WPTR_WRITEBACK_ENABLE, 1); 176 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 177 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 178 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 179 180 return ih_rb_cntl; 181 } 182 183 static uint32_t vega20_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 184 { 185 u32 ih_doorbell_rtpr = 0; 186 187 if (ih->use_doorbell) { 188 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 189 IH_DOORBELL_RPTR, OFFSET, 190 ih->doorbell_index); 191 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 192 IH_DOORBELL_RPTR, 193 ENABLE, 1); 194 } else { 195 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 196 IH_DOORBELL_RPTR, 197 ENABLE, 0); 198 } 199 return ih_doorbell_rtpr; 200 } 201 202 /** 203 * vega20_ih_enable_ring - enable an ih ring buffer 204 * 205 * @adev: amdgpu_device pointer 206 * @ih: amdgpu_ih_ring pointer 207 * 208 * Enable an ih ring buffer (VEGA20) 209 */ 210 static int vega20_ih_enable_ring(struct amdgpu_device *adev, 211 struct amdgpu_ih_ring *ih) 212 { 213 struct amdgpu_ih_regs *ih_regs; 214 uint32_t tmp; 215 216 ih_regs = &ih->ih_regs; 217 218 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 219 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 220 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 221 222 tmp = RREG32(ih_regs->ih_rb_cntl); 223 tmp = vega20_ih_rb_cntl(ih, tmp); 224 if (ih == &adev->irq.ih) 225 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 226 if (ih == &adev->irq.ih1) { 227 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0); 228 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 229 } 230 if (amdgpu_sriov_vf(adev)) { 231 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 232 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 233 return -ETIMEDOUT; 234 } 235 } else { 236 WREG32(ih_regs->ih_rb_cntl, tmp); 237 } 238 239 if (ih == &adev->irq.ih) { 240 /* set the ih ring 0 writeback address whether it's enabled or not */ 241 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 242 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 243 } 244 245 /* set rptr, wptr to 0 */ 246 WREG32(ih_regs->ih_rb_wptr, 0); 247 WREG32(ih_regs->ih_rb_rptr, 0); 248 249 WREG32(ih_regs->ih_doorbell_rptr, vega20_ih_doorbell_rptr(ih)); 250 251 return 0; 252 } 253 254 /** 255 * vega20_ih_reroute_ih - reroute VMC/UTCL2 ih to an ih ring 256 * 257 * @adev: amdgpu_device pointer 258 * 259 * Reroute VMC and UMC interrupts on primary ih ring to 260 * ih ring 1 so they won't lose when bunches of page faults 261 * interrupts overwhelms the interrupt handler(VEGA20) 262 */ 263 static void vega20_ih_reroute_ih(struct amdgpu_device *adev) 264 { 265 uint32_t tmp; 266 267 /* vega20 ih reroute will go through psp 268 * this function is only used for arcturus 269 */ 270 if (adev->asic_type == CHIP_ARCTURUS) { 271 /* Reroute to IH ring 1 for VMC */ 272 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x12); 273 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 274 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 275 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 276 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 277 278 /* Reroute IH ring 1 for UTCL2 */ 279 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x1B); 280 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 281 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 282 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 283 } 284 } 285 286 /** 287 * vega20_ih_irq_init - init and enable the interrupt ring 288 * 289 * @adev: amdgpu_device pointer 290 * 291 * Allocate a ring buffer for the interrupt controller, 292 * enable the RLC, disable interrupts, enable the IH 293 * ring buffer and enable it (VI). 294 * Called at device load and reume. 295 * Returns 0 for success, errors for failure. 296 */ 297 static int vega20_ih_irq_init(struct amdgpu_device *adev) 298 { 299 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 300 u32 ih_chicken; 301 int ret; 302 int i; 303 u32 tmp; 304 305 /* disable irqs */ 306 ret = vega20_ih_toggle_interrupts(adev, false); 307 if (ret) 308 return ret; 309 310 adev->nbio.funcs->ih_control(adev); 311 312 if (adev->asic_type == CHIP_ARCTURUS && 313 adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 314 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 315 if (adev->irq.ih.use_bus_addr) { 316 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 317 MC_SPACE_GPA_ENABLE, 1); 318 } 319 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 320 } 321 322 /* psp firmware won't program IH_CHICKEN for aldebaran 323 * driver needs to program it properly according to 324 * MC_SPACE type in IH_RB_CNTL */ 325 if (adev->asic_type == CHIP_ALDEBARAN) { 326 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN); 327 if (adev->irq.ih.use_bus_addr) { 328 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 329 MC_SPACE_GPA_ENABLE, 1); 330 } 331 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN, ih_chicken); 332 } 333 334 for (i = 0; i < ARRAY_SIZE(ih); i++) { 335 if (ih[i]->ring_size) { 336 if (i == 1) 337 vega20_ih_reroute_ih(adev); 338 ret = vega20_ih_enable_ring(adev, ih[i]); 339 if (ret) 340 return ret; 341 } 342 } 343 344 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 345 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 346 CLIENT18_IS_STORM_CLIENT, 1); 347 WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 348 349 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 350 tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 351 WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 352 353 pci_set_master(adev->pdev); 354 355 /* enable interrupts */ 356 ret = vega20_ih_toggle_interrupts(adev, true); 357 if (ret) 358 return ret; 359 360 if (adev->irq.ih_soft.ring_size) 361 adev->irq.ih_soft.enabled = true; 362 363 return 0; 364 } 365 366 /** 367 * vega20_ih_irq_disable - disable interrupts 368 * 369 * @adev: amdgpu_device pointer 370 * 371 * Disable interrupts on the hw (VEGA20). 372 */ 373 static void vega20_ih_irq_disable(struct amdgpu_device *adev) 374 { 375 vega20_ih_toggle_interrupts(adev, false); 376 377 /* Wait and acknowledge irq */ 378 mdelay(1); 379 } 380 381 /** 382 * vega20_ih_get_wptr - get the IH ring buffer wptr 383 * 384 * @adev: amdgpu_device pointer 385 * @ih: amdgpu_ih_ring pointer 386 * 387 * Get the IH ring buffer wptr from either the register 388 * or the writeback memory buffer (VEGA20). Also check for 389 * ring buffer overflow and deal with it. 390 * Returns the value of the wptr. 391 */ 392 static u32 vega20_ih_get_wptr(struct amdgpu_device *adev, 393 struct amdgpu_ih_ring *ih) 394 { 395 u32 wptr, tmp; 396 struct amdgpu_ih_regs *ih_regs; 397 398 wptr = le32_to_cpu(*ih->wptr_cpu); 399 ih_regs = &ih->ih_regs; 400 401 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 402 goto out; 403 404 /* Double check that the overflow wasn't already cleared. */ 405 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); 406 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 407 goto out; 408 409 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 410 411 /* When a ring buffer overflow happen start parsing interrupt 412 * from the last not overwritten vector (wptr + 32). Hopefully 413 * this should allow us to catchup. 414 */ 415 tmp = (wptr + 32) & ih->ptr_mask; 416 dev_warn(adev->dev, "IH ring buffer overflow " 417 "(0x%08X, 0x%08X, 0x%08X)\n", 418 wptr, ih->rptr, tmp); 419 ih->rptr = tmp; 420 421 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); 422 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 423 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 424 425 out: 426 return (wptr & ih->ptr_mask); 427 } 428 429 /** 430 * vega20_ih_irq_rearm - rearm IRQ if lost 431 * 432 * @adev: amdgpu_device pointer 433 * @ih: amdgpu_ih_ring pointer 434 * 435 */ 436 static void vega20_ih_irq_rearm(struct amdgpu_device *adev, 437 struct amdgpu_ih_ring *ih) 438 { 439 uint32_t v = 0; 440 uint32_t i = 0; 441 struct amdgpu_ih_regs *ih_regs; 442 443 ih_regs = &ih->ih_regs; 444 445 /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */ 446 for (i = 0; i < MAX_REARM_RETRY; i++) { 447 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); 448 if ((v < ih->ring_size) && (v != ih->rptr)) 449 WDOORBELL32(ih->doorbell_index, ih->rptr); 450 else 451 break; 452 } 453 } 454 455 /** 456 * vega20_ih_set_rptr - set the IH ring buffer rptr 457 * 458 * @adev: amdgpu_device pointer 459 * @ih: amdgpu_ih_ring pointer 460 * 461 * Set the IH ring buffer rptr. 462 */ 463 static void vega20_ih_set_rptr(struct amdgpu_device *adev, 464 struct amdgpu_ih_ring *ih) 465 { 466 struct amdgpu_ih_regs *ih_regs; 467 468 if (ih->use_doorbell) { 469 /* XXX check if swapping is necessary on BE */ 470 *ih->rptr_cpu = ih->rptr; 471 WDOORBELL32(ih->doorbell_index, ih->rptr); 472 473 if (amdgpu_sriov_vf(adev)) 474 vega20_ih_irq_rearm(adev, ih); 475 } else { 476 ih_regs = &ih->ih_regs; 477 WREG32(ih_regs->ih_rb_rptr, ih->rptr); 478 } 479 } 480 481 /** 482 * vega20_ih_self_irq - dispatch work for ring 1 and 2 483 * 484 * @adev: amdgpu_device pointer 485 * @source: irq source 486 * @entry: IV with WPTR update 487 * 488 * Update the WPTR from the IV and schedule work to handle the entries. 489 */ 490 static int vega20_ih_self_irq(struct amdgpu_device *adev, 491 struct amdgpu_irq_src *source, 492 struct amdgpu_iv_entry *entry) 493 { 494 uint32_t wptr = cpu_to_le32(entry->src_data[0]); 495 496 switch (entry->ring_id) { 497 case 1: 498 *adev->irq.ih1.wptr_cpu = wptr; 499 schedule_work(&adev->irq.ih1_work); 500 break; 501 case 2: 502 *adev->irq.ih2.wptr_cpu = wptr; 503 schedule_work(&adev->irq.ih2_work); 504 break; 505 default: break; 506 } 507 return 0; 508 } 509 510 static const struct amdgpu_irq_src_funcs vega20_ih_self_irq_funcs = { 511 .process = vega20_ih_self_irq, 512 }; 513 514 static void vega20_ih_set_self_irq_funcs(struct amdgpu_device *adev) 515 { 516 adev->irq.self_irq.num_types = 0; 517 adev->irq.self_irq.funcs = &vega20_ih_self_irq_funcs; 518 } 519 520 static int vega20_ih_early_init(void *handle) 521 { 522 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 523 524 vega20_ih_set_interrupt_funcs(adev); 525 vega20_ih_set_self_irq_funcs(adev); 526 return 0; 527 } 528 529 static int vega20_ih_sw_init(void *handle) 530 { 531 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 532 int r; 533 534 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 535 &adev->irq.self_irq); 536 if (r) 537 return r; 538 539 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true); 540 if (r) 541 return r; 542 543 adev->irq.ih.use_doorbell = true; 544 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 545 546 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 547 if (r) 548 return r; 549 550 adev->irq.ih1.use_doorbell = true; 551 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; 552 553 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 554 if (r) 555 return r; 556 557 adev->irq.ih2.use_doorbell = true; 558 adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1; 559 560 /* initialize ih control registers offset */ 561 vega20_ih_init_register_offset(adev); 562 563 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); 564 if (r) 565 return r; 566 567 r = amdgpu_irq_init(adev); 568 569 return r; 570 } 571 572 static int vega20_ih_sw_fini(void *handle) 573 { 574 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 575 576 amdgpu_irq_fini(adev); 577 amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft); 578 amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 579 amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 580 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 581 582 return 0; 583 } 584 585 static int vega20_ih_hw_init(void *handle) 586 { 587 int r; 588 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 589 590 r = vega20_ih_irq_init(adev); 591 if (r) 592 return r; 593 594 return 0; 595 } 596 597 static int vega20_ih_hw_fini(void *handle) 598 { 599 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 600 601 vega20_ih_irq_disable(adev); 602 603 return 0; 604 } 605 606 static int vega20_ih_suspend(void *handle) 607 { 608 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 609 610 return vega20_ih_hw_fini(adev); 611 } 612 613 static int vega20_ih_resume(void *handle) 614 { 615 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 616 617 return vega20_ih_hw_init(adev); 618 } 619 620 static bool vega20_ih_is_idle(void *handle) 621 { 622 /* todo */ 623 return true; 624 } 625 626 static int vega20_ih_wait_for_idle(void *handle) 627 { 628 /* todo */ 629 return -ETIMEDOUT; 630 } 631 632 static int vega20_ih_soft_reset(void *handle) 633 { 634 /* todo */ 635 636 return 0; 637 } 638 639 static void vega20_ih_update_clockgating_state(struct amdgpu_device *adev, 640 bool enable) 641 { 642 uint32_t data, def, field_val; 643 644 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 645 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 646 field_val = enable ? 0 : 1; 647 data = REG_SET_FIELD(data, IH_CLK_CTRL, 648 IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val); 649 data = REG_SET_FIELD(data, IH_CLK_CTRL, 650 IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val); 651 data = REG_SET_FIELD(data, IH_CLK_CTRL, 652 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 653 data = REG_SET_FIELD(data, IH_CLK_CTRL, 654 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 655 data = REG_SET_FIELD(data, IH_CLK_CTRL, 656 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 657 data = REG_SET_FIELD(data, IH_CLK_CTRL, 658 DYN_CLK_SOFT_OVERRIDE, field_val); 659 data = REG_SET_FIELD(data, IH_CLK_CTRL, 660 REG_CLK_SOFT_OVERRIDE, field_val); 661 if (def != data) 662 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 663 } 664 } 665 666 static int vega20_ih_set_clockgating_state(void *handle, 667 enum amd_clockgating_state state) 668 { 669 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 670 671 vega20_ih_update_clockgating_state(adev, 672 state == AMD_CG_STATE_GATE); 673 return 0; 674 675 } 676 677 static int vega20_ih_set_powergating_state(void *handle, 678 enum amd_powergating_state state) 679 { 680 return 0; 681 } 682 683 const struct amd_ip_funcs vega20_ih_ip_funcs = { 684 .name = "vega20_ih", 685 .early_init = vega20_ih_early_init, 686 .late_init = NULL, 687 .sw_init = vega20_ih_sw_init, 688 .sw_fini = vega20_ih_sw_fini, 689 .hw_init = vega20_ih_hw_init, 690 .hw_fini = vega20_ih_hw_fini, 691 .suspend = vega20_ih_suspend, 692 .resume = vega20_ih_resume, 693 .is_idle = vega20_ih_is_idle, 694 .wait_for_idle = vega20_ih_wait_for_idle, 695 .soft_reset = vega20_ih_soft_reset, 696 .set_clockgating_state = vega20_ih_set_clockgating_state, 697 .set_powergating_state = vega20_ih_set_powergating_state, 698 }; 699 700 static const struct amdgpu_ih_funcs vega20_ih_funcs = { 701 .get_wptr = vega20_ih_get_wptr, 702 .decode_iv = amdgpu_ih_decode_iv_helper, 703 .set_rptr = vega20_ih_set_rptr 704 }; 705 706 static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev) 707 { 708 adev->irq.ih_funcs = &vega20_ih_funcs; 709 } 710 711 const struct amdgpu_ip_block_version vega20_ih_ip_block = 712 { 713 .type = AMD_IP_BLOCK_TYPE_IH, 714 .major = 4, 715 .minor = 2, 716 .rev = 0, 717 .funcs = &vega20_ih_ip_funcs, 718 }; 719