1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 #include "soc15.h" 29 30 #include "oss/osssys_4_2_0_offset.h" 31 #include "oss/osssys_4_2_0_sh_mask.h" 32 33 #include "soc15_common.h" 34 #include "vega20_ih.h" 35 36 #define MAX_REARM_RETRY 10 37 38 #define mmIH_CHICKEN_ALDEBARAN 0x18d 39 #define mmIH_CHICKEN_ALDEBARAN_BASE_IDX 0 40 41 #define mmIH_RETRY_INT_CAM_CNTL_ALDEBARAN 0x00ea 42 #define mmIH_RETRY_INT_CAM_CNTL_ALDEBARAN_BASE_IDX 0 43 #define IH_RETRY_INT_CAM_CNTL_ALDEBARAN__ENABLE__SHIFT 0x10 44 #define IH_RETRY_INT_CAM_CNTL_ALDEBARAN__ENABLE_MASK 0x00010000L 45 46 static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev); 47 48 /** 49 * vega20_ih_init_register_offset - Initialize register offset for ih rings 50 * 51 * @adev: amdgpu_device pointer 52 * 53 * Initialize register offset ih rings (VEGA20). 54 */ 55 static void vega20_ih_init_register_offset(struct amdgpu_device *adev) 56 { 57 struct amdgpu_ih_regs *ih_regs; 58 59 if (adev->irq.ih.ring_size) { 60 ih_regs = &adev->irq.ih.ih_regs; 61 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 62 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 63 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 64 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 65 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 66 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 67 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 68 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 69 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 70 } 71 72 if (adev->irq.ih1.ring_size) { 73 ih_regs = &adev->irq.ih1.ih_regs; 74 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 75 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 76 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 77 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 78 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 79 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 80 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 81 } 82 83 if (adev->irq.ih2.ring_size) { 84 ih_regs = &adev->irq.ih2.ih_regs; 85 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 86 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 87 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 88 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 89 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 90 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 91 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 92 } 93 } 94 95 /** 96 * vega20_ih_toggle_ring_interrupts - toggle the interrupt ring buffer 97 * 98 * @adev: amdgpu_device pointer 99 * @ih: amdgpu_ih_ring pointer 100 * @enable: true - enable the interrupts, false - disable the interrupts 101 * 102 * Toggle the interrupt ring buffer (VEGA20) 103 */ 104 static int vega20_ih_toggle_ring_interrupts(struct amdgpu_device *adev, 105 struct amdgpu_ih_ring *ih, 106 bool enable) 107 { 108 struct amdgpu_ih_regs *ih_regs; 109 uint32_t tmp; 110 111 ih_regs = &ih->ih_regs; 112 113 tmp = RREG32(ih_regs->ih_rb_cntl); 114 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); 115 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1); 116 117 /* enable_intr field is only valid in ring0 */ 118 if (ih == &adev->irq.ih) 119 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); 120 if (amdgpu_sriov_vf(adev)) { 121 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 122 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 123 return -ETIMEDOUT; 124 } 125 } else { 126 WREG32(ih_regs->ih_rb_cntl, tmp); 127 } 128 129 if (enable) { 130 ih->enabled = true; 131 } else { 132 /* set rptr, wptr to 0 */ 133 WREG32(ih_regs->ih_rb_rptr, 0); 134 WREG32(ih_regs->ih_rb_wptr, 0); 135 ih->enabled = false; 136 ih->rptr = 0; 137 } 138 139 return 0; 140 } 141 142 /** 143 * vega20_ih_toggle_interrupts - Toggle all the available interrupt ring buffers 144 * 145 * @adev: amdgpu_device pointer 146 * @enable: enable or disable interrupt ring buffers 147 * 148 * Toggle all the available interrupt ring buffers (VEGA20). 149 */ 150 static int vega20_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable) 151 { 152 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 153 int i; 154 int r; 155 156 for (i = 0; i < ARRAY_SIZE(ih); i++) { 157 if (ih[i]->ring_size) { 158 r = vega20_ih_toggle_ring_interrupts(adev, ih[i], enable); 159 if (r) 160 return r; 161 } 162 } 163 164 return 0; 165 } 166 167 static uint32_t vega20_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 168 { 169 int rb_bufsz = order_base_2(ih->ring_size / 4); 170 171 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 172 MC_SPACE, ih->use_bus_addr ? 1 : 4); 173 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 174 WPTR_OVERFLOW_CLEAR, 1); 175 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 176 WPTR_OVERFLOW_ENABLE, 1); 177 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 178 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 179 * value is written to memory 180 */ 181 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 182 WPTR_WRITEBACK_ENABLE, 1); 183 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 184 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 185 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 186 187 return ih_rb_cntl; 188 } 189 190 static uint32_t vega20_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 191 { 192 u32 ih_doorbell_rtpr = 0; 193 194 if (ih->use_doorbell) { 195 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 196 IH_DOORBELL_RPTR, OFFSET, 197 ih->doorbell_index); 198 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 199 IH_DOORBELL_RPTR, 200 ENABLE, 1); 201 } else { 202 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 203 IH_DOORBELL_RPTR, 204 ENABLE, 0); 205 } 206 return ih_doorbell_rtpr; 207 } 208 209 /** 210 * vega20_ih_enable_ring - enable an ih ring buffer 211 * 212 * @adev: amdgpu_device pointer 213 * @ih: amdgpu_ih_ring pointer 214 * 215 * Enable an ih ring buffer (VEGA20) 216 */ 217 static int vega20_ih_enable_ring(struct amdgpu_device *adev, 218 struct amdgpu_ih_ring *ih) 219 { 220 struct amdgpu_ih_regs *ih_regs; 221 uint32_t tmp; 222 223 ih_regs = &ih->ih_regs; 224 225 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 226 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 227 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 228 229 tmp = RREG32(ih_regs->ih_rb_cntl); 230 tmp = vega20_ih_rb_cntl(ih, tmp); 231 if (ih == &adev->irq.ih) 232 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 233 if (ih == &adev->irq.ih1) 234 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 235 if (amdgpu_sriov_vf(adev)) { 236 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 237 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 238 return -ETIMEDOUT; 239 } 240 } else { 241 WREG32(ih_regs->ih_rb_cntl, tmp); 242 } 243 244 if (ih == &adev->irq.ih) { 245 /* set the ih ring 0 writeback address whether it's enabled or not */ 246 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 247 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 248 } 249 250 /* set rptr, wptr to 0 */ 251 WREG32(ih_regs->ih_rb_wptr, 0); 252 WREG32(ih_regs->ih_rb_rptr, 0); 253 254 WREG32(ih_regs->ih_doorbell_rptr, vega20_ih_doorbell_rptr(ih)); 255 256 return 0; 257 } 258 259 static uint32_t vega20_setup_retry_doorbell(u32 doorbell_index) 260 { 261 u32 val = 0; 262 263 val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, OFFSET, doorbell_index); 264 val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, ENABLE, 1); 265 266 return val; 267 } 268 269 /** 270 * vega20_ih_irq_init - init and enable the interrupt ring 271 * 272 * @adev: amdgpu_device pointer 273 * 274 * Allocate a ring buffer for the interrupt controller, 275 * enable the RLC, disable interrupts, enable the IH 276 * ring buffer and enable it (VI). 277 * Called at device load and reume. 278 * Returns 0 for success, errors for failure. 279 */ 280 static int vega20_ih_irq_init(struct amdgpu_device *adev) 281 { 282 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 283 u32 ih_chicken; 284 int ret; 285 int i; 286 287 /* disable irqs */ 288 ret = vega20_ih_toggle_interrupts(adev, false); 289 if (ret) 290 return ret; 291 292 adev->nbio.funcs->ih_control(adev); 293 294 if ((adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 2, 1)) && 295 adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 296 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 297 if (adev->irq.ih.use_bus_addr) { 298 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 299 MC_SPACE_GPA_ENABLE, 1); 300 } 301 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 302 } 303 304 /* psp firmware won't program IH_CHICKEN for aldebaran 305 * driver needs to program it properly according to 306 * MC_SPACE type in IH_RB_CNTL */ 307 if ((adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 0)) || 308 (adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 2))) { 309 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN); 310 if (adev->irq.ih.use_bus_addr) { 311 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 312 MC_SPACE_GPA_ENABLE, 1); 313 } 314 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN, ih_chicken); 315 } 316 317 for (i = 0; i < ARRAY_SIZE(ih); i++) { 318 if (ih[i]->ring_size) { 319 ret = vega20_ih_enable_ring(adev, ih[i]); 320 if (ret) 321 return ret; 322 } 323 } 324 325 if (!amdgpu_sriov_vf(adev)) 326 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, 327 adev->irq.ih.doorbell_index); 328 329 pci_set_master(adev->pdev); 330 331 /* Allocate the doorbell for IH Retry CAM */ 332 adev->irq.retry_cam_doorbell_index = (adev->doorbell_index.ih + 3) << 1; 333 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RETRY_CAM, 334 vega20_setup_retry_doorbell(adev->irq.retry_cam_doorbell_index)); 335 336 /* Enable IH Retry CAM */ 337 if (adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 0)) 338 WREG32_FIELD15(OSSSYS, 0, IH_RETRY_INT_CAM_CNTL_ALDEBARAN, 339 ENABLE, 1); 340 else 341 WREG32_FIELD15(OSSSYS, 0, IH_RETRY_INT_CAM_CNTL, ENABLE, 1); 342 343 adev->irq.retry_cam_enabled = true; 344 345 /* enable interrupts */ 346 ret = vega20_ih_toggle_interrupts(adev, true); 347 if (ret) 348 return ret; 349 350 if (adev->irq.ih_soft.ring_size) 351 adev->irq.ih_soft.enabled = true; 352 353 return 0; 354 } 355 356 /** 357 * vega20_ih_irq_disable - disable interrupts 358 * 359 * @adev: amdgpu_device pointer 360 * 361 * Disable interrupts on the hw (VEGA20). 362 */ 363 static void vega20_ih_irq_disable(struct amdgpu_device *adev) 364 { 365 vega20_ih_toggle_interrupts(adev, false); 366 367 /* Wait and acknowledge irq */ 368 mdelay(1); 369 } 370 371 /** 372 * vega20_ih_get_wptr - get the IH ring buffer wptr 373 * 374 * @adev: amdgpu_device pointer 375 * @ih: amdgpu_ih_ring pointer 376 * 377 * Get the IH ring buffer wptr from either the register 378 * or the writeback memory buffer (VEGA20). Also check for 379 * ring buffer overflow and deal with it. 380 * Returns the value of the wptr. 381 */ 382 static u32 vega20_ih_get_wptr(struct amdgpu_device *adev, 383 struct amdgpu_ih_ring *ih) 384 { 385 u32 wptr, tmp; 386 struct amdgpu_ih_regs *ih_regs; 387 388 if (ih == &adev->irq.ih || ih == &adev->irq.ih_soft) { 389 /* Only ring0 supports writeback. On other rings fall back 390 * to register-based code with overflow checking below. 391 * ih_soft ring doesn't have any backing hardware registers, 392 * update wptr and return. 393 */ 394 wptr = le32_to_cpu(*ih->wptr_cpu); 395 396 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 397 goto out; 398 } 399 400 ih_regs = &ih->ih_regs; 401 402 /* Double check that the overflow wasn't already cleared. */ 403 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); 404 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 405 goto out; 406 407 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 408 409 /* When a ring buffer overflow happen start parsing interrupt 410 * from the last not overwritten vector (wptr + 32). Hopefully 411 * this should allow us to catchup. 412 */ 413 tmp = (wptr + 32) & ih->ptr_mask; 414 dev_warn(adev->dev, "IH ring buffer overflow " 415 "(0x%08X, 0x%08X, 0x%08X)\n", 416 wptr, ih->rptr, tmp); 417 ih->rptr = tmp; 418 419 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); 420 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 421 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 422 423 out: 424 return (wptr & ih->ptr_mask); 425 } 426 427 /** 428 * vega20_ih_irq_rearm - rearm IRQ if lost 429 * 430 * @adev: amdgpu_device pointer 431 * @ih: amdgpu_ih_ring pointer 432 * 433 */ 434 static void vega20_ih_irq_rearm(struct amdgpu_device *adev, 435 struct amdgpu_ih_ring *ih) 436 { 437 uint32_t v = 0; 438 uint32_t i = 0; 439 struct amdgpu_ih_regs *ih_regs; 440 441 ih_regs = &ih->ih_regs; 442 443 /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */ 444 for (i = 0; i < MAX_REARM_RETRY; i++) { 445 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); 446 if ((v < ih->ring_size) && (v != ih->rptr)) 447 WDOORBELL32(ih->doorbell_index, ih->rptr); 448 else 449 break; 450 } 451 } 452 453 /** 454 * vega20_ih_set_rptr - set the IH ring buffer rptr 455 * 456 * @adev: amdgpu_device pointer 457 * @ih: amdgpu_ih_ring pointer 458 * 459 * Set the IH ring buffer rptr. 460 */ 461 static void vega20_ih_set_rptr(struct amdgpu_device *adev, 462 struct amdgpu_ih_ring *ih) 463 { 464 struct amdgpu_ih_regs *ih_regs; 465 466 if (ih == &adev->irq.ih_soft) 467 return; 468 469 if (ih->use_doorbell) { 470 /* XXX check if swapping is necessary on BE */ 471 *ih->rptr_cpu = ih->rptr; 472 WDOORBELL32(ih->doorbell_index, ih->rptr); 473 474 if (amdgpu_sriov_vf(adev)) 475 vega20_ih_irq_rearm(adev, ih); 476 } else { 477 ih_regs = &ih->ih_regs; 478 WREG32(ih_regs->ih_rb_rptr, ih->rptr); 479 } 480 } 481 482 /** 483 * vega20_ih_self_irq - dispatch work for ring 1 and 2 484 * 485 * @adev: amdgpu_device pointer 486 * @source: irq source 487 * @entry: IV with WPTR update 488 * 489 * Update the WPTR from the IV and schedule work to handle the entries. 490 */ 491 static int vega20_ih_self_irq(struct amdgpu_device *adev, 492 struct amdgpu_irq_src *source, 493 struct amdgpu_iv_entry *entry) 494 { 495 switch (entry->ring_id) { 496 case 1: 497 schedule_work(&adev->irq.ih1_work); 498 break; 499 case 2: 500 schedule_work(&adev->irq.ih2_work); 501 break; 502 default: break; 503 } 504 return 0; 505 } 506 507 static const struct amdgpu_irq_src_funcs vega20_ih_self_irq_funcs = { 508 .process = vega20_ih_self_irq, 509 }; 510 511 static void vega20_ih_set_self_irq_funcs(struct amdgpu_device *adev) 512 { 513 adev->irq.self_irq.num_types = 0; 514 adev->irq.self_irq.funcs = &vega20_ih_self_irq_funcs; 515 } 516 517 static int vega20_ih_early_init(void *handle) 518 { 519 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 520 521 vega20_ih_set_interrupt_funcs(adev); 522 vega20_ih_set_self_irq_funcs(adev); 523 return 0; 524 } 525 526 static int vega20_ih_sw_init(void *handle) 527 { 528 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 529 bool use_bus_addr = true; 530 int r; 531 532 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 533 &adev->irq.self_irq); 534 if (r) 535 return r; 536 537 if ((adev->flags & AMD_IS_APU) && 538 (adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 2))) 539 use_bus_addr = false; 540 541 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); 542 if (r) 543 return r; 544 545 adev->irq.ih.use_doorbell = true; 546 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 547 548 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, use_bus_addr); 549 if (r) 550 return r; 551 552 adev->irq.ih1.use_doorbell = true; 553 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; 554 555 if (adev->ip_versions[OSSSYS_HWIP][0] != IP_VERSION(4, 4, 2)) { 556 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 557 if (r) 558 return r; 559 560 adev->irq.ih2.use_doorbell = true; 561 adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1; 562 } 563 564 /* initialize ih control registers offset */ 565 vega20_ih_init_register_offset(adev); 566 567 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, use_bus_addr); 568 if (r) 569 return r; 570 571 r = amdgpu_irq_init(adev); 572 573 return r; 574 } 575 576 static int vega20_ih_sw_fini(void *handle) 577 { 578 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 579 580 amdgpu_irq_fini_sw(adev); 581 582 return 0; 583 } 584 585 static int vega20_ih_hw_init(void *handle) 586 { 587 int r; 588 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 589 590 r = vega20_ih_irq_init(adev); 591 if (r) 592 return r; 593 594 return 0; 595 } 596 597 static int vega20_ih_hw_fini(void *handle) 598 { 599 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 600 601 vega20_ih_irq_disable(adev); 602 603 return 0; 604 } 605 606 static int vega20_ih_suspend(void *handle) 607 { 608 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 609 610 return vega20_ih_hw_fini(adev); 611 } 612 613 static int vega20_ih_resume(void *handle) 614 { 615 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 616 617 return vega20_ih_hw_init(adev); 618 } 619 620 static bool vega20_ih_is_idle(void *handle) 621 { 622 /* todo */ 623 return true; 624 } 625 626 static int vega20_ih_wait_for_idle(void *handle) 627 { 628 /* todo */ 629 return -ETIMEDOUT; 630 } 631 632 static int vega20_ih_soft_reset(void *handle) 633 { 634 /* todo */ 635 636 return 0; 637 } 638 639 static void vega20_ih_update_clockgating_state(struct amdgpu_device *adev, 640 bool enable) 641 { 642 uint32_t data, def, field_val; 643 644 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 645 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 646 field_val = enable ? 0 : 1; 647 data = REG_SET_FIELD(data, IH_CLK_CTRL, 648 IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val); 649 data = REG_SET_FIELD(data, IH_CLK_CTRL, 650 IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val); 651 data = REG_SET_FIELD(data, IH_CLK_CTRL, 652 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 653 data = REG_SET_FIELD(data, IH_CLK_CTRL, 654 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 655 data = REG_SET_FIELD(data, IH_CLK_CTRL, 656 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 657 data = REG_SET_FIELD(data, IH_CLK_CTRL, 658 DYN_CLK_SOFT_OVERRIDE, field_val); 659 data = REG_SET_FIELD(data, IH_CLK_CTRL, 660 REG_CLK_SOFT_OVERRIDE, field_val); 661 if (def != data) 662 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 663 } 664 } 665 666 static int vega20_ih_set_clockgating_state(void *handle, 667 enum amd_clockgating_state state) 668 { 669 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 670 671 vega20_ih_update_clockgating_state(adev, 672 state == AMD_CG_STATE_GATE); 673 return 0; 674 675 } 676 677 static int vega20_ih_set_powergating_state(void *handle, 678 enum amd_powergating_state state) 679 { 680 return 0; 681 } 682 683 const struct amd_ip_funcs vega20_ih_ip_funcs = { 684 .name = "vega20_ih", 685 .early_init = vega20_ih_early_init, 686 .late_init = NULL, 687 .sw_init = vega20_ih_sw_init, 688 .sw_fini = vega20_ih_sw_fini, 689 .hw_init = vega20_ih_hw_init, 690 .hw_fini = vega20_ih_hw_fini, 691 .suspend = vega20_ih_suspend, 692 .resume = vega20_ih_resume, 693 .is_idle = vega20_ih_is_idle, 694 .wait_for_idle = vega20_ih_wait_for_idle, 695 .soft_reset = vega20_ih_soft_reset, 696 .set_clockgating_state = vega20_ih_set_clockgating_state, 697 .set_powergating_state = vega20_ih_set_powergating_state, 698 }; 699 700 static const struct amdgpu_ih_funcs vega20_ih_funcs = { 701 .get_wptr = vega20_ih_get_wptr, 702 .decode_iv = amdgpu_ih_decode_iv_helper, 703 .decode_iv_ts = amdgpu_ih_decode_iv_ts_helper, 704 .set_rptr = vega20_ih_set_rptr 705 }; 706 707 static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev) 708 { 709 adev->irq.ih_funcs = &vega20_ih_funcs; 710 } 711 712 const struct amdgpu_ip_block_version vega20_ih_ip_block = 713 { 714 .type = AMD_IP_BLOCK_TYPE_IH, 715 .major = 4, 716 .minor = 2, 717 .rev = 0, 718 .funcs = &vega20_ih_ip_funcs, 719 }; 720