1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 #include "soc15.h" 29 30 #include "oss/osssys_4_2_0_offset.h" 31 #include "oss/osssys_4_2_0_sh_mask.h" 32 33 #include "soc15_common.h" 34 #include "vega20_ih.h" 35 36 #define MAX_REARM_RETRY 10 37 38 #define mmIH_CHICKEN_ALDEBARAN 0x18d 39 #define mmIH_CHICKEN_ALDEBARAN_BASE_IDX 0 40 41 static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev); 42 43 /** 44 * vega20_ih_init_register_offset - Initialize register offset for ih rings 45 * 46 * @adev: amdgpu_device pointer 47 * 48 * Initialize register offset ih rings (VEGA20). 49 */ 50 static void vega20_ih_init_register_offset(struct amdgpu_device *adev) 51 { 52 struct amdgpu_ih_regs *ih_regs; 53 54 if (adev->irq.ih.ring_size) { 55 ih_regs = &adev->irq.ih.ih_regs; 56 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 57 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 58 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 59 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 60 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 61 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 62 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 63 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 64 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 65 } 66 67 if (adev->irq.ih1.ring_size) { 68 ih_regs = &adev->irq.ih1.ih_regs; 69 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 70 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 71 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 72 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 73 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 74 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 75 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 76 } 77 78 if (adev->irq.ih2.ring_size) { 79 ih_regs = &adev->irq.ih2.ih_regs; 80 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 81 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 82 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 83 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 84 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 85 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 86 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 87 } 88 } 89 90 /** 91 * vega20_ih_toggle_ring_interrupts - toggle the interrupt ring buffer 92 * 93 * @adev: amdgpu_device pointer 94 * @ih: amdgpu_ih_ring pointer 95 * @enable: true - enable the interrupts, false - disable the interrupts 96 * 97 * Toggle the interrupt ring buffer (VEGA20) 98 */ 99 static int vega20_ih_toggle_ring_interrupts(struct amdgpu_device *adev, 100 struct amdgpu_ih_ring *ih, 101 bool enable) 102 { 103 struct amdgpu_ih_regs *ih_regs; 104 uint32_t tmp; 105 106 ih_regs = &ih->ih_regs; 107 108 tmp = RREG32(ih_regs->ih_rb_cntl); 109 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); 110 /* enable_intr field is only valid in ring0 */ 111 if (ih == &adev->irq.ih) 112 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); 113 if (amdgpu_sriov_vf(adev)) { 114 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 115 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 116 return -ETIMEDOUT; 117 } 118 } else { 119 WREG32(ih_regs->ih_rb_cntl, tmp); 120 } 121 122 if (enable) { 123 ih->enabled = true; 124 } else { 125 /* set rptr, wptr to 0 */ 126 WREG32(ih_regs->ih_rb_rptr, 0); 127 WREG32(ih_regs->ih_rb_wptr, 0); 128 ih->enabled = false; 129 ih->rptr = 0; 130 } 131 132 return 0; 133 } 134 135 /** 136 * vega20_ih_toggle_interrupts - Toggle all the available interrupt ring buffers 137 * 138 * @adev: amdgpu_device pointer 139 * @enable: enable or disable interrupt ring buffers 140 * 141 * Toggle all the available interrupt ring buffers (VEGA20). 142 */ 143 static int vega20_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable) 144 { 145 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 146 int i; 147 int r; 148 149 for (i = 0; i < ARRAY_SIZE(ih); i++) { 150 if (ih[i]->ring_size) { 151 r = vega20_ih_toggle_ring_interrupts(adev, ih[i], enable); 152 if (r) 153 return r; 154 } 155 } 156 157 return 0; 158 } 159 160 static uint32_t vega20_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 161 { 162 int rb_bufsz = order_base_2(ih->ring_size / 4); 163 164 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 165 MC_SPACE, ih->use_bus_addr ? 1 : 4); 166 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 167 WPTR_OVERFLOW_CLEAR, 1); 168 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 169 WPTR_OVERFLOW_ENABLE, 1); 170 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 171 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 172 * value is written to memory 173 */ 174 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 175 WPTR_WRITEBACK_ENABLE, 1); 176 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 177 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 178 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 179 180 return ih_rb_cntl; 181 } 182 183 static uint32_t vega20_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 184 { 185 u32 ih_doorbell_rtpr = 0; 186 187 if (ih->use_doorbell) { 188 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 189 IH_DOORBELL_RPTR, OFFSET, 190 ih->doorbell_index); 191 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 192 IH_DOORBELL_RPTR, 193 ENABLE, 1); 194 } else { 195 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 196 IH_DOORBELL_RPTR, 197 ENABLE, 0); 198 } 199 return ih_doorbell_rtpr; 200 } 201 202 /** 203 * vega20_ih_enable_ring - enable an ih ring buffer 204 * 205 * @adev: amdgpu_device pointer 206 * @ih: amdgpu_ih_ring pointer 207 * 208 * Enable an ih ring buffer (VEGA20) 209 */ 210 static int vega20_ih_enable_ring(struct amdgpu_device *adev, 211 struct amdgpu_ih_ring *ih) 212 { 213 struct amdgpu_ih_regs *ih_regs; 214 uint32_t tmp; 215 216 ih_regs = &ih->ih_regs; 217 218 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 219 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 220 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 221 222 tmp = RREG32(ih_regs->ih_rb_cntl); 223 tmp = vega20_ih_rb_cntl(ih, tmp); 224 if (ih == &adev->irq.ih) 225 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 226 if (ih == &adev->irq.ih1) 227 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 228 if (amdgpu_sriov_vf(adev)) { 229 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 230 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 231 return -ETIMEDOUT; 232 } 233 } else { 234 WREG32(ih_regs->ih_rb_cntl, tmp); 235 } 236 237 if (ih == &adev->irq.ih) { 238 /* set the ih ring 0 writeback address whether it's enabled or not */ 239 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 240 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 241 } 242 243 /* set rptr, wptr to 0 */ 244 WREG32(ih_regs->ih_rb_wptr, 0); 245 WREG32(ih_regs->ih_rb_rptr, 0); 246 247 WREG32(ih_regs->ih_doorbell_rptr, vega20_ih_doorbell_rptr(ih)); 248 249 return 0; 250 } 251 252 /** 253 * vega20_ih_reroute_ih - reroute VMC/UTCL2 ih to an ih ring 254 * 255 * @adev: amdgpu_device pointer 256 * 257 * Reroute VMC and UMC interrupts on primary ih ring to 258 * ih ring 1 so they won't lose when bunches of page faults 259 * interrupts overwhelms the interrupt handler(VEGA20) 260 */ 261 static void vega20_ih_reroute_ih(struct amdgpu_device *adev) 262 { 263 uint32_t tmp; 264 265 /* vega20 ih reroute will go through psp 266 * this function is only used for arcturus 267 */ 268 if (adev->asic_type == CHIP_ARCTURUS) { 269 /* Reroute to IH ring 1 for VMC */ 270 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x12); 271 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 272 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 273 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 274 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 275 276 /* Reroute IH ring 1 for UTCL2 */ 277 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x1B); 278 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 279 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 280 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 281 } 282 } 283 284 /** 285 * vega20_ih_irq_init - init and enable the interrupt ring 286 * 287 * @adev: amdgpu_device pointer 288 * 289 * Allocate a ring buffer for the interrupt controller, 290 * enable the RLC, disable interrupts, enable the IH 291 * ring buffer and enable it (VI). 292 * Called at device load and reume. 293 * Returns 0 for success, errors for failure. 294 */ 295 static int vega20_ih_irq_init(struct amdgpu_device *adev) 296 { 297 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 298 u32 ih_chicken; 299 int ret; 300 int i; 301 302 /* disable irqs */ 303 ret = vega20_ih_toggle_interrupts(adev, false); 304 if (ret) 305 return ret; 306 307 adev->nbio.funcs->ih_control(adev); 308 309 if (adev->asic_type == CHIP_ARCTURUS && 310 adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 311 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 312 if (adev->irq.ih.use_bus_addr) { 313 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 314 MC_SPACE_GPA_ENABLE, 1); 315 } 316 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 317 } 318 319 /* psp firmware won't program IH_CHICKEN for aldebaran 320 * driver needs to program it properly according to 321 * MC_SPACE type in IH_RB_CNTL */ 322 if (adev->asic_type == CHIP_ALDEBARAN) { 323 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN); 324 if (adev->irq.ih.use_bus_addr) { 325 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 326 MC_SPACE_GPA_ENABLE, 1); 327 } 328 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN, ih_chicken); 329 } 330 331 for (i = 0; i < ARRAY_SIZE(ih); i++) { 332 if (ih[i]->ring_size) { 333 if (i == 1) 334 vega20_ih_reroute_ih(adev); 335 ret = vega20_ih_enable_ring(adev, ih[i]); 336 if (ret) 337 return ret; 338 } 339 } 340 341 pci_set_master(adev->pdev); 342 343 /* enable interrupts */ 344 ret = vega20_ih_toggle_interrupts(adev, true); 345 if (ret) 346 return ret; 347 348 if (adev->irq.ih_soft.ring_size) 349 adev->irq.ih_soft.enabled = true; 350 351 return 0; 352 } 353 354 /** 355 * vega20_ih_irq_disable - disable interrupts 356 * 357 * @adev: amdgpu_device pointer 358 * 359 * Disable interrupts on the hw (VEGA20). 360 */ 361 static void vega20_ih_irq_disable(struct amdgpu_device *adev) 362 { 363 vega20_ih_toggle_interrupts(adev, false); 364 365 /* Wait and acknowledge irq */ 366 mdelay(1); 367 } 368 369 /** 370 * vega20_ih_get_wptr - get the IH ring buffer wptr 371 * 372 * @adev: amdgpu_device pointer 373 * @ih: amdgpu_ih_ring pointer 374 * 375 * Get the IH ring buffer wptr from either the register 376 * or the writeback memory buffer (VEGA20). Also check for 377 * ring buffer overflow and deal with it. 378 * Returns the value of the wptr. 379 */ 380 static u32 vega20_ih_get_wptr(struct amdgpu_device *adev, 381 struct amdgpu_ih_ring *ih) 382 { 383 u32 wptr, tmp; 384 struct amdgpu_ih_regs *ih_regs; 385 386 if (ih == &adev->irq.ih) { 387 /* Only ring0 supports writeback. On other rings fall back 388 * to register-based code with overflow checking below. 389 */ 390 wptr = le32_to_cpu(*ih->wptr_cpu); 391 392 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 393 goto out; 394 } 395 396 ih_regs = &ih->ih_regs; 397 398 /* Double check that the overflow wasn't already cleared. */ 399 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); 400 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 401 goto out; 402 403 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 404 405 /* When a ring buffer overflow happen start parsing interrupt 406 * from the last not overwritten vector (wptr + 32). Hopefully 407 * this should allow us to catchup. 408 */ 409 tmp = (wptr + 32) & ih->ptr_mask; 410 dev_warn(adev->dev, "IH ring buffer overflow " 411 "(0x%08X, 0x%08X, 0x%08X)\n", 412 wptr, ih->rptr, tmp); 413 ih->rptr = tmp; 414 415 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); 416 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 417 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 418 419 out: 420 return (wptr & ih->ptr_mask); 421 } 422 423 /** 424 * vega20_ih_irq_rearm - rearm IRQ if lost 425 * 426 * @adev: amdgpu_device pointer 427 * @ih: amdgpu_ih_ring pointer 428 * 429 */ 430 static void vega20_ih_irq_rearm(struct amdgpu_device *adev, 431 struct amdgpu_ih_ring *ih) 432 { 433 uint32_t v = 0; 434 uint32_t i = 0; 435 struct amdgpu_ih_regs *ih_regs; 436 437 ih_regs = &ih->ih_regs; 438 439 /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */ 440 for (i = 0; i < MAX_REARM_RETRY; i++) { 441 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); 442 if ((v < ih->ring_size) && (v != ih->rptr)) 443 WDOORBELL32(ih->doorbell_index, ih->rptr); 444 else 445 break; 446 } 447 } 448 449 /** 450 * vega20_ih_set_rptr - set the IH ring buffer rptr 451 * 452 * @adev: amdgpu_device pointer 453 * @ih: amdgpu_ih_ring pointer 454 * 455 * Set the IH ring buffer rptr. 456 */ 457 static void vega20_ih_set_rptr(struct amdgpu_device *adev, 458 struct amdgpu_ih_ring *ih) 459 { 460 struct amdgpu_ih_regs *ih_regs; 461 462 if (ih->use_doorbell) { 463 /* XXX check if swapping is necessary on BE */ 464 *ih->rptr_cpu = ih->rptr; 465 WDOORBELL32(ih->doorbell_index, ih->rptr); 466 467 if (amdgpu_sriov_vf(adev)) 468 vega20_ih_irq_rearm(adev, ih); 469 } else { 470 ih_regs = &ih->ih_regs; 471 WREG32(ih_regs->ih_rb_rptr, ih->rptr); 472 } 473 } 474 475 /** 476 * vega20_ih_self_irq - dispatch work for ring 1 and 2 477 * 478 * @adev: amdgpu_device pointer 479 * @source: irq source 480 * @entry: IV with WPTR update 481 * 482 * Update the WPTR from the IV and schedule work to handle the entries. 483 */ 484 static int vega20_ih_self_irq(struct amdgpu_device *adev, 485 struct amdgpu_irq_src *source, 486 struct amdgpu_iv_entry *entry) 487 { 488 switch (entry->ring_id) { 489 case 1: 490 schedule_work(&adev->irq.ih1_work); 491 break; 492 case 2: 493 schedule_work(&adev->irq.ih2_work); 494 break; 495 default: break; 496 } 497 return 0; 498 } 499 500 static const struct amdgpu_irq_src_funcs vega20_ih_self_irq_funcs = { 501 .process = vega20_ih_self_irq, 502 }; 503 504 static void vega20_ih_set_self_irq_funcs(struct amdgpu_device *adev) 505 { 506 adev->irq.self_irq.num_types = 0; 507 adev->irq.self_irq.funcs = &vega20_ih_self_irq_funcs; 508 } 509 510 static int vega20_ih_early_init(void *handle) 511 { 512 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 513 514 vega20_ih_set_interrupt_funcs(adev); 515 vega20_ih_set_self_irq_funcs(adev); 516 return 0; 517 } 518 519 static int vega20_ih_sw_init(void *handle) 520 { 521 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 522 int r; 523 524 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 525 &adev->irq.self_irq); 526 if (r) 527 return r; 528 529 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true); 530 if (r) 531 return r; 532 533 adev->irq.ih.use_doorbell = true; 534 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 535 536 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 537 if (r) 538 return r; 539 540 adev->irq.ih1.use_doorbell = true; 541 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; 542 543 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 544 if (r) 545 return r; 546 547 adev->irq.ih2.use_doorbell = true; 548 adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1; 549 550 /* initialize ih control registers offset */ 551 vega20_ih_init_register_offset(adev); 552 553 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); 554 if (r) 555 return r; 556 557 r = amdgpu_irq_init(adev); 558 559 return r; 560 } 561 562 static int vega20_ih_sw_fini(void *handle) 563 { 564 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 565 566 amdgpu_irq_fini(adev); 567 amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft); 568 amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 569 amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 570 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 571 572 return 0; 573 } 574 575 static int vega20_ih_hw_init(void *handle) 576 { 577 int r; 578 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 579 580 r = vega20_ih_irq_init(adev); 581 if (r) 582 return r; 583 584 return 0; 585 } 586 587 static int vega20_ih_hw_fini(void *handle) 588 { 589 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 590 591 vega20_ih_irq_disable(adev); 592 593 return 0; 594 } 595 596 static int vega20_ih_suspend(void *handle) 597 { 598 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 599 600 return vega20_ih_hw_fini(adev); 601 } 602 603 static int vega20_ih_resume(void *handle) 604 { 605 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 606 607 return vega20_ih_hw_init(adev); 608 } 609 610 static bool vega20_ih_is_idle(void *handle) 611 { 612 /* todo */ 613 return true; 614 } 615 616 static int vega20_ih_wait_for_idle(void *handle) 617 { 618 /* todo */ 619 return -ETIMEDOUT; 620 } 621 622 static int vega20_ih_soft_reset(void *handle) 623 { 624 /* todo */ 625 626 return 0; 627 } 628 629 static void vega20_ih_update_clockgating_state(struct amdgpu_device *adev, 630 bool enable) 631 { 632 uint32_t data, def, field_val; 633 634 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 635 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 636 field_val = enable ? 0 : 1; 637 data = REG_SET_FIELD(data, IH_CLK_CTRL, 638 IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val); 639 data = REG_SET_FIELD(data, IH_CLK_CTRL, 640 IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val); 641 data = REG_SET_FIELD(data, IH_CLK_CTRL, 642 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 643 data = REG_SET_FIELD(data, IH_CLK_CTRL, 644 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 645 data = REG_SET_FIELD(data, IH_CLK_CTRL, 646 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 647 data = REG_SET_FIELD(data, IH_CLK_CTRL, 648 DYN_CLK_SOFT_OVERRIDE, field_val); 649 data = REG_SET_FIELD(data, IH_CLK_CTRL, 650 REG_CLK_SOFT_OVERRIDE, field_val); 651 if (def != data) 652 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 653 } 654 } 655 656 static int vega20_ih_set_clockgating_state(void *handle, 657 enum amd_clockgating_state state) 658 { 659 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 660 661 vega20_ih_update_clockgating_state(adev, 662 state == AMD_CG_STATE_GATE); 663 return 0; 664 665 } 666 667 static int vega20_ih_set_powergating_state(void *handle, 668 enum amd_powergating_state state) 669 { 670 return 0; 671 } 672 673 const struct amd_ip_funcs vega20_ih_ip_funcs = { 674 .name = "vega20_ih", 675 .early_init = vega20_ih_early_init, 676 .late_init = NULL, 677 .sw_init = vega20_ih_sw_init, 678 .sw_fini = vega20_ih_sw_fini, 679 .hw_init = vega20_ih_hw_init, 680 .hw_fini = vega20_ih_hw_fini, 681 .suspend = vega20_ih_suspend, 682 .resume = vega20_ih_resume, 683 .is_idle = vega20_ih_is_idle, 684 .wait_for_idle = vega20_ih_wait_for_idle, 685 .soft_reset = vega20_ih_soft_reset, 686 .set_clockgating_state = vega20_ih_set_clockgating_state, 687 .set_powergating_state = vega20_ih_set_powergating_state, 688 }; 689 690 static const struct amdgpu_ih_funcs vega20_ih_funcs = { 691 .get_wptr = vega20_ih_get_wptr, 692 .decode_iv = amdgpu_ih_decode_iv_helper, 693 .set_rptr = vega20_ih_set_rptr 694 }; 695 696 static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev) 697 { 698 adev->irq.ih_funcs = &vega20_ih_funcs; 699 } 700 701 const struct amdgpu_ip_block_version vega20_ih_ip_block = 702 { 703 .type = AMD_IP_BLOCK_TYPE_IH, 704 .major = 4, 705 .minor = 2, 706 .rev = 0, 707 .funcs = &vega20_ih_ip_funcs, 708 }; 709