1 /*
2  * Copyright 2020 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include <linux/pci.h>
25 
26 #include "amdgpu.h"
27 #include "amdgpu_ih.h"
28 #include "soc15.h"
29 
30 #include "oss/osssys_4_2_0_offset.h"
31 #include "oss/osssys_4_2_0_sh_mask.h"
32 
33 #include "soc15_common.h"
34 #include "vega20_ih.h"
35 
36 #define MAX_REARM_RETRY 10
37 
38 static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev);
39 
40 /**
41  * vega20_ih_init_register_offset - Initialize register offset for ih rings
42  *
43  * @adev: amdgpu_device pointer
44  *
45  * Initialize register offset ih rings (VEGA20).
46  */
47 static void vega20_ih_init_register_offset(struct amdgpu_device *adev)
48 {
49 	struct amdgpu_ih_regs *ih_regs;
50 
51 	if (adev->irq.ih.ring_size) {
52 		ih_regs = &adev->irq.ih.ih_regs;
53 		ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE);
54 		ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI);
55 		ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);
56 		ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
57 		ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR);
58 		ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR);
59 		ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO);
60 		ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI);
61 		ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL;
62 	}
63 
64 	if (adev->irq.ih1.ring_size) {
65 		ih_regs = &adev->irq.ih1.ih_regs;
66 		ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1);
67 		ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1);
68 		ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);
69 		ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1);
70 		ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1);
71 		ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1);
72 		ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1;
73 	}
74 
75 	if (adev->irq.ih2.ring_size) {
76 		ih_regs = &adev->irq.ih2.ih_regs;
77 		ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2);
78 		ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2);
79 		ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);
80 		ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2);
81 		ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2);
82 		ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2);
83 		ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2;
84 	}
85 }
86 
87 /**
88  * vega20_ih_toggle_ring_interrupts - toggle the interrupt ring buffer
89  *
90  * @adev: amdgpu_device pointer
91  * @ih: amdgpu_ih_ring pointer
92  * @enable: true - enable the interrupts, false - disable the interrupts
93  *
94  * Toggle the interrupt ring buffer (VEGA20)
95  */
96 static int vega20_ih_toggle_ring_interrupts(struct amdgpu_device *adev,
97 					    struct amdgpu_ih_ring *ih,
98 					    bool enable)
99 {
100 	struct amdgpu_ih_regs *ih_regs;
101 	uint32_t tmp;
102 
103 	ih_regs = &ih->ih_regs;
104 
105 	tmp = RREG32(ih_regs->ih_rb_cntl);
106 	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));
107 	/* enable_intr field is only valid in ring0 */
108 	if (ih == &adev->irq.ih)
109 		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
110 	if (amdgpu_sriov_vf(adev)) {
111 		if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
112 			dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n");
113 			return -ETIMEDOUT;
114 		}
115 	} else {
116 		WREG32(ih_regs->ih_rb_cntl, tmp);
117 	}
118 
119 	if (enable) {
120 		ih->enabled = true;
121 	} else {
122 		/* set rptr, wptr to 0 */
123 		WREG32(ih_regs->ih_rb_rptr, 0);
124 		WREG32(ih_regs->ih_rb_wptr, 0);
125 		ih->enabled = false;
126 		ih->rptr = 0;
127 	}
128 
129 	return 0;
130 }
131 
132 /**
133  * vega20_ih_toggle_interrupts - Toggle all the available interrupt ring buffers
134  *
135  * @adev: amdgpu_device pointer
136  * @enable: enable or disable interrupt ring buffers
137  *
138  * Toggle all the available interrupt ring buffers (VEGA20).
139  */
140 static int vega20_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable)
141 {
142 	struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
143 	int i;
144 	int r;
145 
146 	for (i = 0; i < ARRAY_SIZE(ih); i++) {
147 		if (ih[i]->ring_size) {
148 			r = vega20_ih_toggle_ring_interrupts(adev, ih[i], enable);
149 			if (r)
150 				return r;
151 		}
152 	}
153 
154 	return 0;
155 }
156 
157 static uint32_t vega20_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)
158 {
159 	int rb_bufsz = order_base_2(ih->ring_size / 4);
160 
161 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
162 				   MC_SPACE, ih->use_bus_addr ? 1 : 4);
163 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
164 				   WPTR_OVERFLOW_CLEAR, 1);
165 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
166 				   WPTR_OVERFLOW_ENABLE, 1);
167 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
168 	/* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register
169 	 * value is written to memory
170 	 */
171 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
172 				   WPTR_WRITEBACK_ENABLE, 1);
173 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
174 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
175 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
176 
177 	return ih_rb_cntl;
178 }
179 
180 static uint32_t vega20_ih_doorbell_rptr(struct amdgpu_ih_ring *ih)
181 {
182 	u32 ih_doorbell_rtpr = 0;
183 
184 	if (ih->use_doorbell) {
185 		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
186 						 IH_DOORBELL_RPTR, OFFSET,
187 						 ih->doorbell_index);
188 		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
189 						 IH_DOORBELL_RPTR,
190 						 ENABLE, 1);
191 	} else {
192 		ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
193 						 IH_DOORBELL_RPTR,
194 						 ENABLE, 0);
195 	}
196 	return ih_doorbell_rtpr;
197 }
198 
199 /**
200  * vega20_ih_enable_ring - enable an ih ring buffer
201  *
202  * @adev: amdgpu_device pointer
203  * @ih: amdgpu_ih_ring pointer
204  *
205  * Enable an ih ring buffer (VEGA20)
206  */
207 static int vega20_ih_enable_ring(struct amdgpu_device *adev,
208 				 struct amdgpu_ih_ring *ih)
209 {
210 	struct amdgpu_ih_regs *ih_regs;
211 	uint32_t tmp;
212 
213 	ih_regs = &ih->ih_regs;
214 
215 	/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
216 	WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);
217 	WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);
218 
219 	tmp = RREG32(ih_regs->ih_rb_cntl);
220 	tmp = vega20_ih_rb_cntl(ih, tmp);
221 	if (ih == &adev->irq.ih)
222 		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);
223 	if (ih == &adev->irq.ih1) {
224 		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);
225 		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
226 	}
227 	if (amdgpu_sriov_vf(adev)) {
228 		if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
229 			dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n");
230 			return -ETIMEDOUT;
231 		}
232 	} else {
233 		WREG32(ih_regs->ih_rb_cntl, tmp);
234 	}
235 
236 	if (ih == &adev->irq.ih) {
237 		/* set the ih ring 0 writeback address whether it's enabled or not */
238 		WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
239 		WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);
240 	}
241 
242 	/* set rptr, wptr to 0 */
243 	WREG32(ih_regs->ih_rb_wptr, 0);
244 	WREG32(ih_regs->ih_rb_rptr, 0);
245 
246 	WREG32(ih_regs->ih_doorbell_rptr, vega20_ih_doorbell_rptr(ih));
247 
248 	return 0;
249 }
250 
251 /**
252  * vega20_ih_reroute_ih - reroute VMC/UTCL2 ih to an ih ring
253  *
254  * @adev: amdgpu_device pointer
255  *
256  * Reroute VMC and UMC interrupts on primary ih ring to
257  * ih ring 1 so they won't lose when bunches of page faults
258  * interrupts overwhelms the interrupt handler(VEGA20)
259  */
260 static void vega20_ih_reroute_ih(struct amdgpu_device *adev)
261 {
262 	uint32_t tmp;
263 
264 	/* vega20 ih reroute will go through psp
265 	 * this function is only used for arcturus
266 	 */
267 	if (adev->asic_type == CHIP_ARCTURUS) {
268 		/* Reroute to IH ring 1 for VMC */
269 		WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x12);
270 		tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA);
271 		tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
272 		tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
273 		WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp);
274 
275 		/* Reroute IH ring 1 for UTCL2 */
276 		WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x1B);
277 		tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA);
278 		tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
279 		WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp);
280 	}
281 }
282 
283 /**
284  * vega20_ih_irq_init - init and enable the interrupt ring
285  *
286  * @adev: amdgpu_device pointer
287  *
288  * Allocate a ring buffer for the interrupt controller,
289  * enable the RLC, disable interrupts, enable the IH
290  * ring buffer and enable it (VI).
291  * Called at device load and reume.
292  * Returns 0 for success, errors for failure.
293  */
294 static int vega20_ih_irq_init(struct amdgpu_device *adev)
295 {
296 	struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
297 	u32 ih_chicken;
298 	int ret;
299 	int i;
300 	u32 tmp;
301 
302 	/* disable irqs */
303 	ret = vega20_ih_toggle_interrupts(adev, false);
304 	if (ret)
305 		return ret;
306 
307 	adev->nbio.funcs->ih_control(adev);
308 
309 	if (adev->asic_type == CHIP_ARCTURUS &&
310 	    adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
311 		ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);
312 		if (adev->irq.ih.use_bus_addr) {
313 			ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
314 						   MC_SPACE_GPA_ENABLE, 1);
315 		}
316 		WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);
317 	}
318 
319 	for (i = 0; i < ARRAY_SIZE(ih); i++) {
320 		if (ih[i]->ring_size) {
321 			if (i == 1)
322 				vega20_ih_reroute_ih(adev);
323 			ret = vega20_ih_enable_ring(adev, ih[i]);
324 			if (ret)
325 				return ret;
326 		}
327 	}
328 
329 	tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL);
330 	tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL,
331 			    CLIENT18_IS_STORM_CLIENT, 1);
332 	WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp);
333 
334 	tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL);
335 	tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1);
336 	WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp);
337 
338 	pci_set_master(adev->pdev);
339 
340 	/* enable interrupts */
341 	ret = vega20_ih_toggle_interrupts(adev, true);
342 	if (ret)
343 		return ret;
344 
345 	if (adev->irq.ih_soft.ring_size)
346 		adev->irq.ih_soft.enabled = true;
347 
348 	return 0;
349 }
350 
351 /**
352  * vega20_ih_irq_disable - disable interrupts
353  *
354  * @adev: amdgpu_device pointer
355  *
356  * Disable interrupts on the hw (VEGA20).
357  */
358 static void vega20_ih_irq_disable(struct amdgpu_device *adev)
359 {
360 	vega20_ih_toggle_interrupts(adev, false);
361 
362 	/* Wait and acknowledge irq */
363 	mdelay(1);
364 }
365 
366 /**
367  * vega20_ih_get_wptr - get the IH ring buffer wptr
368  *
369  * @adev: amdgpu_device pointer
370  * @ih: amdgpu_ih_ring pointer
371  *
372  * Get the IH ring buffer wptr from either the register
373  * or the writeback memory buffer (VEGA20).  Also check for
374  * ring buffer overflow and deal with it.
375  * Returns the value of the wptr.
376  */
377 static u32 vega20_ih_get_wptr(struct amdgpu_device *adev,
378 			      struct amdgpu_ih_ring *ih)
379 {
380 	u32 wptr, tmp;
381 	struct amdgpu_ih_regs *ih_regs;
382 
383 	wptr = le32_to_cpu(*ih->wptr_cpu);
384 	ih_regs = &ih->ih_regs;
385 
386 	if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
387 		goto out;
388 
389 	/* Double check that the overflow wasn't already cleared. */
390 	wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);
391 	if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
392 		goto out;
393 
394 	wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
395 
396 	/* When a ring buffer overflow happen start parsing interrupt
397 	 * from the last not overwritten vector (wptr + 32). Hopefully
398 	 * this should allow us to catchup.
399 	 */
400 	tmp = (wptr + 32) & ih->ptr_mask;
401 	dev_warn(adev->dev, "IH ring buffer overflow "
402 		 "(0x%08X, 0x%08X, 0x%08X)\n",
403 		 wptr, ih->rptr, tmp);
404 	ih->rptr = tmp;
405 
406 	tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
407 	tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
408 	WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
409 
410 out:
411 	return (wptr & ih->ptr_mask);
412 }
413 
414 /**
415  * vega20_ih_irq_rearm - rearm IRQ if lost
416  *
417  * @adev: amdgpu_device pointer
418  * @ih: amdgpu_ih_ring pointer
419  *
420  */
421 static void vega20_ih_irq_rearm(struct amdgpu_device *adev,
422 			       struct amdgpu_ih_ring *ih)
423 {
424 	uint32_t v = 0;
425 	uint32_t i = 0;
426 	struct amdgpu_ih_regs *ih_regs;
427 
428 	ih_regs = &ih->ih_regs;
429 
430 	/* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */
431 	for (i = 0; i < MAX_REARM_RETRY; i++) {
432 		v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);
433 		if ((v < ih->ring_size) && (v != ih->rptr))
434 			WDOORBELL32(ih->doorbell_index, ih->rptr);
435 		else
436 			break;
437 	}
438 }
439 
440 /**
441  * vega20_ih_set_rptr - set the IH ring buffer rptr
442  *
443  * @adev: amdgpu_device pointer
444  * @ih: amdgpu_ih_ring pointer
445  *
446  * Set the IH ring buffer rptr.
447  */
448 static void vega20_ih_set_rptr(struct amdgpu_device *adev,
449 			       struct amdgpu_ih_ring *ih)
450 {
451 	struct amdgpu_ih_regs *ih_regs;
452 
453 	if (ih->use_doorbell) {
454 		/* XXX check if swapping is necessary on BE */
455 		*ih->rptr_cpu = ih->rptr;
456 		WDOORBELL32(ih->doorbell_index, ih->rptr);
457 
458 		if (amdgpu_sriov_vf(adev))
459 			vega20_ih_irq_rearm(adev, ih);
460 	} else {
461 		ih_regs = &ih->ih_regs;
462 		WREG32(ih_regs->ih_rb_rptr, ih->rptr);
463 	}
464 }
465 
466 /**
467  * vega20_ih_self_irq - dispatch work for ring 1 and 2
468  *
469  * @adev: amdgpu_device pointer
470  * @source: irq source
471  * @entry: IV with WPTR update
472  *
473  * Update the WPTR from the IV and schedule work to handle the entries.
474  */
475 static int vega20_ih_self_irq(struct amdgpu_device *adev,
476 			      struct amdgpu_irq_src *source,
477 			      struct amdgpu_iv_entry *entry)
478 {
479 	uint32_t wptr = cpu_to_le32(entry->src_data[0]);
480 
481 	switch (entry->ring_id) {
482 	case 1:
483 		*adev->irq.ih1.wptr_cpu = wptr;
484 		schedule_work(&adev->irq.ih1_work);
485 		break;
486 	case 2:
487 		*adev->irq.ih2.wptr_cpu = wptr;
488 		schedule_work(&adev->irq.ih2_work);
489 		break;
490 	default: break;
491 	}
492 	return 0;
493 }
494 
495 static const struct amdgpu_irq_src_funcs vega20_ih_self_irq_funcs = {
496 	.process = vega20_ih_self_irq,
497 };
498 
499 static void vega20_ih_set_self_irq_funcs(struct amdgpu_device *adev)
500 {
501 	adev->irq.self_irq.num_types = 0;
502 	adev->irq.self_irq.funcs = &vega20_ih_self_irq_funcs;
503 }
504 
505 static int vega20_ih_early_init(void *handle)
506 {
507 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
508 
509 	vega20_ih_set_interrupt_funcs(adev);
510 	vega20_ih_set_self_irq_funcs(adev);
511 	return 0;
512 }
513 
514 static int vega20_ih_sw_init(void *handle)
515 {
516 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
517 	int r;
518 
519 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0,
520 			      &adev->irq.self_irq);
521 	if (r)
522 		return r;
523 
524 	r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true);
525 	if (r)
526 		return r;
527 
528 	adev->irq.ih.use_doorbell = true;
529 	adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
530 
531 	r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true);
532 	if (r)
533 		return r;
534 
535 	adev->irq.ih1.use_doorbell = true;
536 	adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1;
537 
538 	r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true);
539 	if (r)
540 		return r;
541 
542 	adev->irq.ih2.use_doorbell = true;
543 	adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1;
544 
545 	/* initialize ih control registers offset */
546 	vega20_ih_init_register_offset(adev);
547 
548 	r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true);
549 	if (r)
550 		return r;
551 
552 	r = amdgpu_irq_init(adev);
553 
554 	return r;
555 }
556 
557 static int vega20_ih_sw_fini(void *handle)
558 {
559 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
560 
561 	amdgpu_irq_fini(adev);
562 	amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft);
563 	amdgpu_ih_ring_fini(adev, &adev->irq.ih2);
564 	amdgpu_ih_ring_fini(adev, &adev->irq.ih1);
565 	amdgpu_ih_ring_fini(adev, &adev->irq.ih);
566 
567 	return 0;
568 }
569 
570 static int vega20_ih_hw_init(void *handle)
571 {
572 	int r;
573 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
574 
575 	r = vega20_ih_irq_init(adev);
576 	if (r)
577 		return r;
578 
579 	return 0;
580 }
581 
582 static int vega20_ih_hw_fini(void *handle)
583 {
584 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
585 
586 	vega20_ih_irq_disable(adev);
587 
588 	return 0;
589 }
590 
591 static int vega20_ih_suspend(void *handle)
592 {
593 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
594 
595 	return vega20_ih_hw_fini(adev);
596 }
597 
598 static int vega20_ih_resume(void *handle)
599 {
600 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
601 
602 	return vega20_ih_hw_init(adev);
603 }
604 
605 static bool vega20_ih_is_idle(void *handle)
606 {
607 	/* todo */
608 	return true;
609 }
610 
611 static int vega20_ih_wait_for_idle(void *handle)
612 {
613 	/* todo */
614 	return -ETIMEDOUT;
615 }
616 
617 static int vega20_ih_soft_reset(void *handle)
618 {
619 	/* todo */
620 
621 	return 0;
622 }
623 
624 static void vega20_ih_update_clockgating_state(struct amdgpu_device *adev,
625 					       bool enable)
626 {
627 	uint32_t data, def, field_val;
628 
629 	if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) {
630 		def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL);
631 		field_val = enable ? 0 : 1;
632 		data = REG_SET_FIELD(data, IH_CLK_CTRL,
633 				     IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val);
634 		data = REG_SET_FIELD(data, IH_CLK_CTRL,
635 				     IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val);
636 		data = REG_SET_FIELD(data, IH_CLK_CTRL,
637 				     DBUS_MUX_CLK_SOFT_OVERRIDE, field_val);
638 		data = REG_SET_FIELD(data, IH_CLK_CTRL,
639 				     OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val);
640 		data = REG_SET_FIELD(data, IH_CLK_CTRL,
641 				     LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val);
642 		data = REG_SET_FIELD(data, IH_CLK_CTRL,
643 				     DYN_CLK_SOFT_OVERRIDE, field_val);
644 		data = REG_SET_FIELD(data, IH_CLK_CTRL,
645 				     REG_CLK_SOFT_OVERRIDE, field_val);
646 		if (def != data)
647 			WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data);
648 	}
649 }
650 
651 static int vega20_ih_set_clockgating_state(void *handle,
652 					  enum amd_clockgating_state state)
653 {
654 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
655 
656 	vega20_ih_update_clockgating_state(adev,
657 				state == AMD_CG_STATE_GATE);
658 	return 0;
659 
660 }
661 
662 static int vega20_ih_set_powergating_state(void *handle,
663 					  enum amd_powergating_state state)
664 {
665 	return 0;
666 }
667 
668 const struct amd_ip_funcs vega20_ih_ip_funcs = {
669 	.name = "vega20_ih",
670 	.early_init = vega20_ih_early_init,
671 	.late_init = NULL,
672 	.sw_init = vega20_ih_sw_init,
673 	.sw_fini = vega20_ih_sw_fini,
674 	.hw_init = vega20_ih_hw_init,
675 	.hw_fini = vega20_ih_hw_fini,
676 	.suspend = vega20_ih_suspend,
677 	.resume = vega20_ih_resume,
678 	.is_idle = vega20_ih_is_idle,
679 	.wait_for_idle = vega20_ih_wait_for_idle,
680 	.soft_reset = vega20_ih_soft_reset,
681 	.set_clockgating_state = vega20_ih_set_clockgating_state,
682 	.set_powergating_state = vega20_ih_set_powergating_state,
683 };
684 
685 static const struct amdgpu_ih_funcs vega20_ih_funcs = {
686 	.get_wptr = vega20_ih_get_wptr,
687 	.decode_iv = amdgpu_ih_decode_iv_helper,
688 	.set_rptr = vega20_ih_set_rptr
689 };
690 
691 static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev)
692 {
693 	adev->irq.ih_funcs = &vega20_ih_funcs;
694 }
695 
696 const struct amdgpu_ip_block_version vega20_ih_ip_block =
697 {
698 	.type = AMD_IP_BLOCK_TYPE_IH,
699 	.major = 4,
700 	.minor = 2,
701 	.rev = 0,
702 	.funcs = &vega20_ih_ip_funcs,
703 };
704