1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 #include "soc15.h" 29 30 #include "oss/osssys_4_2_0_offset.h" 31 #include "oss/osssys_4_2_0_sh_mask.h" 32 33 #include "soc15_common.h" 34 #include "vega20_ih.h" 35 36 #define MAX_REARM_RETRY 10 37 38 #define mmIH_CHICKEN_ALDEBARAN 0x18d 39 #define mmIH_CHICKEN_ALDEBARAN_BASE_IDX 0 40 41 static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev); 42 43 /** 44 * vega20_ih_init_register_offset - Initialize register offset for ih rings 45 * 46 * @adev: amdgpu_device pointer 47 * 48 * Initialize register offset ih rings (VEGA20). 49 */ 50 static void vega20_ih_init_register_offset(struct amdgpu_device *adev) 51 { 52 struct amdgpu_ih_regs *ih_regs; 53 54 if (adev->irq.ih.ring_size) { 55 ih_regs = &adev->irq.ih.ih_regs; 56 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 57 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 58 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 59 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 60 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 61 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 62 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 63 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 64 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 65 } 66 67 if (adev->irq.ih1.ring_size) { 68 ih_regs = &adev->irq.ih1.ih_regs; 69 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 70 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 71 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 72 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 73 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 74 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 75 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 76 } 77 78 if (adev->irq.ih2.ring_size) { 79 ih_regs = &adev->irq.ih2.ih_regs; 80 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 81 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 82 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 83 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 84 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 85 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 86 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 87 } 88 } 89 90 /** 91 * vega20_ih_toggle_ring_interrupts - toggle the interrupt ring buffer 92 * 93 * @adev: amdgpu_device pointer 94 * @ih: amdgpu_ih_ring pointer 95 * @enable: true - enable the interrupts, false - disable the interrupts 96 * 97 * Toggle the interrupt ring buffer (VEGA20) 98 */ 99 static int vega20_ih_toggle_ring_interrupts(struct amdgpu_device *adev, 100 struct amdgpu_ih_ring *ih, 101 bool enable) 102 { 103 struct amdgpu_ih_regs *ih_regs; 104 uint32_t tmp; 105 106 ih_regs = &ih->ih_regs; 107 108 tmp = RREG32(ih_regs->ih_rb_cntl); 109 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); 110 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1); 111 112 /* enable_intr field is only valid in ring0 */ 113 if (ih == &adev->irq.ih) 114 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); 115 if (amdgpu_sriov_vf(adev)) { 116 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 117 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 118 return -ETIMEDOUT; 119 } 120 } else { 121 WREG32(ih_regs->ih_rb_cntl, tmp); 122 } 123 124 if (enable) { 125 ih->enabled = true; 126 } else { 127 /* set rptr, wptr to 0 */ 128 WREG32(ih_regs->ih_rb_rptr, 0); 129 WREG32(ih_regs->ih_rb_wptr, 0); 130 ih->enabled = false; 131 ih->rptr = 0; 132 } 133 134 return 0; 135 } 136 137 /** 138 * vega20_ih_toggle_interrupts - Toggle all the available interrupt ring buffers 139 * 140 * @adev: amdgpu_device pointer 141 * @enable: enable or disable interrupt ring buffers 142 * 143 * Toggle all the available interrupt ring buffers (VEGA20). 144 */ 145 static int vega20_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable) 146 { 147 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 148 int i; 149 int r; 150 151 for (i = 0; i < ARRAY_SIZE(ih); i++) { 152 if (ih[i]->ring_size) { 153 r = vega20_ih_toggle_ring_interrupts(adev, ih[i], enable); 154 if (r) 155 return r; 156 } 157 } 158 159 return 0; 160 } 161 162 static uint32_t vega20_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 163 { 164 int rb_bufsz = order_base_2(ih->ring_size / 4); 165 166 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 167 MC_SPACE, ih->use_bus_addr ? 1 : 4); 168 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 169 WPTR_OVERFLOW_CLEAR, 1); 170 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 171 WPTR_OVERFLOW_ENABLE, 1); 172 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 173 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 174 * value is written to memory 175 */ 176 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 177 WPTR_WRITEBACK_ENABLE, 1); 178 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 179 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 180 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 181 182 return ih_rb_cntl; 183 } 184 185 static uint32_t vega20_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 186 { 187 u32 ih_doorbell_rtpr = 0; 188 189 if (ih->use_doorbell) { 190 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 191 IH_DOORBELL_RPTR, OFFSET, 192 ih->doorbell_index); 193 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 194 IH_DOORBELL_RPTR, 195 ENABLE, 1); 196 } else { 197 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 198 IH_DOORBELL_RPTR, 199 ENABLE, 0); 200 } 201 return ih_doorbell_rtpr; 202 } 203 204 /** 205 * vega20_ih_enable_ring - enable an ih ring buffer 206 * 207 * @adev: amdgpu_device pointer 208 * @ih: amdgpu_ih_ring pointer 209 * 210 * Enable an ih ring buffer (VEGA20) 211 */ 212 static int vega20_ih_enable_ring(struct amdgpu_device *adev, 213 struct amdgpu_ih_ring *ih) 214 { 215 struct amdgpu_ih_regs *ih_regs; 216 uint32_t tmp; 217 218 ih_regs = &ih->ih_regs; 219 220 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 221 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 222 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 223 224 tmp = RREG32(ih_regs->ih_rb_cntl); 225 tmp = vega20_ih_rb_cntl(ih, tmp); 226 if (ih == &adev->irq.ih) 227 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 228 if (ih == &adev->irq.ih1) 229 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 230 if (amdgpu_sriov_vf(adev)) { 231 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 232 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 233 return -ETIMEDOUT; 234 } 235 } else { 236 WREG32(ih_regs->ih_rb_cntl, tmp); 237 } 238 239 if (ih == &adev->irq.ih) { 240 /* set the ih ring 0 writeback address whether it's enabled or not */ 241 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 242 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 243 } 244 245 /* set rptr, wptr to 0 */ 246 WREG32(ih_regs->ih_rb_wptr, 0); 247 WREG32(ih_regs->ih_rb_rptr, 0); 248 249 WREG32(ih_regs->ih_doorbell_rptr, vega20_ih_doorbell_rptr(ih)); 250 251 return 0; 252 } 253 254 /** 255 * vega20_ih_reroute_ih - reroute VMC/UTCL2 ih to an ih ring 256 * 257 * @adev: amdgpu_device pointer 258 * 259 * Reroute VMC and UMC interrupts on primary ih ring to 260 * ih ring 1 so they won't lose when bunches of page faults 261 * interrupts overwhelms the interrupt handler(VEGA20) 262 */ 263 static void vega20_ih_reroute_ih(struct amdgpu_device *adev) 264 { 265 uint32_t tmp; 266 267 /* vega20 ih reroute will go through psp this 268 * function is used for newer asics starting arcturus 269 */ 270 if (adev->ip_versions[OSSSYS_HWIP][0] >= IP_VERSION(4, 2, 1)) { 271 /* Reroute to IH ring 1 for VMC */ 272 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x12); 273 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 274 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 275 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 276 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 277 278 /* Reroute IH ring 1 for UTCL2 */ 279 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x1B); 280 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 281 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 282 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 283 } 284 } 285 286 /** 287 * vega20_ih_irq_init - init and enable the interrupt ring 288 * 289 * @adev: amdgpu_device pointer 290 * 291 * Allocate a ring buffer for the interrupt controller, 292 * enable the RLC, disable interrupts, enable the IH 293 * ring buffer and enable it (VI). 294 * Called at device load and reume. 295 * Returns 0 for success, errors for failure. 296 */ 297 static int vega20_ih_irq_init(struct amdgpu_device *adev) 298 { 299 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 300 u32 ih_chicken; 301 int ret; 302 int i; 303 304 /* disable irqs */ 305 ret = vega20_ih_toggle_interrupts(adev, false); 306 if (ret) 307 return ret; 308 309 adev->nbio.funcs->ih_control(adev); 310 311 if ((adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 2, 1)) && 312 adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 313 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 314 if (adev->irq.ih.use_bus_addr) { 315 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 316 MC_SPACE_GPA_ENABLE, 1); 317 } 318 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 319 } 320 321 /* psp firmware won't program IH_CHICKEN for aldebaran 322 * driver needs to program it properly according to 323 * MC_SPACE type in IH_RB_CNTL */ 324 if ((adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 0)) || 325 (adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 2))) { 326 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN); 327 if (adev->irq.ih.use_bus_addr) { 328 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 329 MC_SPACE_GPA_ENABLE, 1); 330 } 331 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN, ih_chicken); 332 } 333 334 for (i = 0; i < ARRAY_SIZE(ih); i++) { 335 if (ih[i]->ring_size) { 336 if (i == 1) 337 vega20_ih_reroute_ih(adev); 338 ret = vega20_ih_enable_ring(adev, ih[i]); 339 if (ret) 340 return ret; 341 } 342 } 343 344 if (!amdgpu_sriov_vf(adev)) 345 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, 346 adev->irq.ih.doorbell_index); 347 348 pci_set_master(adev->pdev); 349 350 /* enable interrupts */ 351 ret = vega20_ih_toggle_interrupts(adev, true); 352 if (ret) 353 return ret; 354 355 if (adev->irq.ih_soft.ring_size) 356 adev->irq.ih_soft.enabled = true; 357 358 return 0; 359 } 360 361 /** 362 * vega20_ih_irq_disable - disable interrupts 363 * 364 * @adev: amdgpu_device pointer 365 * 366 * Disable interrupts on the hw (VEGA20). 367 */ 368 static void vega20_ih_irq_disable(struct amdgpu_device *adev) 369 { 370 vega20_ih_toggle_interrupts(adev, false); 371 372 /* Wait and acknowledge irq */ 373 mdelay(1); 374 } 375 376 /** 377 * vega20_ih_get_wptr - get the IH ring buffer wptr 378 * 379 * @adev: amdgpu_device pointer 380 * @ih: amdgpu_ih_ring pointer 381 * 382 * Get the IH ring buffer wptr from either the register 383 * or the writeback memory buffer (VEGA20). Also check for 384 * ring buffer overflow and deal with it. 385 * Returns the value of the wptr. 386 */ 387 static u32 vega20_ih_get_wptr(struct amdgpu_device *adev, 388 struct amdgpu_ih_ring *ih) 389 { 390 u32 wptr, tmp; 391 struct amdgpu_ih_regs *ih_regs; 392 393 if (ih == &adev->irq.ih || ih == &adev->irq.ih_soft) { 394 /* Only ring0 supports writeback. On other rings fall back 395 * to register-based code with overflow checking below. 396 * ih_soft ring doesn't have any backing hardware registers, 397 * update wptr and return. 398 */ 399 wptr = le32_to_cpu(*ih->wptr_cpu); 400 401 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 402 goto out; 403 } 404 405 ih_regs = &ih->ih_regs; 406 407 /* Double check that the overflow wasn't already cleared. */ 408 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); 409 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 410 goto out; 411 412 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 413 414 /* When a ring buffer overflow happen start parsing interrupt 415 * from the last not overwritten vector (wptr + 32). Hopefully 416 * this should allow us to catchup. 417 */ 418 tmp = (wptr + 32) & ih->ptr_mask; 419 dev_warn(adev->dev, "IH ring buffer overflow " 420 "(0x%08X, 0x%08X, 0x%08X)\n", 421 wptr, ih->rptr, tmp); 422 ih->rptr = tmp; 423 424 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); 425 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 426 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 427 428 out: 429 return (wptr & ih->ptr_mask); 430 } 431 432 /** 433 * vega20_ih_irq_rearm - rearm IRQ if lost 434 * 435 * @adev: amdgpu_device pointer 436 * @ih: amdgpu_ih_ring pointer 437 * 438 */ 439 static void vega20_ih_irq_rearm(struct amdgpu_device *adev, 440 struct amdgpu_ih_ring *ih) 441 { 442 uint32_t v = 0; 443 uint32_t i = 0; 444 struct amdgpu_ih_regs *ih_regs; 445 446 ih_regs = &ih->ih_regs; 447 448 /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */ 449 for (i = 0; i < MAX_REARM_RETRY; i++) { 450 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); 451 if ((v < ih->ring_size) && (v != ih->rptr)) 452 WDOORBELL32(ih->doorbell_index, ih->rptr); 453 else 454 break; 455 } 456 } 457 458 /** 459 * vega20_ih_set_rptr - set the IH ring buffer rptr 460 * 461 * @adev: amdgpu_device pointer 462 * @ih: amdgpu_ih_ring pointer 463 * 464 * Set the IH ring buffer rptr. 465 */ 466 static void vega20_ih_set_rptr(struct amdgpu_device *adev, 467 struct amdgpu_ih_ring *ih) 468 { 469 struct amdgpu_ih_regs *ih_regs; 470 471 if (ih == &adev->irq.ih_soft) 472 return; 473 474 if (ih->use_doorbell) { 475 /* XXX check if swapping is necessary on BE */ 476 *ih->rptr_cpu = ih->rptr; 477 WDOORBELL32(ih->doorbell_index, ih->rptr); 478 479 if (amdgpu_sriov_vf(adev)) 480 vega20_ih_irq_rearm(adev, ih); 481 } else { 482 ih_regs = &ih->ih_regs; 483 WREG32(ih_regs->ih_rb_rptr, ih->rptr); 484 } 485 } 486 487 /** 488 * vega20_ih_self_irq - dispatch work for ring 1 and 2 489 * 490 * @adev: amdgpu_device pointer 491 * @source: irq source 492 * @entry: IV with WPTR update 493 * 494 * Update the WPTR from the IV and schedule work to handle the entries. 495 */ 496 static int vega20_ih_self_irq(struct amdgpu_device *adev, 497 struct amdgpu_irq_src *source, 498 struct amdgpu_iv_entry *entry) 499 { 500 switch (entry->ring_id) { 501 case 1: 502 schedule_work(&adev->irq.ih1_work); 503 break; 504 case 2: 505 schedule_work(&adev->irq.ih2_work); 506 break; 507 default: break; 508 } 509 return 0; 510 } 511 512 static const struct amdgpu_irq_src_funcs vega20_ih_self_irq_funcs = { 513 .process = vega20_ih_self_irq, 514 }; 515 516 static void vega20_ih_set_self_irq_funcs(struct amdgpu_device *adev) 517 { 518 adev->irq.self_irq.num_types = 0; 519 adev->irq.self_irq.funcs = &vega20_ih_self_irq_funcs; 520 } 521 522 static int vega20_ih_early_init(void *handle) 523 { 524 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 525 526 vega20_ih_set_interrupt_funcs(adev); 527 vega20_ih_set_self_irq_funcs(adev); 528 return 0; 529 } 530 531 static int vega20_ih_sw_init(void *handle) 532 { 533 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 534 int r; 535 536 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 537 &adev->irq.self_irq); 538 if (r) 539 return r; 540 541 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true); 542 if (r) 543 return r; 544 545 adev->irq.ih.use_doorbell = true; 546 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 547 548 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 549 if (r) 550 return r; 551 552 adev->irq.ih1.use_doorbell = true; 553 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; 554 555 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 556 if (r) 557 return r; 558 559 adev->irq.ih2.use_doorbell = true; 560 adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1; 561 562 /* initialize ih control registers offset */ 563 vega20_ih_init_register_offset(adev); 564 565 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); 566 if (r) 567 return r; 568 569 r = amdgpu_irq_init(adev); 570 571 return r; 572 } 573 574 static int vega20_ih_sw_fini(void *handle) 575 { 576 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 577 578 amdgpu_irq_fini_sw(adev); 579 580 return 0; 581 } 582 583 static int vega20_ih_hw_init(void *handle) 584 { 585 int r; 586 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 587 588 r = vega20_ih_irq_init(adev); 589 if (r) 590 return r; 591 592 return 0; 593 } 594 595 static int vega20_ih_hw_fini(void *handle) 596 { 597 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 598 599 vega20_ih_irq_disable(adev); 600 601 return 0; 602 } 603 604 static int vega20_ih_suspend(void *handle) 605 { 606 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 607 608 return vega20_ih_hw_fini(adev); 609 } 610 611 static int vega20_ih_resume(void *handle) 612 { 613 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 614 615 return vega20_ih_hw_init(adev); 616 } 617 618 static bool vega20_ih_is_idle(void *handle) 619 { 620 /* todo */ 621 return true; 622 } 623 624 static int vega20_ih_wait_for_idle(void *handle) 625 { 626 /* todo */ 627 return -ETIMEDOUT; 628 } 629 630 static int vega20_ih_soft_reset(void *handle) 631 { 632 /* todo */ 633 634 return 0; 635 } 636 637 static void vega20_ih_update_clockgating_state(struct amdgpu_device *adev, 638 bool enable) 639 { 640 uint32_t data, def, field_val; 641 642 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 643 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 644 field_val = enable ? 0 : 1; 645 data = REG_SET_FIELD(data, IH_CLK_CTRL, 646 IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val); 647 data = REG_SET_FIELD(data, IH_CLK_CTRL, 648 IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val); 649 data = REG_SET_FIELD(data, IH_CLK_CTRL, 650 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 651 data = REG_SET_FIELD(data, IH_CLK_CTRL, 652 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 653 data = REG_SET_FIELD(data, IH_CLK_CTRL, 654 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 655 data = REG_SET_FIELD(data, IH_CLK_CTRL, 656 DYN_CLK_SOFT_OVERRIDE, field_val); 657 data = REG_SET_FIELD(data, IH_CLK_CTRL, 658 REG_CLK_SOFT_OVERRIDE, field_val); 659 if (def != data) 660 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 661 } 662 } 663 664 static int vega20_ih_set_clockgating_state(void *handle, 665 enum amd_clockgating_state state) 666 { 667 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 668 669 vega20_ih_update_clockgating_state(adev, 670 state == AMD_CG_STATE_GATE); 671 return 0; 672 673 } 674 675 static int vega20_ih_set_powergating_state(void *handle, 676 enum amd_powergating_state state) 677 { 678 return 0; 679 } 680 681 const struct amd_ip_funcs vega20_ih_ip_funcs = { 682 .name = "vega20_ih", 683 .early_init = vega20_ih_early_init, 684 .late_init = NULL, 685 .sw_init = vega20_ih_sw_init, 686 .sw_fini = vega20_ih_sw_fini, 687 .hw_init = vega20_ih_hw_init, 688 .hw_fini = vega20_ih_hw_fini, 689 .suspend = vega20_ih_suspend, 690 .resume = vega20_ih_resume, 691 .is_idle = vega20_ih_is_idle, 692 .wait_for_idle = vega20_ih_wait_for_idle, 693 .soft_reset = vega20_ih_soft_reset, 694 .set_clockgating_state = vega20_ih_set_clockgating_state, 695 .set_powergating_state = vega20_ih_set_powergating_state, 696 }; 697 698 static const struct amdgpu_ih_funcs vega20_ih_funcs = { 699 .get_wptr = vega20_ih_get_wptr, 700 .decode_iv = amdgpu_ih_decode_iv_helper, 701 .decode_iv_ts = amdgpu_ih_decode_iv_ts_helper, 702 .set_rptr = vega20_ih_set_rptr 703 }; 704 705 static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev) 706 { 707 adev->irq.ih_funcs = &vega20_ih_funcs; 708 } 709 710 const struct amdgpu_ip_block_version vega20_ih_ip_block = 711 { 712 .type = AMD_IP_BLOCK_TYPE_IH, 713 .major = 4, 714 .minor = 2, 715 .rev = 0, 716 .funcs = &vega20_ih_ip_funcs, 717 }; 718