1bebd4c79SHawking Zhang /* 2bebd4c79SHawking Zhang * Copyright 2020 Advanced Micro Devices, Inc. 3bebd4c79SHawking Zhang * 4bebd4c79SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5bebd4c79SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6bebd4c79SHawking Zhang * to deal in the Software without restriction, including without limitation 7bebd4c79SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8bebd4c79SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9bebd4c79SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10bebd4c79SHawking Zhang * 11bebd4c79SHawking Zhang * The above copyright notice and this permission notice shall be included in 12bebd4c79SHawking Zhang * all copies or substantial portions of the Software. 13bebd4c79SHawking Zhang * 14bebd4c79SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15bebd4c79SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16bebd4c79SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17bebd4c79SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18bebd4c79SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19bebd4c79SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20bebd4c79SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21bebd4c79SHawking Zhang * 22bebd4c79SHawking Zhang */ 23bebd4c79SHawking Zhang 24bebd4c79SHawking Zhang #include <linux/pci.h> 25bebd4c79SHawking Zhang 26bebd4c79SHawking Zhang #include "amdgpu.h" 27bebd4c79SHawking Zhang #include "amdgpu_ih.h" 28bebd4c79SHawking Zhang #include "soc15.h" 29bebd4c79SHawking Zhang 30bebd4c79SHawking Zhang #include "oss/osssys_4_2_0_offset.h" 31bebd4c79SHawking Zhang #include "oss/osssys_4_2_0_sh_mask.h" 32bebd4c79SHawking Zhang 33bebd4c79SHawking Zhang #include "soc15_common.h" 34bebd4c79SHawking Zhang #include "vega20_ih.h" 35bebd4c79SHawking Zhang 36bebd4c79SHawking Zhang #define MAX_REARM_RETRY 10 37bebd4c79SHawking Zhang 38eed4bbd3SHawking Zhang #define mmIH_CHICKEN_ALDEBARAN 0x18d 39eed4bbd3SHawking Zhang #define mmIH_CHICKEN_ALDEBARAN_BASE_IDX 0 40eed4bbd3SHawking Zhang 41318e431bSMukul Joshi #define mmIH_RETRY_INT_CAM_CNTL_ALDEBARAN 0x00ea 42318e431bSMukul Joshi #define mmIH_RETRY_INT_CAM_CNTL_ALDEBARAN_BASE_IDX 0 43318e431bSMukul Joshi #define IH_RETRY_INT_CAM_CNTL_ALDEBARAN__ENABLE__SHIFT 0x10 44318e431bSMukul Joshi #define IH_RETRY_INT_CAM_CNTL_ALDEBARAN__ENABLE_MASK 0x00010000L 45318e431bSMukul Joshi 46bebd4c79SHawking Zhang static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev); 47bebd4c79SHawking Zhang 48bebd4c79SHawking Zhang /** 49bebd4c79SHawking Zhang * vega20_ih_init_register_offset - Initialize register offset for ih rings 50bebd4c79SHawking Zhang * 51bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 52bebd4c79SHawking Zhang * 53bebd4c79SHawking Zhang * Initialize register offset ih rings (VEGA20). 54bebd4c79SHawking Zhang */ 55bebd4c79SHawking Zhang static void vega20_ih_init_register_offset(struct amdgpu_device *adev) 56bebd4c79SHawking Zhang { 57bebd4c79SHawking Zhang struct amdgpu_ih_regs *ih_regs; 58bebd4c79SHawking Zhang 59bebd4c79SHawking Zhang if (adev->irq.ih.ring_size) { 60bebd4c79SHawking Zhang ih_regs = &adev->irq.ih.ih_regs; 61bebd4c79SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 62bebd4c79SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 63bebd4c79SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 64bebd4c79SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 65bebd4c79SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 66bebd4c79SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 67bebd4c79SHawking Zhang ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 68bebd4c79SHawking Zhang ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 69bebd4c79SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 70bebd4c79SHawking Zhang } 71bebd4c79SHawking Zhang 72bebd4c79SHawking Zhang if (adev->irq.ih1.ring_size) { 73bebd4c79SHawking Zhang ih_regs = &adev->irq.ih1.ih_regs; 74bebd4c79SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 75bebd4c79SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 76bebd4c79SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 77bebd4c79SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 78bebd4c79SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 79bebd4c79SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 80bebd4c79SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 81bebd4c79SHawking Zhang } 82bebd4c79SHawking Zhang 83bebd4c79SHawking Zhang if (adev->irq.ih2.ring_size) { 84bebd4c79SHawking Zhang ih_regs = &adev->irq.ih2.ih_regs; 85bebd4c79SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 86bebd4c79SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 87bebd4c79SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 88bebd4c79SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 89bebd4c79SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 90bebd4c79SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 91bebd4c79SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 92bebd4c79SHawking Zhang } 93bebd4c79SHawking Zhang } 94bebd4c79SHawking Zhang 95bebd4c79SHawking Zhang /** 96bebd4c79SHawking Zhang * vega20_ih_toggle_ring_interrupts - toggle the interrupt ring buffer 97bebd4c79SHawking Zhang * 98bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 9993a2ba14SLee Jones * @ih: amdgpu_ih_ring pointer 100bebd4c79SHawking Zhang * @enable: true - enable the interrupts, false - disable the interrupts 101bebd4c79SHawking Zhang * 102bebd4c79SHawking Zhang * Toggle the interrupt ring buffer (VEGA20) 103bebd4c79SHawking Zhang */ 104bebd4c79SHawking Zhang static int vega20_ih_toggle_ring_interrupts(struct amdgpu_device *adev, 105bebd4c79SHawking Zhang struct amdgpu_ih_ring *ih, 106bebd4c79SHawking Zhang bool enable) 107bebd4c79SHawking Zhang { 108bebd4c79SHawking Zhang struct amdgpu_ih_regs *ih_regs; 109bebd4c79SHawking Zhang uint32_t tmp; 110bebd4c79SHawking Zhang 111bebd4c79SHawking Zhang ih_regs = &ih->ih_regs; 112bebd4c79SHawking Zhang 113bebd4c79SHawking Zhang tmp = RREG32(ih_regs->ih_rb_cntl); 114bebd4c79SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); 1159a9c59a8SAlex Sierra tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1); 1169a9c59a8SAlex Sierra 117bebd4c79SHawking Zhang /* enable_intr field is only valid in ring0 */ 118bebd4c79SHawking Zhang if (ih == &adev->irq.ih) 119bebd4c79SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); 120bebd4c79SHawking Zhang if (amdgpu_sriov_vf(adev)) { 121bebd4c79SHawking Zhang if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 122bebd4c79SHawking Zhang dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 123bebd4c79SHawking Zhang return -ETIMEDOUT; 124bebd4c79SHawking Zhang } 125bebd4c79SHawking Zhang } else { 126bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_cntl, tmp); 127bebd4c79SHawking Zhang } 128bebd4c79SHawking Zhang 129bebd4c79SHawking Zhang if (enable) { 130bebd4c79SHawking Zhang ih->enabled = true; 131bebd4c79SHawking Zhang } else { 132bebd4c79SHawking Zhang /* set rptr, wptr to 0 */ 133bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_rptr, 0); 134bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_wptr, 0); 135bebd4c79SHawking Zhang ih->enabled = false; 136bebd4c79SHawking Zhang ih->rptr = 0; 137bebd4c79SHawking Zhang } 138bebd4c79SHawking Zhang 139bebd4c79SHawking Zhang return 0; 140bebd4c79SHawking Zhang } 141bebd4c79SHawking Zhang 142bebd4c79SHawking Zhang /** 143bebd4c79SHawking Zhang * vega20_ih_toggle_interrupts - Toggle all the available interrupt ring buffers 144bebd4c79SHawking Zhang * 145bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 146bebd4c79SHawking Zhang * @enable: enable or disable interrupt ring buffers 147bebd4c79SHawking Zhang * 148bebd4c79SHawking Zhang * Toggle all the available interrupt ring buffers (VEGA20). 149bebd4c79SHawking Zhang */ 150bebd4c79SHawking Zhang static int vega20_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable) 151bebd4c79SHawking Zhang { 152bebd4c79SHawking Zhang struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 153bebd4c79SHawking Zhang int i; 154bebd4c79SHawking Zhang int r; 155bebd4c79SHawking Zhang 156bebd4c79SHawking Zhang for (i = 0; i < ARRAY_SIZE(ih); i++) { 157bebd4c79SHawking Zhang if (ih[i]->ring_size) { 158bebd4c79SHawking Zhang r = vega20_ih_toggle_ring_interrupts(adev, ih[i], enable); 159bebd4c79SHawking Zhang if (r) 160bebd4c79SHawking Zhang return r; 161bebd4c79SHawking Zhang } 162bebd4c79SHawking Zhang } 163bebd4c79SHawking Zhang 164bebd4c79SHawking Zhang return 0; 165bebd4c79SHawking Zhang } 166bebd4c79SHawking Zhang 167bebd4c79SHawking Zhang static uint32_t vega20_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 168bebd4c79SHawking Zhang { 169bebd4c79SHawking Zhang int rb_bufsz = order_base_2(ih->ring_size / 4); 170bebd4c79SHawking Zhang 171bebd4c79SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 172bebd4c79SHawking Zhang MC_SPACE, ih->use_bus_addr ? 1 : 4); 173bebd4c79SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 174bebd4c79SHawking Zhang WPTR_OVERFLOW_CLEAR, 1); 175bebd4c79SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 176bebd4c79SHawking Zhang WPTR_OVERFLOW_ENABLE, 1); 177bebd4c79SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 178bebd4c79SHawking Zhang /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 179bebd4c79SHawking Zhang * value is written to memory 180bebd4c79SHawking Zhang */ 181bebd4c79SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 182bebd4c79SHawking Zhang WPTR_WRITEBACK_ENABLE, 1); 183bebd4c79SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 184bebd4c79SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 185bebd4c79SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 186bebd4c79SHawking Zhang 187bebd4c79SHawking Zhang return ih_rb_cntl; 188bebd4c79SHawking Zhang } 189bebd4c79SHawking Zhang 190bebd4c79SHawking Zhang static uint32_t vega20_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 191bebd4c79SHawking Zhang { 192bebd4c79SHawking Zhang u32 ih_doorbell_rtpr = 0; 193bebd4c79SHawking Zhang 194bebd4c79SHawking Zhang if (ih->use_doorbell) { 195bebd4c79SHawking Zhang ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 196bebd4c79SHawking Zhang IH_DOORBELL_RPTR, OFFSET, 197bebd4c79SHawking Zhang ih->doorbell_index); 198bebd4c79SHawking Zhang ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 199bebd4c79SHawking Zhang IH_DOORBELL_RPTR, 200bebd4c79SHawking Zhang ENABLE, 1); 201bebd4c79SHawking Zhang } else { 202bebd4c79SHawking Zhang ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 203bebd4c79SHawking Zhang IH_DOORBELL_RPTR, 204bebd4c79SHawking Zhang ENABLE, 0); 205bebd4c79SHawking Zhang } 206bebd4c79SHawking Zhang return ih_doorbell_rtpr; 207bebd4c79SHawking Zhang } 208bebd4c79SHawking Zhang 209bebd4c79SHawking Zhang /** 210bebd4c79SHawking Zhang * vega20_ih_enable_ring - enable an ih ring buffer 211bebd4c79SHawking Zhang * 212bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 213bebd4c79SHawking Zhang * @ih: amdgpu_ih_ring pointer 214bebd4c79SHawking Zhang * 215bebd4c79SHawking Zhang * Enable an ih ring buffer (VEGA20) 216bebd4c79SHawking Zhang */ 217bebd4c79SHawking Zhang static int vega20_ih_enable_ring(struct amdgpu_device *adev, 218bebd4c79SHawking Zhang struct amdgpu_ih_ring *ih) 219bebd4c79SHawking Zhang { 220bebd4c79SHawking Zhang struct amdgpu_ih_regs *ih_regs; 221bebd4c79SHawking Zhang uint32_t tmp; 222bebd4c79SHawking Zhang 223bebd4c79SHawking Zhang ih_regs = &ih->ih_regs; 224bebd4c79SHawking Zhang 225bebd4c79SHawking Zhang /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 226bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 227bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 228bebd4c79SHawking Zhang 229bebd4c79SHawking Zhang tmp = RREG32(ih_regs->ih_rb_cntl); 230bebd4c79SHawking Zhang tmp = vega20_ih_rb_cntl(ih, tmp); 231bebd4c79SHawking Zhang if (ih == &adev->irq.ih) 232bebd4c79SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 233b672cb1eSPhilip Yang if (ih == &adev->irq.ih1) 234bebd4c79SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 235bebd4c79SHawking Zhang if (amdgpu_sriov_vf(adev)) { 236bebd4c79SHawking Zhang if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 237bebd4c79SHawking Zhang dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 238bebd4c79SHawking Zhang return -ETIMEDOUT; 239bebd4c79SHawking Zhang } 240bebd4c79SHawking Zhang } else { 241bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_cntl, tmp); 242bebd4c79SHawking Zhang } 243bebd4c79SHawking Zhang 244bebd4c79SHawking Zhang if (ih == &adev->irq.ih) { 245bebd4c79SHawking Zhang /* set the ih ring 0 writeback address whether it's enabled or not */ 246bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 247bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 248bebd4c79SHawking Zhang } 249bebd4c79SHawking Zhang 250bebd4c79SHawking Zhang /* set rptr, wptr to 0 */ 251bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_wptr, 0); 252bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_rptr, 0); 253bebd4c79SHawking Zhang 254bebd4c79SHawking Zhang WREG32(ih_regs->ih_doorbell_rptr, vega20_ih_doorbell_rptr(ih)); 255bebd4c79SHawking Zhang 256bebd4c79SHawking Zhang return 0; 257bebd4c79SHawking Zhang } 258bebd4c79SHawking Zhang 259318e431bSMukul Joshi static uint32_t vega20_setup_retry_doorbell(u32 doorbell_index) 260726e5b37SHawking Zhang { 261318e431bSMukul Joshi u32 val = 0; 262726e5b37SHawking Zhang 263318e431bSMukul Joshi val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, OFFSET, doorbell_index); 264318e431bSMukul Joshi val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, ENABLE, 1); 265726e5b37SHawking Zhang 266318e431bSMukul Joshi return val; 267726e5b37SHawking Zhang } 268726e5b37SHawking Zhang 269726e5b37SHawking Zhang /** 270bebd4c79SHawking Zhang * vega20_ih_irq_init - init and enable the interrupt ring 271bebd4c79SHawking Zhang * 272bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 273bebd4c79SHawking Zhang * 274bebd4c79SHawking Zhang * Allocate a ring buffer for the interrupt controller, 275bebd4c79SHawking Zhang * enable the RLC, disable interrupts, enable the IH 276bebd4c79SHawking Zhang * ring buffer and enable it (VI). 277bebd4c79SHawking Zhang * Called at device load and reume. 278bebd4c79SHawking Zhang * Returns 0 for success, errors for failure. 279bebd4c79SHawking Zhang */ 280bebd4c79SHawking Zhang static int vega20_ih_irq_init(struct amdgpu_device *adev) 281bebd4c79SHawking Zhang { 282bebd4c79SHawking Zhang struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 283bebd4c79SHawking Zhang u32 ih_chicken; 284bebd4c79SHawking Zhang int ret; 285bebd4c79SHawking Zhang int i; 286bebd4c79SHawking Zhang 287bebd4c79SHawking Zhang /* disable irqs */ 288bebd4c79SHawking Zhang ret = vega20_ih_toggle_interrupts(adev, false); 289bebd4c79SHawking Zhang if (ret) 290bebd4c79SHawking Zhang return ret; 291bebd4c79SHawking Zhang 292bebd4c79SHawking Zhang adev->nbio.funcs->ih_control(adev); 293bebd4c79SHawking Zhang 294886f1816SAlex Deucher if ((adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 2, 1)) && 295bebd4c79SHawking Zhang adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 296bebd4c79SHawking Zhang ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 297bebd4c79SHawking Zhang if (adev->irq.ih.use_bus_addr) { 298bebd4c79SHawking Zhang ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 299bebd4c79SHawking Zhang MC_SPACE_GPA_ENABLE, 1); 300bebd4c79SHawking Zhang } 301bebd4c79SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 302bebd4c79SHawking Zhang } 303bebd4c79SHawking Zhang 304eed4bbd3SHawking Zhang /* psp firmware won't program IH_CHICKEN for aldebaran 305eed4bbd3SHawking Zhang * driver needs to program it properly according to 306eed4bbd3SHawking Zhang * MC_SPACE type in IH_RB_CNTL */ 3072b396e75SLe Ma if ((adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 0)) || 3082b396e75SLe Ma (adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 2))) { 309eed4bbd3SHawking Zhang ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN); 310eed4bbd3SHawking Zhang if (adev->irq.ih.use_bus_addr) { 311eed4bbd3SHawking Zhang ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 312eed4bbd3SHawking Zhang MC_SPACE_GPA_ENABLE, 1); 313eed4bbd3SHawking Zhang } 314eed4bbd3SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN, ih_chicken); 315eed4bbd3SHawking Zhang } 316eed4bbd3SHawking Zhang 317bebd4c79SHawking Zhang for (i = 0; i < ARRAY_SIZE(ih); i++) { 318bebd4c79SHawking Zhang if (ih[i]->ring_size) { 319bebd4c79SHawking Zhang ret = vega20_ih_enable_ring(adev, ih[i]); 320bebd4c79SHawking Zhang if (ret) 321bebd4c79SHawking Zhang return ret; 322bebd4c79SHawking Zhang } 323bebd4c79SHawking Zhang } 324bebd4c79SHawking Zhang 325dc1d85cbSAlex Deucher if (!amdgpu_sriov_vf(adev)) 326dc1d85cbSAlex Deucher adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, 327dc1d85cbSAlex Deucher adev->irq.ih.doorbell_index); 328dc1d85cbSAlex Deucher 329bebd4c79SHawking Zhang pci_set_master(adev->pdev); 330bebd4c79SHawking Zhang 331318e431bSMukul Joshi /* Allocate the doorbell for IH Retry CAM */ 332318e431bSMukul Joshi adev->irq.retry_cam_doorbell_index = (adev->doorbell_index.ih + 3) << 1; 333318e431bSMukul Joshi WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RETRY_CAM, 334318e431bSMukul Joshi vega20_setup_retry_doorbell(adev->irq.retry_cam_doorbell_index)); 335318e431bSMukul Joshi 336318e431bSMukul Joshi /* Enable IH Retry CAM */ 33740b832aaSMukul Joshi if (adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 0) || 33840b832aaSMukul Joshi adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 2)) 339318e431bSMukul Joshi WREG32_FIELD15(OSSSYS, 0, IH_RETRY_INT_CAM_CNTL_ALDEBARAN, 340318e431bSMukul Joshi ENABLE, 1); 341318e431bSMukul Joshi else 342318e431bSMukul Joshi WREG32_FIELD15(OSSSYS, 0, IH_RETRY_INT_CAM_CNTL, ENABLE, 1); 343318e431bSMukul Joshi 344318e431bSMukul Joshi adev->irq.retry_cam_enabled = true; 345318e431bSMukul Joshi 346bebd4c79SHawking Zhang /* enable interrupts */ 347bebd4c79SHawking Zhang ret = vega20_ih_toggle_interrupts(adev, true); 348bebd4c79SHawking Zhang if (ret) 349bebd4c79SHawking Zhang return ret; 350bebd4c79SHawking Zhang 351f44a6c76SHawking Zhang if (adev->irq.ih_soft.ring_size) 352f44a6c76SHawking Zhang adev->irq.ih_soft.enabled = true; 353f44a6c76SHawking Zhang 354bebd4c79SHawking Zhang return 0; 355bebd4c79SHawking Zhang } 356bebd4c79SHawking Zhang 357bebd4c79SHawking Zhang /** 358bebd4c79SHawking Zhang * vega20_ih_irq_disable - disable interrupts 359bebd4c79SHawking Zhang * 360bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 361bebd4c79SHawking Zhang * 362bebd4c79SHawking Zhang * Disable interrupts on the hw (VEGA20). 363bebd4c79SHawking Zhang */ 364bebd4c79SHawking Zhang static void vega20_ih_irq_disable(struct amdgpu_device *adev) 365bebd4c79SHawking Zhang { 366bebd4c79SHawking Zhang vega20_ih_toggle_interrupts(adev, false); 367bebd4c79SHawking Zhang 368bebd4c79SHawking Zhang /* Wait and acknowledge irq */ 369bebd4c79SHawking Zhang mdelay(1); 370bebd4c79SHawking Zhang } 371bebd4c79SHawking Zhang 372bebd4c79SHawking Zhang /** 373bebd4c79SHawking Zhang * vega20_ih_get_wptr - get the IH ring buffer wptr 374bebd4c79SHawking Zhang * 375bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 37693a2ba14SLee Jones * @ih: amdgpu_ih_ring pointer 377bebd4c79SHawking Zhang * 378bebd4c79SHawking Zhang * Get the IH ring buffer wptr from either the register 379bebd4c79SHawking Zhang * or the writeback memory buffer (VEGA20). Also check for 380bebd4c79SHawking Zhang * ring buffer overflow and deal with it. 381bebd4c79SHawking Zhang * Returns the value of the wptr. 382bebd4c79SHawking Zhang */ 383bebd4c79SHawking Zhang static u32 vega20_ih_get_wptr(struct amdgpu_device *adev, 384bebd4c79SHawking Zhang struct amdgpu_ih_ring *ih) 385bebd4c79SHawking Zhang { 386bebd4c79SHawking Zhang u32 wptr, tmp; 387bebd4c79SHawking Zhang struct amdgpu_ih_regs *ih_regs; 388bebd4c79SHawking Zhang 389de8341eeSMukul Joshi if (ih == &adev->irq.ih || ih == &adev->irq.ih_soft) { 390b672cb1eSPhilip Yang /* Only ring0 supports writeback. On other rings fall back 391b672cb1eSPhilip Yang * to register-based code with overflow checking below. 392de8341eeSMukul Joshi * ih_soft ring doesn't have any backing hardware registers, 393de8341eeSMukul Joshi * update wptr and return. 394b672cb1eSPhilip Yang */ 395bebd4c79SHawking Zhang wptr = le32_to_cpu(*ih->wptr_cpu); 396bebd4c79SHawking Zhang 397bebd4c79SHawking Zhang if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 398bebd4c79SHawking Zhang goto out; 399b672cb1eSPhilip Yang } 400b672cb1eSPhilip Yang 401b672cb1eSPhilip Yang ih_regs = &ih->ih_regs; 402bebd4c79SHawking Zhang 403bebd4c79SHawking Zhang /* Double check that the overflow wasn't already cleared. */ 404bebd4c79SHawking Zhang wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); 405bebd4c79SHawking Zhang if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 406bebd4c79SHawking Zhang goto out; 407bebd4c79SHawking Zhang 408bebd4c79SHawking Zhang wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 409bebd4c79SHawking Zhang 410bebd4c79SHawking Zhang /* When a ring buffer overflow happen start parsing interrupt 411bebd4c79SHawking Zhang * from the last not overwritten vector (wptr + 32). Hopefully 412bebd4c79SHawking Zhang * this should allow us to catchup. 413bebd4c79SHawking Zhang */ 414bebd4c79SHawking Zhang tmp = (wptr + 32) & ih->ptr_mask; 415bebd4c79SHawking Zhang dev_warn(adev->dev, "IH ring buffer overflow " 416bebd4c79SHawking Zhang "(0x%08X, 0x%08X, 0x%08X)\n", 417bebd4c79SHawking Zhang wptr, ih->rptr, tmp); 418bebd4c79SHawking Zhang ih->rptr = tmp; 419bebd4c79SHawking Zhang 420bebd4c79SHawking Zhang tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); 421bebd4c79SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 422bebd4c79SHawking Zhang WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 423bebd4c79SHawking Zhang 424bebd4c79SHawking Zhang out: 425bebd4c79SHawking Zhang return (wptr & ih->ptr_mask); 426bebd4c79SHawking Zhang } 427bebd4c79SHawking Zhang 428bebd4c79SHawking Zhang /** 429bebd4c79SHawking Zhang * vega20_ih_irq_rearm - rearm IRQ if lost 430bebd4c79SHawking Zhang * 431bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 43293a2ba14SLee Jones * @ih: amdgpu_ih_ring pointer 433bebd4c79SHawking Zhang * 434bebd4c79SHawking Zhang */ 435bebd4c79SHawking Zhang static void vega20_ih_irq_rearm(struct amdgpu_device *adev, 436bebd4c79SHawking Zhang struct amdgpu_ih_ring *ih) 437bebd4c79SHawking Zhang { 438bebd4c79SHawking Zhang uint32_t v = 0; 439bebd4c79SHawking Zhang uint32_t i = 0; 440bebd4c79SHawking Zhang struct amdgpu_ih_regs *ih_regs; 441bebd4c79SHawking Zhang 442bebd4c79SHawking Zhang ih_regs = &ih->ih_regs; 443bebd4c79SHawking Zhang 444bebd4c79SHawking Zhang /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */ 445bebd4c79SHawking Zhang for (i = 0; i < MAX_REARM_RETRY; i++) { 446bebd4c79SHawking Zhang v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); 447bebd4c79SHawking Zhang if ((v < ih->ring_size) && (v != ih->rptr)) 448bebd4c79SHawking Zhang WDOORBELL32(ih->doorbell_index, ih->rptr); 449bebd4c79SHawking Zhang else 450bebd4c79SHawking Zhang break; 451bebd4c79SHawking Zhang } 452bebd4c79SHawking Zhang } 453bebd4c79SHawking Zhang 454bebd4c79SHawking Zhang /** 455bebd4c79SHawking Zhang * vega20_ih_set_rptr - set the IH ring buffer rptr 456bebd4c79SHawking Zhang * 457bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 45893a2ba14SLee Jones * @ih: amdgpu_ih_ring pointer 459bebd4c79SHawking Zhang * 460bebd4c79SHawking Zhang * Set the IH ring buffer rptr. 461bebd4c79SHawking Zhang */ 462bebd4c79SHawking Zhang static void vega20_ih_set_rptr(struct amdgpu_device *adev, 463bebd4c79SHawking Zhang struct amdgpu_ih_ring *ih) 464bebd4c79SHawking Zhang { 465bebd4c79SHawking Zhang struct amdgpu_ih_regs *ih_regs; 466bebd4c79SHawking Zhang 467de8341eeSMukul Joshi if (ih == &adev->irq.ih_soft) 468de8341eeSMukul Joshi return; 469de8341eeSMukul Joshi 470bebd4c79SHawking Zhang if (ih->use_doorbell) { 471bebd4c79SHawking Zhang /* XXX check if swapping is necessary on BE */ 472bebd4c79SHawking Zhang *ih->rptr_cpu = ih->rptr; 473bebd4c79SHawking Zhang WDOORBELL32(ih->doorbell_index, ih->rptr); 474bebd4c79SHawking Zhang 475bebd4c79SHawking Zhang if (amdgpu_sriov_vf(adev)) 476bebd4c79SHawking Zhang vega20_ih_irq_rearm(adev, ih); 477bebd4c79SHawking Zhang } else { 478bebd4c79SHawking Zhang ih_regs = &ih->ih_regs; 479bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_rptr, ih->rptr); 480bebd4c79SHawking Zhang } 481bebd4c79SHawking Zhang } 482bebd4c79SHawking Zhang 483bebd4c79SHawking Zhang /** 484bebd4c79SHawking Zhang * vega20_ih_self_irq - dispatch work for ring 1 and 2 485bebd4c79SHawking Zhang * 486bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 487bebd4c79SHawking Zhang * @source: irq source 488bebd4c79SHawking Zhang * @entry: IV with WPTR update 489bebd4c79SHawking Zhang * 490bebd4c79SHawking Zhang * Update the WPTR from the IV and schedule work to handle the entries. 491bebd4c79SHawking Zhang */ 492bebd4c79SHawking Zhang static int vega20_ih_self_irq(struct amdgpu_device *adev, 493bebd4c79SHawking Zhang struct amdgpu_irq_src *source, 494bebd4c79SHawking Zhang struct amdgpu_iv_entry *entry) 495bebd4c79SHawking Zhang { 496bebd4c79SHawking Zhang switch (entry->ring_id) { 497bebd4c79SHawking Zhang case 1: 498bebd4c79SHawking Zhang schedule_work(&adev->irq.ih1_work); 499bebd4c79SHawking Zhang break; 500bebd4c79SHawking Zhang case 2: 501bebd4c79SHawking Zhang schedule_work(&adev->irq.ih2_work); 502bebd4c79SHawking Zhang break; 503bebd4c79SHawking Zhang default: break; 504bebd4c79SHawking Zhang } 505bebd4c79SHawking Zhang return 0; 506bebd4c79SHawking Zhang } 507bebd4c79SHawking Zhang 508bebd4c79SHawking Zhang static const struct amdgpu_irq_src_funcs vega20_ih_self_irq_funcs = { 509bebd4c79SHawking Zhang .process = vega20_ih_self_irq, 510bebd4c79SHawking Zhang }; 511bebd4c79SHawking Zhang 512bebd4c79SHawking Zhang static void vega20_ih_set_self_irq_funcs(struct amdgpu_device *adev) 513bebd4c79SHawking Zhang { 514bebd4c79SHawking Zhang adev->irq.self_irq.num_types = 0; 515bebd4c79SHawking Zhang adev->irq.self_irq.funcs = &vega20_ih_self_irq_funcs; 516bebd4c79SHawking Zhang } 517bebd4c79SHawking Zhang 518bebd4c79SHawking Zhang static int vega20_ih_early_init(void *handle) 519bebd4c79SHawking Zhang { 520bebd4c79SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 521bebd4c79SHawking Zhang 522bebd4c79SHawking Zhang vega20_ih_set_interrupt_funcs(adev); 523bebd4c79SHawking Zhang vega20_ih_set_self_irq_funcs(adev); 524bebd4c79SHawking Zhang return 0; 525bebd4c79SHawking Zhang } 526bebd4c79SHawking Zhang 527bebd4c79SHawking Zhang static int vega20_ih_sw_init(void *handle) 528bebd4c79SHawking Zhang { 529bebd4c79SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 530bc71daffSLijo Lazar bool use_bus_addr = true; 531bebd4c79SHawking Zhang int r; 532bebd4c79SHawking Zhang 533bebd4c79SHawking Zhang r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 534bebd4c79SHawking Zhang &adev->irq.self_irq); 535bebd4c79SHawking Zhang if (r) 536bebd4c79SHawking Zhang return r; 537bebd4c79SHawking Zhang 538bc71daffSLijo Lazar if ((adev->flags & AMD_IS_APU) && 539bc71daffSLijo Lazar (adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 2))) 540bc71daffSLijo Lazar use_bus_addr = false; 541bc71daffSLijo Lazar 542*bf80d34bSPhilip Yang r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, use_bus_addr); 543bebd4c79SHawking Zhang if (r) 544bebd4c79SHawking Zhang return r; 545bebd4c79SHawking Zhang 546bebd4c79SHawking Zhang adev->irq.ih.use_doorbell = true; 547bebd4c79SHawking Zhang adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 548bebd4c79SHawking Zhang 549bc71daffSLijo Lazar r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, use_bus_addr); 550bebd4c79SHawking Zhang if (r) 551bebd4c79SHawking Zhang return r; 552bebd4c79SHawking Zhang 553bebd4c79SHawking Zhang adev->irq.ih1.use_doorbell = true; 554bebd4c79SHawking Zhang adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; 555bebd4c79SHawking Zhang 5564c93c62eSLe Ma if (adev->ip_versions[OSSSYS_HWIP][0] != IP_VERSION(4, 4, 2)) { 557bebd4c79SHawking Zhang r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 558bebd4c79SHawking Zhang if (r) 559bebd4c79SHawking Zhang return r; 560bebd4c79SHawking Zhang 561bebd4c79SHawking Zhang adev->irq.ih2.use_doorbell = true; 562bebd4c79SHawking Zhang adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1; 5634c93c62eSLe Ma } 564bebd4c79SHawking Zhang 565bebd4c79SHawking Zhang /* initialize ih control registers offset */ 566bebd4c79SHawking Zhang vega20_ih_init_register_offset(adev); 567bebd4c79SHawking Zhang 568*bf80d34bSPhilip Yang r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, use_bus_addr); 569f44a6c76SHawking Zhang if (r) 570f44a6c76SHawking Zhang return r; 571f44a6c76SHawking Zhang 572bebd4c79SHawking Zhang r = amdgpu_irq_init(adev); 573bebd4c79SHawking Zhang 574bebd4c79SHawking Zhang return r; 575bebd4c79SHawking Zhang } 576bebd4c79SHawking Zhang 577bebd4c79SHawking Zhang static int vega20_ih_sw_fini(void *handle) 578bebd4c79SHawking Zhang { 579bebd4c79SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 580bebd4c79SHawking Zhang 58172c8c97bSAndrey Grodzovsky amdgpu_irq_fini_sw(adev); 582bebd4c79SHawking Zhang 583bebd4c79SHawking Zhang return 0; 584bebd4c79SHawking Zhang } 585bebd4c79SHawking Zhang 586bebd4c79SHawking Zhang static int vega20_ih_hw_init(void *handle) 587bebd4c79SHawking Zhang { 588bebd4c79SHawking Zhang int r; 589bebd4c79SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 590bebd4c79SHawking Zhang 591bebd4c79SHawking Zhang r = vega20_ih_irq_init(adev); 592bebd4c79SHawking Zhang if (r) 593bebd4c79SHawking Zhang return r; 594bebd4c79SHawking Zhang 595bebd4c79SHawking Zhang return 0; 596bebd4c79SHawking Zhang } 597bebd4c79SHawking Zhang 598bebd4c79SHawking Zhang static int vega20_ih_hw_fini(void *handle) 599bebd4c79SHawking Zhang { 600bebd4c79SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 601bebd4c79SHawking Zhang 602bebd4c79SHawking Zhang vega20_ih_irq_disable(adev); 603bebd4c79SHawking Zhang 604bebd4c79SHawking Zhang return 0; 605bebd4c79SHawking Zhang } 606bebd4c79SHawking Zhang 607bebd4c79SHawking Zhang static int vega20_ih_suspend(void *handle) 608bebd4c79SHawking Zhang { 609bebd4c79SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 610bebd4c79SHawking Zhang 611bebd4c79SHawking Zhang return vega20_ih_hw_fini(adev); 612bebd4c79SHawking Zhang } 613bebd4c79SHawking Zhang 614bebd4c79SHawking Zhang static int vega20_ih_resume(void *handle) 615bebd4c79SHawking Zhang { 616bebd4c79SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 617bebd4c79SHawking Zhang 618bebd4c79SHawking Zhang return vega20_ih_hw_init(adev); 619bebd4c79SHawking Zhang } 620bebd4c79SHawking Zhang 621bebd4c79SHawking Zhang static bool vega20_ih_is_idle(void *handle) 622bebd4c79SHawking Zhang { 623bebd4c79SHawking Zhang /* todo */ 624bebd4c79SHawking Zhang return true; 625bebd4c79SHawking Zhang } 626bebd4c79SHawking Zhang 627bebd4c79SHawking Zhang static int vega20_ih_wait_for_idle(void *handle) 628bebd4c79SHawking Zhang { 629bebd4c79SHawking Zhang /* todo */ 630bebd4c79SHawking Zhang return -ETIMEDOUT; 631bebd4c79SHawking Zhang } 632bebd4c79SHawking Zhang 633bebd4c79SHawking Zhang static int vega20_ih_soft_reset(void *handle) 634bebd4c79SHawking Zhang { 635bebd4c79SHawking Zhang /* todo */ 636bebd4c79SHawking Zhang 637bebd4c79SHawking Zhang return 0; 638bebd4c79SHawking Zhang } 639bebd4c79SHawking Zhang 640bebd4c79SHawking Zhang static void vega20_ih_update_clockgating_state(struct amdgpu_device *adev, 641bebd4c79SHawking Zhang bool enable) 642bebd4c79SHawking Zhang { 643bebd4c79SHawking Zhang uint32_t data, def, field_val; 644bebd4c79SHawking Zhang 645bebd4c79SHawking Zhang if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 646bebd4c79SHawking Zhang def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 647bebd4c79SHawking Zhang field_val = enable ? 0 : 1; 648bebd4c79SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 649bebd4c79SHawking Zhang IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val); 650bebd4c79SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 651bebd4c79SHawking Zhang IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val); 652bebd4c79SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 653bebd4c79SHawking Zhang DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 654bebd4c79SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 655bebd4c79SHawking Zhang OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 656bebd4c79SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 657bebd4c79SHawking Zhang LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 658bebd4c79SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 659bebd4c79SHawking Zhang DYN_CLK_SOFT_OVERRIDE, field_val); 660bebd4c79SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 661bebd4c79SHawking Zhang REG_CLK_SOFT_OVERRIDE, field_val); 662bebd4c79SHawking Zhang if (def != data) 663bebd4c79SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 664bebd4c79SHawking Zhang } 665bebd4c79SHawking Zhang } 666bebd4c79SHawking Zhang 667bebd4c79SHawking Zhang static int vega20_ih_set_clockgating_state(void *handle, 668bebd4c79SHawking Zhang enum amd_clockgating_state state) 669bebd4c79SHawking Zhang { 670bebd4c79SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 671bebd4c79SHawking Zhang 672bebd4c79SHawking Zhang vega20_ih_update_clockgating_state(adev, 673bebd4c79SHawking Zhang state == AMD_CG_STATE_GATE); 674bebd4c79SHawking Zhang return 0; 675bebd4c79SHawking Zhang 676bebd4c79SHawking Zhang } 677bebd4c79SHawking Zhang 678bebd4c79SHawking Zhang static int vega20_ih_set_powergating_state(void *handle, 679bebd4c79SHawking Zhang enum amd_powergating_state state) 680bebd4c79SHawking Zhang { 681bebd4c79SHawking Zhang return 0; 682bebd4c79SHawking Zhang } 683bebd4c79SHawking Zhang 684bebd4c79SHawking Zhang const struct amd_ip_funcs vega20_ih_ip_funcs = { 685bebd4c79SHawking Zhang .name = "vega20_ih", 686bebd4c79SHawking Zhang .early_init = vega20_ih_early_init, 687bebd4c79SHawking Zhang .late_init = NULL, 688bebd4c79SHawking Zhang .sw_init = vega20_ih_sw_init, 689bebd4c79SHawking Zhang .sw_fini = vega20_ih_sw_fini, 690bebd4c79SHawking Zhang .hw_init = vega20_ih_hw_init, 691bebd4c79SHawking Zhang .hw_fini = vega20_ih_hw_fini, 692bebd4c79SHawking Zhang .suspend = vega20_ih_suspend, 693bebd4c79SHawking Zhang .resume = vega20_ih_resume, 694bebd4c79SHawking Zhang .is_idle = vega20_ih_is_idle, 695bebd4c79SHawking Zhang .wait_for_idle = vega20_ih_wait_for_idle, 696bebd4c79SHawking Zhang .soft_reset = vega20_ih_soft_reset, 697bebd4c79SHawking Zhang .set_clockgating_state = vega20_ih_set_clockgating_state, 698bebd4c79SHawking Zhang .set_powergating_state = vega20_ih_set_powergating_state, 699bebd4c79SHawking Zhang }; 700bebd4c79SHawking Zhang 701bebd4c79SHawking Zhang static const struct amdgpu_ih_funcs vega20_ih_funcs = { 702bebd4c79SHawking Zhang .get_wptr = vega20_ih_get_wptr, 703bebd4c79SHawking Zhang .decode_iv = amdgpu_ih_decode_iv_helper, 7043c2d6ea2SPhilip Yang .decode_iv_ts = amdgpu_ih_decode_iv_ts_helper, 705bebd4c79SHawking Zhang .set_rptr = vega20_ih_set_rptr 706bebd4c79SHawking Zhang }; 707bebd4c79SHawking Zhang 708bebd4c79SHawking Zhang static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev) 709bebd4c79SHawking Zhang { 710bebd4c79SHawking Zhang adev->irq.ih_funcs = &vega20_ih_funcs; 711bebd4c79SHawking Zhang } 712bebd4c79SHawking Zhang 713bebd4c79SHawking Zhang const struct amdgpu_ip_block_version vega20_ih_ip_block = 714bebd4c79SHawking Zhang { 715bebd4c79SHawking Zhang .type = AMD_IP_BLOCK_TYPE_IH, 716bebd4c79SHawking Zhang .major = 4, 717bebd4c79SHawking Zhang .minor = 2, 718bebd4c79SHawking Zhang .rev = 0, 719bebd4c79SHawking Zhang .funcs = &vega20_ih_ip_funcs, 720bebd4c79SHawking Zhang }; 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