1*bebd4c79SHawking Zhang /* 2*bebd4c79SHawking Zhang * Copyright 2020 Advanced Micro Devices, Inc. 3*bebd4c79SHawking Zhang * 4*bebd4c79SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5*bebd4c79SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6*bebd4c79SHawking Zhang * to deal in the Software without restriction, including without limitation 7*bebd4c79SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*bebd4c79SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9*bebd4c79SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10*bebd4c79SHawking Zhang * 11*bebd4c79SHawking Zhang * The above copyright notice and this permission notice shall be included in 12*bebd4c79SHawking Zhang * all copies or substantial portions of the Software. 13*bebd4c79SHawking Zhang * 14*bebd4c79SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*bebd4c79SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*bebd4c79SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*bebd4c79SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*bebd4c79SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*bebd4c79SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*bebd4c79SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21*bebd4c79SHawking Zhang * 22*bebd4c79SHawking Zhang */ 23*bebd4c79SHawking Zhang 24*bebd4c79SHawking Zhang #include <linux/pci.h> 25*bebd4c79SHawking Zhang 26*bebd4c79SHawking Zhang #include "amdgpu.h" 27*bebd4c79SHawking Zhang #include "amdgpu_ih.h" 28*bebd4c79SHawking Zhang #include "soc15.h" 29*bebd4c79SHawking Zhang 30*bebd4c79SHawking Zhang #include "oss/osssys_4_2_0_offset.h" 31*bebd4c79SHawking Zhang #include "oss/osssys_4_2_0_sh_mask.h" 32*bebd4c79SHawking Zhang 33*bebd4c79SHawking Zhang #include "soc15_common.h" 34*bebd4c79SHawking Zhang #include "vega20_ih.h" 35*bebd4c79SHawking Zhang 36*bebd4c79SHawking Zhang #define MAX_REARM_RETRY 10 37*bebd4c79SHawking Zhang 38*bebd4c79SHawking Zhang static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev); 39*bebd4c79SHawking Zhang 40*bebd4c79SHawking Zhang /** 41*bebd4c79SHawking Zhang * vega20_ih_init_register_offset - Initialize register offset for ih rings 42*bebd4c79SHawking Zhang * 43*bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 44*bebd4c79SHawking Zhang * 45*bebd4c79SHawking Zhang * Initialize register offset ih rings (VEGA20). 46*bebd4c79SHawking Zhang */ 47*bebd4c79SHawking Zhang static void vega20_ih_init_register_offset(struct amdgpu_device *adev) 48*bebd4c79SHawking Zhang { 49*bebd4c79SHawking Zhang struct amdgpu_ih_regs *ih_regs; 50*bebd4c79SHawking Zhang 51*bebd4c79SHawking Zhang if (adev->irq.ih.ring_size) { 52*bebd4c79SHawking Zhang ih_regs = &adev->irq.ih.ih_regs; 53*bebd4c79SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 54*bebd4c79SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 55*bebd4c79SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 56*bebd4c79SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 57*bebd4c79SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 58*bebd4c79SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 59*bebd4c79SHawking Zhang ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 60*bebd4c79SHawking Zhang ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 61*bebd4c79SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 62*bebd4c79SHawking Zhang } 63*bebd4c79SHawking Zhang 64*bebd4c79SHawking Zhang if (adev->irq.ih1.ring_size) { 65*bebd4c79SHawking Zhang ih_regs = &adev->irq.ih1.ih_regs; 66*bebd4c79SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 67*bebd4c79SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 68*bebd4c79SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 69*bebd4c79SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 70*bebd4c79SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 71*bebd4c79SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 72*bebd4c79SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 73*bebd4c79SHawking Zhang } 74*bebd4c79SHawking Zhang 75*bebd4c79SHawking Zhang if (adev->irq.ih2.ring_size) { 76*bebd4c79SHawking Zhang ih_regs = &adev->irq.ih2.ih_regs; 77*bebd4c79SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 78*bebd4c79SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 79*bebd4c79SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 80*bebd4c79SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 81*bebd4c79SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 82*bebd4c79SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 83*bebd4c79SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 84*bebd4c79SHawking Zhang } 85*bebd4c79SHawking Zhang } 86*bebd4c79SHawking Zhang 87*bebd4c79SHawking Zhang /** 88*bebd4c79SHawking Zhang * vega20_ih_toggle_ring_interrupts - toggle the interrupt ring buffer 89*bebd4c79SHawking Zhang * 90*bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 91*bebd4c79SHawking Zhang * @ih: amdgpu_ih_ring pointet 92*bebd4c79SHawking Zhang * @enable: true - enable the interrupts, false - disable the interrupts 93*bebd4c79SHawking Zhang * 94*bebd4c79SHawking Zhang * Toggle the interrupt ring buffer (VEGA20) 95*bebd4c79SHawking Zhang */ 96*bebd4c79SHawking Zhang static int vega20_ih_toggle_ring_interrupts(struct amdgpu_device *adev, 97*bebd4c79SHawking Zhang struct amdgpu_ih_ring *ih, 98*bebd4c79SHawking Zhang bool enable) 99*bebd4c79SHawking Zhang { 100*bebd4c79SHawking Zhang struct amdgpu_ih_regs *ih_regs; 101*bebd4c79SHawking Zhang uint32_t tmp; 102*bebd4c79SHawking Zhang 103*bebd4c79SHawking Zhang ih_regs = &ih->ih_regs; 104*bebd4c79SHawking Zhang 105*bebd4c79SHawking Zhang tmp = RREG32(ih_regs->ih_rb_cntl); 106*bebd4c79SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); 107*bebd4c79SHawking Zhang /* enable_intr field is only valid in ring0 */ 108*bebd4c79SHawking Zhang if (ih == &adev->irq.ih) 109*bebd4c79SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); 110*bebd4c79SHawking Zhang if (amdgpu_sriov_vf(adev)) { 111*bebd4c79SHawking Zhang if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 112*bebd4c79SHawking Zhang dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 113*bebd4c79SHawking Zhang return -ETIMEDOUT; 114*bebd4c79SHawking Zhang } 115*bebd4c79SHawking Zhang } else { 116*bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_cntl, tmp); 117*bebd4c79SHawking Zhang } 118*bebd4c79SHawking Zhang 119*bebd4c79SHawking Zhang if (enable) { 120*bebd4c79SHawking Zhang ih->enabled = true; 121*bebd4c79SHawking Zhang } else { 122*bebd4c79SHawking Zhang /* set rptr, wptr to 0 */ 123*bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_rptr, 0); 124*bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_wptr, 0); 125*bebd4c79SHawking Zhang ih->enabled = false; 126*bebd4c79SHawking Zhang ih->rptr = 0; 127*bebd4c79SHawking Zhang } 128*bebd4c79SHawking Zhang 129*bebd4c79SHawking Zhang return 0; 130*bebd4c79SHawking Zhang } 131*bebd4c79SHawking Zhang 132*bebd4c79SHawking Zhang /** 133*bebd4c79SHawking Zhang * vega20_ih_toggle_interrupts - Toggle all the available interrupt ring buffers 134*bebd4c79SHawking Zhang * 135*bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 136*bebd4c79SHawking Zhang * @enable: enable or disable interrupt ring buffers 137*bebd4c79SHawking Zhang * 138*bebd4c79SHawking Zhang * Toggle all the available interrupt ring buffers (VEGA20). 139*bebd4c79SHawking Zhang */ 140*bebd4c79SHawking Zhang static int vega20_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable) 141*bebd4c79SHawking Zhang { 142*bebd4c79SHawking Zhang struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 143*bebd4c79SHawking Zhang int i; 144*bebd4c79SHawking Zhang int r; 145*bebd4c79SHawking Zhang 146*bebd4c79SHawking Zhang for (i = 0; i < ARRAY_SIZE(ih); i++) { 147*bebd4c79SHawking Zhang if (ih[i]->ring_size) { 148*bebd4c79SHawking Zhang r = vega20_ih_toggle_ring_interrupts(adev, ih[i], enable); 149*bebd4c79SHawking Zhang if (r) 150*bebd4c79SHawking Zhang return r; 151*bebd4c79SHawking Zhang } 152*bebd4c79SHawking Zhang } 153*bebd4c79SHawking Zhang 154*bebd4c79SHawking Zhang return 0; 155*bebd4c79SHawking Zhang } 156*bebd4c79SHawking Zhang 157*bebd4c79SHawking Zhang static uint32_t vega20_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 158*bebd4c79SHawking Zhang { 159*bebd4c79SHawking Zhang int rb_bufsz = order_base_2(ih->ring_size / 4); 160*bebd4c79SHawking Zhang 161*bebd4c79SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 162*bebd4c79SHawking Zhang MC_SPACE, ih->use_bus_addr ? 1 : 4); 163*bebd4c79SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 164*bebd4c79SHawking Zhang WPTR_OVERFLOW_CLEAR, 1); 165*bebd4c79SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 166*bebd4c79SHawking Zhang WPTR_OVERFLOW_ENABLE, 1); 167*bebd4c79SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 168*bebd4c79SHawking Zhang /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 169*bebd4c79SHawking Zhang * value is written to memory 170*bebd4c79SHawking Zhang */ 171*bebd4c79SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 172*bebd4c79SHawking Zhang WPTR_WRITEBACK_ENABLE, 1); 173*bebd4c79SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 174*bebd4c79SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 175*bebd4c79SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 176*bebd4c79SHawking Zhang 177*bebd4c79SHawking Zhang return ih_rb_cntl; 178*bebd4c79SHawking Zhang } 179*bebd4c79SHawking Zhang 180*bebd4c79SHawking Zhang static uint32_t vega20_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 181*bebd4c79SHawking Zhang { 182*bebd4c79SHawking Zhang u32 ih_doorbell_rtpr = 0; 183*bebd4c79SHawking Zhang 184*bebd4c79SHawking Zhang if (ih->use_doorbell) { 185*bebd4c79SHawking Zhang ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 186*bebd4c79SHawking Zhang IH_DOORBELL_RPTR, OFFSET, 187*bebd4c79SHawking Zhang ih->doorbell_index); 188*bebd4c79SHawking Zhang ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 189*bebd4c79SHawking Zhang IH_DOORBELL_RPTR, 190*bebd4c79SHawking Zhang ENABLE, 1); 191*bebd4c79SHawking Zhang } else { 192*bebd4c79SHawking Zhang ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 193*bebd4c79SHawking Zhang IH_DOORBELL_RPTR, 194*bebd4c79SHawking Zhang ENABLE, 0); 195*bebd4c79SHawking Zhang } 196*bebd4c79SHawking Zhang return ih_doorbell_rtpr; 197*bebd4c79SHawking Zhang } 198*bebd4c79SHawking Zhang 199*bebd4c79SHawking Zhang /** 200*bebd4c79SHawking Zhang * vega20_ih_enable_ring - enable an ih ring buffer 201*bebd4c79SHawking Zhang * 202*bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 203*bebd4c79SHawking Zhang * @ih: amdgpu_ih_ring pointer 204*bebd4c79SHawking Zhang * 205*bebd4c79SHawking Zhang * Enable an ih ring buffer (VEGA20) 206*bebd4c79SHawking Zhang */ 207*bebd4c79SHawking Zhang static int vega20_ih_enable_ring(struct amdgpu_device *adev, 208*bebd4c79SHawking Zhang struct amdgpu_ih_ring *ih) 209*bebd4c79SHawking Zhang { 210*bebd4c79SHawking Zhang struct amdgpu_ih_regs *ih_regs; 211*bebd4c79SHawking Zhang uint32_t tmp; 212*bebd4c79SHawking Zhang 213*bebd4c79SHawking Zhang ih_regs = &ih->ih_regs; 214*bebd4c79SHawking Zhang 215*bebd4c79SHawking Zhang /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 216*bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 217*bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 218*bebd4c79SHawking Zhang 219*bebd4c79SHawking Zhang tmp = RREG32(ih_regs->ih_rb_cntl); 220*bebd4c79SHawking Zhang tmp = vega20_ih_rb_cntl(ih, tmp); 221*bebd4c79SHawking Zhang if (ih == &adev->irq.ih) 222*bebd4c79SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 223*bebd4c79SHawking Zhang if (ih == &adev->irq.ih1) { 224*bebd4c79SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0); 225*bebd4c79SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 226*bebd4c79SHawking Zhang } 227*bebd4c79SHawking Zhang if (amdgpu_sriov_vf(adev)) { 228*bebd4c79SHawking Zhang if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 229*bebd4c79SHawking Zhang dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 230*bebd4c79SHawking Zhang return -ETIMEDOUT; 231*bebd4c79SHawking Zhang } 232*bebd4c79SHawking Zhang } else { 233*bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_cntl, tmp); 234*bebd4c79SHawking Zhang } 235*bebd4c79SHawking Zhang 236*bebd4c79SHawking Zhang if (ih == &adev->irq.ih) { 237*bebd4c79SHawking Zhang /* set the ih ring 0 writeback address whether it's enabled or not */ 238*bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 239*bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 240*bebd4c79SHawking Zhang } 241*bebd4c79SHawking Zhang 242*bebd4c79SHawking Zhang /* set rptr, wptr to 0 */ 243*bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_wptr, 0); 244*bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_rptr, 0); 245*bebd4c79SHawking Zhang 246*bebd4c79SHawking Zhang WREG32(ih_regs->ih_doorbell_rptr, vega20_ih_doorbell_rptr(ih)); 247*bebd4c79SHawking Zhang 248*bebd4c79SHawking Zhang return 0; 249*bebd4c79SHawking Zhang } 250*bebd4c79SHawking Zhang 251*bebd4c79SHawking Zhang /** 252*bebd4c79SHawking Zhang * vega20_ih_irq_init - init and enable the interrupt ring 253*bebd4c79SHawking Zhang * 254*bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 255*bebd4c79SHawking Zhang * 256*bebd4c79SHawking Zhang * Allocate a ring buffer for the interrupt controller, 257*bebd4c79SHawking Zhang * enable the RLC, disable interrupts, enable the IH 258*bebd4c79SHawking Zhang * ring buffer and enable it (VI). 259*bebd4c79SHawking Zhang * Called at device load and reume. 260*bebd4c79SHawking Zhang * Returns 0 for success, errors for failure. 261*bebd4c79SHawking Zhang */ 262*bebd4c79SHawking Zhang static int vega20_ih_irq_init(struct amdgpu_device *adev) 263*bebd4c79SHawking Zhang { 264*bebd4c79SHawking Zhang struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 265*bebd4c79SHawking Zhang u32 ih_chicken; 266*bebd4c79SHawking Zhang int ret; 267*bebd4c79SHawking Zhang int i; 268*bebd4c79SHawking Zhang u32 tmp; 269*bebd4c79SHawking Zhang 270*bebd4c79SHawking Zhang /* disable irqs */ 271*bebd4c79SHawking Zhang ret = vega20_ih_toggle_interrupts(adev, false); 272*bebd4c79SHawking Zhang if (ret) 273*bebd4c79SHawking Zhang return ret; 274*bebd4c79SHawking Zhang 275*bebd4c79SHawking Zhang adev->nbio.funcs->ih_control(adev); 276*bebd4c79SHawking Zhang 277*bebd4c79SHawking Zhang if (adev->asic_type == CHIP_ARCTURUS && 278*bebd4c79SHawking Zhang adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 279*bebd4c79SHawking Zhang ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 280*bebd4c79SHawking Zhang if (adev->irq.ih.use_bus_addr) { 281*bebd4c79SHawking Zhang ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 282*bebd4c79SHawking Zhang MC_SPACE_GPA_ENABLE, 1); 283*bebd4c79SHawking Zhang } else { 284*bebd4c79SHawking Zhang ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, 285*bebd4c79SHawking Zhang MC_SPACE_FBPA_ENABLE, 1); 286*bebd4c79SHawking Zhang } 287*bebd4c79SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 288*bebd4c79SHawking Zhang } 289*bebd4c79SHawking Zhang 290*bebd4c79SHawking Zhang for (i = 0; i < ARRAY_SIZE(ih); i++) { 291*bebd4c79SHawking Zhang if (ih[i]->ring_size) { 292*bebd4c79SHawking Zhang ret = vega20_ih_enable_ring(adev, ih[i]); 293*bebd4c79SHawking Zhang if (ret) 294*bebd4c79SHawking Zhang return ret; 295*bebd4c79SHawking Zhang } 296*bebd4c79SHawking Zhang } 297*bebd4c79SHawking Zhang 298*bebd4c79SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 299*bebd4c79SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 300*bebd4c79SHawking Zhang CLIENT18_IS_STORM_CLIENT, 1); 301*bebd4c79SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 302*bebd4c79SHawking Zhang 303*bebd4c79SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 304*bebd4c79SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 305*bebd4c79SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 306*bebd4c79SHawking Zhang 307*bebd4c79SHawking Zhang pci_set_master(adev->pdev); 308*bebd4c79SHawking Zhang 309*bebd4c79SHawking Zhang /* enable interrupts */ 310*bebd4c79SHawking Zhang ret = vega20_ih_toggle_interrupts(adev, true); 311*bebd4c79SHawking Zhang if (ret) 312*bebd4c79SHawking Zhang return ret; 313*bebd4c79SHawking Zhang 314*bebd4c79SHawking Zhang return 0; 315*bebd4c79SHawking Zhang } 316*bebd4c79SHawking Zhang 317*bebd4c79SHawking Zhang /** 318*bebd4c79SHawking Zhang * vega20_ih_irq_disable - disable interrupts 319*bebd4c79SHawking Zhang * 320*bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 321*bebd4c79SHawking Zhang * 322*bebd4c79SHawking Zhang * Disable interrupts on the hw (VEGA20). 323*bebd4c79SHawking Zhang */ 324*bebd4c79SHawking Zhang static void vega20_ih_irq_disable(struct amdgpu_device *adev) 325*bebd4c79SHawking Zhang { 326*bebd4c79SHawking Zhang vega20_ih_toggle_interrupts(adev, false); 327*bebd4c79SHawking Zhang 328*bebd4c79SHawking Zhang /* Wait and acknowledge irq */ 329*bebd4c79SHawking Zhang mdelay(1); 330*bebd4c79SHawking Zhang } 331*bebd4c79SHawking Zhang 332*bebd4c79SHawking Zhang /** 333*bebd4c79SHawking Zhang * vega20_ih_get_wptr - get the IH ring buffer wptr 334*bebd4c79SHawking Zhang * 335*bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 336*bebd4c79SHawking Zhang * 337*bebd4c79SHawking Zhang * Get the IH ring buffer wptr from either the register 338*bebd4c79SHawking Zhang * or the writeback memory buffer (VEGA20). Also check for 339*bebd4c79SHawking Zhang * ring buffer overflow and deal with it. 340*bebd4c79SHawking Zhang * Returns the value of the wptr. 341*bebd4c79SHawking Zhang */ 342*bebd4c79SHawking Zhang static u32 vega20_ih_get_wptr(struct amdgpu_device *adev, 343*bebd4c79SHawking Zhang struct amdgpu_ih_ring *ih) 344*bebd4c79SHawking Zhang { 345*bebd4c79SHawking Zhang u32 wptr, tmp; 346*bebd4c79SHawking Zhang struct amdgpu_ih_regs *ih_regs; 347*bebd4c79SHawking Zhang 348*bebd4c79SHawking Zhang wptr = le32_to_cpu(*ih->wptr_cpu); 349*bebd4c79SHawking Zhang ih_regs = &ih->ih_regs; 350*bebd4c79SHawking Zhang 351*bebd4c79SHawking Zhang if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 352*bebd4c79SHawking Zhang goto out; 353*bebd4c79SHawking Zhang 354*bebd4c79SHawking Zhang /* Double check that the overflow wasn't already cleared. */ 355*bebd4c79SHawking Zhang wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); 356*bebd4c79SHawking Zhang if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 357*bebd4c79SHawking Zhang goto out; 358*bebd4c79SHawking Zhang 359*bebd4c79SHawking Zhang wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 360*bebd4c79SHawking Zhang 361*bebd4c79SHawking Zhang /* When a ring buffer overflow happen start parsing interrupt 362*bebd4c79SHawking Zhang * from the last not overwritten vector (wptr + 32). Hopefully 363*bebd4c79SHawking Zhang * this should allow us to catchup. 364*bebd4c79SHawking Zhang */ 365*bebd4c79SHawking Zhang tmp = (wptr + 32) & ih->ptr_mask; 366*bebd4c79SHawking Zhang dev_warn(adev->dev, "IH ring buffer overflow " 367*bebd4c79SHawking Zhang "(0x%08X, 0x%08X, 0x%08X)\n", 368*bebd4c79SHawking Zhang wptr, ih->rptr, tmp); 369*bebd4c79SHawking Zhang ih->rptr = tmp; 370*bebd4c79SHawking Zhang 371*bebd4c79SHawking Zhang tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); 372*bebd4c79SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 373*bebd4c79SHawking Zhang WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 374*bebd4c79SHawking Zhang 375*bebd4c79SHawking Zhang out: 376*bebd4c79SHawking Zhang return (wptr & ih->ptr_mask); 377*bebd4c79SHawking Zhang } 378*bebd4c79SHawking Zhang 379*bebd4c79SHawking Zhang /** 380*bebd4c79SHawking Zhang * vega20_ih_irq_rearm - rearm IRQ if lost 381*bebd4c79SHawking Zhang * 382*bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 383*bebd4c79SHawking Zhang * 384*bebd4c79SHawking Zhang */ 385*bebd4c79SHawking Zhang static void vega20_ih_irq_rearm(struct amdgpu_device *adev, 386*bebd4c79SHawking Zhang struct amdgpu_ih_ring *ih) 387*bebd4c79SHawking Zhang { 388*bebd4c79SHawking Zhang uint32_t v = 0; 389*bebd4c79SHawking Zhang uint32_t i = 0; 390*bebd4c79SHawking Zhang struct amdgpu_ih_regs *ih_regs; 391*bebd4c79SHawking Zhang 392*bebd4c79SHawking Zhang ih_regs = &ih->ih_regs; 393*bebd4c79SHawking Zhang 394*bebd4c79SHawking Zhang /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */ 395*bebd4c79SHawking Zhang for (i = 0; i < MAX_REARM_RETRY; i++) { 396*bebd4c79SHawking Zhang v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); 397*bebd4c79SHawking Zhang if ((v < ih->ring_size) && (v != ih->rptr)) 398*bebd4c79SHawking Zhang WDOORBELL32(ih->doorbell_index, ih->rptr); 399*bebd4c79SHawking Zhang else 400*bebd4c79SHawking Zhang break; 401*bebd4c79SHawking Zhang } 402*bebd4c79SHawking Zhang } 403*bebd4c79SHawking Zhang 404*bebd4c79SHawking Zhang /** 405*bebd4c79SHawking Zhang * vega20_ih_set_rptr - set the IH ring buffer rptr 406*bebd4c79SHawking Zhang * 407*bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 408*bebd4c79SHawking Zhang * 409*bebd4c79SHawking Zhang * Set the IH ring buffer rptr. 410*bebd4c79SHawking Zhang */ 411*bebd4c79SHawking Zhang static void vega20_ih_set_rptr(struct amdgpu_device *adev, 412*bebd4c79SHawking Zhang struct amdgpu_ih_ring *ih) 413*bebd4c79SHawking Zhang { 414*bebd4c79SHawking Zhang struct amdgpu_ih_regs *ih_regs; 415*bebd4c79SHawking Zhang 416*bebd4c79SHawking Zhang if (ih->use_doorbell) { 417*bebd4c79SHawking Zhang /* XXX check if swapping is necessary on BE */ 418*bebd4c79SHawking Zhang *ih->rptr_cpu = ih->rptr; 419*bebd4c79SHawking Zhang WDOORBELL32(ih->doorbell_index, ih->rptr); 420*bebd4c79SHawking Zhang 421*bebd4c79SHawking Zhang if (amdgpu_sriov_vf(adev)) 422*bebd4c79SHawking Zhang vega20_ih_irq_rearm(adev, ih); 423*bebd4c79SHawking Zhang } else { 424*bebd4c79SHawking Zhang ih_regs = &ih->ih_regs; 425*bebd4c79SHawking Zhang WREG32(ih_regs->ih_rb_rptr, ih->rptr); 426*bebd4c79SHawking Zhang } 427*bebd4c79SHawking Zhang } 428*bebd4c79SHawking Zhang 429*bebd4c79SHawking Zhang /** 430*bebd4c79SHawking Zhang * vega20_ih_self_irq - dispatch work for ring 1 and 2 431*bebd4c79SHawking Zhang * 432*bebd4c79SHawking Zhang * @adev: amdgpu_device pointer 433*bebd4c79SHawking Zhang * @source: irq source 434*bebd4c79SHawking Zhang * @entry: IV with WPTR update 435*bebd4c79SHawking Zhang * 436*bebd4c79SHawking Zhang * Update the WPTR from the IV and schedule work to handle the entries. 437*bebd4c79SHawking Zhang */ 438*bebd4c79SHawking Zhang static int vega20_ih_self_irq(struct amdgpu_device *adev, 439*bebd4c79SHawking Zhang struct amdgpu_irq_src *source, 440*bebd4c79SHawking Zhang struct amdgpu_iv_entry *entry) 441*bebd4c79SHawking Zhang { 442*bebd4c79SHawking Zhang uint32_t wptr = cpu_to_le32(entry->src_data[0]); 443*bebd4c79SHawking Zhang 444*bebd4c79SHawking Zhang switch (entry->ring_id) { 445*bebd4c79SHawking Zhang case 1: 446*bebd4c79SHawking Zhang *adev->irq.ih1.wptr_cpu = wptr; 447*bebd4c79SHawking Zhang schedule_work(&adev->irq.ih1_work); 448*bebd4c79SHawking Zhang break; 449*bebd4c79SHawking Zhang case 2: 450*bebd4c79SHawking Zhang *adev->irq.ih2.wptr_cpu = wptr; 451*bebd4c79SHawking Zhang schedule_work(&adev->irq.ih2_work); 452*bebd4c79SHawking Zhang break; 453*bebd4c79SHawking Zhang default: break; 454*bebd4c79SHawking Zhang } 455*bebd4c79SHawking Zhang return 0; 456*bebd4c79SHawking Zhang } 457*bebd4c79SHawking Zhang 458*bebd4c79SHawking Zhang static const struct amdgpu_irq_src_funcs vega20_ih_self_irq_funcs = { 459*bebd4c79SHawking Zhang .process = vega20_ih_self_irq, 460*bebd4c79SHawking Zhang }; 461*bebd4c79SHawking Zhang 462*bebd4c79SHawking Zhang static void vega20_ih_set_self_irq_funcs(struct amdgpu_device *adev) 463*bebd4c79SHawking Zhang { 464*bebd4c79SHawking Zhang adev->irq.self_irq.num_types = 0; 465*bebd4c79SHawking Zhang adev->irq.self_irq.funcs = &vega20_ih_self_irq_funcs; 466*bebd4c79SHawking Zhang } 467*bebd4c79SHawking Zhang 468*bebd4c79SHawking Zhang static int vega20_ih_early_init(void *handle) 469*bebd4c79SHawking Zhang { 470*bebd4c79SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 471*bebd4c79SHawking Zhang 472*bebd4c79SHawking Zhang vega20_ih_set_interrupt_funcs(adev); 473*bebd4c79SHawking Zhang vega20_ih_set_self_irq_funcs(adev); 474*bebd4c79SHawking Zhang return 0; 475*bebd4c79SHawking Zhang } 476*bebd4c79SHawking Zhang 477*bebd4c79SHawking Zhang static int vega20_ih_sw_init(void *handle) 478*bebd4c79SHawking Zhang { 479*bebd4c79SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 480*bebd4c79SHawking Zhang int r; 481*bebd4c79SHawking Zhang 482*bebd4c79SHawking Zhang r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 483*bebd4c79SHawking Zhang &adev->irq.self_irq); 484*bebd4c79SHawking Zhang if (r) 485*bebd4c79SHawking Zhang return r; 486*bebd4c79SHawking Zhang 487*bebd4c79SHawking Zhang r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true); 488*bebd4c79SHawking Zhang if (r) 489*bebd4c79SHawking Zhang return r; 490*bebd4c79SHawking Zhang 491*bebd4c79SHawking Zhang adev->irq.ih.use_doorbell = true; 492*bebd4c79SHawking Zhang adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 493*bebd4c79SHawking Zhang 494*bebd4c79SHawking Zhang r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 495*bebd4c79SHawking Zhang if (r) 496*bebd4c79SHawking Zhang return r; 497*bebd4c79SHawking Zhang 498*bebd4c79SHawking Zhang adev->irq.ih1.use_doorbell = true; 499*bebd4c79SHawking Zhang adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; 500*bebd4c79SHawking Zhang 501*bebd4c79SHawking Zhang r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 502*bebd4c79SHawking Zhang if (r) 503*bebd4c79SHawking Zhang return r; 504*bebd4c79SHawking Zhang 505*bebd4c79SHawking Zhang adev->irq.ih2.use_doorbell = true; 506*bebd4c79SHawking Zhang adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1; 507*bebd4c79SHawking Zhang 508*bebd4c79SHawking Zhang /* initialize ih control registers offset */ 509*bebd4c79SHawking Zhang vega20_ih_init_register_offset(adev); 510*bebd4c79SHawking Zhang 511*bebd4c79SHawking Zhang r = amdgpu_irq_init(adev); 512*bebd4c79SHawking Zhang 513*bebd4c79SHawking Zhang return r; 514*bebd4c79SHawking Zhang } 515*bebd4c79SHawking Zhang 516*bebd4c79SHawking Zhang static int vega20_ih_sw_fini(void *handle) 517*bebd4c79SHawking Zhang { 518*bebd4c79SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 519*bebd4c79SHawking Zhang 520*bebd4c79SHawking Zhang amdgpu_irq_fini(adev); 521*bebd4c79SHawking Zhang amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 522*bebd4c79SHawking Zhang amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 523*bebd4c79SHawking Zhang amdgpu_ih_ring_fini(adev, &adev->irq.ih); 524*bebd4c79SHawking Zhang 525*bebd4c79SHawking Zhang return 0; 526*bebd4c79SHawking Zhang } 527*bebd4c79SHawking Zhang 528*bebd4c79SHawking Zhang static int vega20_ih_hw_init(void *handle) 529*bebd4c79SHawking Zhang { 530*bebd4c79SHawking Zhang int r; 531*bebd4c79SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 532*bebd4c79SHawking Zhang 533*bebd4c79SHawking Zhang r = vega20_ih_irq_init(adev); 534*bebd4c79SHawking Zhang if (r) 535*bebd4c79SHawking Zhang return r; 536*bebd4c79SHawking Zhang 537*bebd4c79SHawking Zhang return 0; 538*bebd4c79SHawking Zhang } 539*bebd4c79SHawking Zhang 540*bebd4c79SHawking Zhang static int vega20_ih_hw_fini(void *handle) 541*bebd4c79SHawking Zhang { 542*bebd4c79SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 543*bebd4c79SHawking Zhang 544*bebd4c79SHawking Zhang vega20_ih_irq_disable(adev); 545*bebd4c79SHawking Zhang 546*bebd4c79SHawking Zhang return 0; 547*bebd4c79SHawking Zhang } 548*bebd4c79SHawking Zhang 549*bebd4c79SHawking Zhang static int vega20_ih_suspend(void *handle) 550*bebd4c79SHawking Zhang { 551*bebd4c79SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 552*bebd4c79SHawking Zhang 553*bebd4c79SHawking Zhang return vega20_ih_hw_fini(adev); 554*bebd4c79SHawking Zhang } 555*bebd4c79SHawking Zhang 556*bebd4c79SHawking Zhang static int vega20_ih_resume(void *handle) 557*bebd4c79SHawking Zhang { 558*bebd4c79SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 559*bebd4c79SHawking Zhang 560*bebd4c79SHawking Zhang return vega20_ih_hw_init(adev); 561*bebd4c79SHawking Zhang } 562*bebd4c79SHawking Zhang 563*bebd4c79SHawking Zhang static bool vega20_ih_is_idle(void *handle) 564*bebd4c79SHawking Zhang { 565*bebd4c79SHawking Zhang /* todo */ 566*bebd4c79SHawking Zhang return true; 567*bebd4c79SHawking Zhang } 568*bebd4c79SHawking Zhang 569*bebd4c79SHawking Zhang static int vega20_ih_wait_for_idle(void *handle) 570*bebd4c79SHawking Zhang { 571*bebd4c79SHawking Zhang /* todo */ 572*bebd4c79SHawking Zhang return -ETIMEDOUT; 573*bebd4c79SHawking Zhang } 574*bebd4c79SHawking Zhang 575*bebd4c79SHawking Zhang static int vega20_ih_soft_reset(void *handle) 576*bebd4c79SHawking Zhang { 577*bebd4c79SHawking Zhang /* todo */ 578*bebd4c79SHawking Zhang 579*bebd4c79SHawking Zhang return 0; 580*bebd4c79SHawking Zhang } 581*bebd4c79SHawking Zhang 582*bebd4c79SHawking Zhang static void vega20_ih_update_clockgating_state(struct amdgpu_device *adev, 583*bebd4c79SHawking Zhang bool enable) 584*bebd4c79SHawking Zhang { 585*bebd4c79SHawking Zhang uint32_t data, def, field_val; 586*bebd4c79SHawking Zhang 587*bebd4c79SHawking Zhang if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 588*bebd4c79SHawking Zhang def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 589*bebd4c79SHawking Zhang field_val = enable ? 0 : 1; 590*bebd4c79SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 591*bebd4c79SHawking Zhang IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val); 592*bebd4c79SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 593*bebd4c79SHawking Zhang IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val); 594*bebd4c79SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 595*bebd4c79SHawking Zhang DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 596*bebd4c79SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 597*bebd4c79SHawking Zhang OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 598*bebd4c79SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 599*bebd4c79SHawking Zhang LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 600*bebd4c79SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 601*bebd4c79SHawking Zhang DYN_CLK_SOFT_OVERRIDE, field_val); 602*bebd4c79SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 603*bebd4c79SHawking Zhang REG_CLK_SOFT_OVERRIDE, field_val); 604*bebd4c79SHawking Zhang if (def != data) 605*bebd4c79SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 606*bebd4c79SHawking Zhang } 607*bebd4c79SHawking Zhang } 608*bebd4c79SHawking Zhang 609*bebd4c79SHawking Zhang static int vega20_ih_set_clockgating_state(void *handle, 610*bebd4c79SHawking Zhang enum amd_clockgating_state state) 611*bebd4c79SHawking Zhang { 612*bebd4c79SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 613*bebd4c79SHawking Zhang 614*bebd4c79SHawking Zhang vega20_ih_update_clockgating_state(adev, 615*bebd4c79SHawking Zhang state == AMD_CG_STATE_GATE); 616*bebd4c79SHawking Zhang return 0; 617*bebd4c79SHawking Zhang 618*bebd4c79SHawking Zhang } 619*bebd4c79SHawking Zhang 620*bebd4c79SHawking Zhang static int vega20_ih_set_powergating_state(void *handle, 621*bebd4c79SHawking Zhang enum amd_powergating_state state) 622*bebd4c79SHawking Zhang { 623*bebd4c79SHawking Zhang return 0; 624*bebd4c79SHawking Zhang } 625*bebd4c79SHawking Zhang 626*bebd4c79SHawking Zhang const struct amd_ip_funcs vega20_ih_ip_funcs = { 627*bebd4c79SHawking Zhang .name = "vega20_ih", 628*bebd4c79SHawking Zhang .early_init = vega20_ih_early_init, 629*bebd4c79SHawking Zhang .late_init = NULL, 630*bebd4c79SHawking Zhang .sw_init = vega20_ih_sw_init, 631*bebd4c79SHawking Zhang .sw_fini = vega20_ih_sw_fini, 632*bebd4c79SHawking Zhang .hw_init = vega20_ih_hw_init, 633*bebd4c79SHawking Zhang .hw_fini = vega20_ih_hw_fini, 634*bebd4c79SHawking Zhang .suspend = vega20_ih_suspend, 635*bebd4c79SHawking Zhang .resume = vega20_ih_resume, 636*bebd4c79SHawking Zhang .is_idle = vega20_ih_is_idle, 637*bebd4c79SHawking Zhang .wait_for_idle = vega20_ih_wait_for_idle, 638*bebd4c79SHawking Zhang .soft_reset = vega20_ih_soft_reset, 639*bebd4c79SHawking Zhang .set_clockgating_state = vega20_ih_set_clockgating_state, 640*bebd4c79SHawking Zhang .set_powergating_state = vega20_ih_set_powergating_state, 641*bebd4c79SHawking Zhang }; 642*bebd4c79SHawking Zhang 643*bebd4c79SHawking Zhang static const struct amdgpu_ih_funcs vega20_ih_funcs = { 644*bebd4c79SHawking Zhang .get_wptr = vega20_ih_get_wptr, 645*bebd4c79SHawking Zhang .decode_iv = amdgpu_ih_decode_iv_helper, 646*bebd4c79SHawking Zhang .set_rptr = vega20_ih_set_rptr 647*bebd4c79SHawking Zhang }; 648*bebd4c79SHawking Zhang 649*bebd4c79SHawking Zhang static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev) 650*bebd4c79SHawking Zhang { 651*bebd4c79SHawking Zhang adev->irq.ih_funcs = &vega20_ih_funcs; 652*bebd4c79SHawking Zhang } 653*bebd4c79SHawking Zhang 654*bebd4c79SHawking Zhang const struct amdgpu_ip_block_version vega20_ih_ip_block = 655*bebd4c79SHawking Zhang { 656*bebd4c79SHawking Zhang .type = AMD_IP_BLOCK_TYPE_IH, 657*bebd4c79SHawking Zhang .major = 4, 658*bebd4c79SHawking Zhang .minor = 2, 659*bebd4c79SHawking Zhang .rev = 0, 660*bebd4c79SHawking Zhang .funcs = &vega20_ih_ip_funcs, 661*bebd4c79SHawking Zhang }; 662